**4. Conclusions**

In this article, a low-power, high-data-rate, area-efficient BPSK demodulator utilizing a delayed digitized format of the input BPSK signal is presented. The presented circuit is designed and simulated in a standard 0.18 μm CMOS process using a 1.8 V power supply. Post-layout simulation and Monte Carlo analysis show that the presented circuit (including the clock recovery block) consumes 5.6 μW, 6.7 μW, and 8.5 μW at frequencies of 2 MHz, 10 MHz, and 20 MHz, respectively. The occupied active area of the whole circuit is 17 × 27 μm<sup>2</sup> and besides simplicity and low power consumption, the designed demodulator circuit benefits from a DRCF of 100%.

**Author Contributions:** Conceptualization and design, M.G.; formal analysis, M.G.; software, M.G.; investigation, M.H.M.; writing—original draft preparation, M.G.; writing—review and editing, M.H.M.; supervision, M.H.M., P.A., and S.H.-H.; funding acquisition, S.H.-H. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research received no external funding.

**Conflicts of Interest:** The authors declare no conflict of interest.
