**Design of Reconfigurable Time-to-Digital Converter Based on Cascaded Time Interpolators for Electrical Impedance Spectroscopy** †

**Sounghun Shin 1,**‡**,§, Yoontae Jung 2,**‡**, Soon-Jae Kweon 2,\*, Eunseok Lee 2, Jeong-Ho Park 3,§, Jinuk Kim 2, Hyung-Joun Yoo <sup>2</sup> and Minkyu Je <sup>2</sup>**


Received: 17 February 2020; Accepted: 26 March 2020; Published: 29 March 2020

**Abstract:** This paper presents a reconfigurable time-to-digital converter (TDC) used to quantize the phase of the impedance in electrical impedance spectroscopy (EIS). The TDC in the EIS system must handle a wide input-time range for analysis in the low-frequency range and have a high resolution for analysis in the high-frequency range. The proposed TDC adopts a coarse counter to support a wide input-time range and cascaded time interpolators to improve the time resolution in the high-frequency analysis without increasing the counting clock speed. When the same large interpolation factor is adopted, the cascaded time interpolators have shorter measurement time and smaller chip area than a single-stage time interpolator. A reconfigurable time interpolation factor is adopted to maintain the phase resolution with reasonable measurement time. The fabricated TDC has a peak-to-peak phase error of less than 0.72◦ over the input frequency range from 1 kHz to 512 kHz and the phase error of less than 2.70◦ when the range is extended to 2.048 MHz, which demonstrates a competitive performance when compared with previously reported designs.

**Keywords:** electrical impedance spectroscopy (EIS); time-to-digital converter (TDC); time interpolator; phase; polar demodulator; quantization; reconfigurability

#### **1. Introduction**

Electrical impedance spectroscopy (EIS), which measures the impedance over a range of frequencies, has been widely used in today's biomedical applications such as body composition analysis [1–3], cancer diagnosis [4–6], and detection of allergic contact reaction [7], and so on. The frequency range from 1 kHz to several MHz, which is associated with the polarization of macromolecules [8], is required for these applications. With growing demands on portable EIS systems, today's research is focused on designing fully integrated EIS systems that support a wide frequency range.

The impedance spectrum can be obtained by measuring the impedance for a particular frequency and then repeating the measurement with sweeping the frequency, which is called the frequency response analyzing (FRA) method [9]. When a sinusoidal current signal is injected into the material under the experiment, the resulting sinusoidal voltage signal is generated with the magnitude and time delay that depend on the magnitude and phase of the material's impedance, respectively [10,11]. The EIS system is generally composed of two parts: a sinusoidal signal generator (SSG) and a demodulator. The SSG injects the sinusoidal current signal into the target material, and the demodulator measures the resulting voltage signal. Considering that the EIS system that supports sensor array includes several demodulators with one SSG [9,12,13], it is important to design a demodulator to be hardware-efficient and to have high precision.

Conventional quadrature demodulators extract real and imaginary parts of impedance using quadrature mixers and low-pass filters (LPFs) [12–14]. When the resulting signal depending on the target impedance is multiplied by a signal that is in phase with the injected signal and then low-pass filtered, the output value represents the real part of the impedance. When multiplied by a signal that is 90◦ out of phase with the injected signal and then low-pass filtered, the imaginary part of the impedance is provided. In such a process, incomplete synchronization among the aforementioned signals becomes a dominant source of error, and the need for phase-correction circuitry increases the implementation complexity [15]. To resolve this synchronization issue, polar demodulators, which asynchronously measure the magnitude variation and time delay of the resulting signal, have been proposed [10,11,15–17]. In particular, the polar demodulators in [10,11,17] mitigate the complexity of analog front-end significantly because the magnitude variation is measured without large-time-constant LPFs and the time delay is measured with one of simple logics such as XOR, XNOR, and latch. In quadrature demodulators, the large-time-constant LPFs limit measurement speed [17] and occupy large area. In polar demodulators, contrarily, the simple logic produces a pulse having the width that corresponds to the time delay, and then a time-to-digital converter (TDC) is used to quantize the pulse width. Note that the pulse width is proportional not only to the phase of impedance but also to the period of the injected signal. Therefore, the TDC should be able to handle wide input-time range to support the analysis at low frequencies, and also achieve a high resolution to support the analysis at high frequencies. It is, therefore, important to design the TDC to meet these requirements in a simple and efficient way for implementing a low-complexity polar demodulator.

Two types of TDCs have been proposed for the EIS system: TDCs based on a time-to-voltage converter (TVC) [15] and a counter [17–19]. The TVC converts the pulse width to the voltage by charging a capacitor with a current source, and the following analog-to-digital converter (ADC) quantizes the output of the TVC [15]. However, the phase error increases with the frequency of the injected signal because the full-scale output voltage of the TVC decreases as the frequency of the injected signal increases. Since counter-based TDCs have an input-time range that is theoretically unlimited [20], this type of TDCs appear to be attractive phase quantizers in the EIS system. However, the TDC in [17] requires high-speed counting clock for high-frequency analysis because the counting speed solely decides the time resolution. This TDC adopts a 3.3-GHz counting clock to support the maximum frequency of up to 10 MHz.

We have proposed two reconfigurable TDCs combining counters with time interpolators to improve resolution without increasing the counting clock speed and verified them by simulation [18,19]. Both TDCs employ a coarse counter to secure wide input-time range. The TDC in [18] uses cascaded time interpolators with a reconfigurable time interpolation factor. When the same large interpolation factor is used, the cascaded time interpolators have shorter measurement time and smaller chip area than a single-stage time interpolator. Since both the required input-time range and time resolution vary with the frequency of the injected signal, the reconfigurable time interpolation factor is employed to maintain phase error within an appropriate level while providing reasonable measurement time. Instead of the cascaded time interpolators, the TDC in [19] utilizes a time interpolator with a low

interpolation factor and a chain delay line to further reduce the phase error. Although the TDC in [19] shows improved precision, the TDC in [18] allows more efficient implementation in terms of chip size.

This paper presents the reconfigurable TDC based on cascaded time interpolators [18], which has been fabricated in 0.25-μm CMOS process, with providing comprehensive explanation, detailed analysis, and measurement results. The fabricated TDC quantizes the pulse width corresponding to the phase of 0◦ to 90◦ with the peak-to-peak phase error of under 0.72◦ up to 512-kHz frequency and the phase error of under 2.70◦ up to 2.048-MHz frequency, demonstrating competitive performances compared to previously reported designs.

#### **2. Background and Design Specifications**

This section describes the impedance measurement principle and phase measurement scheme in EIS systems. From this background, design specifications are derived at the end of the section.

#### *2.1. Impedance Measurement Principle*

When a sinusoidal current signal *iin*(*t*) is injected into the target material, a resulting sinusoidal voltage signal *vb*(*t*) is generated, and its magnitude and time delay with respect to *iin*(*t*) depend on the impedance of the material, as shown in Figure 1. *Zb* is the impedance of the target material, and |*Zb*| and θ are the magnitude and phase of *Zb*, respectively.

**Figure 1.** Magnitude and phase of the resulting voltage determined by the impedance under measurement.

Polar demodulators measure the magnitude and time delay of *vb*(*t*) for a particular frequency. |*Zb*| and θ can be calculated as follows: 

$$|Z\_b| = \frac{|v\_b(t)|}{|I\_{IN}|},\tag{1}$$

$$
\theta = \frac{T\_b}{T\_{in}} \,\mathrm{\,\,\,}\tag{2}
$$

where |*vb*(*t*)| and *Tb* are the magnitude and time delay of *vb*(*t*), respectively. |*IIN*| is the magnitude of *iin*(*t*), and *Tin* is the period of *iin*(*t*) and *vb*(*t*). Impedance spectrum is obtained by using the FRA method, which analyzes one frequency at a time, repeatedly with sweeping the frequency [9].

#### *2.2. Phase Measurement Scheme in Polar Demodulators*

Figure 2 shows the phase measurement scheme adopted in polar demodulators [10,11,15–17]. When *iin*(*t*) is injected into the target material and reference resistor, *vr*(*t*) with the same phase as *iin*(*t*) is generated from the resistor in addition to *vb*(*t*). Comparators convert *vr*(*t*) and *vb*(*t*) to clock signals, φ*<sup>r</sup>* and φ*b*, from which an XOR gate and an SR latch create clock signals, φ*XOR* and φ*SR*, respectively. These clock signals have the pulse width of *Tb*, which corresponds to θ, as shown in Figure 2. From Equation (2), when the frequency of the injected current, *fin* = 1/*Tin* is known, θ can be determined by measuring *Tb*.

**Figure 2.** (**a**) Block diagram and (**b**) waveforms of the phase measurement scheme (reproduced from [19] with permission from the IEEE).

#### *2.3. Design Specifications*

Design specifications of TDC proposed in this paper are presented in Table 1. *fin* is set from 1 kHz to 2.048 MHz because the proposed TDC is implemented in the form of a fully integrated chip for EIS systems in biomedical applications. Considering that the impedance measured in such applications [15] usually has capacitive reactance, θ ranges from 0◦ to 90◦, and the corresponding input-time range is 0 to 122 ns at the shortest when *fin* is 2.048 MHz and 0 to 250 μs at the widest when *fin* is 1 kHz. Referring to performances of the previous works reported in [15,17], this TDC aims to have maximum phase error under 1◦ and phase resolution over 10 bits for the suggested range of *fin*. This amount of phase error corresponds to 1.35 ns in the worst case when *fin* is 2.048 MHz. Lastly, the frequency of the reference clock (*fclk*) is set to 32.768 MHz, which is only 16 times the maximum *fin*. Compared to the TDC in [17], where *fclk* is 330 times higher than the maximum *fin*, the proposed TDC aims to achieve competitive phase error performance with much lower *fclk*.

**Table 1.** Design specifications of the proposed time-to-digital converter (TDC).


#### **3. Architecture of the Proposed TDC**

As shown in Table 1, the requirements of both the input-time range and time resolution vary with *fin*. The proposed TDC operates across three different modes to meet the design specifications with maintaining reasonable measurement time. This section describes overall architecture and operation in each mode.

#### *3.1. Overall Architecture and Operation*

The block diagram of the proposed TDC is presented in Figure 3. The input pulse signal whose pulse width carries θ is denoted as φ*in*. φ*clk* is the reference clock, and the outputs of the system are the digital bits, *Dc*, *Df*1, and *Df*2. This TDC is composed of three stages, namely a coarse stage, the first fine stage, and the second fine stage. The coarse stage consists of a 12-bit coarse counter with digital logics. Each fine stage consists of a time splitter, a reconfigurable time interpolator, and a 4-bit counter. The coarse counter is used to implement a wide input-time range, and two fine stages are employed to

improve resolution without increasing *fclk*. In each fine stage, the time splitter extracts quantization error of the preceding stage and the time interpolator stretches the quantization error. The resolution can be improved by quantizing the stretched quantization error through the fine counters and φ*clk*.

**Figure 3.** Block diagram of the proposed TDC (reproduced from [18] with permission from the IEEE).

The proposed TDC operates in one of the three modes to achieve the phase resolution over 10 bits. In mode A, only the coarse stage is used, and the time resolution is *Tclk*. For low *fin* of 1 kHz and 2 kHz, *fclk* is high enough to achieve target phase resolution. For 4-kHz *fin* upwards, the fine stages are used with the coarse stage to further improve the time resolution without increasing *fclk*. In mode B, the coarse stage and the first fine stage are used for *fin* from 4 kHz to 32 kHz. The first fine stage further quantizes the quantization error of the coarse stage with a time interpolation factor of *AT*1. The time resolution in mode B is *Tclk*/*AT*1, which is *AT*<sup>1</sup> times higher than the highest resolution in mode A while keeping *fclk* = 32.768 MHz. In mode C, for 32-kHz *fin* upwards, the coarse stage and the first fine stage operate in the same manner. In addition, the second fine stage further quantizes the quantization error of the first fine stage. The time resolution in mode C is *Tclk*/(*AT*1*AT*2), which is *AT*1*AT*<sup>2</sup> times higher than the highest one in mode A, still keeping *fclk* = 32.768 MHz. When *fin* = 2.048 MHz, the coarse stage only achieves a 2-bit resolution for θ range from 0◦ to 90◦ with *fclk* = 32.768 MHz. Therefore, the total interpolation factor (*AT*) of up to 256 is required to achieve a 10-bit resolution for the whole *fin* range. *AT*<sup>1</sup> and *AT*<sup>2</sup> are set, as shown in Table 2, across three different modes, A, B, and C, for varying values of *fin*.


**Table 2.** Assignment of the interpolation factor for different operation modes and values of *fin.*

When utilizing the time interpolator, *AT* is determined by the ratio of discharging capacitance and discharging current [20]. If the current increases for implementing a large *AT*, the power consumption of TDC increases accordingly. Moreover, since the pulse width of the interpolated signal increases, the conversion time increases significantly, which leads to the degraded conversion rate. Thus, the large *AT* is realized in two steps by dividing *AT* into *AT*<sup>1</sup> and *AT*<sup>2</sup> to offer much more relaxed design conditions. *AT*<sup>1</sup> and *AT*<sup>2</sup> can be adjusted between 2, 4, 8, and 16 to provide 1, 2, 3, and 4 additional bits, respectively. Reconfigurable *AT*<sup>1</sup> and *AT*<sup>2</sup> maintain the phase resolution over 10 bits with reasonably short measurement time.

#### *3.2. Operation in Mode A*

This mode offers only counter-based time quantization, and the timing diagram of its operation is depicted in Figure 4.

**Figure 4.** Timing diagram of the proposed TDC in mode A.

The proposed TDC in mode A outputs digital bits *Dc* with the relation as follows:

$$T\_b = D\_c \times T\_{clk} - T\_{q.c.} \tag{3}$$

where *Tq,c* is the quantization error of the coarse stage and smaller than *Tclk*. The time resolution in mode A becomes one period of the clock signal, *Tclk*. To achieve a 12-bit phase resolution for θ range from 0◦ to 90◦ at low *fin*, this mode is used for *fin* of up to 2 kHz.

#### *3.3. Operation in Mode B*

Mode B uses the coarse stage and the first fine stage, each generating output digital bits, *Dc* and *Df*1, respectively. The timing diagram of its operation is presented in Figure 5.

**Figure 5.** Timing diagram of the proposed TDC in Mode B.

The pulse width of *Tf*<sup>1</sup> is generated by the time splitter in the first fine stage and expressed as follows:

$$T\_{f1} = T\_{q,\mathcal{E}} + T\_{c\mathbb{R}}.\tag{4}$$

The time interpolator in the first stage stretches *Tf*<sup>1</sup> to *Tint*1, which is described by:

$$T\_{\rm int1} = A\_{T1} \cdot T\_{f1}.\tag{5}$$

The fine counter quantizes *Tint*<sup>1</sup> with the reference clock, to output up to four fine digital bits, *Df*1. The relation among *Tb*, *Dc*, and *Df*<sup>1</sup> is given by:

$$T\_b = T\_\varepsilon - \left(T\_{f1} - T\_{\rm clk}\right) = \left(D\_\varepsilon \times T\_{\rm clk}\right) - \left(\frac{T\_{\rm int1}}{A\_{T1}} - T\_{\rm clk}\right) = \left(D\_\varepsilon \times T\_{\rm clk}\right) - \left(\frac{D\_{f1} \times T\_{\rm clk} - T\_{q,f1}}{A\_{T1}} - T\_{\rm clk}\right). \tag{6}$$

where *Tq,f*1/*AT*<sup>1</sup> is always smaller than *Tclk*. The time resolution in mode B is improved from *Tclk* to *Tclk*/*AT*1, which is *AT*<sup>1</sup> times higher than the highest resolution in mode A while keeping *fclk* =32.768 MHz. To achieve a 12-bit phase resolution for θ range from 0◦ to 90◦, *fin* must satisfy the following condition:

$$\frac{1}{f\_{\rm in}} \cdot \frac{90}{360} \cdot \frac{1}{2^{12}} < \frac{T\_{\rm clk}}{A\_{T1}}.\tag{7}$$

With the maximum *AT*<sup>1</sup> of 16, this mode is used until *fin* increases up to 32 kHz.

#### *3.4. Operation in Mode C*

The mode C uses the coarse stage, the first fine stage, and the second fine stage, each generating output digital bits, *Dc*, *Df*1, and *Df2*, respectively. The timing diagram of its operation is presented in Figure 6.

**Figure 6.** Timing diagram of the proposed TDC in mode C.

The coarse stage and the first fine stage operate in the same manner as in mode B. The time splitter in the second stage generates *Tf*2, which is expressed as:

$$T\_{f2} = T\_{q,f1} + T\_{clk}.\tag{8}$$

The time interpolator in the second stage stretches *Tf*<sup>2</sup> to *Tint*2, which is described by:

$$T\_{\rm int2} = A\_{T2} \cdot T\_{f2}.\tag{9}$$

*Sensors* **2020**, *20*, 1889

The fine counter in the second fine stage quantizes *Tint*<sup>2</sup> with the reference clock, to output up to four fine digital bits, *D2*. The relation among *Tb*, *Dc*, *Df*1, and *Df*<sup>2</sup> is given by:

$$\begin{aligned} T\_{\rm b} &= (D\_{\rm c} \times T\_{\rm c\rm lk}) - \left( \frac{D\_{f1} \times T\_{\rm c\rm l} - T\_{\rm f1}}{A\_{\rm T1}} - T\_{\rm c\rm lk} \right) = (D\_{\rm c} \times T\_{\rm c\rm l\rm k}) - \left\{ \frac{D\_{f1} \times T\_{\rm c\rm l\rm l} - \left( T\_{f2} - T\_{\rm c\rm l\rm l} \right)}{A\_{\rm T1}} - T\_{\rm c\rm l\rm k} \right\} \\ &= (D\_{\rm c} \times T\_{\rm c\rm l\rm k}) - \left\{ \frac{D\_{f1} \times T\_{\rm c\rm l\rm l} - \left( \frac{D\_{f2} \times T\_{\rm c\rm l\rm l\rm l} - T\_{\rm c\rm l\rm l}}{A\_{\rm T1}} - T\_{\rm c\rm l\rm k} \right)}{A\_{\rm T1}} - T\_{\rm c\rm l\rm k} \right\} \\ &= \{ (D\_{\rm c} + 1) \times T\_{\rm c\rm l\rm l} \} - \left\{ \frac{(D\_{f1} - 1) \times T\_{\rm c\rm l\rm l}}{A\_{\rm T1}} \right\} + \left( \frac{D\_{f2} \times T\_{\rm c\rm l\rm l\rm l} - T\_{\rm c\rm l\rm l\rm l}}{A\_{\rm T1} A\_{\rm T2}} \right) . \end{aligned} \tag{10}$$

where *Tq,f*2/(*AT*1*AT*2) is always smaller than *Tclk*. The time resolution in mode C is improved from *Tclk* to *Tclk*/(*AT*1*AT*2), which is *AT*1*AT*<sup>2</sup> times higher than the highest resolution in mode A, even though *fclk* = 32.768 MHz is kept. To achieve a 10-bit phase resolution for θ range from 0◦ to 90◦, *fin* must satisfy the following condition:

$$\frac{1}{f\_{\rm in}} \cdot \frac{90}{360} \cdot \frac{1}{2^{10}} < \frac{T\_{\rm clk}}{A\_{T1} A\_{T2}}.\tag{11}$$

with the maximum *AT*<sup>1</sup> and *AT*<sup>2</sup> of 16, this mode is used for *fin* of up to 2.048 MHz.

#### **4. Circuit Design**

This section describes how the first fine stage is designed to realize time interpolation with reconfigurable *AT*1. The second fine stage is designed to be identical to the first one.

#### *4.1. Time Splitter*

Figure 7 shows the structure of the time splitter, which consists of three D flip-flops and one NOR gate. As shown in Figures 5 and 6, the time splitter extracts the quantization error of the coarse stage with an offset of *Tclk*. This offset is employed to avoid the metastability issue of the D flip-flops [20]. Therefore, *Tf*<sup>1</sup> takes the value from *Tclk* to 2*Tclk*, corresponding to 30.52 ns to 61.04 ns. As shown in Equations (6) and (10), in mode B and C, the offset is compensated when *Tb* is calculated from the digital outputs.

**Figure 7.** Structure of the time splitter (reproduced from [18] with permission from the IEEE).

#### *4.2. Reconfigurable Time Interpolator*

Figure 8 shows the block diagram and timing diagram of the reconfigurable time interpolator. The reconfigurable time interpolator is similar to the time interpolator in [20]. A variable discharging capacitor, which has the capacitance of *CINT*, is added to obtain reconfigurable *AT*1.

While φ*f*1, which has the pulse width of *Tf*1, is high, a capacitor which has the capacitance of *CF* is discharged by a constant current, *IF*, such that *v*1(*t*) drops by Δ*V*. Δ*V* is expressed as follows:

$$
\Delta V = \frac{I\_F \cdot T\_{f1}}{C\_F}.\tag{12}
$$

From the falling edge of φ*f*1, a capacitor of *CINT* is discharged by a constant current, *IINT*, during φ*f*1*,q* is high. In the same manner with Equation (12), the pulse width of φ*f*1*,q* is expressed as follows:

$$A\_{T1} \cdot T\_{f1} = \frac{\mathbf{C\_{INT}}}{I\_{INT}} \cdot \Delta V = \frac{\mathbf{C\_{INT}}}{I\_{INT}} \cdot \frac{I\_F}{\mathbf{C\_F}} \cdot T\_{f1} = \frac{\mathbf{C\_{INT}}}{\mathbf{C\_F}} \cdot \frac{I\_F}{I\_{INT}} \cdot T\_{f1} = (M \cdot N) \cdot T\_{f1\prime} \tag{13}$$

where *M* is the capacitance ratio, *CINT*/*CF*, *N* is the current ratio, *IF*/*IINT*, and *AT*<sup>1</sup> is *M*·*N*.

In the proposed TDC, *N* is kept constant while *M* is controlled to change *AT*<sup>1</sup> between 2, 4, 8, and 16. Adjustment of the capacitance value is selected over the current value because controlling the capacitance ratio is more accurate than controlling the current ratio in IC implementation. In each fine stage, since *N* is fixed to 2, *CF* is kept constant as 3.6 pF, and *CINT* is changed across 3.6 pF, 7.2 pF, 14.4 pF, and 28.8 pF. *IF* and *IINT* are 80 μA and 40 μA, respectively.

**Figure 8.** Block diagram and timing diagram of the reconfigurable time interpolator (reproduced from [18] with permission from the IEEE).

#### *4.3. Novel Features of the Proposed TDC*

The proposed TDC employs time interpolation technique, which can improve time resolution without increasing *fclk* in the counter-based TDC. However, two inherent issues are associated with large *AT*. Although the resolution becomes much higher when the front-stage quantization error is interpolated with *AT*, the chip size or power consumption increases by a substantial amount because *AT* is determined by capacitance ratio or current ratio. Also, the conversion time increases significantly because the interpolated pulse width increases as *AT* increases. A novel structure of cascading two separate fine stages resolves these two issues at the same time.

When *AT* of 256 is obtained by using a single-stage time interpolator with *CF* of 1 pF and *CINT* of 256 pF, this results in excessively large chip size and poor area efficiency. In the proposed TDC, two interpolation stages are cascaded. As a result, the interpolation factor of only 16 is required in each stage instead of 256. In other words, this system requires two capacitors with the size of *CINT*, which is equal to 16 *CF*. Compared to the single stage with *AT* of 256, this approach reduces the area used for implementing the discharging capacitors by a factor of 257/34 = ~7.6 times considering that one time interpolator has two discharging capacitors with the sizes of *CINT* and *CF*. As the time interpolators in fine stages occupy a significant portion of the chip size, the area efficiency of the system is greatly improved. On the other hand, when *AT* of 256 is set by the capacitance ratio, the current consumption of the cascaded time interpolation stages is two times higher than that of the single-stage time interpolator. For the single interpolator with *AT* of 256, from the falling edge of φ*c*, the conversion time of *ATTf*<sup>1</sup> is required for fine conversion, and the maximum conversion time is 2*ATTclk* considering the offset of the time splitter. For two cascaded interpolation stages with *AT*<sup>1</sup> and *AT*<sup>2</sup> of 16, the conversion time of each fine stage is *AT*1*Tf*<sup>1</sup> or *AT*2*Tf*1, and the maximum conversion time of each stage is 2*AT*1*Tclk* or 2*AT*2*Tclk*. Compared to the single interpolator with *AT* of 256, when *AT*<sup>1</sup> = *AT*<sup>2</sup> = 16, the conversion time for fine conversion is reduced by approximately 8 times.

When *Nf* of time interpolation stages are cascaded and *AT* is set by the capacitance ratio, the area efficiency (*EA*), power efficiency (*EP*), and conversion-time efficiency for fine stages (*EC*) can be defined and expressed as follows:

$$E\_A = \frac{\text{Total capacitance in an interpolation stage when } N\_f = 1}{\text{Total capacitance in interpolation stages when } N\_f > 1} = \frac{(1 + A\_T)\mathbb{C}\_F}{N\_f \left(1 + \sqrt[N]{Ar}\right)\mathbb{C}\_F} = \frac{1 + A\gamma}{N\_f \left(1 + \sqrt[N]{Ar}\right)},\tag{14}$$

$$Ep = \frac{\text{The current consumption of an interpolation stage when } N\_f = 1}{\text{The current consumption of interpolation stages when } N\_f > 1} = \frac{I\_{final}}{N\_f \cdot I\_{final}} = \frac{1}{N\_f},\tag{15}$$

$$E\_{\mathbb{C}} = \frac{\text{The max. conversion time through a fine stage when } N\_f = 1}{\text{The max. conversion time through fine stages when } N\_f > 1} \approx \frac{A\_{\Gamma} \cdot 2T\_{\text{clk}}}{N\_f \cdot \sqrt[N]{A\_{\Gamma}} \cdot 2T\_{\text{clk}}} = \frac{A\_{\Gamma}}{N\_f \cdot \sqrt[N]{A\_{\Gamma}}},\tag{16}$$

where *Ifine* is the current consumption of a single time interpolation stage.

Table 3 summarizes *EA*, *EP*, and *EC* calculated using Equations (14)–(16). Although the maximum *EA*·*EP*·*EC* value is obtained when *Nf* = 4, we chose *Nf* = 2 to minimize the current consumption while taking advantages of the cascaded time interpolators in terms of area and conversion time. The largest capacitor with size of 28.8 pF is small enough to integrate on chip and 2*AT*1*Tclk* = ~1 μs of conversion time for the fine stage is short enough.

**Table 3.** *EA*, *EP*, and *EC* versus *Nf* when *AT* is set by the capacitance ratio.


It is also possible to obtain *AT* through the current ratio of *IF*/*IINT* in Figure 8. In this case, setting the current ratio to 256 directly affects the static power, severely degrading the power efficiency of the system. Total discharging current of cascaded time interpolation stages when *Nf* = 2 could be 7.6-times smaller than that of a single time interpolation stage when *Nf* = 1, and the total capacitance of cascaded time interpolation stages when *Nf* = 2 could be two times larger than that of a single time interpolation stage when *Nf* = 1. Compared to the single interpolator with *AT* of 256 and *Nf* = 1, when *Nf* = 2, the time for fine conversion is reduced by approximately eight times. The optimization process when *AT* is set by the current ratio would be similar to that when *AT* is set by the capacitance ratio.

#### **5. Measurement Results**

The proposed TDC has been fabricated with a 0.25-μm CMOS process. The size of the circuit is 787 <sup>μ</sup>m <sup>×</sup> 524 <sup>μ</sup>m (0.412 mm2). The chip photograph and layout of the fabricated IC are presented in Figure 9.

**Figure 9.** Chip photograph and layout.

Figure 10 shows the measurement setup. Two Agilent 33250A function generators are used, one for generating φ*clk* and another for generating φ*in* whose pulse width varies from 0 to 0.25 of the period which corresponds to the phase of 0◦ to 90◦. These two function generators are synchronized with each other. In the case of generating φ*in* in the form of pulse train, the period can be adjusted from 20.00 ns to 2000.0 s, and its pulse width can be controlled from 8.0 ns to 1999.9 s. Therefore, when *fin* = 2.048 MHz, the phase above 5.9◦ could be measured. Arduino DUE was selected for a microcontroller unit because it has 54 digital I/O pins which are enough for receiving digital output bits and transmitting assignment codes through SPI for the reconfiguration of TDC. Moreover, its clock speed of 84 MHz allows generating required signals to initialize the SPI communication and select between the read and write modes. Monitoring pads are placed on the main propagation path of signal to examine whether each block and each stage operate as expected. Keysight Technologies DSO7104A oscilloscope was used throughout the measurement. The oscilloscope has enough sample rate of 4 Gsps, bandwidth of 1 GHz, and four scope channels.

**Figure 10.** Measurement setup.

In this section, measurement results for one frequency in mode A, one in mode B, and one in mode C are shown. The input-output characteristics of the fabricated TDC are described in Figures 11a, 12a and 13a. Figures 11b, 12b and 13b present the phase errors in each frequency.

#### *5.1. Mode A*

Measurement results for *fin* = 1 kHz are shown in Figure 11. Only the coarse stage is used, and the TDC operates as a counter-based TDC with *fclk* = 16.384 MHz, halved from the 32.768-MHz clock signal provided by the function generator. The input-output characteristic of the TDC is shown in Figure 11a, where the horizontal axis indicates the pulse width of the input signal in seconds, and the vertical axis shows the TDC output code in units of LSB. The solid line represents theoretical output values for given pulse widths of the input. Figure 11b presents the phase error calculated from the digital output code as a function of the actual phase injected at the input. The input phase is varied with a step size of 0.0005◦, which corresponds to about 1.4 ns. The difference between the maximum and minimum phase errors is about 0.022◦, implying that the error of the measured output lies within 12-bit-resolution quantization error for θ range from 0◦ to 90◦ and that the TDC operates as expected.

**Figure 11.** (**a**) Measured input-output characteristic of TDC, and (**b**) phase errors for *fin* = 1 kHz.

#### *5.2. Mode B*

Measurement results for *fin* = 8 kHz are shown in Figure 12. The coarse stage and the first fine stage are used with *fclk* = 32.768 MHz and *AT*<sup>1</sup> = 4. However, *AT*<sup>1</sup> of 4.05 is obtained from the measured *Tint*<sup>1</sup> and *Tf*1, and this value is substituted to Equation (6) to derive *Tb* using output code. The input-output characteristic of the TDC is shown in Figure 12a, where the horizontal axis, vertical axis, and solid line are as described in Figure 11a. Figure 12b presents the phase error calculated from the digital output code as a function of the actual phase injected at the input. The input phase is varied with a step size of 0.0003◦, which corresponds to 0.1 ns. The peak-to-peak phase error is about 0.022◦, implying that the error of the measured output lies within 12-bit-resolution quantization error for θ range from 0◦ to 90◦. This result shows a good agreement with the theoretical prediction.

**Figure 12.** (**a**) Measured input-output characteristic of TDC, and (**b**) phase errors for *fin* = 8 kHz.

#### *5.3. Mode C*

Measurement results for *fin* = 2.048 MHz are shown in Figure 13. For *fin* = 2.048 MHz, *AT*<sup>1</sup> and *AT*<sup>2</sup> are both set to 16 to achieve the largest *AT* of 256. However, *AT*<sup>1</sup> of 15.9 and *AT*<sup>2</sup> of 15.9 are obtained, and these values are substituted to Equation (10) to derive *Tb* using output code. The input-output characteristic of the TDC is shown in Figure 13a, where the horizontal axis, vertical axis, and the solid line are as described in Figure 11a. Figure 13b presents the phase error calculated from the digital

output code as a function of the actual phase injected at the input. The input phase is varied with a step size of 0.07◦, which corresponds to 0.1 ns. The peak positive phase error is 1.123◦, and the peak negative phase error is −1.846◦, resulting in the peak-to-peak phase error of 2.969◦. This phase error is beyond the target quantization error of 0.088◦ and target phase error of 1◦. The error analysis for the mode-C operation is presented in the next sub-section with a summary of the measurement results.

**Figure 13.** (**a**) Measured input-output characteristic of TDC, and (**b**) the maximum positive phase error for *fin* = 2.048 MHz.

#### *5.4. Error Analysis*

The peak-to-peak phase error and corresponding time error for *fin* from 1 kHz to 2.048 MHz are described in Figure 14. The peak-to-peak phase error is proportional to *fin* and exceeds 1◦ for only when *fin* = 1.024 MHz and *fin* = 2.048 MHz.

**Figure 14.** Peak-to-peak phase error and corresponding time error for *fin* from 1 kHz to 2.048 MHz.

Table 4 summarizes the exact values of the peak-to-peak phase error and corresponding time error as a function of *fin*. It also shows the values of *AT*<sup>1</sup> and *AT*<sup>2</sup> set for the measurement. Although *AT*<sup>2</sup> increases, the corresponding time error does not decrease below 1.06 ns.


**Table 4.** Peak-to-peak phase error and corresponding time error in mode C.

These extra errors would come from the uncertainty of comparator operation in time interpolators. The schematic of comparators and the uncertainty caused by the comparator operation during time interpolation are shown in Figure 15a,b, respectively. The comparators are designed by cascading two self-biased inverters as in [21,22].

**Figure 15.** (**a**) Schematic of comparators and (**b**) the uncertainty caused by comparators during time interpolation.

As shown in Figure 15b, if there is a voltage-domain uncertainty of Δ*vcomp* when *v*1(*t*) and *v*2(*t*) cross each other, Δ*vcomp* causes a time-domain uncertainty of Δ*tcomp*, which is given by:

$$
\Delta t\_{comp} = \Delta v\_{comp} \frac{\mathbf{C}\_{INT}}{I\_{INT}}.\tag{17}
$$

Therefore, Δ*vcomp* should be minimized in order to reduce Δ*tcomp* and hence extra time errors. The finite resolution and noise of the comparator would cause the uncertainty in the voltage domain, which, in turn, is translated into the uncertainty in the time domain.

The resolution of the comparator (Δ*vmin,comp*), which means the minimum input difference that saturates the output, is expressed as follows [23]:

$$
\Delta v\_{\rm min,comp} = \frac{V\_{\rm OH} - V\_{\rm OL,}}{A\_{\rm r0}},
\tag{18}
$$

where *Av*<sup>0</sup> is the open-loop gain of the comparator, *VOH* is the output voltage when the output is high, and *VOL* is the output voltage when the output is low. *VOH* and *VOL* should be large and small enough, respectively, so that the following digital logic can distinguish binary states. That is, when the transient behavior of *v*1(*t*) and *v*2(*t*) is not fast enough or *Av*<sup>0</sup> is not sufficiently large, the comparator suffers from a substantial uncertainty in time domain (Δ*tcomp*) because it will take relatively longer time for the following digital logic to determine binary states.

Considering that *Tf*<sup>1</sup> and *Tf*<sup>2</sup> vary within the range from *Tclk* to 2*Tclk,* the crossing point of *v*1(*t*) and *v*2(*t*) in Figure 15b falls within the voltage range from 0.9 V to 1.4 V. In this voltage range, *Av*<sup>0</sup> varies between 41.8 dB and 58.0 dB depending on the voltage level where *v*1(*t*) and *v*2(*t*) intersect. From *Av*<sup>0</sup> = 41.8 dB and supply voltage of 2.5 V, Δ*vmin,comp* is about 20.3 mV. For *fin* = 128 kHz with *AT*<sup>1</sup> = 15.9 and *AT*<sup>2</sup> = 4.05, Δ*tcomp* in the first stage caused by Δ*vmin,comp* is calculated as about 14.6 ns by substituting *CINT* = 28.8 pF and *IINT* = 40 μA into Equation (17). This Δ*tcomp* in the first fine stage is divided by *AT*<sup>1</sup> after being quantized by the fine counter. Therefore, the fabricated TDC could not achieve the time error below 0.92 ns.

The noise of comparator would become another source of uncertainty. The input-referred noise voltage of the differential-to-single-ended self-biased inverter in Figure 15a is expressed as follows [24]:

$$\overline{V\_{n,inv}}^2(f) = \left[\frac{1}{\mathcal{W}\_PL\_P} + \frac{1}{\mathcal{W}\_NL\_N}\right] \cdot \frac{2K}{f \cdot \mathbb{C}\_{OX}} + \frac{8kT\gamma}{\mathcal{g}\_{m,N} + \mathcal{g}\_{m,P}},\tag{19}$$

where *WP* and *LP* are the width and length of the input PMOS transistor, respectively, while *WN* and *LN* are the width and length of the input NMOS transistor, respectively. *K* is the process-dependent flicker noise constant. *gm,N* and *gm,P* are the transconductances of the NMOS and PMOS input transistors, respectively. The input-referred noise of the fully differential self-biased inverter is also given by Equation (19).

Since the noise of the first stage is dominant compared to that of the second stage and the 1/f noise can be ignored because of the wide bandwidth of the comparator, the input-referred noise voltage of the comparator can be approximated as follows:

$$\overline{\left|V\_{n,comp}\right|^2(f)} \approx \frac{8kT\gamma}{\mathcal{g}\_{m,N} + \mathcal{g}\_{m,P}}.\tag{20}$$

When *T* = 300 K, γ = 1, and noise bandwidth = 100 MHz, the input-referred noise of the comparator is about 1.8 mVrms, 180 μVrms, and 18 μVrms for *gm,N* + *gm,P* = 1 μS, *gm,N* + *gm,P* = 10 μS, *gm,N* + *gm,P* = 100 μS, respectively. Since our TDC consumes enough current, the uncertainty due to the comparator noise is not significant in our design. However, if the bandwidth of the comparator is very large and *gm,N* + *gm,P* is small, considerable uncertainties may occur. For *fin* = 128 kHz with *AT*<sup>1</sup> = 15.9 and *AT*<sup>2</sup> = 4.05, the voltage-domain uncertainty of 1.8 mVrms causes Δ*tcomp* = 1.3 nsrms, which corresponds to the time error of 0.08 nsrms. In particular, it is important to ensure that the value of *gm,N* + *gm,P* is sufficiently large when the bandwidth of the comparator is wide.

Since the extra time errors are mainly due to the resolution of comparators, the errors would be mitigated if the comparators based on multi-stage amplifiers are used as in [15]. In such comparators, the optimum number of amplifier stages, *NOPT*, is expressed as follows [15]:

$$N\_{OPT} \approx 1.1 \times \ln\left(\frac{V\_{OH}}{\Delta v\_{\text{min,comp}}}\right) + 0.79.\tag{21}$$

By replacing the two-stage high-gain amplifiers with multiple stages of low-gain amplifiers, the improved Δ*tcomp* can be obtained as Δ*vmin,comp* is reduced.

Moreover, when *AT*<sup>2</sup> increases from 8 to 16, the time error increases rather than decreases. Therefore, another way of improving the extra time error is measuring the quantization error of the first stage without performing time interpolation of the second fine stage. In [19], we employed a chain delay line in the second fine stage instead of the time interpolator, and the results were verified by simulation. Since the mismatches between unit delay cells would occur, the proposed architecture needs to be verified by measurement.

#### *5.5. Performance Summary and Comparison*

Table 5 summarizes performances of the presented TDC, together with those of two polar demodulators and two TDCs, reported previously. In comparison with the TDC in [20] that consists of a coarse counter and a single-stage time interpolator with large *AT* of 250, our TDC offers lower complexity and shorter conversion time for achieving the same phase resolution, as analyzed in Section 4.3. Compared to the TDC presented in this manuscript, another kind of our TDC in [19] seems to achieve smaller phase error. However, the TDC in [19] has not yet been verified by measurement. Through our future work, the TDC in [19] will be fabricated and measured. The phase error performance of our TDC presented in this paper is competitive when compared with previously reported designs in [15,17].


**Table 5.** Performance summary and comparison.

\* Total power consumption or size of entire polar demodulator for EIS system.

#### **6. Conclusions**

A reconfigurable time-to-digital converter (TDC) used to quantize the phase of impedance in electrical impedance spectroscopy (EIS) is introduced in this manuscript and verified through the fabricated IC. This TDC adopts a coarse counter to have a wide input-time range and cascaded time interpolators to improve resolution in the high-frequency analysis without increasing counting clock speed. When the same large interpolation factor is assumed, the cascaded time interpolators have shorter measurement time and smaller chip area than a single-stage time interpolator. The reconfigurable time interpolation factor maintains phase resolution within an appropriate level while providing reasonable measurement time. The fabricated TDC achieves the peak-to-peak phase error of under 0.72◦ for the input frequency range from 1 kHz to 512 kHz and the peak-to-peak phase error of 2.70◦ when it covers up to 2.048 MHz, demonstrating competitive performances in comparison with previously reported designs. Two precision improvement methods are also proposed: revision of the comparator, and revision of the second fine stage. As future work, we plan to fabricate the TDC that uses chain delay lines in the second fine stage and compare it with the TDC based on cascaded time interpolators.

**Author Contributions:** S.S., S.-J.K., and J.-H.P. implemented and measured the IC. S.S. and Y.J. analyzed the measurement results and wrote the draft of the manuscript through E.L. and J.K.'s editing and discussion. H.-J.Y. and M.J. helped in setting the target specification. S.-J.K. is the corresponding author, reviewed and edited this manuscript through discussion with H.-J.Y. and M.J. All authors discussed the results and commented on the manuscript. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was supported in part by Basic Science Research Program under grant number NRF-2018R1A6A3A01013018 and BK21 plus program through the National Research Foundation (NRF) of Korea funded by the Ministry of Education. In addition, this research was supported in part by the Convergence Technology Development Program for Bionic Arm (2017M3C1B2085296) through NRF of Korea funded by the Ministry of Science & ICT.

**Acknowledgments:** The EDA tool was supported by the IC Design Education Center (IDEC), Korea.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


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