**5. Conclusions**

We proposed a 3-D synapse array architecture based on a CTF memory device. To resolve the drawback of the previous version of the architecture, a ground select decoder was newly added. Also, we introduced the ISPP scheme to improve the linearity of the conductance modulation. The characteristics of synaptic weight modulation was characterized using a TCAD device simulation. In addition, we demonstrated the feasibility of the proposed architecture for neuromorphic system applications through a MATLAB simulation for the MNIST pattern recognition. The proposed 3-D synapse array architecture that exhibits a compact chip configuration and a high-integration ability will be a promising technology that can realize hardware-based neuromorphic systems.

**Author Contributions:** H.-S.C. and Y.K. designed the architecture design and wrote the manuscript. Y.J.P. performed the device simulations. Y.K. confirmed the validities of the designed architecture and simulated synaptic operation. J.-H.L. conceived and developed the various types of 3-D synapse structures, initiated the overall research project. All authors have read and agreed to the published version of the manuscript.

**Funding:** This work was supported by the 2019 Research Fund of the University of Seoul for Yoon Kim. Also, this work was supported by the MOTIE (Ministry of Trade, Industry & Energy (10080583) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device for Jong-Ho Lee.

**Conflicts of Interest:** The authors declare no conflict of interest.
