**3-D Synapse Array Architecture Based on Charge-Trap Flash Memory for Neuromorphic Application**

#### **Hyun-Seok Choi <sup>1</sup> , Yu Jeong Park <sup>2</sup> , Jong-Ho Lee <sup>3</sup> and Yoon Kim 1,\***


Received: 29 November 2019; Accepted: 29 December 2019; Published: 30 December 2019

**Abstract:** In order to address a fundamental bottleneck of conventional digital computers, there is recently a tremendous upsurge of investigations on hardware-based neuromorphic systems. To emulate the functionalities of artificial neural networks, various synaptic devices and their 2-D cross-point array structures have been proposed. In our previous work, we proposed the 3-D synapse array architecture based on a charge-trap flash (CTF) memory. It has the advantages of high-density integration of 3-D stacking technology and excellent reliability characteristics of mature CTF device technology. This paper examines some issues of the 3-D synapse array architecture. Also, we propose an improved structure and programming method compared to the previous work. The synaptic characteristics of the proposed method are closely examined and validated through a technology computer-aided design (TCAD) device simulation and a system-level simulation for the pattern recognition task. The proposed technology will be the promising solution for high-performance and high-reliability of neuromorphic hardware systems.

**Keywords:** 3-D neuromorphic system; 3-D stacked synapse array; charge-trap flash synapse
