**1. Introduction**

Neuromorphic systems have been attracting much attention for next-generation computing systems to overcome the von Neumann architecture [1–5]. The term "neuromorphic" refers to an artificial neural system that mimics neurons and synapses of the biological nervous system [3]. A neuron generates a spike when a membrane potential which is the result of the spatial and temporal summation of the signal received from the pre-neuron exceeds a threshold, and the generated spike is transmitted to the post-neuron. A synapse refers to the junction between neurons, and each synapse has its own synaptic weight which is the connection strength between neurons [6]. In a neuromorphic system, synaptic weight can be represented by the conductance of synapse device.

The requirements of a synapse device to implement a neuromorphic system are as follows: small cell size, low-energy consumption, multi-level operations, symmetric and linear weight change, high endurance and complementary metal-oxide semiconductor (CMOS) compatibility [5]. Various memory devices, such as static random-access memories (SRAM) [7], resistive random-access memories (RRAM) [8], phase change memories (PCM) [9], floating gate- memories (FG-memory) [10] and charge-trap flash memories [11] have been proposed to implement the synapse operation. Among them, charge-trap flash (CTF) devices have good CMOS compatibility and excellent reliability [12–15].

In our previous work, we proposed a 3-D stacked synapse array based on a charge trap flash (CTF) device [11]. Three-dimensional stacking technology is currently used in the commercialized Not AND

(NAND) flash memory products for ultra-high density [14]. Similarly, a 3-D stacked synapse array has the advantage of chip-size reduction when implementing very-large-size artificial neural networks. Consequently, it has the potential to be a promising technology for implementing neuromorphic hardware systems. For the design of the 3-D stacked synapse array architecture, there are several issues. At the full array level, how to operate each layer selectively and how to efficiently form the metal interconnects with peripheral circuits are critical issues. At the device level, how to implement accurate synaptic weight levels with low energy consumption is an important issue. Especially, linear and symmetric synaptic weight (conductance) modulations are essential to improve the accuracy of neuromorphic hardware systems [1–4].

In this paper, we examine these issues and suggest two improvements in terms of an architecture design and a device operation method. The rest of the paper is structured as follows: Section 2 contains design methods based on the viewpoint of a full-chip architecture. In this section, we review the 3-D stacked synapse array structure developed in the previous work [11] and propose an improved version of the 3-D stacked synapse array architecture to solve the unwanted problem of the previous version. In Section 3, we propose an improved programming method to obtain linear and symmetric conductance changes. Using a pattern recognition application with the Modified National Institute of Standards and Technology (MNIST) database, we demonstrate the improvement of the proposed method.
