*3.4. Spike-Timing-Di*ff*erence Plasticity and Array Architecture*

Table 2 summarizes the bias conditions for the synaptic operations and the required energy consumption per the realizable synaptic event along with the calculated synaptic device density. In order to exactly calculate the energy consumption, the current is integrated with time and multiplied by voltage. In Table 2, the energy consumption was obtained in the case of maximum value to consider

the worst case. There are approximately 10<sup>15</sup> synapses in the brain, about 1% of them are activated at the same time, and the frequency of neuron spike is about 10 Hz [31–33]. On this bases, human brain consumes power of ~20 W, and 55% out of the total power is consumed by the action potential [34–37]. In other words, it is assumed that power of 11 W is consumed for the synaptic activities. The power consumption per biological synaptic event is derived to be 1.1 <sup>×</sup> <sup>10</sup>−<sup>12</sup> W. Considering that each synaptic event has a ~100 ms duration, the energy consumption per synaptic event is calculated to be about 10 fJ. For the inference operation, 20 ns of rising and falling times and 10 ns of pulse duration are schemed, and then, this time period is multiplied by the inference voltage of −0.1 V and the current depending on weight for calculation of the energy consumption. The energies required for respective synaptic operations are summarized in Table 2, and most of them are very close to those for the biological synapse. Potentiation operation increases the conductance of the synaptic device so that a relatively large energy consumption is required; however, the amount is still low. Owing to the low operation voltage and tunneling-based injection mechanism, maximum energy consumption of only 0.52 pJ is needed for a potentiation event. For a depression event, the trapped holes tunnel back to the channel, which necessitates a relatively high operation voltage on the gate 2. However, even in the worst case, the required energy consumption is much lower than that for a potentiation event. Although the energy consumption for individual potentiation or depression event can be higher than that for an inference operation, the energy for an inference event can be spanned over a large range depending on the conductance. With the help of low-power and high-speed operation capabilities, the proposed synaptic transistor requires only a femto-joule energy even after 40 potentiation pulses are applied. Assuming that a unit cell has a footprint of 158 nm by 150 nm, the density of synaptic device array is calculated to be 9.09 <sup>×</sup> <sup>10</sup><sup>9</sup> /cm<sup>2</sup> . Here, the critical dimensions of the designed device and the metal pitches in one of the most recent memory technologies have been considered [38], where the wordline (WL) and bitline (BL) pitches are 48 and 54 nm, respectively. activated at the same time, and the frequency of neuron spike is about 10 Hz [31–33]. On this bases, human brain consumes power of ~20 W, and 55% out of the total power is consumed by the action potential [34–37]. In other words, it is assumed that power of 11 W is consumed for the synaptic activities. The power consumption per biological synaptic event is derived to be 1.1×10−<sup>12</sup> W. Considering that each synaptic event has a ~100 ms duration, the energy consumption per synaptic event is calculated to be about 10 fJ. For the inference operation, 20 ns of rising and falling times and 10 ns of pulse duration are schemed, and then, this time period is multiplied by the inference voltage of -0.1 V and the current depending on weight for calculation of the energy consumption. The energies required for respective synaptic operations are summarized in Table 2, and most of them are very close to those for the biological synapse. Potentiation operation increases the conductance of the synaptic device so that a relatively large energy consumption is required; however, the amount is still low. Owing to the low operation voltage and tunneling-based injection mechanism, maximum energy consumption of only 0.52 pJ is needed for a potentiation event. For a depression event, the trapped holes tunnel back to the channel, which necessitates a relatively high operation voltage on the gate 2. However, even in the worst case, the required energy consumption is much lower than that for a potentiation event. Although the energy consumption for individual potentiation or depression event can be higher than that for an inference operation, the energy for an inference event can be spanned over a large range depending on the conductance. With the help of low-power and high-speed operation capabilities, the proposed synaptic transistor requires only a femto-joule energy even after 40 potentiation pulses are applied. Assuming that a unit cell has a footprint of 158 nm by 150 nm, the density of synaptic device array is calculated to be 9.09 × 10<sup>9</sup> /cm<sup>2</sup> . Here, the critical dimensions of the designed device and the metal pitches in one of the most recent memory technologies have been considered [38], where the wordline (WL) and bitline (BL) pitches are 48 and 54 nm, respectively.

*Electronics* **2019**, *8*, x FOR PEER REVIEW 9 of 12

characteristics under different interval time conditions for the same total number of potentiation pulses of 10. It is assured that a short enough time interval allows the synaptic device to enter the

Table 2 summarizes the bias conditions for the synaptic operations and the required energy consumption per the realizable synaptic event along with the calculated synaptic device density. In order to exactly calculate the energy consumption, the current is integrated with time and multiplied

consider the worst case. There are approximately 10<sup>15</sup> synapses in the brain, about 1% of them are

LTP states and modulate the electrical conductivity for learning.

*3.4. Spike-Timing-Difference Plasticity and Array Architecture*


**Table 2.** Energy consumption per realizable synaptic event and the calculated synapse density. **Table 2.** Energy consumption per realizable synaptic event and the calculated synapse density**.**

Furthermore, the spike-timing-dependent plasticity (STDP) characteristics have been obtained by adjusting the pulse profile and time difference as demonstrated in Figure 7. The inset describes the potentiation and depression pulse schemes in the STDP simulations. The spiking pulse has 950 ns of rising time and 100 ns falling time, respectively, and the positive and negative voltage peak is 0.72 V in magnitude. The pre-neuron is connected with drain, and the post-neuron is with gate 1 and gate 2. When a pre-neuron spike comes earlier than a post-neuron one, the synaptic transistor is potentiated since the holes generated by tunneling operation from channel to drain are stored in the nitride charge-trap layer, which improves the conductance of the device. In the reversed order, the Furthermore, the spike-timing-dependent plasticity (STDP) characteristics have been obtained by adjusting the pulse profile and time difference as demonstrated in Figure 7. The inset describes the potentiation and depression pulse schemes in the STDP simulations. The spiking pulse has 950 ns of rising time and 100 ns falling time, respectively, and the positive and negative voltage peak is 0.72 V in magnitude. The pre-neuron is connected with drain, and the post-neuron is with gate 1 and gate 2. When a pre-neuron spike comes earlier than a post-neuron one, the synaptic transistor is potentiated since the holes generated by tunneling operation from channel to drain are stored in the nitride charge-trap layer, which improves the conductance of the device. In the reversed order, the device is depressed owing to ejection of the trapped holes out of the nitride layer. When the timing difference between pre- and post-neuron spikes is larger than 900 ns, the conductance of the device is not changed but left as the initial value, which indicates that two neurons are not so closely correlated, and there is neither potentiation nor depression. It is noticeable that the synaptic transistor has a large current difference for the different spike timing, which substantially reduces the complexity of the sensing circuits and enhances the system reliability. Figure 8 demonstrates a presumable array architecture with the designed synaptic transistor for a hardware-driven neuromorphic system.

neuromorphic system.

neuromorphic system.

nitride charge-trap layer, which improves the conductance of the device. In the reversed order, the device is depressed owing to ejection of the trapped holes out of the nitride layer. When the timing difference between pre- and post-neuron spikes is larger than 900 ns, the conductance of the device is not changed but left as the initial value, which indicates that two neurons are not so closely correlated, and there is neither potentiation nor depression. It is noticeable that the synaptic transistor has a large current difference for the different spike timing, which substantially reduces the complexity of the sensing circuits and enhances the system reliability. Figure 8 demonstrates a

nitride charge-trap layer, which improves the conductance of the device. In the reversed order, the device is depressed owing to ejection of the trapped holes out of the nitride layer. When the timing difference between pre- and post-neuron spikes is larger than 900 ns, the conductance of the device is not changed but left as the initial value, which indicates that two neurons are not so closely correlated, and there is neither potentiation nor depression. It is noticeable that the synaptic transistor has a large current difference for the different spike timing, which substantially reduces the complexity of the sensing circuits and enhances the system reliability. Figure 8 demonstrates a

*Electronics* **2019**, *8*, x FOR PEER REVIEW 10 of 12

**Figure 7.** Spike-timing-dependent plasticity characteristic of the proposed synaptic device. The inset describes the potentiation and depression pulse schemes. **Figure 7.** Spike-timing-dependent plasticity characteristic of the proposed synaptic device. The inset describes the potentiation and depression pulse schemes. **Figure 7.** Spike-timing-dependent plasticity characteristic of the proposed synaptic device. The inset describes the potentiation and depression pulse schemes.

**Figure 8.** Array architecture with the proposed four-terminal synaptic transistor towards a highdensity and high-reliability hardware-driven neuromorphic system. **Figure 8.** Array architecture with the proposed four-terminal synaptic transistor towards a highdensity and high-reliability hardware-driven neuromorphic system. **Figure 8.** Array architecture with the proposed four-terminal synaptic transistor towards a high-density and high-reliability hardware-driven neuromorphic system.

### **4. Conclusions 4. Conclusions**

**4. Conclusions** In this work, a synaptic transistor having SiGe quantum well and nitride charge-trap layer was schemed and characterized by a series of rigorous simulation works. The synaptic device has successfully demonstrated the synaptic operations including STP, LTP, and inference with high energy efficiency not exceeding a two femto-joules in the worst case. Further, spike-timingdependent plasticity was verified through a properly adjusted pulse scheme. A presumable array In this work, a synaptic transistor having SiGe quantum well and nitride charge-trap layer was schemed and characterized by a series of rigorous simulation works. The synaptic device has successfully demonstrated the synaptic operations including STP, LTP, and inference with high energy efficiency not exceeding a two femto-joules in the worst case. Further, spike-timingdependent plasticity was verified through a properly adjusted pulse scheme. A presumable array In this work, a synaptic transistor having SiGe quantum well and nitride charge-trap layer was schemed and characterized by a series of rigorous simulation works. The synaptic device has successfully demonstrated the synaptic operations including STP, LTP, and inference with high energy efficiency not exceeding a two femto-joules in the worst case. Further, spike-timing-dependent plasticity was verified through a properly adjusted pulse scheme. A presumable array architecture is also conceived with the four-terminal synaptic device, and its density was calculated to be 9.09 <sup>×</sup> <sup>10</sup><sup>9</sup> /cm<sup>2</sup> based on the interconnect schemes in the 18-nm DRAM technology node.

**Author Contributions:** E.Y. and S.C. conceived the device structure and wrote the manuscript. E.Y. performed the device simulations and evaluated the device scalability and array density. S.C. approved the simulation results in confirmation of the biological analogies. B.-G.P. conceived and developed the various types of hardware-driven neuromorphic systems, initiated the overall research project, and confirmed the validities of the simulated synaptic operations towards the artificial spike neural network.

**Funding:** This work was supported by Nano·Material Technology Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (MSIT) (Grant No. NRF-2016M3A7B4910348) and by Mid-Career Researcher Program through NRF funded by the MSIT (Grant No. NRF-2017R1A2B2011570).

**Conflicts of Interest:** The authors declare no conflict of interest.
