**1. Introduction**

Conventional computer architectures are mostly based on von Neumann's architecture since modern computer systems have been represented by electronic delay storage automatic calculator (EDSAC)—since 1949. The architecture consists of two main parts of processing and memory units performing the processes in the series' manner through single instruction and single data. Due to the physically differentiated system architecture, memory bus has been considered to be a bottleneck in determining the system processing speed, which is getting even worse in these days when big data are more increasingly demanded. In order to overcome this limit in the von Neumann computer architecture parallel processing capability of the artificial intelligent, of parallel processing with tremendous amount of data, contributions have been dedicated by the software-based neural networks. Although unimaginably many kinds of tasks have been accomplished by the software-driven technology in the given hardware system, with great resemblance to the way the human brain works, there is much room for enhancement of energy efficiency, which is the incomparable essence of biological system.

As a solution for the energy consumption issue, spiking neural network (SNN) is considered as one of the powerful schemes inspired by the biological system, which requires fundamental hardware innovation with synaptic transistors and neuron circuits [1,2]. Intellectual functions in human brain are determined by the strength and accuracy in connectivity among neurons. In human brain, there are a few tens of quadrillions of synapses and, through the synapses, humans become able to recognize, calculate, memorize, and learn. Thus, for hardware-driven neuromorphic systems to achieve more human-brain like computing efficiency, the synaptic device is required to have high scalability, multi-level weight adjustability, large inference margin, strong tolerance, and ultra-low energy consumption. Moreover, in order to gain higher access to the chip-level production lowering time and cost barriers, the SNN should be realized on the Si platform being helped by the mature Si processing technology. energy consumption. Moreover, in order to gain higher access to the chip-level production lowering time and cost barriers, the SNN should be realized on the Si platform being helped by the mature Si processing technology. A number of synaptic devices have been proposed with memristors such as resistive-switching

scalability, multi-level weight adjustability, large inference margin, strong tolerance, and ultra-low

*Electronics* **2019**, *8*, x FOR PEER REVIEW 2 of 12

A number of synaptic devices have been proposed with memristors such as resistive-switching random-access memory (ReRAM) and phase-change random-access memory (PcRAM). They are considered to be good candidates for the electronic synapse owing to their high structure simplicity and volume scalability, mainly by their great geometrical resemblance to the two-terminal structure of the biological synapse and energy efficiency [3–6]. Although memristors have these advantages, there is still room for further improving the rather low endurance and reproducibility and for enhancing the completeness in realizing the biological synaptic functions. Moreover, some of the existing memristor devices are not in consideration of Si processing compatibility. The simple structure requires functional compensation by additional devices or circuits, which might cause increased overhead in the SNN architecture [7–9]. In this work, a novel synaptic device has been designed, which has SiGe quantum well (QW) and Si3N<sup>4</sup> charge-trap layer to realize the short-term potentiation (STP) and long-term potentiation (LTP), respectively, and its synaptic operations have been validated through technology computer-aided design (TCAD) device simulation, Silvaco Atlas [10]. Although the designed synaptic device is in a more complicated structure with a larger number of terminals compared with the two-terminal synaptic devices, it is capable of complementing the aforementioned weak points of the memristors, with an emphasis on higher energy efficiency and Si processing compatible materials. While most of the memristor synaptic devices have shown energy consumption higher than 1 pJ [11], the largest energy consumption required for a potentiation event has been demonstrated to be 1.51 fJ. random-access memory (ReRAM) and phase-change random-access memory (PcRAM). They are considered to be good candidates for the electronic synapse owing to their high structure simplicity and volume scalability, mainly by their great geometrical resemblance to the two-terminal structure of the biological synapse and energy efficiency [3–6]. Although memristors have these advantages, there is still room for further improving the rather low endurance and reproducibility and for enhancing the completeness in realizing the biological synaptic functions. Moreover, some of the existing memristor devices are not in consideration of Si processing compatibility. The simple structure requires functional compensation by additional devices or circuits, which might cause increased overhead in the SNN architecture [7–9]. In this work, a novel synaptic device has been designed, which has SiGe quantum well (QW) and Si3N<sup>4</sup> charge-trap layer to realize the short-term potentiation (STP) and long-term potentiation (LTP), respectively, and its synaptic operations have been validated through technology computer-aided design (TCAD) device simulation, Silvaco Atlas [10]. Although the designed synaptic device is in a more complicated structure with a larger number of terminals compared with the two-terminal synaptic devices, it is capable of complementing the aforementioned weak points of the memristors, with an emphasis on higher energy efficiency and Si processing compatible materials. While most of the memristor synaptic devices have shown energy consumption higher than 1 pJ [11], the largest energy consumption required for a potentiation event has been demonstrated to be 1.51 fJ.

#### **2. Device Structure and Design Strategies 2. Device Structure and Design Strategies**

More detailed explanations on the operation principles of the synaptic device and the models used in the device simulation along with the related physics are provided as follows. Figure 1 shows the schematic of the proposed synaptic device which has a *p* <sup>+</sup> SiGe layer at the drain-side channel and a charge-trap layer on the channel. More detailed explanations on the operation principles of the synaptic device and the models used in the device simulation along with the related physics are provided as follows. Figure 1 shows the schematic of the proposed synaptic device which has a *p* <sup>+</sup> SiGe layer at the drain-side channel and a charge-trap layer on the channel.

**Figure 1.** Schematic of the proposed synaptic device having an embedded SiGe quantum well and charge-storage layer for realizing the short-term and long-term plasticity, respectively. **Figure 1.** Schematic of the proposed synaptic device having an embedded SiGe quantum well and charge-storage layer for realizing the short-term and long-term plasticity, respectively.

As the number of potentiation pulses increases, the electrons in the SiGe valence band tunnel into the drain conduction band and fill the empty energy states. As a result, the holes generated in the SiGe layer are confined in the layer owing to a large valence-band offset (VBO) between Si and SiGe. The confined holes give an effect of elevating the hole potential energy and the probability of hole tunneling into the nitride charge-trap layer, which realizes the LTP operation.

Designing a synaptic device with high reliability is paramount in building up a hardware architecture for the neuromorphic system. In order to demonstrate the device operation more accurately, multiple models are simultaneously activated. The mathematical and physical backgrounds of the used models can be glanced as follows. One of the essential differential equations used in the TCAD simulation is Poisson equation in Equation (1).

$$\operatorname{div}(\varepsilon \nabla \psi) = -\rho \tag{1}$$

Here, ε is the local electrical permittivity of the material, ψ is the electrostatic potential, and ρ is the volume charge density.

$$\frac{\partial \mathbf{n}}{\partial t} - \frac{1}{q} \text{div} \overrightarrow{\mathbf{J}\_{\mathbf{n}}} = \mathbf{G}\_{\mathbf{n}} - \mathbf{R}\_{\mathbf{n}} \tag{2}$$

Continuity equation in Equation (2) can be applied for obtaining the electron and hole current densities. *n*, *J*n, *G*n, and *R*<sup>n</sup> are concentration of mobile electrons, areal electron current density, generation rate of electron, and recombination rate of electron, respectively. *n* can be substituted with *p* for hole description. *q* is the magnitude of electron charge. Based on the above equations, various models are equipped for higher accuracy and reliable simulation results. For an inversion layer mobility model, Lombardi model was used, which is suitable to non-planar devices, with dependences on both parallel and vertical electric fields, doping concentration, and temperature. The underlying physics comes from Matthiessen's rule.

$$
\mu\_\mathrm{T}^{-1} = \mu\_\mathrm{AC}^{-1} + \mu\_\mathrm{b}^{-1} + \mu\_\mathrm{sr}^{-1} \tag{3}
$$

Here, µT, µAC, µb, and µsr indicate the total mobility, the surface mobility limited by scattering with acoustic phonons, the mobility limited by scattering with optical intervalley phonons, and the surface roughness factor, respectively.

$$f(E) = \frac{1}{1 + \exp\left(\frac{E}{kT\_{\rm L}}\right)}\tag{4}$$

For carrier statistics, Fermi–Dirac statistics was employed. In Equation (4), *f*(*E*) is the probability that an available electron state with energy *E* is occupied by an electron, *k* is Boltzmann constant, and *T*<sup>L</sup> is lattice temperature. Moreover, the model is useful for the proposed device to describe the STP-to-LTP transition. The accumulated holes in the SiGe quantum well, which should be at the Fermi distribution tail, have higher probabilities of injection into the charge-trap layer. Moreover, non-local band-to-band tunneling calculation method was adopted, which has higher accuracy than the several tunneling models given as default in the TCAD simulation. This is due to the fact that the proposed device has the degenerately doped SiGe channel and drain, and the method calculates the tunneling probabilities by considering not only both forward and reverse tunneling currents but also the spatial variation of energy band and generation/recombination rates as shown in Equations (5) and (6).

$$J(E) = \frac{q}{\pi\hbar} \iint T(E) [f\_{\rm I}(E + E\_{\rm T}) - f\_{\rm I}(E + E\_{\rm T})] \rho(E\_{\rm T}) dE dE\_{\rm T} \tag{5}$$

$$T(E) = \exp\left(-2\int\_{\chi\_{\text{start}}}^{\chi\_{\text{end}}} k(\mathbf{x})d\mathbf{x}\right) \tag{6}$$

Here, *J*(*E*) is the net current density for a carrier with longitudinal (*E*) and transverse energy (*E*T) under the assumption that the tunneling current is the result of bidirectional transfers of carriers across the junction. *f* <sup>l</sup> and *f*<sup>r</sup> are the Fermi–Dirac functions using the quasi-Fermi levels in the left-side and right-side materials of the respective junctions. ρ(*E*T) and *k*(*x*) represent the density of states corresponding to the transverse wavevector components and the wavevector at *x*. *T*(*E*) indicates the tunneling probability for a carrier having an energy of *E* from the Wentzel–Kramers–Brilluoin

(WKB) approximation. Moreover, Shockley–Read–Hall recombination model, impact-ionization model, and bandgap narrowing model have been used. The aforementioned models are reflected for all the regions, and the non-local band-to-band model was applied locally between SiGe and Si where the tunneling events actually take place. In order to demonstrate the charge-trapping mechanism of nitride, a macro model (DYNASONOS) was employed, which includes various transport mechanisms such as thermionic emission, Poole–Frenkel emission, direct tunneling model, Fowler–Nordheim (FN) tunneling, and hot carrier injection at the same time. These models for the gate current are automatically applied for the Si3N<sup>4</sup> layer and the regions in contact, which substantially affects the dynamics of the carriers moving into and out of the charge-trap layer. Without just using the default values given in the TCAD simulation package, the mobilities (µ) [12,13], saturation velocities (*v*sat) [14–19], bandgap energy (*E*g) [20], and electron affinity (χ) [21–27] of Si and SiGe have been fed into the device simulation [28]. This is because the SiGe layer, which stores holes, is considered as the important region for the synaptic operation. The values of the parameters are tabulated in Table 1.

**Table 1.** Parameters used in this work for Si and SiGe.


The SiGe layer is 50 nm long in the vertical direction and 50 nm wide (channel thickness = 50 nm). The *p*-type Si region is 100 nm long and the physical gate length (*L*g) is 100 nm. Thus, whole SiGe region and the half of Si region are brought under the gate. In order to confine the holes generated over the potentiation process in the SiGe quantum well (QW) effectively, Ge fraction should be optimally controlled for a large valence-band offset (VBO) and the Si/SiGe interface status in the epitaxy processing as well, which is fixed to 0.3 throughout the design work. The gate oxide thickness for the gate 1 is 3 nm. The storage node is made up of oxide/nitride/oxide = 2/4/6 nm between the channel and the gate 2. The doping concentrations of source and drain junctions are both *n* <sup>+</sup>-type 10<sup>20</sup> cm−<sup>3</sup> , and those of *p* <sup>+</sup> SiGe QW and *p*-type Si channel are 10<sup>18</sup> cm−<sup>3</sup> and 10<sup>16</sup> cm−<sup>3</sup> , respectively.
