*3.2. Validation of Short- and Long-Term Plasticities*

The proposed device has strong advantages particularly in energy-efficiency. There are many resources to make the device energy-efficient, such as introduction of SiGe QW, band-to-band tunneling mechanism, and STP characteristics. STP helps the device discriminate less important signals. Otherwise, when the weight of a synaptic device is changed at every input signal, the overall current over the synaptic device array would increase and large energy consumption is resulted.

*3.2. Validation of Short- and Long-Term Plasticities*

current over the synaptic device array would increase and large energy consumption is resulted.

The proposed device has strong advantages particularly in energy-efficiency. There are many resources to make the device energy-efficient, such as introduction of SiGe QW, band-to-band tunneling mechanism, and STP characteristics. STP helps the device discriminate less important

**Figure 3.** Drain current and nitride-trapped charges vs. learning pulses. The training pulse has a 1-μs width and a 1-μs interval. **Figure 3.** Drain current and nitride-trapped charges vs. learning pulses. The training pulse has a 1-µs width and a 1-µs interval.

Figure 3 indicates the timing diagram of drain current (*I*D) and the amount of nitride-trapped charges as a function of time. The potentiation pulse is a set of (gate 1 voltage (*V*G1), gate 2 voltage (*V*G2), drain voltage (*V*DS) = (−0.2 V, −0.7 V, 0.55 V), and the hold bias is (*V*G1, *V*G2, *V*DS) = (−0.3 V, 0 V, 0 V). When a potentiation pulse is applied, holes are generated by band-to-band tunneling and confined in the SiGe layer. At the fourth pulse, *I*<sup>D</sup> rapidly increases since the number of holes in the SiGe exceeds a certain threshold value and induces a drastic injection into the nitride charge-trap layer as shown in Figure 3. The trapped holes lower the threshold voltage of the synaptic device and increase the channel conductance. Figure 4a shows the conduction-band edges obtained after different number of pulses are Figure 3 indicates the timing diagram of drain current (*I*D) and the amount of nitride-trapped charges as a function of time. The potentiation pulse is a set of (gate 1 voltage (*V*G1), gate 2 voltage (*V*G2), drain voltage (*V*DS) = (−0.2 V, −0.7 V, 0.55 V), and the hold bias is (*V*G1, *V*G2, *V*DS) = (−0.3 V, 0 V, 0 V). When a potentiation pulse is applied, holes are generated by band-to-band tunneling and confined in the SiGe layer. At the fourth pulse, *I*<sup>D</sup> rapidly increases since the number of holes in the SiGe exceeds a certain threshold value and induces a drastic injection into the nitride charge-trap layer as shown in Figure 3. The trapped holes lower the threshold voltage of the synaptic device and increase the channel conductance.

applied: 0, 1, 5, 10, 20, 30, 40, and 50 pulses. The insets depict the three-dimensional (3-D) contours of conduction band edge surfaces at the initial state and at a state after 30 pulses are applied, respectively. The line spectra representing the conduction band edges have been extracted from the channel vicinity of *V*G2 where the main current conduction path is formed. It is revealed that most of potential barrier lowering takes place by the holes in the SiGe region. Figure 4b plots the electron current density contours at the inference operations after different number of potentiation pulses: 1, 5, and 30 pulses. The inference process in the biological nervous system is analogous to the read operation in the memory array, and the electrical disturbance of the current data should be avoided. For the nondestructive inference, a voltage scheme was found to be *V*GS1 = *V*DS = −0.1 V. As the number of pulses increases, more holes are populated in the charge-trap layer, and the potential barrier seen by the source electrons is lowered. Consequently, higher *I*<sup>D</sup> is read at the same inference voltage as can be confirmed by Figure 4b. Figure 5a demonstrates the transient characteristics of the synaptic transistor after different Figure 4a shows the conduction-band edges obtained after different number of pulses are applied: 0, 1, 5, 10, 20, 30, 40, and 50 pulses. The insets depict the three-dimensional (3-D) contours of conduction band edge surfaces at the initial state and at a state after 30 pulses are applied, respectively. The line spectra representing the conduction band edges have been extracted from the channel vicinity of *V*G2 where the main current conduction path is formed. It is revealed that most of potential barrier lowering takes place by the holes in the SiGe region. Figure 4b plots the electron current density contours at the inference operations after different number of potentiation pulses: 1, 5, and 30 pulses. The inference process in the biological nervous system is analogous to the read operation in the memory array, and the electrical disturbance of the current data should be avoided. For the nondestructive inference, a voltage scheme was found to be *V*GS1 = *V*DS = −0.1 V. As the number of pulses increases, more holes are populated in the charge-trap layer, and the potential barrier seen by the source electrons is lowered. Consequently, higher *I*<sup>D</sup> is read at the same inference voltage as can be confirmed by Figure 4b.

number of potentiation pulses. Through Figure 5a, it is confirmed that the proposed synaptic device is capable of both STP and LTP functions. The STP increases the channel conductivity for a short time, and the effect is diminished as time passes. As a result, *I*<sup>D</sup> is eventually converged to the initial-state current level: The starting point can be varied but the final *I*<sup>D</sup> is the same in the STP operation. On the other hand, *I*<sup>D</sup> higher than the initial low current is consistently retained for up to 10<sup>4</sup> sec or more Figure 5a demonstrates the transient characteristics of the synaptic transistor after different number of potentiation pulses. Through Figure 5a, it is confirmed that the proposed synaptic device is capable of both STP and LTP functions. The STP increases the channel conductivity for a short time, and the effect is diminished as time passes. As a result, *I*<sup>D</sup> is eventually converged to the initial-state current level: The starting point can be varied but the final *I*<sup>D</sup> is the same in the STP operation. On the other hand, *I*<sup>D</sup> higher than the initial low current is consistently retained for up to 10<sup>4</sup> sec or more

When the synaptic device is brought into the LTP states. Here, it is notable that a large current difference takes place between states as the number of potentiation pulses increases. In Figure 5b, the actual transfer curves of the synaptic device obtained after the corresponding different number of pulses are applied in Figure 5a are depicted. In the STP operation, there is steady-state threshold voltage (*V*th) shift. Once the device is in the LTP condition, a larger number of pulses lead to lower *V*th without a temporal change. This is because the trapped holes in the nitride layer result in the inversion layer under the gate 2 at the inference bias. In Figure 5b, the proposed device demonstrates the large current ratio between high and low conductance states, which can be a beneficial aspect of a

fully-Si electron device. The successfully suppressed leakage current stems from the high potential barrier constructed by the large VBO. If there is only STP, there would be no *V*th shift. Only in the LTP condition, *V*th begins the left-shifts due to the holes trapped in the nitride layer. It is shown that *V*th of the proposed synaptic device is shifted by 1.5 V after 40 potentiation pulses are applied. *Electronics* **2019**, *8*, x FOR PEER REVIEW 7 of 12 *Electronics* **2019**, *8*, x FOR PEER REVIEW 7 of 12

**Figure 4.** Analysis on potentiation operation. (**a**) Change in the conduction band surface with regard to the number of potentiation pulses: initial (left) and after 30 pulses (right). Line traces of the conduction band edges in the vicinity of gate 2. (**b**) Electron current densities after 1, 5, and 30 potentiation pulses applied to the synaptic device. **Figure 4.** Analysis on potentiation operation. (**a**) Change in the conduction band surface with regard to the number of potentiation pulses: initial (left) and after 30 pulses (right). Line traces of the conduction band edges in the vicinity of gate 2. (**b**) Electron current densities after 1, 5, and 30 potentiation pulses applied to the synaptic device. **Figure 4.** Analysis on potentiation operation. (**a**) Change in the conduction band surface with regard to the number of potentiation pulses: initial (left) and after 30 pulses (right). Line traces of the conduction band edges in the vicinity of gate 2. (**b**) Electron current densities after 1, 5, and 30 potentiation pulses applied to the synaptic device.

**Figure 5.** Electrical characteristics of the proposed synaptic device after different number of pulses: from 0 to 50 pulses. (**a**) Transient characteristics under read bias condition. (**b**) Transfer characteristics. **Figure 5.** Electrical characteristics of the proposed synaptic device after different number of pulses: from 0 to 50 pulses. (**a**) Transient characteristics under read bias condition. (**b**) Transfer characteristics. **Figure 5.** Electrical characteristics of the proposed synaptic device after different number of pulses: from 0 to 50 pulses. (**a**) Transient characteristics under read bias condition. (**b**) Transfer characteristics.

When the synaptic device is brought into the LTP states. Here, it is notable that a large current

When the synaptic device is brought into the LTP states. Here, it is notable that a large current

#### *3.3. Interval Time E*ff*ects on STP and LTP Characteristics* the proposed synaptic device is shifted by 1.5 V after 40 potentiation pulses are applied.

Figure 6a–c shows how the transition from STP to LTP is made. As shown in Figure 6a, increasing the interval time between potentiation pulses makes it difficult to get into the LTP state. The holes in the SiGe layer temporarily generated by the pulses vanish by recombination and diffusion, which does not provide the boosting effect in band-to-band tunneling into the charge-trap layer. With the interval time of 1 ms, the synaptic device is not allowed to move to the LTP states as shown in Figure 6a and confirmed by Figure 6b. Figure 6b demonstrates the transient and DC characteristics under different interval time conditions for the same total number of potentiation pulses of 10. It is assured that a short enough time interval allows the synaptic device to enter the LTP states and modulate the electrical conductivity for learning. *3.3. Interval Time Effects on STP and LTP Characteristics* Figure 6a–c shows how the transition from STP to LTP is made. As shown in Figure 6a, increasing the interval time between potentiation pulses makes it difficult to get into the LTP state. The holes in the SiGe layer temporarily generated by the pulses vanish by recombination and diffusion, which does not provide the boosting effect in band-to-band tunneling into the charge-trap layer. With the interval time of 1 ms, the synaptic device is not allowed to move to the LTP states as shown in Figure 6a and confirmed by Figure 6b. Figure 6b demonstrates the transient and DC characteristics under different interval time conditions for the same total number of potentiation pulses of 10. It is assured that a short enough time interval allows the synaptic device to enter the LTP states and modulate the electrical conductivity for learning.

*Electronics* **2019**, *8*, x FOR PEER REVIEW 8 of 12

pulses are applied in Figure 5a are depicted. In the STP operation, there is steady-state threshold voltage (*V*th) shift. Once the device is in the LTP condition, a larger number of pulses lead to lower *V*th without a temporal change. This is because the trapped holes in the nitride layer result in the inversion layer under the gate 2 at the inference bias. In Figure 5b, the proposed device demonstrates the large current ratio between high and low conductance states, which can be a beneficial aspect of

condition, *V*th begins the left-shifts due to the holes trapped in the nitride layer. It is shown that *V*th of

**Figure 6.** Operation characteristics depending on the number of pulse interval times. (**a**) Current changes with different pulse interval times: 10 µs, 100 µs, and 1 ms. (**b**) Transient (left) and DC sweep (right) characteristics with different interval times. For a shorter interval time at a given number of potentiation pulses, the saturation current increases and the *V*th shift gets wider.
