*4.1. Synthetic Subset*

The Synthetic subset is named in relation to its load shaping being defined by a controller that switches the loads ON or OFF in a programmed pattern. To collect data for the synthetic subset, a single-phase 1 kW jig was designed and built according to the requirements of Section 3.

#### 4.1.1. Data Collecting Jig Hardware Design

The Jig block diagram is presented in Figure 1. The protection block consists of an emergency stop button, a circuit breaker, and a fast fuse. The current sensors, for the operator's protection sake, are connected in the neutral line, while the loads are switched in the phase line. Two current sensors, shunt, and hall, are used to compare the hall performance to the shunt, in loads with high derivatives of current as well as asymmetrical loads. To sense the AC mains voltage, a resistor divider is used. An oscilloscope provides a performance benchmark for the current and voltage sensors.

**Figure 1.** Block diagram of data collecting jig. adapted from [9].

The control module senses the AC mains zero crossing; therefore, a precise timing is achieved in every power ON or OFF event. The load power control is provided by a relay in parallel to a TRIAC, each with its independent driver module. The TRIAC provides precise power switching at a giving point of the AC mains cycle while the relay operates as a conventional switch. As the relay presents a delay between the relay driver signal and the actual opening/closing of the relay contacts, a power sensor provides a precise indication of when a load is actually powered. It is possible to trigger a load only with the relay or the TRIAC, as well as with both simultaneously. Triggering only the TRIAC makes it possible to obtain a dimmer effect on the load(s).

The signal conditioning module has low pass filters and differential amplifiers so that the sensors' signals are adequate to the embedded module analog to digital converter. The embedded module uses a National Instruments MyRio [39] board with the following functionalities: A/D conversion, load event registering obtained by the trigger signal sent by the control module, and dataset storage in a non-volatile storage device (such as a USB flash disk).

Figure 2 shows the synthetic LIT-Dataset Jig. An aluminum structure and an acrylic panel were used to support the jig's components. The wiring is inside PVC ducts. On the left are the power connection, auxiliary power supplies, and the sockets for the jig's equipment power supplies. The protection board is on the left side. The eight sockets for the monitored loads are on the top right, and below are the relays and TRIACs, and the control and driver boards. In the center of the board are the voltage and current sensors. On the bottom right are the conditioning boards and the MyRio Embedded Module.

**Figure 2.** Data collecting jig.

#### 4.1.2. Data Collecting Jig Software Architecture

The embedded module block diagram is presented in Figure 3. The signal conditioning board delivers the conditioned signals from the voltage and current sensors to the MyRio module. The MyRio FPGA implements an acquisition loop that operates at 15,360 Hz, as per DSReq 6 s. On every cycle of this loop, a set of three 12-bit samples is obtained, corresponding to the A/D conversions. A GPS receiver sends a Pulse Per Second (PPS) signal, which is grouped in a data tuple with the sample signals, indicating precise 1 s periods, typically less than 100 ns jitter. An 8-bit ID and an event notification signal are also grouped in this data tuple to indicate the samples when the control module commands a load event.

The real-time application runs into the CORTEX A9 processor, composed of three NI LabView timed loops, which act as independent periodic threads. The tuple is sent by the FPGA to the real-time application via DMA. An external GPS receiver sends the NMEA strings to the GPS Parsing Timed Loop. The absolute time fields are decoded from a specific NMEA message (GPRMC) and converted to a 32-bit time-stamp value. The Sample Processing Timed Loop uses this 32-bit time-stamp, together with the event information contained in the tuple received from the FPGA, to store the time-stamped events into the event annotation file. This loop also shifts each 12-bit sample of the tuple one bit to the left and adds the PPS signal as its least significant bit, thus, allowing a precise identification of the samples during which the 1 s transitions occurred. The resulting 13-bit sample data is sent to the Storage Timed Loop via an internal FIFO, which stores the data for each of the sample inputs as a separate field of a NI Technical Data Management Streaming (TDMS) file into the USB flash disk attached to the MyRIO. The TDMS file may be processed by a PC application, to add its collected data to the LIT-Dataset.

**Figure 3.** Block diagram of data acquisition using the MyRio device. Adapted from [9].
