*Article* **Double Sliding-Surface Multiloop Control Reducing Semiconductor Voltage Stress on the Boost Inverter**

#### **Oswaldo López-Santos 1,\* and Germain García 2**


Received: 18 May 2020; Accepted: 13 July 2020; Published: 17 July 2020

**Abstract:** Sliding-mode control (SMC) has been successfully applied to boost inverters, which solves the tracking problem of imposing sinusoidal behavior to the output voltage despite the coupled or decoupled operation of both boost cells in the converter. Most of the results reported in the literature were obtained using the conventional cascade-control structure involving outer loops that generate references for one or two sliding surfaces defined using linear combinations of inductor currents and capacitor voltages. As expected, all proposed methods share the inherent robustness and insensitivity to the uncertainties of SMC, which are the reasons why one of the few comparison criteria between them is the simplicity of their implementation that is evaluated according to the required measurements and mathematical operations. Furthermore, the slight differences between the obtained dynamic performances do not allow a clear distinction of the best solution. This study presents a new SMC approach applied to a boost inverter in which two boost cells are independently commutated. Each of these boost cells integrates an outer loop, enforcing the tracking of harmonic-enriched waveforms to the capacitor voltage. Although this approach increases by two the number of measurements and requires multiloop controllers, it allows effective alleviation of the semiconductor voltage stress by reducing the required voltage gain. A complete analytical study using harmonic balance technique allows deducing a simplified model allowing to obtain a PI controller valid into to the whole set of operation conditions. The several simulation results completely verified the potential of the control proposal and the accuracy of the employed methods.

**Keywords:** boost inverter; harmonic balance; sliding mode control

#### **1. Introduction**

The DC–AC boost converter, boost inverter, differential boost inverter or dual boost inverter, as it has been called by different authors in the literature, was introduced by Caceres and Barbi in the 1990s [1]. The potential that allowed this converter to attract the interest of researchers in the following decades was its ability to overcome the most restrictive limitations of the conventional and well-established full-bridge inverter. This is mainly related to the possibility of generating AC voltages with amplitudes larger than the input DC voltage without requiring more than one conversion stage or increasing the number of power semiconductors. This interesting topology is composed of two identical cells using symmetrical bidirectional boost DC–DC converters that share a back-to-back or bridge connection and differentially provide the output voltage between their outputs. This feature is characterized by a reduced common-mode noise but can be affected by DC current circulation in the load if the bias component of the output voltage of the cells is not correctly equalized [2].

Although the aforementioned features of the boost inverter are very attractive, these can only be achieved by developing more complex controllers or applying more complex methods to synthesize the required controllers. Compared with its counterpart, i.e., the full-bridge inverter, the highly nonlinear dynamic behavior of the output voltage as a function of the operating duty cycle makes devising an effective control solution difficult. The higher the required gain to generate the output voltage is, the higher is the effect of nonlinearity on the dynamic behavior causing that linear controllers cannot guarantee a proper operation. Further, we need to mention that the approach performance based on linear control is directly affected by the non-minimum phase nature of the output voltage to control the transfer function of each boost cell.

Sliding-mode control (SMC) was practically the first approach in the reported literature applied to control a boost converter in the context of a stand-alone operation. In [1], Caceres and Barbi defined a sliding surface for each boost cell using a linear combination of current and voltage errors. Although the required voltage references were nothing more than two DC-biased sinusoidal waveforms with a 180◦ phase shift between them, the current references were difficult to synthesize because it depended on the input voltage and load current. Hence, the current-error component of the surfaces was obtained by measuring the high-frequency component of the inductor currents by assuming perfect tracking of the references in the stationary state. This approach was implemented using hysteresis comparators that then generated a variable switching frequency. This first proposal could be classified into a set of double-surface SMC (DS-SMC) approaches. A second method that employed SMC was introduced by Cortes et al. in [3] in which the control of both boost cells were correlated by complementarily coupling the commutation of the switches in the boost cells. In that work, a unique sliding surface was defined that involved the difference between the inductor currents and the proportional and integral actions that both operated under an output–voltage error. This second proposal, which could be classified as a single-surface SMC, was implemented using a single hysteresis comparator and required one less measurement because the voltage of the capacitors were not separately controlled. Furthermore, in the selected sliding surface, identifying the form of the well-known indirect control applied to regulate the output voltage of DC–DC converters was possible using an outer proportional–integral (PI) controller and a current inner loop. More recently, Flores-Bahamonde et al. have reemployed the same technique by preserving the coupled control action between the converter cells and applying an equivalent control technique to provide an analytical solution for synthesizing the outer voltage controller [4]. From the perspective of that work, the converter was controlled by imposing a periodic reference to the difference between the input currents of the cells, which in turn was generated by a PI outer loop that was configured to enforce the desired shape on the output voltage. That work also employs a hysteresis comparator for implementation. Finally, from a different perspective of the SMC application in this field and using a constant-frequency modulator, Wai et al. developed an adaptive fuzzy-neural-network control (AFNNC) in combination with a total sliding-mode controller [5]. To design the controller, an additional loop, called as curbing controller, allowed modification of the sliding surface to cope with unpredictable disturbances, whereas the AFNNC modified the sliding-surface parameters to ensure permanent stability. Naturally, despite the achieved good performance, the required implementation was considerably complex compared with that in [4]. In addition, SMC has been applied to the control of boost inverters in grid-connected applications, which is similar to the work reported in [6] in which a boost-inverter-based hybrid energy-storage system (HESS) integrates both batteries and supercapacitors to the grid using two sliding-mode controllers. A particular aspect to consider regarding this work is the fact that the system can be considered as two boost inverters that share the connection to the cell capacitors and then share the AC-side differential connection. The complexity of the control in this approach then comes from the power control used to inject apparent power into the grid (both active and reactive power), the control used to impose the charge–discharge regimes of the storage devices and the compact configuration of the HESS.

More recently, following the interest in systems involving batteries and fuel cells, researchers have paid more attention to the input–current behavior of the boost inverter mainly because of the scientific results that demonstrate that the ripple content exerts an important negative effect on the lifetime of storage devices. In a stand-alone case, to adequately shape the output voltage, the control must minimize the ripple content of the input current, which constitutes an important control objective. As expected, the simultaneous accomplishment of these two functions results in new stationary behavior in the inner variables, which is reflected in their harmonic content. In [7], Jha et al. presented a cascade-control approach based on the use of a linearization function that evolved depending on the load and input–voltage operating conditions. A particular feature of this proposal was the use of three voltage measurements that shared the same reference and that no current measurement was required. Similarly, Zhu el al. proposed in [8] a waveform control using a cascade controller with two loops: one that shaped the voltage of the capacitors of the boost cells and the other that shaped the overall output voltage. These two controllers exhibited the characteristic of avoiding the use of current measurements.

In the grid-connected case, the control of the inverter forces the shape of not only the output voltage, but also the current to inject the generated power into the grid. This application of the boost inverter was explored by Angelidis and Vassilos et al. in [9] using a cascade-control scheme that involved a loop compensation of the nonlinear gain of each boost cell and then provided the reference of the inner loops that affected the inductor currents. Similar to the stand-alone case, the enforcement of the input current to be simultaneously constant with the primary control objective implies an adjustment of the stationary behavior of the converter variables. A rule-based cascade controller that determined a component to be added to the voltage references in order to cancel the second-order harmonic of the input current was developed in [10]. The proposed scheme required the measurement of the ripple component of the input current to compute the amplitude and phase of the voltage references of the cascade loops that included a voltage outer loop and a current inner loop per boost cell. The innovative feature of this controller was the use of a perturb and observe algorithm that computed the amplitude and phase of the required additional components. Again, a similar cascade-control scheme was proposed in [11] where an additional outer loop generated the added components from the measurement of the AC component of the input current. The proposed loop separately determined the AC components to avoid undesired phase shifts. The common feature of these last three controllers was the use of harmonic-enriched references in the capacitor-voltage control loops, which increased the ability of the control system to perform a second function in addition to the tracking of the output voltage or current. Other interesting works that improved the control of boost inverters can be found into battery-charging [12,13] and fuel-cell-based applications [14,15].

This study presents an alternative DS-SMC approach that is applied to a boost inverter in which the boost cells are independently commutated using one cascade controller per cell, thereby enforcing tracking of harmonic-enriched reference waveforms to shape the capacitor voltage. Second- and fourth-order terms are introduced to reduce the instantaneous-voltage gain of the cells, which results in the alleviation of the voltage stress of the switches throughout the period of the output voltage, as previously assessed in [16] where the same converter was modified by introducing additional power semiconductors and using half-cycle rectified voltage references. In contrast to the SMC approach developed in [4], the proposed control requires two additional voltage measurements, one additional hysteresis comparator and a complementary reference generator to produce the two required harmonic components. Although this last aspect supposes an increment in terms of cost of the solution, the three required voltage measurements share the same electric reference which suppose no need of isolation. Furthermore, since isolation is preferred for increased values of nominal power of the inverter, the cost of the additional electronics will become irrelevant. Beside this, complexity of the system is not really affected because the control philosophy is the same (hysteresis comparison and PI outer loop). The size of the electronic circuit or the computational cost increase depending on the type of implementation, but this aspect is not comparable with the considerable reduction of the semiconductor voltage stress.

The rest of the study is organized as follows: The boost converter operation and the fundamentals of the performance improvement are presented in Section 2. After that, in Section 3, the ideal sliding motion is analyzed for the entire range of operation conditions using the harmonic balance technique. The constraints to ensure asymptotic stability when tracking the required periodic behavior are provided as well as a simplified model of the inner loop dynamics. The fundamentals for synthesis

and implementation of the outer controllers are also explained. Comparative simulation results demonstrate the feasibility and advantages of the proposed control in Section 4. Finally, conclusions and future work are presented in Section 5.

#### **2. Fundamentals of the Performance Improvement**

The boost inverter depicted in Figure 1 is a fourth order DC–AC converter which is composed by two conventional boost converter cells. The sub-indices *x* = {1, 2} were defined to differentiate left and right sides of the converter, respectively. Each cell is integrated by one inductor (*L*), one capacitor (*C*) and two controlled switches (*Sx*1: high-side and *Sx*2: low-side). The two switches into a cell assemble a bridge leg and then the complete circuit topology is quite similar to the conventional full-bridge inverter. The input voltage *vin* is applied to the inputs of the two cells and the output voltage (*vo*) is obtained as the difference between the voltages of the output capacitors of the cells (*v*<sup>1</sup> and *v*2). The study is developed considering a resistive load *ro*. – = {1,2} 1 2 <sup>1</sup> <sup>2</sup> 

**Figure 1.** Schematic diagram of the boost inverter circuit.

Stand-alone applications demand that inverter produces a pure sinusoidal signal from a DC input voltage which in the case of the boost inverter can be lower that the amplitude of the desired output. Then consider the following output voltage:

$$v\_{o\varepsilon} = V\_m \sin \omega t = 2V\_{s1} \sin \omega t \tag{1}$$

 = 2 1 = − 1 sin being *V<sup>m</sup>* the desired amplitude and ω = 2π*f*, for *f* being the desired output frequency. To obtain this voltage, majority of control proposals define as objective the tracking of DC-biased sinusoidal references in the capacitor voltages. These references have the form:

$$v\_{1\varepsilon} = V\_{dc} - V\_{s1} \sin \omega t \tag{2}$$

$$v\_{2\varepsilon} = V\_{d\varepsilon} + V\_{s1} \sin at\tag{3}$$

1 2 1 = − 1 sin + 1 cos + ∑ sin + cos ∞ Considering that Equation (1) is obtained from the difference between Equations (3) and (2), it is easy to note that the same result can be produced using references *v*1*<sup>e</sup>* and *v*2*<sup>e</sup>* with enriched harmonic content as follows:

$$v\_{1\varepsilon} = V\_{d\varepsilon} - V\_{s1}\sin\omega t + V\_{c1}\cos\omega t + \sum\_{n=2}^{\infty} V\_{sn}\sin n\omega t + V\_{cn}\cos n\omega t \tag{4}$$

$$v\_{2\varepsilon} = V\_{dc} + V\_{s1} \sin \omega t + V\_{s1} \cos \omega t + \sum\_{n=2}^{\infty} V\_{sn} \sin \omega n t + V\_{cn} \cos n\omega t \tag{5}$$

As it was developed in [16], the voltage stress of the semiconductors in the boost inverter is directly related with the shape of the capacitor voltages. Then, that work shows how enforcing a DC-biased half-wave rectified sinusoidal is optimal to alleviate the switching losses improving the efficiency of the converter. However, in that work, the desired behavior is obtained by using two additional switches increasing the number of semiconductors and the required auxiliary circuitry. Then, the concept developed in this study consists of enforcing the desired shape in the capacitor voltages through independent controllers for each boost cell of the inverter simultaneously ensuring an output voltage of high quality. Then, two objectives are defined: (a) generating the adequate voltage references and (b) guaranteeing a robust tracking of these references.

Consider that references are defined to enforce the DC-biased half-wave rectified sinusoidal shape in the capacitor voltages as follows:

$$v\_{1\varepsilon} = V\_{d\varepsilon} - V\_{s1} + 2V\_{s1}\sin\omega t[1 + \text{sign}(\sin\omega t)]\tag{6}$$

$$v\_{2\varepsilon} = V\_{d\varepsilon} + V\_{s1} + 2V\_{s1}\sin\omega t[1 + \text{sign}(\sin\omega t)]\tag{7}$$

Although references Equations (6) and (7) can be easily produced, they can introduce negative effects into the control loop because of the discontinuity of their derivatives. Then, it is proposed to build approximate, but smooth references by adding one or two harmonic components to Equations (2) and (3). To sake of simplicity, analysis is shown only for reference signal *v*2*<sup>e</sup>* as follows: 2 = + 1 + 21 sin [1 + sign(sin )]

$$v\_{2\varepsilon} = V\_{dc} - V\_{s1} + V\_{c2} + V\_{s1} \sin \omega t - V\_{c2} \cos 2\omega t \tag{8}$$

$$v\_{2\varepsilon} = V\_{d\varepsilon} - V\_{s1} + V\_{c2} + V\_{c4} + V\_{s1}\sin\omega t - V\_{c2}\cos 2\omega t - V\_{c4}\cos 4\omega t \tag{9}$$

Figure 2 depicts a comparison between signals obtained from numeric evaluation of Equations (7)–(9). Although a higher number of harmonics can improve the results, solutions given by Equations (8) and (9) are acceptably good. As it can be observed, for Equation (8) the signal remains below the pure sinusoidal by a considerable margin while the difference with respect to the signal Equation (9) is slight, but also important. –

Deduction of the amplitude of the added components is constrained to obtain a reference which maximum and minimum values be the same of the pure sinusoidal. A numeric analysis allows deduce that for Equation (8), *Vc*<sup>2</sup> = 0.256*Vs*<sup>1</sup> is optimal, while for Equation (9), *Vc*<sup>2</sup> = 0.36*Vs*<sup>1</sup> and *Vc*<sup>4</sup> = 0.036*Vs*<sup>1</sup> are optimal. 2 = 0.2561 2 = 0.361 4 = 0.0361

2 **Figure 2.** Comparison of possible waveforms for *v*<sup>2</sup> constraining the voltage excursion.

 = = . = . The minimum limits of the waveforms in the graphic comparison are the same because *Vdc* = 0 for Equation (7), *Vdc* = 0.75*Vs*<sup>1</sup> for Equation (8) and *Vdc* = 0.676*Vs*<sup>1</sup> for Equation (9). Consequently, the value of *Vdc* into the references must be defined adequately to ensure that this limit be always higher that the instantaneous input voltage.

#### **3. Control of the Inverter**

In this work, the adopted control scheme is a classical cascade control structure. The two inner loops, one for each boost cell, are current control loops. Due to its great flexibility and ease of implementation, a sliding mode control strategy was retained. The outer loops, one for each boost cell, are voltage control loops based on saturated PI controllers whose outputs provide an adequate current reference for the inner loop controllers. The need of saturated PI controllers will be justified later. An important step for the success of the adopted control strategy is the generation of appropriate voltage references considering the performance improvements discussed and proposed in Section 2. These voltage references are determined by a harmonic balance method applied to a power balance which constitutes a constraint imposed by the inverter structure. Figure 3 depicts the overall controlled system. Note that the sliding modes controllers are implemented by using simple hysteresis comparators leading to inner controls expressed as:

$$\mu\_{\mathfrak{X}} = \begin{cases} 0 & \text{if} \\ 1 & \text{if} \quad S\_{\mathfrak{X}}(\mathfrak{x}) < -\delta \end{cases} \quad \mathfrak{x} = 1, 2$$

where δ is a small positive number defined to constraint the maximum switching frequency of the converter and *Sx*(*x*) are the sliding surfaces introduced in a next paragraph. Note that possible variations of the input source voltage is considered in the proposed strategy to modify the DC-component of the voltage references. This aspect is covered by taking measure of *vin*(*t*) and using a low-pass (LP) filter to smooth the effect of ripple content. The cutoff frequency of the LP filter must be selected accordingly with the output frequency (three or four times is enough). () ()

**Figure 3.** Block diagram of the complete control proposal: reference-generation and control.

#### *3.1. Model of the Inverter*

<sup>1</sup> <sup>2</sup> = 0 1 2 = 1 1 2 = 1, 2 The model of the inverter is deduced from the four circuit structures presented in Figure 4. Introducing the control signals *u*<sup>1</sup> and *u*2, corresponding to *u<sup>x</sup>* = 0 if *Sx*<sup>1</sup> is on and *Sx*<sup>2</sup> is off and conversely *u<sup>x</sup>* = 1 if *Sx*<sup>1</sup> is off and *Sx*<sup>2</sup> is on, *x* = 1, 2, the converter circuit can be modeled by means of the following state equations:

$$\frac{di\_1(t)}{dt} = \frac{1}{L}v\_{in}(t) - \frac{1-\mu\_1}{L}v\_1(t) \tag{10}$$

$$\frac{d i\_2(t)}{dt} = \frac{1}{L} v\_{in}(t) - \frac{1 - \mu\_2}{L} v\_2(t) \tag{11}$$

$$\frac{dv\_1(t)}{dt} = \frac{1 - u\_1}{\mathbb{C}} i\_1(t) + \frac{1}{r\_0 \mathbb{C}} v\_o(t) \tag{12}$$

$$\frac{dv\_2(t)}{dt} = \frac{1 - \mu\_2}{\mathbb{C}} \dot{\mathbf{r}}\_2(t) - \frac{1}{r\_0 \mathbb{C}} v\_o(t) \tag{13}$$

() (1

() = <sup>2</sup>

$$v\_o(t) = v\_2(t) - v\_1(t) \tag{14}$$

where **u**<sup>1</sup> is the control signal of the left-side boost cell and **u**<sup>2</sup> is the control signal of the right-side cell.

**Figure 4.** Circuit structures of the boost inverter operating in DS-SMC. (**a**) Cell 1 state 0, (**b**) cell 1 state 1, (**c**) cell 2 state 0 and (**d**) cell 2 state 1.

#### *3.2. Inner Current Control Loops*

To enforce a sliding mode regime, the switches of the boost inverter can be operated using two different commutation techniques which have in common the complementarity between the states of the high-side and low-side switches of each boost cell, i.e., when one of them is turned on, the other is turned off. A brief description of features distinguishing these techniques can be summarized below:


DC biased pure sine-waves are normally used as references, as discussed in the previous section, enriching their harmonic content allows considerably reducing the voltage stress of the switches. Therefore, this control approach is adopted to develop the contribution of this study.

Consider the following sliding surfaces

$$\mathbf{S}(\mathbf{x}) = \begin{bmatrix} \mathbf{S}\_1(\mathbf{x}) \\ \mathbf{S}\_2(\mathbf{x}) \end{bmatrix} = \begin{bmatrix} i\_1(t) - i\_{1\ell}(t) \\ i\_2(t) - i\_{2\ell}(t) \end{bmatrix} \tag{15}$$

where *i*1*e*(*t*) and *i*2*e*(*t*) are given current signals. By applying the invariance conditions *S*(*x*) = 0 and replacing in Equations (9) and (10), the equivalent controls are given by:

$$1 - \mu\_{1\_{eq}} = \frac{v\_{\text{in}}(t) - L\frac{di\_{1\epsilon}(t)}{dt}}{v\_1(t)} > 0 \Rightarrow \frac{di\_{1\epsilon}(t)}{dt} < \frac{v\_{\text{in}}(t)}{L} \tag{16}$$

$$1 - \mu\_{\mathbb{Z}\_{\neq}} = \frac{v\_{\text{in}}(t) - L\frac{d i\_{2\epsilon}(t)}{dt}}{v\_{2}(t)} > 0 \Rightarrow \frac{d i\_{2\epsilon}(t)}{dt} < \frac{v\_{\text{in}}(t)}{L} \tag{17}$$

Replacing Equations (16) and (17) in Equations (12) and (13) and because on the surface *i*1(*t*) = *i*1*e*(*t*) and *i*2(*t*) −*i*2*e*(*t*), the following equations are obtained defining the ideal sliding dynamic of the inverter:

$$\frac{dv\_1}{dt} = \frac{1}{\mathbb{C}} \frac{v\_{\text{in}} i\_{1\varepsilon}}{v\_1} + \frac{1}{r\_0 \mathbb{C}} (v\_2 - v\_1) - \frac{L}{\mathbb{C}} \frac{i\_{1\varepsilon}}{v\_1} \frac{di\_{1\varepsilon}}{dt} \tag{18}$$

$$\frac{dv\_2}{dt} = \frac{1}{\mathcal{C}} \frac{v\_{in} i\_{2\varepsilon}}{v\_2} - \frac{1}{r\_0 \mathcal{C}} (v\_2 - v\_1) - \frac{L}{\mathcal{C}} \frac{i\_{2\varepsilon}}{v\_2} \frac{di\_{2\varepsilon}}{dt} \tag{19}$$

Now, consider that converter variables has incremental variations around one instantaneous operation point *<sup>v</sup>*<sup>1</sup> <sup>=</sup> *<sup>V</sup>*<sup>1</sup> <sup>+</sup>e*v*1, *<sup>v</sup>*<sup>2</sup> <sup>=</sup> *<sup>V</sup>*<sup>2</sup> <sup>+</sup>e*v*2, *<sup>i</sup>*1*<sup>e</sup>* <sup>=</sup> *<sup>I</sup>*1*<sup>e</sup>* <sup>+</sup>e*i*1*<sup>e</sup>* , *i*2*<sup>e</sup>* = *I*2*<sup>e</sup>* +e*i*2*<sup>e</sup>* , *di*1*<sup>e</sup> dt* = *I* ′ 1*e* +e*i* ′ 1*e* , *di*2*<sup>e</sup> dt* = *I* ′ <sup>2</sup>*<sup>e</sup>* +e*i* ′ 2*e* , *<sup>v</sup>in* <sup>=</sup> *<sup>V</sup>in* <sup>+</sup> <sup>e</sup>*vin* and *<sup>r</sup>*<sup>0</sup> <sup>=</sup> *<sup>R</sup>*<sup>0</sup> <sup>+</sup>e*ro*. By following the conventional linearization procedure preserving only first-order terms, it is obtained that:

$$\frac{d\overline{v}\_1}{dt} = \mathcal{W}\_{11}\overline{i}\_{1\varepsilon} - L\mathcal{W}\_{12}\overline{i}\_{1\varepsilon}' - (\mathcal{C}\mathcal{W}\_{11}\mathcal{W}\_{12} + b)\overline{v}\_1 + b\overline{v}\_2 + \mathcal{W}\_{12}\overline{v}\_{\text{in}} - \mathcal{W}\_3\overline{r}\_o \tag{20}$$

$$\frac{d\overline{\upsilon}\_{2}}{dt} = \mathcal{W}\_{21}\overline{i}\_{2\varepsilon} - L\mathcal{W}\_{22}\overline{i}\_{2\varepsilon}' - (\mathcal{C}\mathcal{W}\_{21}\mathcal{W}\_{22} + b)\overline{\upsilon}\_{1} + b\overline{\upsilon}\_{1} + \mathcal{W}\_{22}\overline{\upsilon}\_{\text{in}} + \mathcal{W}\_{3}\overline{r}\_{o} \tag{21}$$

$$\begin{array}{ll} W\_{11} = \frac{1}{\overline{\text{CV}}\_{1}} \left( V\_{\text{in}} - \text{LI}\_{1\varepsilon}' \right) \\ W\_{21} = \frac{1}{\overline{\text{CV}}\_{2}} \left( V\_{\text{in}} - \text{LI}\_{2\varepsilon}' \right) \end{array} \qquad \begin{array}{ll} W\_{12} = \frac{I\_{1\varepsilon}}{\overline{\text{CV}}\_{1}} \\ W\_{22} = \frac{I\_{2\varepsilon}}{\overline{\text{CV}}\_{2}} \end{array} \qquad \begin{array}{ll} b = \frac{1}{\overline{\text{R}}\_{0} \overline{\text{C}}} \\ W\_{3} = \frac{V\_{2} - V\_{1}}{R\_{0}^{2} \overline{\text{C}}} \end{array} \tag{22}$$

By applying the Laplace transform to Equations (20) and (21), Equations (23) and (24) are obtained with which the linear model of whole system can be represented using the block diagram in Figure 5. Transfer functions are defined using the polynomial Equations (25)–(30) considering *G*1(*s*) = *B*1(*s*)/*A*(*s*), *G*2(*s*) = *B*2(*s*)/*A*(*s*), *H*12(*s*) = *C*1(*s*)/*A*(*s*), *H*21(*s*) = *C*2(*s*)/*A*(*s*), *Hv*1(*s*) = *D*1(*s*)/*A*(*s*), *Hv*2(*s*) = *D*2(*s*)/*A*(*s*), *Hr*1(*s*) = *E*1(*s*)/*A*(*s*) and *Hr*2(*s*) = *E*2(*s*)/*A*(*s*).

$$V\_1(\mathbf{s}) = G\_1(\mathbf{s})I\_{1\varepsilon}(\mathbf{s}) + H\_{12}(\mathbf{s})I\_{2\varepsilon}(\mathbf{s}) + H\_{\upsilon1}(\mathbf{s})V\_{\text{int}}(\mathbf{s}) - H\_{r1}(\mathbf{s})R\_0(\mathbf{s})\tag{23}$$

$$V\_{\mathcal{Z}}(\mathbf{s}) = \mathbf{G}\_{\mathcal{Z}}(\mathbf{s})I\_{\mathcal{Z}\mathcal{E}}(\mathbf{s}) + H\_{\mathcal{Z}1}(\mathbf{s})I\_{\mathcal{U}}(\mathbf{s}) + H\_{\mathcal{U}2}(\mathbf{s})V\_{\text{int}}(\mathbf{s}) + H\_{\mathcal{V}2}(\mathbf{s})R\_{\mathcal{U}}(\mathbf{s})\tag{24}$$

$$\mathbf{S}(\mathbf{s}) = \mathbf{s}^2 + [\mathbb{C}(\mathbf{W}\_{11}\mathbf{W}\_{12} + \mathbf{W}\_{21}\mathbf{W}\_{22}) + \mathbf{b}]\mathbf{s} + \mathbf{C}^2\mathbf{W}\_{11}\mathbf{W}\_{12}\mathbf{W}\_{21}\mathbf{W}\_{22} + \mathbf{b}\mathbf{C}(\mathbf{W}\_{11}\mathbf{W}\_{12} + \mathbf{W}\_{21}\mathbf{W}\_{22})\tag{25}$$

$$B\_1(\mathbf{s}) = -L\mathcal{W}\_{12}\mathbf{s}^2 + [\mathcal{W}\_{11} - L\mathcal{W}\_{12}(\mathbf{C}\mathcal{W}\_{21}\mathcal{W}\_{22} + b)]\mathbf{s} + \mathcal{W}\_{11}(\mathbf{C}\mathcal{W}\_{21}\mathcal{W}\_{22} + b) \tag{26}$$

$$B\_{2}(\mathbf{s}) = -LW\_{22}\mathbf{s}^{2} + [W\_{21} - LW\_{22}(\mathbf{C}\mathcal{W}\_{11}\mathcal{W}\_{12} + b)]\mathbf{s} + \mathcal{W}\_{21}(\mathbf{C}\mathcal{W}\_{11}\mathcal{W}\_{12} + b) \tag{27}$$

$$\mathbf{C}\_{1}(\mathbf{s}) = b(\mathcal{W}\_{21} - L\mathcal{W}\_{22}\mathbf{s}) \tag{28} \\ \text{and} \\ \mathbf{C}\_{2}(\mathbf{s}) = b(\mathcal{W}\_{11} - L\mathcal{W}\_{12}\mathbf{s}) \tag{28}$$

$$D\_1(\mathbf{s}) = \mathcal{W}\_{12}\mathbf{s} + \mathcal{W}\_{12}(\mathcal{C}\mathcal{W}\_{21}\mathcal{W}\_{12} + b) + b\mathcal{W}\_{22} \qquad \qquad D\_2(\mathbf{s}) = \mathcal{W}\_{22}\mathbf{s} + \mathcal{W}\_{22}(\mathcal{C}\mathcal{W}\_{11}\mathcal{W}\_{12} + b) + b\mathcal{W}\_{12} \tag{29}$$

$$E\_1(\mathbf{s}) = \mathcal{W}\_3(\mathbf{s} + \mathcal{C}\mathcal{W}\_{21}\mathcal{W}\_{22}) \qquad \qquad \qquad E\_2(\mathbf{s}) = \mathcal{W}\_3(\mathbf{s} + \mathcal{C}\mathcal{W}\_{11}\mathcal{W}\_{12}) \tag{30}$$

As it can be noted, the parameters of the plant transfer functions *G*1(*s*) and *G*2(*s*). have a high dependence not only on the operation point defined by the input voltage and the load, but also on the shape of the converter waveforms. In order to accurately model the behavior of these parameters, the inductor currents and their derivatives are analyzed in the next section through application of harmonic balance technique facilitating the synthesis of the simplest controller.

**Figure 5.** Block diagram of the outer voltage controllers.

#### () = <sup>2</sup> + [(11<sup>12</sup> + 21<sup>22</sup> ) + ] + <sup>2</sup>111221<sup>22</sup> + (11<sup>12</sup> + 21<sup>22</sup> *3.3. Analysis of the Dynamic Behavior using Harmonic Balance*

() = −22

1 

1 = − 1 sin − 1 cos + ∑(−1)

2 

2

1

() = 12 + <sup>12</sup>

1

1 () = −12 <sup>2</sup> + [<sup>11</sup> − <sup>12</sup> (21<sup>22</sup> + )] + <sup>11</sup> (21<sup>22</sup> + ) <sup>2</sup> + [<sup>21</sup> − <sup>22</sup> From the analysis in Section 2, the reference required to enforce the desired shape in the capacitor voltages has the following form:

$$v\_{1c} = V\_{dc} - V\_{s1} \sin \omega t + V\_{c2} \cos 2\omega t + V\_{c4} \cos 4\omega t \tag{31}$$

(11<sup>12</sup> + )

( + 11<sup>12</sup>

)

(11<sup>12</sup> + )] + <sup>21</sup>

)

$$v\_{2\varepsilon} = V\_{d\varepsilon} + V\_{s1} \sin \omega t + V\_{c2} \cos 2\omega t + V\_{c4} \cos 4\omega t \tag{32}$$

() = <sup>3</sup>

1 () = <sup>3</sup> ( + 21<sup>22</sup> ) <sup>2</sup> The corresponding time derivatives are given by:

$$\frac{dv\_{1\epsilon}}{dt} = -\omega V\_{s1}\cos\omega t - 2\omega V\_{c2}\sin 2\omega t - 4\omega V\_{c4}\sin 4\omega t \tag{33}$$

$$\frac{dv\_{2\varepsilon}}{dt} = \omega V\_{s1} \cos \omega t - 2\omega V\_{c2} \sin 2\omega t - 4\omega V\_{c4} \sin 4\omega t \tag{34}$$

Now, suppose that the stationary periodic behavior of the inductor currents can be approximated, in a satisfactory way by means of the following waveforms and its derivatives:

$$\dot{q}\_{1\varepsilon} = I\_{d\varepsilon} - I\_{s1}\sin\omega t - I\_{c1}\cos\omega t + \sum\_{n=2}^{4} (-1)^{n+1} [I\_{s\text{fl}}\sin n\omega t + I\_{c\text{fl}}\cos n\omega t] \tag{35}$$

$$i\_{2\varepsilon} = I\_{d\varepsilon} + I\_{s1} \sin \omega t + I\_{c1} \cos \omega t - \sum\_{n=2}^{4} \left[ I\_{sn} \sin n\omega t + I\_{cn} \cos n\omega t \right] \tag{36}$$

[ sin + cos ]

+1

4

=2

4

=2

2 = + 1 sin + 1 cos − ∑ [ sin + cos ]

= 1 cos − 22 sin 2 − 44 sin 4

$$\frac{d\dot{\imath}\_{\ell 1}}{dt} = \omega I\_{\ell 1} \sin \omega t - \omega I\_{\ell 1} \cos \omega t + \omega \sum\_{n=2}^{4} n \left[ (-1)^{n} I\_{\ell n} \sin n\omega t + (-1)^{n+1} I\_{\text{sil}} \cos n\omega t \right] \tag{37}$$

$$\frac{d\mathbf{i\_{2\varepsilon}}}{dt} = -\omega \mathbf{I\_{c1}} \sin \omega t + \omega \mathbf{I\_{s1}} \cos \omega t + \omega \sum\_{n=2}^{4} n [\mathbf{I\_{c1}} \sin n\omega t - \mathbf{I\_{s1}} \cos n\omega t] \tag{38}$$

On the other hand, expressions Equations (18) and (19) can be interpreted as power balance constraints for the boost inverter cells. Then, they can be rewritten as follows:

$$Li\_{1\varepsilon} \frac{di\_{1\varepsilon}}{dt} + \mathcal{C}v\_{1\varepsilon} \frac{dv\_1}{dt} - \left(v\_{in}i\_{1\varepsilon} + \frac{v\_1 v\_{o\varepsilon}}{r\_0}\right) = 0\tag{39}$$

$$\mathrm{Li}\_{2\varepsilon} \frac{d i\_{2\varepsilon}}{dt} + \mathrm{Cv}\_{2} \frac{d v\_{2}}{dt} - \left(v\_{\mathrm{in}} i\_{2\varepsilon} - \frac{v\_{2} v\_{0\varepsilon}}{r\_{0}}\right) = 0 \tag{40}$$

Summing Equations (39) and (40), the power balance equation for the complete inverter can be written as:

$$\mathbf{L}\left(\dot{\imath}\_{\ell2}\frac{d\dot{\imath}\_{\ell2}}{dt} + \dot{\imath}\_{\ell1}\frac{d\dot{\imath}\_{\ell1}}{dt}\right) + \mathbf{C}\left(\upsilon\_{\ell1}\frac{d\upsilon\_{\ell1}}{dt} + \upsilon\_{\ell2}\frac{d\upsilon\_{\ell2}}{dt}\right) - \left[\upsilon\_{\dot{m}}(\dot{\imath}\_{\ell1} + \dot{\imath}\_{\ell2}) - \frac{\upsilon\_{\ell\nu}}{r\_0}\right] = 0\tag{41}$$

By replacing Equations (31)–(38) into Equation (41) and applying the harmonic balance technique, it is obtained a set of nonlinear algebraic equations, whose unknowns are the amplitudes of the harmonic components of the currents. It can be compactly written as:

$$F\_{\rm B}(I\_{\rm d\varepsilon}, I\_{\rm s1}, I\_{\rm c1}, I\_{\rm s2}, I\_{\rm c2}, I\_{\rm s3}, I\_{\rm c3}, I\_{\rm s4}, V\_{\rm d\varepsilon}, V\_{\rm s1}, V\_{\rm c2}, V\_{\rm c4}) = 0 \tag{42}$$

where the components of *F<sup>B</sup>* are expressed by:

F*dc* = 2*VinIdc* − 2*Vs*<sup>1</sup> 2 *r*0 F*s*<sup>2</sup> = ω*L Is*1 <sup>2</sup> <sup>−</sup> *<sup>I</sup>c*<sup>1</sup> <sup>2</sup> <sup>+</sup> <sup>4</sup>*IdcIc*<sup>2</sup> <sup>+</sup> <sup>2</sup>*Is*1*Is*<sup>3</sup> <sup>+</sup> <sup>2</sup>*Ic*1*Ic*<sup>3</sup> <sup>−</sup> <sup>2</sup>*Is*2*Is*<sup>4</sup> <sup>−</sup> <sup>2</sup>*Ic*2*Ic*<sup>4</sup> + ω*C Vs*<sup>1</sup> <sup>2</sup> <sup>−</sup> <sup>4</sup>*VdcVc*<sup>2</sup> <sup>−</sup> <sup>2</sup>*Vc*2*Vc*<sup>4</sup> + 2*VinIs*<sup>2</sup> F*c*<sup>2</sup> = 2ω*L*(*Is*1*Ic*<sup>1</sup> − 2*IdcIs*<sup>2</sup> + 2*Is*1*Ic*<sup>3</sup> − 2*Is*3*Ic*<sup>1</sup> + 2*Is*4*Ic*<sup>2</sup> − 2*Is*2*Ic*4) − −2*VinIc*<sup>2</sup> + 2*Vs*<sup>1</sup> 2 *r*0 F*s*<sup>4</sup> = 2ω*L Is*2 <sup>2</sup> <sup>−</sup> *<sup>I</sup>c*<sup>2</sup> <sup>2</sup> <sup>−</sup> <sup>2</sup>*Is*1*Is*<sup>3</sup> <sup>+</sup> <sup>2</sup>*Ic*1*Ic*<sup>3</sup> <sup>+</sup> <sup>4</sup>*IdcIc*<sup>4</sup> + 2ω*C* −*Vc*<sup>2</sup> <sup>2</sup> <sup>−</sup> <sup>4</sup>*VdcVc*<sup>4</sup> + 2*VinIs*<sup>4</sup> F*c*<sup>4</sup> = 4ω*L*(*Is*2*Ic*<sup>2</sup> − *Is*3*Ic*<sup>1</sup> − *Is*1*Ic*<sup>3</sup> − 2*IdcIs*4) + 2*VinIc*<sup>4</sup> F*s*<sup>6</sup> = 3ω*L Is*3 <sup>2</sup> <sup>−</sup> *<sup>I</sup>c*<sup>3</sup> <sup>2</sup> <sup>+</sup> <sup>2</sup>*Is*2*Is*<sup>4</sup> <sup>−</sup> <sup>2</sup>*Ic*2*Ic*<sup>4</sup> − 6ω*CVc*2*Vc*<sup>4</sup> F*c*<sup>6</sup> = 6ω*L*(*Is*3*Ic*<sup>3</sup> + *Is*2*Ic*<sup>4</sup> + *Is*4*Ic*2) F*s*<sup>7</sup> = 7ω*L*(−*Is*3*Is*<sup>4</sup> + *Ic*3*Ic*4) F*c*<sup>7</sup> = 7ω*L*(−*Is*3*Ic*<sup>4</sup> − *Is*4*Ic*3) F*s*<sup>8</sup> = 4ω*L Is*4 <sup>2</sup> <sup>−</sup> *<sup>I</sup>c*<sup>4</sup> 2 − 4ω*CVc*<sup>4</sup> 2 F*c*<sup>8</sup> = 8ω*LIs*4*Ic*<sup>4</sup> (43)

Numeric evaluation of this nonlinear equation system for the entire range of *vin* and *r*<sup>0</sup> allows to obtain the shape of the inductor currents and their derivatives which beside to the desired voltage references allow to analyze the dynamic behavior of the system. Solutions are obtained by using the function *lsqnonlin* of MATLAB considering the input–output ranges listed in Table 1 and parameters in Table 3. For the subsequent analysis, recall that harmonic components of the capacitor voltages for a given amplitude *V<sup>m</sup>* of the desired output voltage *v*0(*t*) are expressed by *Vs*10.5*Vm*, *Vc*20.18*V<sup>m</sup>* and *Vc*40.018*Vm*. The dC component of the voltage references is computed some volts higher than the minimum permissible value: *Vdc* = *Vin* + 0.338*V<sup>m</sup>* + *V*+.


**Table 1.** Range of operation of the converter used for numeric analysis.

By evaluating the periodic terms of Equations (16) and (17), it is possible to observe that their values are always lower than any value of the input voltage in the range of operation of the converter. Figure 6 shows three cycles of these terms evaluated for 30 coordinates into the range of input voltage and output load including extreme values. A coincidence of the produced waveforms around zero is recognized. From these results, it is easy to conclude, that operating with constant voltage and load values, this condition will never be violated. However, during transient response to input voltage or power load disturbances, the value of the derivative can considerably increase enforcing the loss of the sliding regime. As we will see later, maintaining the system in the sliding regime can be ensured saturating the derivative of the currents.

**Figure 6.** Evaluation of three cycles of the waveforms of the inductor voltages for the entire range of input voltage at full load. (**a**) Standard 220 V @ 50 Hz and (**b**) standard 120 V @ 60 Hz.

Figure 7 depicts the inductor current waveforms evaluated for the same 30 coordinates into the set of operation conditions of the converter. As it can be observed, when the inductor current of one cell takes negative values, the current in the other one takes positive values. In some few cases and for short intervals close to the end of each half-period, both currents can take negative values simultaneously. A coincidence around zero is also observed for this variable.

1 () =

1 () =

**Figure 7.** Evaluation of three cycles of the waveforms of the inductor currents for the entire ranges of input voltage and output load. (**a**) Standard 220 V @ 50 Hz and (**b**) standard 120 V @ 60 Hz.

 Figure 8 shows the capacitor voltage waveforms evaluated for the whole range of input voltage of the converter. Please note that impose these voltage waveforms is one of the control objectives and then the shape of the voltages must be independent of the power load. It is possible to observe how independent of the output frequency, the waveforms show coincidence at the end of each half-cycle taking values in the vicinity of 2*Vin*. 

**Figure 8.** Evaluation of three cycles of the waveforms of the capacitor voltages for the entire range of input voltage at full load. (**a**) Standard 220 V @ 50 Hz and (**b**) standard 120 V @ 60 Hz.

 () () From the results of the previous analysis, it seems to be reasonable to evaluate the parameters of the polynomial Equations (25) and (27) to obtain *G*2(*s*) around the average point Equation (44) which results in the reference current to capacitor voltage transfer functions given by Equation (45).

$$\left(i\_{1\epsilon\prime}i\_{2\epsilon\prime}v\_1, v\_2, L\frac{di\_{1\epsilon}}{dt}, L\frac{di\_{2\epsilon}}{dt}, v\_{in\nu}r\_0\right) = \left(0, 0, 2V\_{\rm in\nu}2V\_{\rm in\nu}0, 0, V\_{\rm in\nu}R\_0\right) \tag{44}$$

$$\mathcal{G}\_1(s) = \frac{s+b}{2\mathcal{C}(s+2b)s} \qquad\qquad \mathcal{G}\_2(s) = \frac{s+b}{2\mathcal{C}(s+2b)s} \tag{45}$$

The resulting model shows that system dynamics is not asymptotically stable nor unstable. Around the linearization point, an integral effect can be observed, but this effect diminishes as we move away from it. The following as conclusions can be considered for the controller design stage.

1. Without an outer loop, having that the average value of the currents is positive, the voltages of the capacitors will increase until the permitted physical limits;


#### *3.4. Outer Voltage Controllers*

The tracking of the voltage references is guaranteed by the outer loops with PI voltage compensators defined by:

$$\begin{cases} s\_{\mathbf{x}}(t) = \operatorname{sat}\_{\mathsf{u}\_{0}} \Big\{ \mathcal{K}\_{p} \Big[ \frac{d(\upsilon\_{\mathbf{x}}(t) - \upsilon\_{\mathbf{x}\mathbf{e}}(t))}{dt} + a(\upsilon\_{\mathbf{x}}(t) - \upsilon\_{\mathbf{x}\mathbf{e}}(t)) \Big] \Big\} \\\ i\_{\mathbf{x}\mathbf{e}}(t) = \int\_{-\infty}^{t} s\_{\mathbf{x}}(\tau) d\tau \ \mathbf{x} = \mathbf{1}, \mathbf{2} \end{cases} \tag{46}$$

where *satu*<sup>0</sup> (*x*) is the classical symmetrical saturation function [17] having *u*<sup>0</sup> = *vin*(*t*) *L* defining its limits. *K<sup>p</sup>* and α are positive design parameters, *K<sup>p</sup>* being the proportional gain and α*K<sup>p</sup>* the integral gain. When the signal *sx*(*t*) does not saturate, the controller is a classical PI controller whose expression is:

$$\dot{u}\_{\mathbf{x}\varepsilon}(t) = \mathcal{K}\_{\mathcal{p}}(v\_{\mathbf{x}}(t) - v\_{\mathbf{x}\varepsilon}(t)) + \alpha \mathcal{K}\_{\mathcal{p}} \int\_{-\infty}^{t} (v\_{\mathbf{x}}(\tau) - v\_{\mathbf{x}\varepsilon}(\tau)) d\tau, \ \mathbf{x} = 1, 2$$

The presence of saturation function ensures that the overall controlled system is asymptotically stable. This can be deduced from the stability result developed in the previous section, simply by noting that functions *ax*(*t*), *x* = 1, 2, remain positive if condition Equation (15) is satisfied, that is, if:

$$\frac{di\_{\text{xc}}(t)}{dt} < \frac{v\_{\text{in}}(t)}{L}, \text{ } x = 1, 2$$

Equation (15) being also a necessary condition for the existence of a sliding regime. In such situation, for all positive *K<sup>p</sup>* and α, we will have:

$$\lim\_{t \to \infty} v\_1(t) = v\_{1\varepsilon}(t) \text{ and } \lim\_{t \to \infty} v\_2(t) = v\_{2\varepsilon}(t)$$

For ease implementation of the proposed controller, we can remark that an expression of the outer control can be formulated with a saturation function whose limit is constant and equal to a positive real number *s*<sup>0</sup> (i.e., independent of time) chosen to facilitate the controller implementation. An alternate expression with such a property could be:

$$\begin{cases} s\_{\mathbf{x}}(t) = \frac{v\_{\mathrm{in}}(t)}{Ls\_{0}} \mathrm{sat}\_{\mathbf{s}\_{0}} \left\{ \frac{Ls\_{0}}{v\_{\mathrm{m}}(t)} K\_{p} \left[ \frac{d(v\_{\mathbf{x}}(t) - v\_{\mathbf{x}\mathbf{r}}(t))}{dt} + \alpha (v\_{\mathbf{x}}(t) - v\_{\mathbf{x}\mathbf{r}}(t)) \right] \right\} \\\ i\_{\mathbf{x}\mathbf{r}}(t) = \int\_{-\infty}^{t} s\_{\mathbf{x}}(\tau) d\tau \ \mathbf{x} = \mathbf{1}, \mathbf{2} \end{cases} \tag{47}$$

Figure 9 represents the block-diagram of the proposed saturated PI controller.

To simplify the controller structure and then its implementation, if there exists a value *vinmin* > 0 such that for all t, *vin*(*t*) > *vinmin* , it is possible to drop the measurement of *vin*(*t*) and replace it by *vinmin* in the control expression. It is also possible to use a non-saturated PI controller if the converter was adequately designed to track the reference signals of interest (i.e., in a way guaranteeing that the control never saturates).

To end with the outer loop, the choice of constants *K<sup>p</sup>* and α have an influence on the transient behavior of the controlled system, but asymptotic stability is always ensured. Even if asymptotic stability is a necessary condition, it is not sufficient in practice. A good performance level is often needed. The parameters *K<sup>p</sup>* and α*K<sup>p</sup>* can be selected as done classically for a nonsaturated PI controller. However, it is important to remark that while the stability will be preserved, the performance associated

with such a choice will only be guaranteed in the zone of linearity of the saturated PI controller. When the controller will saturate, except stability, no performance level can be guaranteed.

**Figure 9.** Block diagram of the outer voltage controllers.

>

#### **4. Validation Results via Simulation**

0 () > () To validate the accurateness of the mathematical procedures and the correct operation of the proposed control, two simulation tests were built in PSIM software, one for standard of 120 V @ 60 Hz (Simulation test 1) and another for 220 V @ 50 Hz (Simulation test 2). Comparison of voltage stress in semiconductors with respect to the SS-SMC presented in [4] is also performed. The simulation step time was configured to be 2.60417 × 10 −7 s for the test 1 and 3.125 × 10 −7 s for the test 2. The parameters of the power converter and its control are listed in Tables 2 and 3. Parasitic resistances of elements were obtained from datasheets: Equivalent series resistances in inductors and capacitors (*R<sup>L</sup>* and *RC*, respectively) and Drain-Source on–resistance in MOSFETs (*RM*). Considering that the proposed control can be entirely implemented with analog electronics, digitalization effects were only considered for reference generation. The generation method presented in [18] was considered, where signals are produced by using a look-up table storing 128 samples of 10 bits for a cycle of the output signal. It is worth mentioning that these features are typical of low cost microcontroller.


**Table 2.** Control parameters used in simulations.


**Table 3.** Parameters of the power converter in simulations.

 mΩ 120 μH mΩ mΩ In both simulation tests, five points are enforced to assess the stationary and transient behavior. Selected conditions and time intervals are listed in Table 4. Sudden transitions are enforced during the load changes while ramp type transitions with intervals of 3 ms are applied for input voltage changes.


**Table 4.** Operation conditions and time intervals used in simulation tests.

#### *4.1. Simulation Test 1 (American Standard 120 V @ 60 Hz)*

Figure 10 presents the waveforms at the output of the converter (voltage and current), the capacitor voltages and the inductor currents for the simulation test 1. As it can be observed, the output signal accurately track the high quality sinusoidal in both stationary and transient regimes. After disturbances, the AC component of the capacitor voltages remains unchanged while its average value adapts to the input voltage. Table 5 summarizes the obtained THD (lower than 1%) and RMS error (lower than 0.2%) demonstrating the high performance of proposed control in the five selected operation points.

**Figure 10.** Simulated results during Experiment 1 using the proposed DS-SMC.

**al ) )** 

–

= + 0.338 + <sup>+</sup> <sup>+</sup>

–

– – –

ndition 2 –


**Table 5.** Output voltage quality for simulation test 1 (120 V @ 60 Hz).

Figure 11 shows a comparison between the DS–SMC approach developed in this work and the SS-SMC approach developed in [4]. As it can be noted, the voltage of the capacitors which is the same voltage applied to open semiconductors in each boost cell is always lower for the DS-SMC. It is relevant to mention that two features of the proposed control are responsible of the improvement: (a) the harmonic content included in the capacitor voltages and (b) their average component. The DC component cannot be accessed using the SS-SMC approach while using the proposed DS-SMC this component allows to enforce the minimum value of the output capacitors to be almost equal to the input voltage. In this simulation test *Vdc* = *Vin* + 0.338*V<sup>m</sup>* + *V*<sup>+</sup> being *V*<sup>+</sup> settled to 5 V.

**Figure 11.** Simulated semiconductor voltages comparing SS-SMC and DS-SMC for simulation test 1.

#### *4.2. Simulation Test 2 (European Standard 220 V @ 50 Hz)*

Figure 12 presents the waveforms at the converter for the simulation test 2. It is possible to confirm that the output signal accurately track the high quality sinusoidal. Table 6 summarizes the obtained THD and RMS error which show values lower than 1% and 0.2%, respectively. It is worth mentioning that the required voltage gain increases around 50% without affecting the performance of the control which use the same parameters.



ndition 5 –

**Figure 12.** Simulated waveforms during experiment 2 using the proposed DS-SMC.

– = + 0.338 + <sup>+</sup> <sup>+</sup> Equal to the previous test, the DS–SMC and SS-SMC approaches were compared. Again, the voltage applied to semiconductors is always lower for the DS-SMC. The expression *Vdc* = *Vin* + 0.338*V<sup>m</sup>* + *V*<sup>+</sup> being *V*+ settled to 5 V is used to define input voltage. In addition, similar to the previous case, the alleviation of the semiconductor voltage stress is at least of 30 V and becomes up to 100 V. A more accurate analysis is presented in the next subsection.

#### *4.3. Semiconductor Voltage Stress Comparison*

A further analysis was done by reviewing the maximum, minimum and average semiconductor voltage stress for inverter operating with the two studied standards using the same simulations producing Figures 11 and 13. In addition to the two methods compared in these figures, the proposed control without adding the harmonic components in the voltage references is also assessed. In Table 7, the minimum voltage corresponds with intervals in which the input voltage is minimum (125 V–25%), the maximum voltage corresponds to the intervals in which the input voltage is maximum (125 V + 25%) and the average is computed considering the complete simulation interval for both standards.

**Figure 13.** Simulated semiconductor voltages comparing SS-SMC and DS-SMC for simulation test 2.


DS-SMC (Modified references) 97 331 182 97 472 235

**Table 7.** Comparison of control methods regarding semiconductor voltage stress.

Results demonstrate how the voltage stress of the semiconductors reduces considerably by employing the DS-SMC proposed in this study (Separate voltage control loops minimizing the DC-bias of the references) even without additional harmonic components into the voltage references. Beyond that, results also demonstrate conclusively how the addition of the two harmonic components in the references further improve this feature.

–

#### **5. Conclusions**

In this study, the sliding mode control technique was effectively applied to accomplish two main objectives in the operation of the boost inverter: (a) provide a high quality output voltage and (b) minimize the required voltage gain in the boost cells to alleviate semiconductor voltage stress. Different from all previously published works related to the control of this converter, the voltage of the capacitors are enforced to have additional optimal values of double and fourth harmonic terms. The objectives are accomplished by means of two independent multiloop controllers involving an inner loop of sliding mode control implemented using hysteresis comparators and PI compensators ensuring the tracking of harmonic enriched references. Additionally, having a degree of freedom to modify the average value of the capacitor voltages, an adaptive feed-forward loop was integrated helping to further reduce the required gain in the converter cells. A complete study of the stationary behavior of the converter was developed to obtain a simple model of its dynamics by using the harmonic balance technique. A PI controller with saturation of the output derivative allowed to ensure the sliding regime of the inner loop which is also an innovative feature of the proposed control scheme. The obtained THD is lower than 0.8% and the regulation of the RMS value is lower than 0.2% in the entire range of operation of the converter for both standards used as case study. The alleviation of the semiconductor voltage stress is very important also for both analyzed standards.

From the results of the present work, a new control scheme is being developed using a multiple input multiple output perspective of the problem, this allowing a better action on the coupling dynamics of the boost cells. Prospective work involves experimental validation using a laboratory prototype.

**Author Contributions:** All authors contributed equally to all the stages of the research process and the preparation of the manuscript. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was developed with the partial support of the Ministerio de Ciencia, Tecnología e Innovación de Colombia (MinCiencias) under contract 018–2016 and the HisPaliS project supported by the Agence Nationale de la Recherce de France (ANR).

**Conflicts of Interest:** The authors declare no conflicts of interest.

#### **References**


© 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

#### *Article*
