*Article* **ADC Quantization Effects in Two-Loop Digital Current Controlled DC-DC Power Converters: Analysis and Design Guidelines**

**Catalina González-Castaño <sup>1</sup> , Carlos Restrepo <sup>2</sup> , Roberto Giral <sup>1</sup> , Enric Vidal-Idiarte 1,\* and Javier Calvente <sup>1</sup>**


Received: 23 September 2020; Accepted: 9 October 2020; Published: 15 October 2020

**Abstract:** This paper analyzes the presence of undesired quantization-induced perturbations (QIP) in a dc-dc buck-boost converter using a two-loop digital current control. This work introduces design conditions regarding control laws gains and signal quantization to avoid the quantization effects due to the addition of the outer voltage loop in a digital current controlled converter. The two-loop controller is composed of a multisampled average current control (MACC) in the inner current-programmed loop and a proportional-integrator compensator at the external loop. QIP conditions have been evaluated through simulations and experiments using a digitally controlled pulse width modulation (DPWM) buck-boost converter. A 400 V 1.6 kW proof-of-concept converter has been used to illustrate the presence of QIP and verify the design conditions. The controller is programmed in a digital signal controller (DSC) TMS320F28377S with a DPWM with 8.96-bit equivalent resolution, a 12-bit ADC for current sampling, and a 12-bit ADC for voltage sampling or a 16-bit ADC for voltage error sampling.

**Keywords:** dc-dc power converter; multisampled average current control (MACC); digital control; limit-cycle oscillation (LCO); quantization-induced perturbations (QIP)

#### **1. Introduction**

Digital control in dc-dc converters is of interest because its many potential advantages such as low power consumption and flexibility to program and design advanced control strategies to improve the system performance [1–3]. Therefore, the digital closed-loop configuration is increasingly being used in dc-dc converters [4–6]. Digital control depicts an important element of power converters for renewable energy systems [7], automobile industry [8], and industrial applications [9]. However, many works report disadvantageous quantization effects related to the existence of limit cycles in digitally controlled pulse width modulation (DPWM) converters. Static and dynamic models taking into account the quantization effects are derived and used to explain the origins of limit-cycle oscillations (LCO) for voltage single-loop digital control in [10,11]. A DPWM resolution lower than ADC resolution usually causes LCO that affects the regulation of the controlled variable [12]. Therefore, DPWM with resolution higher than the ADC is usually implemented in order to reduce the effect of limit-cycle oscillations in voltage single-loop digital

*Appl. Sci.* **2020**, *10*, 7179; doi:10.3390/app10207179 www.mdpi.com/journal/applsci

control, where the difference between the voltage reference and the output voltage is quantized to a digital number to represent the error signal [13,14].

It is well known that cascade control of dc-dc converters generally offers better performance than single-loop control [15,16]. Moreover, current control strategies are always needed to connect in parallel some converters to increase power management. Therefore, two-loop digital control structures have been extensively applied last teen years [17–21]. Analysis of LCO are given in [22–24] for digital current mode control. In these works, the resolution of the DPWM is also greater than the ADC resolution in the outer voltage loop. In [22], an estimation algorithm has been applied to the average current control of a buck converter in order to reduce quantization effects in the inductor current loop and, consequently, the presence of limit cycle oscillations. A method to design a two-loop digital control is developed in [23], where the current reference is dynamically adjusted to give a solution to the LCO problem. A technique to compute the steady-state duty cycle in real-time was considered in [24], where a time-to-digital converter translates the duty ratio information into a digital code using a moving average filter and an adjustable current loop sampling frequency. At steady-state, the strategy disables the current-loop sampling and the control computation. Then, a virtual open loop configuration is used to reduce oscillations of the inductor current.

In order to improve the resolution of the DPWM in single-loop digital voltage controllers, some authors use sigma-delta modulation to eliminate the quantization noise and the LCO. In [12], a non-zero error method is used to encode the output voltage error improving the low resolution of the DPWM. A sigma delta modulation scheme and switching frequency modulation strategy are combined in [25] to increase the effective resolution of the DPWM. Nonetheless, there are not reported works that show the effects of quantization in dc-dc converter with a two-loop digital control having an integral term of its output voltage error.

This paper presents design conditions to avoid the effects of the quantization in two-loop current controlled dc-dc switching converter. LCOs conditions presented in [10] are extended to a two-loop digital control in order to obtain restrictions associated with the gains of the control laws and the quantization resolution for each control loop. When the condition proposed for the external loop is fulfilled, simulation and experimental results verify that the QIP are suppressed from the current signals.

Section 2 presents the conditions for each digital loop to observe the two-loop quantization effects. Section 3 describes the implementation of the digitally controlled buck-boost converter in order to validate the restrictions. Experimental and simulation results for a 400 V 1.6 kW digitally controlled coupled-inductor dc-dc buck-boost converter are presented in Section 4. Conclusions are given in Section 5.

#### **2. Two-Loop Quantization Effects**

Quantization effects have been deeply studied in [10,11,26], where authors studied limit cycling conditions regarding plant and controller gains besides ADC and PWM resolution in a single-loop voltage control. This section presents dynamic conditions to avoid limit cycles in a two-loop digital current controller converter.

In this case, both inner and outer small-signal representation of the control to output transfer function can be represented in general form as

$$G\_p(\mathbf{s}) = \frac{\mathbf{G}}{\mathbf{s}}\tag{1}$$

where *G* is the gain of the transfer function and 1/*s* represents the transfer function of an integrator. In the case of the inner current control (see Figure 1a), the transfer Function (1) becomes

$$G\_{\rm pin}(s) = \frac{m\_1 + m\_2}{s} \tag{2}$$

where *m*<sup>1</sup> is the positive slope and *m*<sup>2</sup> is the negative slope of the output current. Finally, for the voltage loop (see Figure 1b) the transfer Function (1) becomes

$$G\_{pou}(\mathbf{s}) = \frac{1}{\mathbb{C}\_o s} \tag{3}$$

where *C<sup>o</sup>* represents the output filter capacitor of the converter. A standard Proportional-Integral (PI) controller is used in both control loops

$$\mathbf{G}\_{pl}(\mathbf{s}) = \mathbf{K}\_p + \frac{\mathbf{K}\_i}{\mathbf{s}} \tag{4}$$

where *Gpi*(*s*) = *Gpii*(*s*) for the inner loop (Figure 1a) and *Gpi*(*s*) = *Gpiv*(*s*) for the external loop (Figure 1b).

(**a**)

**Figure 1.** Proportional-integrator control block diagram of (**a**) inner loop dynamic model and (**b**) outer loop dynamic model.

The dynamic model for each loop is shown in Figure 1, where *q* is the quantization level for an input or an output signal. Therefore, *q<sup>i</sup>* , *qv*, and *qDPWM* represent, respectively, the output current *iL*, the output voltage *vo*, and the DPWM quantization level. *T* is the switching period (1/ *fs*). Finally, *e<sup>v</sup>* and *e<sup>i</sup>* are the error signals of the measured voltage and current, respectively. Then, in the inner loop, *Gpii*(*s*) generates the control variable *u*, taking into account the mean value of the output current converter to change the duty cycle. Nonetheless, *Gpiv*(*s*) for the output voltage gives the current reference for the inner loop based on the error voltage.

The loop gains of the linear part of the system are defined without quantization [10,26] as follows,

$$T\_L(\mathbf{s}) = G\_{p\bar{\imath}}(\mathbf{s}) G\_{p}(\mathbf{s}).\tag{5}$$

Therefore, using (1) and (4) we obtain the crossover angular frequency as

$$
\omega\_{\mathfrak{C}} = \mathcal{K}\_p \mathcal{G}\_{\prime} \tag{6}
$$

A typical design of PI parameters usually places the zero of the controller at least one decade below of the desired crossing frequency *ωc*, thus giving the following condition,

$$K\_i/K\_p << \omega\_\circ \tag{7}$$

Then, we have to adjust *K<sup>p</sup>* and *K<sup>i</sup>* in order to obtain the desired phase margin. Phase margin (PM) is usually adjusted to be greater than 50◦ by tuning *K<sup>p</sup>* and satisfying (7).

#### *2.1. Outer Loop Condition*

In digital power converter operation, the static and the integral gain condition must be satisfied to avoid limit cycling due to quantization [27–29]. Then, the necessary no-limit-cycling condition that allows the existence of a steady-state solution inside ADC zero-error bin, given in [28,29], can be written for the external voltage loop in Figure 1b as

$$q\_i T G < q\_\upsilon \,\,\_{\upsilon} \tag{8}$$

Condition (8) indicates that the minimum output voltage variation, due to the minimum output current step change provoked by a variation in the output voltage, must be smaller than the quantization level of the output voltage. In this condition (8), the gain *G* is defined as 1/*Co*. The no-limit-cycling condition involving the integral gain is

$$
\mathfrak{q}\_{\mathcal{V}} T \mathcal{K}\_{\dot{\mathcal{V}}} < \mathfrak{q}\_{\mathcal{i}}.\tag{9}
$$

The output current reference change provoked by a minimum error in the voltage loop is *Kpvqv*. To guarantee output voltage regulation, the compensator must develop a correction action when *e<sup>v</sup>* is different from 0 [29], thus giving

$$
\mathfrak{q}\_{\upsilon} K\_{p\upsilon} > \mathfrak{q}\_{\text{i.}}.\tag{10}
$$

Combining restrictions (9) and (10) results in the following condition,

$$K\_{i\upsilon}T < \frac{q\_i}{q\_{\upsilon}} < K\_{p\upsilon}.\tag{11}$$

Condition (12) is derived replacing (10) in (8)

$$K\_{pv}TG < 1.\tag{12}$$

Employing Equation (6) and replacing *K<sup>p</sup>* = *Kpv* in (12), we obtain an upper limit for the crossing frequency

$$
\omega\_{\mathcal{C}} < \frac{1}{T}.\tag{13}
$$

#### *2.2. Inner Loop Condition*

Restriction (11) can be extended in terms of the inner loop block diagram representation of Figure 1a. Following the same procedure as in the outer loop, the condition for the inner loop is given by

$$K\_{\rm li}T < \frac{q\_{\rm DPWM}}{q\_{\rm li}} < K\_{\rm pi} \tag{14}$$

Following (7), we select *KiiT* = *Kpi*/10 and adjust *Kpi* to obtain a PM greater than 50◦ .

#### **3. Validation of the Restrictions**

The fulfillment of Conditions (11) and (14), which guarantee a stable digital two-loop control, have been verified using a buck-boost converter with coupled inductors. The topology of the dc-dc buck-boost converter for a voltage regulation application shown in Figure 2 was introduced as an unidirectional buck-boost converter in [30] and presented for electric vehicle and high-voltage application in [31,32]. The bidirectional power stage shown in Figure 2 is composed of two coupled inductors with unitary turns ratio and magnetic coupling coefficient *k* = 0.5. Therefore, primary self-inductance *L*<sup>1</sup> is equal to secondary self-inductance *L*<sup>2</sup> (*L*<sup>1</sup> = *L*<sup>2</sup> = *L*), and their mutual inductance is *M* = *L*/2. The two-loop digital voltage controller proposed in Figure 3 consists of a MACC [33] inner current programmed controller and a discrete-time PI compensator at the outer voltage feedback loop. Note, in Figure 3 we also

represent two measuring approaches that allows to obtain different quantization levels of the measured output voltage error.

**Figure 2.** Power stage of a coupled-inductor buck-boost converter.

**Figure 3.** Block diagram of the digital controller for the voltage regulation of the buck-boost converter. Bottom Left: Conventional voltage error subcircuit. Bottom Right: Proposed improved approach subcircuit.

#### *3.1. Multisampled Average Current Control (MACC)*

The multisampled average current control for the bidirectional buck-boost converter was presented in [33]. The MACC stage generates the control variable (*u*) that is processed by a dual digital PWM to obtain the discrete control signals (*u*<sup>1</sup> and *u*2) that activate the converter half-bridges. The external loop regulates the output voltage by providing the MACC with the output current reference through a discrete proportional-integral control transfer function *Gvpi*(*z*), as it is seen in Figure 3. An important element of the MACC loop is the ripple filter processing the error between output current *iL*[*n*] and its desired reference *iLre f* [*n* − 1]. The ripple filter averages two consecutive samples per switching period (*fsamp* = 2 *fs*) of the output current error. This strategy eliminates the switching ripple in the current loop without significant phase loss [34].

The discrete-time ripple filter transfer function can be expressed as

$$\mathfrak{A}[n] = \frac{\mathcal{K}\_{pi}}{2} \left( \mathfrak{B}e\_{i}[n] + 2e\_{i}[n-1] - e\_{i}[n-2] \right). \tag{15}$$

The proportional gain can be written in terms of the output current waveform slopes as

$$K\_{pi} = \frac{K\_{\text{fl}}}{(m\_1 + m\_2)T} \tag{16}$$

where the output current has a periodic triangular waveform with rising and falling current slopes *m*<sup>1</sup> and −*m*2, respectively. The expression *m*<sup>1</sup> + *m*<sup>2</sup> is obtained for each converter operation mode, yielding

$$m\_1 + m\_2 = \begin{cases} \frac{Mv\_o[n]}{L^2 - M^2} & \text{for boost mode} \\ \frac{LV\_g}{L^2 - M^2} & \text{for back mode} \end{cases} \tag{17}$$

Parameter *K<sup>n</sup>* has been adjusted to 0.35 to obtain a crossover frequency (CF) of approximately 11 kHz and a phase margin (PM) of 58◦ as in [33].

The digital PI compensator in the z-domain added to the current control loop has been implemented using forward-Euler method as follows,

$$G\_{ijl}(z) = 1 + \frac{K\_i}{2} \frac{1}{z - 1} \tag{18}$$

Figure 3 shows the implementation of the discrete-time PI compensator, whose integral gain can be chosen as in [33].

#### *3.2. Digital Proportional-Integral Voltage Control*

A slower outer voltage loop providing current reference *iLre f* is added to the inner current loop. The PI voltage controller is designed taken into account the value of the output filter capacitor (*Co*) and the desired loop-gain crossover frequency (*fc*). The transfer function of the PI voltage controller can be expressed in the *z* domain using the forward Euler method as

$$G\_{vpi}(z) = K\_{pv} + \frac{K\_{iv}T\_{sample}}{z - 1}z^{-1} \tag{19}$$

where *Kpv* = *Co*2*πf c* , *Kiv* = *Kpv*/*T<sup>i</sup>* , and *Tsamp* is the sample period (1/ *fsamp*). Therefore, the bandwidth of the voltage loop depends on the proportional coefficient (*Kpv*), while the phase margin (PM) is adjusted to be greater than 50◦ adjusting *Kpv* after setting *T<sup>i</sup>* = 10/(2*π fc*) for the integral coefficient (*Kiv*). The forward-Euler method is used to find the recurrence equations for the discrete-time PI controller as

$$\begin{aligned} i\_{Lp}[n] &= K\_{p\upsilon} e\_{\upsilon}[n] \\ i\_{Li}[n] &= K\_{i\upsilon} T\_{samp} e\_{\upsilon}[n] + i\_{Li}[n-1] \\ i\_{Lref}[n] &= i\_{Lp}[n] + i\_{Li}[n]. \end{aligned} \tag{20}$$

#### **4. Simulation and Experimental Results**

The set-up used to carried out the different experiments with the MACC-based two-loop digital control is shown in Figure 4. It is composed of a 400 V 1.6 kW buck-boost prototype converter with the parameters described in Table 1 and the TMS320F28377S DSC. The design of the buck-boost converter is presented in [32].

The tests were carried out changing quantization values and controller parameters, as described next. Test 1 has been done using the conventional voltage error approach shown in Figure 3 using a 12 bit ADC to take the samples of output current and voltage. The external loop compensator is designed to obtain a cross-over frequency of *f<sup>c</sup>* = 4 kHz. Test 2 also corresponds to the conventional voltage error measurement approach used in Test 1 but tuning *f<sup>c</sup>* = 2 kHz. In order to reduce the voltage error quantization value *qv*, Test 3 has been carried out with the proposed voltage error block shown in Figure 3, using a 16 bit ADC in differential mode and *f<sup>c</sup>* = 4 kHz for the external closed loop. In Test 4, the ADC quantization level of the output current and voltage is increased, scaling ADC resolution to 8 and 11 bits respectively for the current and voltage sampled values [35], and using the conventional approach error voltage block in Figure 3. Loop gains of the external control loop for the last test are selected to obtain *f<sup>c</sup>* = 4 kHz.

**Figure 4.** Experimental set-up of the buck-boost voltage regulator: (**a**) coupled-inductor buck-boost power stage, (**b**) digital signal controller with output capacitor *C<sup>o</sup>* = 28 µF, (**c**) oscilloscope, (**d**) constant resistive load *R<sup>o</sup>* = 200 Ω (**e**) input dc power supply, and (**f**) auxiliary power supply for DSC and MOSFET drivers.


**Table 1.** Parameters for the buck-boost setup.

Figure 5 shows simulated waveforms of output current reference *iLre f* , variable control *u*, and voltage error *e<sup>v</sup>* when the converter operates in steady-state with *V<sup>g</sup>* = 200 V and *v<sup>o</sup>* = 300 V.

A summary of the tests and evaluations of the fulfillment of the stability conditions for each loop, obtained by replacing the parameters of Tables 2 and 3 in the restrictions (11) and (14), are shown in Table 4. Figure 5a shows quantization-induced perturbations (QIP) in all signals for the Test 1, when neither *qDPWM*/*q<sup>i</sup>* < *Kpi* for the restriction (14) of the inner current loop nor *KivT* < *qi*/*q<sup>v</sup>* of the external loop are fulfilled. In Test 2, although condition (14) is not fulfilled, QIP are reduced for the output current reference as can be seen in Figure 5b. The condition for the external loop (11) is satisfied due to the reduction of the gains *Kiv* and *Kpv*, but, as the cross-over frequency depends on the proportional gain *Kpv*, the loop bandwidth is reduced. The ADC quantization level of the output voltage quantization *q<sup>v</sup>* is reduced in

Test 3, where the condition for the external loop is fulfilled with a wide bandwidth, and the effects of QIP on the output current reference are significantly reduced.

**Figure 5.** Simulation of output current reference *iLre f* , signal control *u*, and voltage error *e<sup>v</sup>* with the converter operating in steady-state: (**a**) Test 1; (**b**) Test 2; (**c**) Test 3; (**d**) Test 4.


**Table 2.** Analog parameters controller design.


**Table 3.** ADC quantization parameters controller design.



To compare the bandwidths and stability margins provided by each of the tests, the corresponding Bode plots of the voltage loop-gains for the converter operating in boost mode are provided in Figure 6, being the loop gain frequency response in a switched converter a powerful tool commonly used for the design of the controllers used in the control stage [36]. It is important to note that the results for the Test 1 have not been included in the frequency response analysis previously described. This test does not present a stable inner loop regulation which is evidenced by the presence of high current peak perturbations. This peak would be destructive for the converter if an experimental frequency response analysis is performed (please see the temporary experimental results presented below). Experimental plots in Figure 6b show that the Tests 3 and 4 with *Kpv* = 0.7 provide a CF of 4 kHz and a PM of 52◦ , while Test 2 with *Kpv* = 0.35 A/Vs, with smaller quantization perturbations (see Figure 5b), yields a CF = 2.16 kHz and PM = 59.58◦ .

Simulation tests were done using two voltage error measurement approaches shown in Figure 3. The conventional approach on the left side uses an ADC for sampling the voltage and then computes the voltage error. On the right side, the proposed method quantizes the voltage error by using an ADC in differential mode. Previously, it produces an analog voltage reference from the digital one. Through this last approach, it is possible to increase the error voltage resolution. The values of the analog control gains for the inner and for the external loop at different cross-over frequencies are shown in Table 2.

The proportional gain for the outer control is selected using the expression *Kpv* = *Co*2*πf c* for different crossover frequencies (*f<sup>c</sup>* = 2 KHz and *f<sup>c</sup>* = 4 kHz) and with *C<sup>o</sup>* = 28 µF. Then, the proportional gain for the inner control is adjusted using the expression (16) with *K<sup>n</sup>* = 0.35, employing the Equation (17) for boost mode with an output voltage of *V<sup>o</sup>* = 300 V in Equation (16). The statement *KiT* = *Kp*/10 ensures to obtain a PM greater than 50◦ (see Figure 6), therefore *KivT* = *Kpv*/10 for the outer loop and *KiiT* = *Kpi*/10 for the inner loop. The parameters for the different tests are listed in Table 3.

Nonetheless, the condition for the inner loop is not fulfilled in this test, therefore the control variable *u* and voltage error *e<sup>v</sup>* are not free of QIP effects as it is shown in Figure 5c. The simulated results of Test 4, in which both stability conditions are satisfied, are shown in Figure 5d, where the QIP perturbations have

disappeared from all signals. It is also noticeable that, in comparison with previous tests, the control effort has been also reduced, which is indicated by the small amplitude of control variable *u*.

**Figure 6.** Voltage loop-gain Bode plots: (**a**) simulated, (**b**) experimental.

These values are in good agreement with the simulated results in Figure 6a. Despite the fact that Tests 2 and 3 do not satisfy all conditions, it is possible to operate the converter with these designs, obtaining a wider bandwidth using the proposed approach seen in Figure 3 for the Test 3.

Additional experiments and simulations have been performed to observe the current waveforms during start-up together with about 12 ms of steady-state regimes. Figure 7 depicts waveforms of input (*ig*) and output (*iL*) currents, as well as input (*vo*) and output (*Vg*) voltages in the same cases previously shown in Figure 5.

In Figure 7, waveforms of the experimental results show higher QIP in relation to the simulation results due to noise in the experimental tests. In the same way, Figure 7a,b corresponds to Test 1 using the conventional approach, where the DPWM was configured for 8.96-bit. Output voltage and current ADC resolution are set to 12 bits, and the input ADC input voltage range goes from 0 V to 3 V. Figure 7a,b shows the simulated and experimental results when the proportional gain of the voltage loop is selected as *Kpv* = 0.7. In this case, the current waveforms present perturbations with high current overshoot and undershoot values. Results when the gain *Kpv* is reduced to the more conservative value of 0.35 in Test 2 are plotted in Figure 7c,d, showing that limiting the voltage loop bandwidth using the conventional error-calculation method reduces QIP in both currents improving the closed-loop stability. The current waveforms in Test 3 with the proposed improved error measurement approach in Figure 7e,f, show that there are no significant current perturbations when the proportional gain is again selected to *Kpv* = 0.7, so that a wide bandwidth voltage loop is obtained with a phase margin larger than 50◦ . In this case, the DPWM has been configured with 8.96-bit resolution, while the ADCs sampling the output current and the voltage error have been configured with resolutions of 12-bit and 16-bit differential mode, respectively. Figure 7g,h shows the simulated and experimental results for the Test 4, when the proportional gain is *Kpv* = 0.7 and both conditions (11) and (14) are fulfilled. Time domain current waveforms of the prototype for the different tests when it works in boost mode are shown in Figure 8. Figure 8a current waveforms for Test 1 present high current undershoot because conditions (11) and (14) are not fulfilled. The rest of test results show that the QIP is reduced, obtaining better results for the Test 4 with a *f<sup>c</sup>* = 4 kHz (Figure 8d). It is important to remark that fulfilling condition (11) for the external loop is enough to reduce QIP and

LCO at the current waveforms in steady-state when the control of the converter is a two-loop with an integrator due to the external loop not cause induced perturbations in the internal loop.

**Figure 7.** Simulated (**a**,**c**,**e**,**g**) and experimental (**b**,**d**,**f**,**h**) start-up waveforms: (**a**,**b**) Test 1, (**c**,**d**) Test 2, (**e**,**f**) Test 3, and (**g**,**h**) Test 4 (*V<sup>g</sup>* = 200 V, *v<sup>o</sup>* = 300 V, and *R<sup>o</sup>* = 200 Ω). CH1: *v<sup>o</sup>* (100 V/div). CH2: *V<sup>g</sup>* (100 V/div) CH3: *i<sup>g</sup>* (2 A/div), CH4: *i<sup>L</sup>* (2 A/div).

**Figure 8.** Time domain waveforms of *i<sup>g</sup>* and *iL*: (**a**) Test 1, (**b**) Test 2, (**c**) Test 3, (**d**) Test 4. CH3: *i<sup>g</sup>* (2 A/div), CH4: *i<sup>L</sup>* (2 A/div), and time base of 200 µs.

#### **5. Conclusions**

Limit cycle oscillations conditions due to quantization-induced perturbation in a digital two-loop current controlled converter are presented and analyzed in this paper. LCO conditions includes both loops ADCs quantization, DPWM quantization and gains of the to control laws to show the undesired quantization effects in a two-loop digital voltage regulator of a dc-dc converter with an integrator at its output. Simulation and experimental results, obtained after developing different tests on a 400 V 1.6 kW coupled-inductor buck-boost purpose-built prototype, validate that the current waveforms present perturbations when these conditions are not fulfilled. These tests also demonstrate that fulfilling the condition for the external loop is enough to reduce the quantization induced perturbations. Nevertheless, the comparison of test results suggests that fulfilling conditions for both loops is the best option to avoid LCO and QIP in the system variables. The work presents a useful guidance for the design of the PI digital controllers in DC-DC converters, in order to improve significantly the dynamic responses, increasing the voltage loop bandwidth without ADC quantization effects.

**Author Contributions:** Conceptualization, J.C. and E.V.-I.; methodology, C.G.-C.; software, C.R.; validation, C.G.-C., C.R., and R.G.; formal analysis, J.C.; investigation, C.G.-C. resources, C.R.; data curation, C.R.; writing—original draft preparation, C.G.-C. and R.G.; writing—review and editing, C.R., R.G., and E.V.-I.; visualization, C.R. and C.G.-C.; supervision, J.C.; project administration, E.V.-I.; funding acquisition, E.V.-I. All authors have read and agreed to the published version of the manuscript.

**Funding:** This work was supported by the Spanish Agencia Estatal de Investigación (AEI) and the Fondo Europeo de Desarrollo Regional (FEDER) under research projects DPI2016-80491-R (AEI/FEDER, UE) and DPI2017-84572-C2-1-R (AEI/FEDER, UE). The work was also supported by the the Chilean Government under Project CONICYT/FONDECYT 1191680 and by SERC Chile (CONICYT/FONDAP/15110019).

**Conflicts of Interest:** The authors declare no conflicts of interest.

#### **Abbreviations**

The following abbreviations are used in this manuscript.


#### **References**




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## *Article* **Analysis of Subharmonic Oscillation and Slope Compensation for a Differential Boost Inverter**

#### **Abdelali El Aroudi 1,\* ID , Mohamed Al-Numay <sup>2</sup> ID , Reham Haroun <sup>1</sup> ID and Meng Huang <sup>3</sup>**


Received: 10 July 2020; Accepted: 11 August 2020; Published: 13 August 2020

**Abstract:** This paper focuses on the steady-behavior of a differential boost inverter used for generating a sinewave AC voltage in rural areas. The analysis of its dynamics will be performed using an accurate approach based on discrete time models and Floquet theory and adopting a quasi-static approximation. In particular, the undesired subharmonic oscillation exhibited by the inverter will be analyzed and its boundary in the parameter space will be predicted and delimited. Combining analytical expressions and computational procedures to determine the quasi-static duty cycle, subharmonic oscillation is accurately predicted. It is found that subharmonic oscillation takes place at critical values of the sinewave voltage reference cycle, which can cause distortion to the input current and degrade the harmonic content of the output voltage. The results provide useful information for the design of the boost inverter to avoid distortion caused by subharmonic oscillation. Namely, the minimum value of the compensation slope and the maximum proportional gain of the AC output voltage controller guaranteeing a pure sinewave voltage and clean inductor current during the entire AC cycle will be determined. Numerical simulations performed on the switched model implemented using PSIM© software confirm the theoretical predictions.

**Keywords:** differential boost inverter; current mode control; nonlinear behavior; subharmonic oscillation; slope compensation

#### **1. Introduction**

DC-AC inverters find widespread usage in many residential, industrial and military applications. With the ever-increasing development of the renewable energy technology, DC-AC inverters have become one of the most attractive and viable solutions to the power conversion problem. They are extensively used and play key roles in various actual applications of power electronics technologies for renewable energy sources [1–3]. They are also used in motor drive [4,5] and DSTATCOM applications [6] as well as in many uninterruptible power supply system applications such as plant facilities and factories, medical equipments and centers in hospitals, airline computer and communication systems in server farms and web hosting sites [7]. One of the important tasks in the design of DC-AC inverters is the control loop implementation which must ensure a system free from any kind of instabilities. However, it is well known that this aim is difficult to be achieved for all values of system parameters and that many undesired nonlinear phenomena can arise in these kinds of indispensable parts of modern and emerging energy systems. These phenomena can significantly jeopardize the system performance and can cause serious consequences on its reliability.

*Appl. Sci.* **2020**, *10*, 5626; doi:10.3390/app10165626 www.mdpi.com/journal/applsci

Therefore, understanding these nonlinear phenomena, their analysis, prediction and control have increasingly become of great concern of many researchers all over the world [8–22]. The major part of the analytical results on subharmonic oscillation in power electronics converters has been achieved for DC-DC converters [23–40]. DC-AC inverters are more difficult to deal with, since their dynamics is governed by two vastly different frequencies, namely the high switching frequency and the low frequency of the output voltage reference sinewave.

For reliable and desirable operation, the stability of the system must be guaranteed for the whole range of its parameters. In [13], the dynamics behavior of an H-bridge under a digital Current Mode Control (CMC) was investigated by using a one dimensional discrete time model. Different dynamical behaviors for the system were revealed by varying the proportional gain of the current controller. In [14] a similar approach was applied and it was demonstrated that different types of bifurcations (instabilities) can take place such as period doubling leading to Subharmonic Oscillation (SO) and border collision bifurcations leading directly to chaotic behavior.

Using the quasi-static approximation, in [15] the slow-scale and fast-scale instabilities in a voltage-mode controlled H-bridge inverter are reported and analyzed using an averaged model and a discrete-time model respectively. It is well known that conventional averaged model cannot predict the fast-scale instability and for that the discrete-time model must be used. A closed form discrete time model was used in [16] to predict both the slow-scale and the fast-scale instabilities in an H-bridge inverter demonstrating that the system may undergo instability phenomenon when the proportional gain of the voltage controller is increased. In an H-bridge digital-controlled grid-connected inverter system, bifurcation behavior was investigated and loss of system stability was shown by increasing the current controller gain [19] and it was shown that in this system only slow scale instability may take place leading to low-frequency oscillation. The same system, but with double edge modulation, has been studied in [9] using an analytical closed-form expression for predicting a period doubling phenomenon.

Single-stage grid-connected DC-AC conversion systems with boosting voltage capability have recently attracted the attention of many researchers. Single-stage structures of inverters not only perform DC-AC conversion but also perform voltage boosting. Moreover, differential inverter topologies seem to prevail in price and size due to the utilization of small passive elements of DC-DC converters hence improving the efficiency. In contrast to the conventional H-bridge inverter, the differential boost inverter is a flexible DC-AC inverter topology providing voltage step-up capability and could be a potential candidate for many DC-AC electrical energy conversion applications such as for power processing stage fuel-cell energy system [41,42], for high quality sine wave generation with a high oscillation frequency [43], for AC-module microinverters in PV systems such as in [44–46] among others.

In stand-alone operation mode, the load is directly supplied by the inverter. Single-phase H-bridge inverters are simple bidirectional converter topologies capable of handling both real and reactive power having their performance evaluated in terms of power quality and stability. Therefore, generating a high quality output voltage with low distortion and good voltage regulation is the main target. Other relevant performance metrics include disturbance rejection, transient response, and insensitivity to load and system parameter variations. These metrics can only be achieved with a design free from any kind of instability.

Since its introduction in [47], many studies have dealt with the control design of the differential boost inverter using different approaches and strategies [44,45,47–49]. The focus in most of the works published about this inverter is on the control design. However, the analysis of its nonlinear behavior has not been addressed in the past. Namely, SO has not been studied in this kind of inverter. Therefore the aim of this paper is to apply the Floquet theory for accurately predicting the onset of SO in a differential boost inverter. In contrast to existing works on predicting such a complex behavior in DC-AC inverters based mainly on numerical procedures, here both numerical and analytical approaches are combined to provide a comprehensive study of the systems dynamical behavior.

The prediction of this phenomenon is of high importance from both theoretical and practical points of view because it leads to an increase in the ripple of the currents and voltages and this has a harmful effect on the system performances since the overall losses become more significant. The power quality can also be jeopardized if SO is more pronounced since it can increase the THD and the current stress on the switches. Therefore, accurate modeling and stability analysis are necessary for exploring the dynamic behavior and predicting the stability boundaries of DC-AC inverters.

The remaining of this paper is organized as follows. In Section 2, the system dealt with in this study is described. In Section 3, the dynamic behavior of the system is explored revealing that the behavior of the system waveforms is phase-dependent. The system is shown to exhibit local instability phenomenon over a specific interval within the main sinusoidal cycle. The onset of the observed bubbling is associated to a SO phenomenon taking place at the fast switching scale. The mathematical modeling is addressed in Section 4 in the continuous-time domain. In order to analyze the observed phenomena in Section 3, Floquet theory is applied to the derived model in Section 5. Thereafter, in Section 6, the stability boundaries in terms of suitable parameters is reported. Finally, in Section 7 the results of the study are summarized.

#### **2. Differential Boost Inverter under Two-Loop Control**

The system under study in this paper consists of a differential boost inverter which is obtained by connecting two identical DC-DC boost converters in parallel supplied from a common electrical energy source and feeding a floating voltage load connected between the outputs of the two converters [47,50]. Its schematic diagram is shown in Figure 1. The current drawn by the input is shared properly between the two boost converters by the action of a CMC scheme using the difference between the two inductor currents, as will be detailed later. For that, two complementary control signals are considered to control the switches of the differential inverter.

Let us denote the two connected converters as Converter 1 with inductor *L*<sup>1</sup> and inductor current *i*<sup>1</sup> and Converter 2 with inductor *L*<sup>2</sup> and inductor current *i*2. Both converters are controlled in a complementary way using CMC via single Pulse-Width Modulation (PWM) scheme so that Converter 2 is phase shifted 2*πD* with respect to Converter 1 at the switching time scale, *D* being the operating duty cycle. Namely, the difference between *i*<sup>1</sup> and *i*<sup>2</sup> (scaled by a sensing resistance *rs*) is controlled using a conventional peak CMC by comparing the signal *rs*(*i*<sup>1</sup> − *i*2) to the signal *r<sup>s</sup> i*ref. A periodic ramp signal *v*ramp with amplitude *V<sup>M</sup>* and period *T* is subtracted from *r<sup>s</sup> i*ref for slope compensation. The comparison of the signal *rs*(*i*<sup>1</sup> − *i*2) with the signal *r<sup>s</sup> i*ref − *v*ramp by using a comparator and a set-reset flip-flop generate the high and low values of the pulses driving the switches as shown in Figure 1 where the block diagram of the inner current control together with the outer voltage control are depicted.

The reference current for the difference between the two inductor currents is provided by an external voltage loop. The activation of the switches Q1, Q2, Q<sup>3</sup> and Q<sup>4</sup> is carried out as follows: the signal *rs*(*i*<sup>1</sup> − *i*2) is connected to the non inverting pin of the comparator whereas the signal *r<sup>s</sup> i*ref − *v*ramp is applied to the inverting pin. The output of the comparator is applied to the reset input of a set-reset flip-flop and a periodic clock signal is connected to its set input, as shown in Figure 1, in such a way that the switch Q<sup>2</sup> and Q<sup>4</sup> are ON at the beginning of each switching cycle and are turned OFF whenever *rs*(*i*<sup>1</sup> − *i*2) = *r<sup>s</sup> i*ref − *v*ramp. The state of the switches Q<sup>1</sup> and Q<sup>3</sup> are complementary to the switches Q<sup>2</sup> and Q<sup>4</sup> respectively.

To fulfill the requirements of the underlying electronic application, a DC-AC inverter has to produce a periodic sinewave-shaped output voltage under normal operational conditions. Let *v*ref(*t*) be the voltage reference that can be expressed as *v*ref(*t*) = *V*ref sin(2*π fgt*) = *V*ref sin(*ϕ*), where *ϕ* = 2*π fgt* ∈ (0, 2*π*), *V*ref is the peak value of the output voltage reference, *ω*<sup>0</sup> its angular frequency and *ϕ* its phase angle. In practical applications, the switching frequency is much higher than the AC output voltage frequency. This condition is met in this paper and it allows the use of quasi-static approximation. The error voltage *v*ref − *v<sup>o</sup>* is the input signal to the voltage controller of which the task is to make the output voltage of the inverter an AC sinusoidal signal with zero DC component. Therefore, the load connected between the converters outputs will be subjected to an AC sinusoidal voltage with a zero DC component. This control strategy is different from the one used in most of the published works about this inverter topology such as [44,45,47] where the control is performed such that each boost converter generates a DC bias and an AC component. In the low frequency averaged sense, the AC component of each converter is out of phase regarding the other converter. The DC component is the same for both converters.

The voltage controller is conventionally a PI regulator aiming to make the load voltage *v<sup>o</sup>* to accurately track the sinewave voltage reference *v*ref. Its transfer function can be expressed as *H*pi(*s*) = *kp*(*τs* +1)/(*sτ*), where *k<sup>p</sup>* is its proportional gain and *τ* is its time constant.

**Figure 1.** The differential boost inverter under two-loop control.

#### **3. Behavior of the Differential Boost Inverter**

The dynamical behavior of the boost inverter is explored in this section with the aim to gain insight on suitable ways of obtaining an appropriate model that can be used for its accurate stability analysis. The system is first studied through simulations using the full-order switched model of the inverter implemented using PSIM© software by varying suitable system parameters. The focus is first on system stability in terms of the time varying voltage reference. The fixed parameter values used for the rest of the study are reported in Table 1. Many time-domain waveforms have been computed to get a clear view of the system behavior and only representative results are shown below. The simulation is run for sufficiently long time to allow the system to reach its steady-state. The data obtained during time transient within the startup phase and during the transient regime of the regulation phase are fully eliminated. Only the last two cycles of the output voltage reference are plotted.

**Table 1.** The used parameters for the DC-AC differential boost inverter.


Figure 2 shows the system waveforms when the system is stable. The figure shows the time-domain waveforms of the reference voltage *v*ref and the output voltage *vo*, the capacitor voltages *vo*<sup>1</sup> and *vo*2, the inductor currents *i*<sup>1</sup> and *i*<sup>2</sup> and the control signal *rs*(*i*<sup>1</sup> − *i*2) and the signal *r<sup>s</sup> i*ref − *v*ramp. It is worth noting that the output voltage cannot be distinguished from its reference signal *v*ref due to the practically zero amplitude and phase errors. Note also that the state variables and the control signal oscillate at two main frequencies, the switching frequency (100 kHz) and the reference voltage frequency (50 Hz). From a practical point of view, the output voltage is characterized by a low value of THD as required in any application.

As parameters are varied, the state variables undergo a sudden distortion by exhibiting SO at the fast switching scale as shown in Figure 3 for *k<sup>p</sup>* = 0.4. This phenomenon takes place when the proportional gain *k<sup>p</sup>* gradually increases and reaches a critical value close to 0.22. As shown in Figure 3, it can be observed that the inductor currents *i*<sup>1</sup> and *i*<sup>2</sup> exhibit SO leading to disrupting bubbling phenomenon of the waveforms. In particular, when *k<sup>p</sup>* ≈ 0.22, the fast-scale instability develops in all the state variables but it is more visible and pronounced in the inductor current waveforms *i*<sup>1</sup> and *i*<sup>2</sup> and their combination *rs*(*i*<sup>1</sup> − *i*2). As stated before, such behavior manifests itself as a period-doubling phenomenon at the fast switching scale [9,51]. It can also be noticed in Figure 4 that the phenomenon already becomes visible in the capacitor voltages and the output voltage hence it can deteriorate the performance of the inverter and therefore its prediction is an important task from a practical point of view.

**Figure 2.** Steady-state response of boost inverter with *k<sup>p</sup>* = 0.2 and *V<sup>M</sup>* = 2 V. (**a**) Capacitor voltages *vo*<sup>1</sup> and *vo*2, output and reference voltages *v<sup>o</sup>* and *v*ref. (**b**) Inductor currents *i*<sup>1</sup> and *i*<sup>2</sup> and control signals *rs*(*i*<sup>1</sup> − *i*2) and *rsi*ref − *v*ramp. For each subplot, traces correspond to the shown voltages in [V] and currents in [A].

**Figure 3.** Steady-state response of boost inverter with *k<sup>p</sup>* = 0.4 and *V<sup>M</sup>* = 2 V. (**a**) Capacitor voltages *vo*<sup>1</sup> and *vo*2, output and reference voltages *v<sup>o</sup>* and *v*ref. (**b**) Inductor currents *i*<sup>1</sup> and *i*<sup>2</sup> and control signals *rs*(*i*<sup>1</sup> − *i*2) and *rsi*ref − *v*ramp. For each subplot, traces correspond to the shown voltages in [V] and currents in [A].

**Figure 4.** Steady-state response of boost inverter with *k<sup>p</sup>* = 0.8 and *V<sup>M</sup>* = 2 V. (**a**) Capacitor voltages *vo*<sup>1</sup> and *vo*2, output and reference voltages *v<sup>o</sup>* and *v*ref. (**b**) Inductor currents *i*<sup>1</sup> and *i*<sup>2</sup> and control signals *rs*(*i*<sup>1</sup> − *i*2) and *rsi*ref − *v*ramp. For each subplot, traces correspond to the shown voltages in [V] and currents in [A].

By carefully examining the waveforms, the following statements can be made:


A powerful tool for clearly illustrating the SO phenomenon is by using the sampled waveforms. In order to clearly appreciate the change in the behavior of the system, sampled steady-state values of the state variables at time instants *<sup>t</sup>* <sup>=</sup> *nT* (*<sup>n</sup>* <sup>∈</sup> <sup>N</sup>) are obtained. Therefore, the state variables are sampled at every clock instant and then plotted in the time domain. A priori, any one of the state variables can be used for illustrating the behavior of the system. However, as observed in the previous time domain numerical simulations, SO is more pronounced in some state variables than others. An interesting and naturally sampled variable for which SO is well noticed is the duty cycle of the binary signal *u*.

Figure <sup>5</sup> shows the waveforms of the duty cycle *<sup>d</sup>*(*nT*) (*<sup>n</sup>* <sup>∈</sup> <sup>N</sup>) during one complete sinewave cycle for four different values of the proportional gain *kp*. The duty cycle waveforms are plotted in terms of the phase angle within the interval (0, 2*π*). For *k<sup>p</sup>* = 0.2, the system exhibits a stable periodic regime in steady-state, the duty cycle does not present any disruption and its samples represent a clean and smooth waveform. When the SO regime starts taking place, one gets a different picture. For instance, for *k<sup>p</sup>* = 0.4, it can be clearly seen that there is a certain phase interval within the first half of the sinewave cycle during which the duty cycle waveforms is disrupted. Namely, within the phase interval defined by two critical phase angles, two different branches of duty cycle values appear instead of one a kind of bubble emerges [18]. It can be observed that the onset of bubbling phenomenon depicted in Figure 5 is gradual. First, for a relatively small value of the parameter *kp*, the cycle is smooth, then, for increasing *kp*, it becomes disrupted in a small phase interval. Thereafter, as *k<sup>p</sup>* is further increased, the interval (*ϕ*1, *ϕ*2) of *ϕ* during which SO takes place grows up as can be seen in Figure 5. If the proportional gain is further increased, this interval gets wider and the phenomenon usually spreads through the whole line cycle. Figure 5 also shows that successive period doubling inside the SO interval may also take place in the first half cycle where the voltage reference is positive, i.e., when *D* > 0.5. When *k<sup>p</sup>* becomes even larger, the bubbles start appearing even in the second half cycle of voltage reference where *D* < 0.5. Therefore, even for *D* < 0.5, the voltage loop may have a destabilizing effect since when the proportional gain *k<sup>p</sup>* is increased beyond a critical value *<sup>k</sup><sup>p</sup>* <sup>≈</sup> 0.8, SO and the associated bubbling starts appearing for *<sup>D</sup>* <sup>&</sup>lt; 0.5 and even in the presence of slope compensation. Therefore, the ramp slope needed for eliminating SO is larger than the one obtained when ignoring the effect of the voltage loop. This destabilizing effect of the voltage loop is similar to the one reported in [27] for the buck converter and in [24] for the boost

converter. Similar behaviors have been obtained when other parameters such as the input voltage *V<sup>g</sup>* or the inductance *L* are varied.

**Figure 5.** Waveforms of the duty cycle *d*(*nT*) at steady-state operation in terms of the phase angle in [◦ ] for different values of *k<sup>p</sup>* and for *V<sup>M</sup>* = 2 V.

#### **4. Continuous-Time Modeling of the Differential Boost Inverter**

#### *4.1. Quasi-Steady-State Analysis*

From the simulation results presented in the previous section, it has been observed that SO takes place when suitable parameters are varied. One of the widespread tools to analyze and to investigate this kind of nonlinear behavior is Floquet theory [52,53]. Considering the switched model of the system, one can identify possible periodic orbits, their stability as well as several other important aspects of the

dynamical behavior. To apply this theory, the mathematical model is first derived. By applying KVL and KCL, the switched model of the differential boost inverter can be expressed as follows

$$\frac{\mathbf{d}i\_1}{\mathbf{d}t} = \frac{1}{L\_1}(V\_\mathcal{g} - v\_{o2}(1-u)) - \frac{r\_1}{L\_1}i\_1 \tag{1}$$

$$\frac{\text{d}i\_2}{\text{d}t}\_{\text{d}} = \frac{1}{L\_2}(V\_{\text{\textdegree}} - \mu v\_{o2}) - \frac{r\_2}{L\_2}i\_{2\prime} \tag{2}$$

$$\frac{\mathbf{d}v\_{o1}}{\mathbf{d}t} = \frac{1}{C\_1}((1-\mu)i\_1 + \frac{v\_{o1} - v\_{o2}}{R}),\tag{3}$$

$$\frac{\text{d}v\_{o2}}{\text{d}t}^{\text{d}} = \frac{1}{C\_2} (\dot{u}i\_2 - \frac{v\_{o1} - v\_{o2}}{R}) ,\tag{4}$$

where *L*<sup>1</sup> and *L*<sup>2</sup> are the inductance of the inductors of the differential boost inverter with stray resistances *r*<sup>1</sup> and *r*<sup>2</sup> respectively, *C*<sup>1</sup> and *C*<sup>2</sup> are the capacitances of their capacitors. *V<sup>g</sup>* is the DC input voltage and *R* is the AC load resistance. All other parameters appearing in (1)–(4) are shown in Figure 1. The quasi-steady-state average values of the state variables are related to the quasi-steady-state duty cycle *D* by the following expressions:

$$I\_1 \quad = \quad \frac{V\_\mathcal{S}(2D-1)}{RD(1-D)^2}, \quad I\_2 = -\frac{V\_\mathcal{S}(2D-1)}{RD^2(1-D)}\tag{5}$$

$$V\_{o1} = \frac{V\_{\mathcal{S}}}{1 - D'} \qquad V\_{o2} = \frac{V\_{\mathcal{S}}}{D} \tag{6}$$

These expressions have been obtained by using the averaged model of the inverter within a switching period. Using (6) and the fact that *v<sup>o</sup>* = *vo*<sup>1</sup> − *vo*2, the voltage gain of the differential boost inverter can be expressed as follows

$$M(D) := \frac{v\_{\text{ref}}}{V\_{\text{\\_}}} = \frac{2D - 1}{D(1 - D)}\tag{7}$$

The inverter gain *M*(*D*) reaches its maximum value *M*max = *V*ref/*V<sup>g</sup>* when the voltage reference *v*ref reaches its peak value *V*ref. From the expression of *M*(*D*), the steady-state value of the duty cycle can be derived and this can be expressed as follows

$$D(t) = \begin{cases} \frac{1}{2} - \frac{V\_{\mathcal{S}}}{v\_{\text{ref}}} + \frac{\sqrt{4V\_{\mathcal{S}}^2 + v\_{\text{ref}}^2}}{2v\_{\text{ref}}} & \text{if } v\_{\text{ref}}(t) > 0, \\\frac{1}{2} - \frac{V\_{\mathcal{S}}}{v\_{\text{ref}}} - \frac{\sqrt{4V\_{\mathcal{S}}^2 + v\_{\text{ref}}^2}}{2v\_{\text{ref}}} & \text{if } v\_{\text{ref}}(t) < 0. \end{cases} \tag{8}$$

In terms of the phase angle *ϕ*, the quasi-steady-state duty cycle can be expressed as follows

$$D(\boldsymbol{\varrho}) = \begin{cases} \frac{1}{2} - \frac{1}{M\_{\text{max}} \sin(\boldsymbol{\varrho})} + \sqrt{M\_{\text{max}} + \frac{1}{4}} & \text{if } \boldsymbol{\varrho} \in (0, \pi), \\\frac{1}{2} - \frac{1}{M\_{\text{max}} \sin(\boldsymbol{\varrho})} - \sqrt{M\_{\text{max}} + \frac{1}{4}} & \text{if } \boldsymbol{\varrho} \in (\pi, 2\pi). \end{cases} \tag{9}$$

#### *4.2. The State-Space Switched Model*

Let **x** = (*i*1, *i*2, *vo*1, *vo*2,) <sup>⊺</sup> be the vector of the state variables of the power stage of the inverter. The system can be described by a piecewise linear switched model as follows

$$\dot{\mathbf{x}} \quad = \quad \mathbf{A}\_1 \mathbf{x} + \mathbf{B}\_1 V\_{\mathcal{R}'} \quad \text{for} \quad \boldsymbol{\mu} = 1,\tag{10}$$

$$\dot{\mathbf{x}} \quad = \quad \mathbf{A}\_0 \mathbf{x} + \mathbf{B}\_0 V\_{\mathcal{S}'} \quad \text{for} \quad u = 0,\tag{11}$$

$$
\psi\_i \quad = \quad \upsilon\_{\text{ref}} - (\upsilon\_{o1} - \upsilon\_{o2}) = \upsilon\_{\text{ref}} - \mathbf{C}^{\mathsf{T}} \mathbf{x} \tag{12}
$$

where **C** <sup>⊺</sup> = (0 0 1 − <sup>1</sup>) and *<sup>v</sup><sup>i</sup>* := R (*v*ref <sup>−</sup> *<sup>v</sup>o*)d*<sup>t</sup>* is the integral of the error signal *<sup>v</sup>*ref <sup>−</sup> *<sup>v</sup>o*. **<sup>A</sup>**<sup>0</sup> <sup>∈</sup> <sup>R</sup>4×<sup>4</sup> , **<sup>A</sup>**<sup>1</sup> <sup>∈</sup> <sup>R</sup>4×<sup>4</sup> , **<sup>B</sup>**<sup>0</sup> <sup>∈</sup> <sup>R</sup>4×<sup>1</sup> and **<sup>B</sup>**<sup>1</sup> <sup>∈</sup> <sup>R</sup>4×<sup>1</sup> are the system state matrices presented below. The variable *<sup>v</sup><sup>i</sup>* was deliberately separated from the rest of state variables to avoid matrix singularities appearing in the expressions of the system trajectories and their steady-state values at the switching time instants [25,26]. The matrices **A**1, **A**0, **B**<sup>1</sup> and **B**<sup>0</sup> are as follows:

$$\mathbf{A}\_{1} = \begin{pmatrix} -\frac{r\_{1}}{L\_{1}} & 0 & 0 & 0\\ 0 & -\frac{r\_{2}}{L\_{2}} & 0 & -\frac{1}{L\_{2}}\\ 0 & 0 & -\frac{1}{RC\_{1}} & \frac{1}{RC\_{1}}\\ 0 & \frac{1}{C\_{2}} & \frac{1}{RC\_{2}} & -\frac{1}{RC\_{2}} \end{pmatrix}, \qquad \mathbf{B}\_{1} = \begin{pmatrix} 1\\ \frac{1}{L\_{1}}\\ \frac{1}{L\_{2}}\\ 0\\ 0 \end{pmatrix} \tag{13}$$
 
$$\begin{pmatrix} -\frac{r\_{1}}{L\_{1}} & 0 & -\frac{1}{L\_{2}} & 0 \end{pmatrix} \tag{14}$$

$$\mathbf{A}\_{0} = \begin{pmatrix} -\frac{1}{L\_{1}} & 0 & -\frac{1}{L\_{1}} & 0\\ 0 & -\frac{r\_{2}}{L\_{2}} & 0 & 0\\ \frac{1}{C\_{1}} & 0 & -\frac{1}{RC\_{1}} & \frac{1}{RC\_{1}}\\ 0 & 0 & \frac{1}{RC\_{2}} & -\frac{1}{RC\_{2}} \end{pmatrix}, \qquad \mathbf{B}\_{0} = \begin{pmatrix} 1\\ \frac{1}{L\_{1}}\\ \frac{1}{L\_{2}}\\ 0\\ 0 \end{pmatrix} \tag{14}$$

The output of the voltage PI voltage controller providing the current reference for the control signal *rs*(*i*<sup>1</sup> − *i*2) can be expressed as follows

$$k\_{\rm s} i\_{\rm ref} = \left. k\_p (v\_{\rm ref} - \mathbf{C}^{\sf T} \mathbf{x}) + \mathcal{W}\_{\rm l} v\_{\rm l} \right. \tag{15}$$

Therefore, the switching condition when the signal *rs*(*i*<sup>1</sup> − *i*2) reaches its peak value *r<sup>s</sup> i*ref − *v*ramp within a switching cycle is given by

$$k\_p(\upsilon\_{\text{ref}} - \mathbf{C}^\mathsf{T} \mathbf{x}) + \mathcal{W}\_l \upsilon\_l - (\upsilon\_{\text{ramp}}(t) + r\_s(i\_1 - i\_2)) = 0,\tag{16}$$

which can be expressed in the following form

$$k\_p v\_{\text{ref}} + \mathbf{Kx}(t) + \mathcal{W}\_i v\_i(t) - v\_{\text{ramp}}(t) = 0,\tag{17}$$

where **K** = (−*r<sup>s</sup> r<sup>s</sup>* − *k<sup>p</sup> kp*) is the vector of feedback coefficients.

#### **5. Accurate Stability Analysis Using Floquet Theory**

The differential equations describing the dynamics of switching converters are time periodic with the switching period *T* determining the periodicity of solutions at the fast switching scale. DC-AC inverters are also time periodic with the switching period *T* and the voltage reference period *T<sup>g</sup>* = 1/ *fg*. For such time periodic systems Floquet theory can be used to study the stability of periodic orbits [53]. Here, this theory

will be applied using a quasi-static approximation treating the DC-AC inverter as a DC-DC converter with a slowly varying reference voltage and duty cycle. With this approximation, the reference voltage *v*ref is considered constant within a switching cycle.

Floquet theory has been widely used in the analysis of stability of dynamical systems [53] in general and switching converters in particular [38–40]. For DC-DC converters, the stability dynamics at the fast switching cycle can be accurately predicted by analyzing the stability of the fixed points of the Poincaré map of the system using its Jacobian matrix or using Floquet theory combined with Filippov method which leads to the same results as the Poincaré map [38]. The main tool for studying the stability of periodic orbits using Floquet theory is the principal fundamental matrix or the monodromy matrix **M**. This matrix plays a key role in the accurate stability analysis of switching systems [38–40,53]. The monodromy matrix is such that the dynamics in the vicinity of a quasi-static periodic orbit can be expressed as follows

$$\|\mathbf{\hat{x}}(t+T) = \mathbf{M}\mathbf{\hat{x}}(t)\qquad\forall t\tag{18}$$

where the overhat stands for small signal variations. Its eigenvalues are called the *characteristic multipliers* or *Floquet multipliers* and it can be seen that they determine the amount of contraction or expansion near a periodic orbit and hence they determine the stability of these periodic orbits.

Let us start by finding the monodromy matrix **M**. Let **x**(*t*) ≈ **x**(*t* + *T*) the quasi-steady-state value of the state vector. Let **<sup>x</sup>**(*DT*) = (**<sup>I</sup>** <sup>−</sup> **<sup>Φ</sup>**) <sup>−</sup>1**<sup>Ψ</sup>** <sup>≈</sup> **<sup>x</sup>**(*t*) <sup>≈</sup> **<sup>x</sup>**(*DT*) be the value of **<sup>x</sup>**(*t*) at time instant *DT*, where **Φ** = **Φ**1**Φ**0, **Φ**<sup>1</sup> = *e* **A**1*DT* , **Φ**<sup>0</sup> = *e* **A**0(1−*D*)*T* , **Ψ**<sup>1</sup> = (*e* **<sup>A</sup>**1*DT* <sup>−</sup> **<sup>I</sup>**)**<sup>A</sup>** −1 1 **B***Vg*, **Ψ**<sup>0</sup> = (*e* **<sup>A</sup>**0(1−*D*)*<sup>T</sup>* <sup>−</sup> **<sup>I</sup>**)**<sup>A</sup>** −1 0 **B***Vg*, **Ψ** = **Φ**1**Ψ**<sup>0</sup> + **Ψ**1. Let **m**1(**x**(*t*)) = **A**1**x**(*t*) + **B**1*V<sup>g</sup>* and **m**0(**x**(*t*)) = **A**0**x**(*t*) + **B**0*V<sup>g</sup>* be the vector fields for *u* = 1 and *u* = 0 respectively. Let us define the augmented state vector **x***<sup>a</sup>* = (*i*1, *i*2, *vo*1, *vo*2, *vi*) ⊺ . Let **A***a*1, **A***a*0, **B***a*1, **B***a*0, **w***<sup>a</sup>* and **K***<sup>a</sup>* be, respectively, the associated augmented state matrices, input vectors, vector of external parameters and vector of feedback coefficients that are expressed as follows

$$\mathbf{A}\_{a1} = \begin{pmatrix} \mathbf{A}\_1 & \mathbf{0} \\ -1 & \mathbf{0} \end{pmatrix}, \mathbf{B}\_{a1} = \begin{pmatrix} \mathbf{B}\_1 & 0 \\ \mathbf{0} & 1 \end{pmatrix} \tag{19}$$

$$\mathbf{A}\_{a0} \quad = \begin{pmatrix} \mathbf{A}\_0 & \mathbf{0} \\ -1 & \mathbf{0} \end{pmatrix}, \ \mathbf{B}\_{a0} = \begin{pmatrix} \mathbf{B}\_0 & 0 \\ \mathbf{0} & 1 \end{pmatrix} \tag{20}$$

$$\mathbf{K}\_d \quad = \begin{pmatrix} \mathbf{K} \ \mathbf{W}\_i \end{pmatrix}, \mathbf{w}\_d = \begin{pmatrix} V\_{\mathcal{S}} \\ v\_{\text{ref}} \end{pmatrix} \tag{21}$$

Let us also define the augmented state transition matrices **Φ***a*<sup>1</sup> = *e* **<sup>A</sup>***a*1*DT* and **Φ***a*<sup>0</sup> = *e* **A***a*0(1−*D*)*T* and the augmented vector fields **m***a*1(**x***a*(*t*)) = **A***a*1**x***a*(*t*) + **B***a*1**w***<sup>a</sup>* and **m***a*0(**x***a*(*t*)) = **A***a*0**x***a*(*t*) + **B***a*0**w***a*. Then, the full-order monodromy matrix can be expressed as follows [38]

$$\mathbf{M} = \Phi\_{a0} \mathbf{S} \Phi\_{a1} \tag{22}$$

where **S** is the saltation matrix adapted from [38] as follows

$$\mathbf{S} = \mathbf{I} + \frac{(\mathbf{m}\_{d0}(\mathbf{x}\_d(DT)) - \mathbf{m}\_{d1}(\mathbf{x}\_d(DT)))\mathbf{K}\_d^\mathsf{T}}{W\_l(v\_{\text{ref}} - v\_o(DT)) + \mathbf{K}^\mathsf{T}\mathbf{m}\_1(\mathbf{x}(DT)) - m\_{\text{ramp}} - m\_{\text{ref}}}.\tag{23}$$

where *m*ramp = *VM*/*T* is the slope of the ramp compensator and *m*ref = *kpV*ref2*π f<sup>g</sup>* cos(2*π fgDT*) is the slope contributed by the time variation of the sinusoidal voltage reference. The expression of *vi*(*DT*),

the third component of **x***a*(*DT*), can be obtained from (17) in steady-state which gives the following expression for *vi*(*DT*)

$$w\_i(DT) = \frac{1}{W\_i} (m\_{\text{ramp}}DT - \mathbf{K}^{\text{I}}\mathbf{x}(DT) - k\_p v\_{\text{ref}}) \tag{24}$$

Now that the expression of the monodromy matrix was derived, hereinafter, we will pay special attention to the movement of the Floquet multipliers as the voltage reference *v*ref varies quasi-statically. This is equivalent to changing the phase angle *ϕ* or the quasi-steady-state duty cycle *D*. We will also study the movement of the Floquet multipliers when the proportional gain *k<sup>p</sup>* of the controller or the amplitude of the ramp compensator *V<sup>M</sup>* are varied. Any crossing from the interior of the unit circle to its exterior indicates a lost of stability of the desired orbit. The system becomes unstable, if at least one root of the Floquet multiplier leaves the unit circle, which is equivalent to an eigenvalue **M** leaving the unit circle. Thus, for the stability boundary |*λ*| = 1 for at least one eigenvalue of **M** holds. In particular, if a real characteristic multiplier goes through −1 as it moves out of the unit circle, SO at the fast switching scale takes place.

To locate the boundary of SO, the Floquet multipliers are obtained. By varying the quasi-steady-state duty cycle *D*, the operating point **x**(*DT*) was first calculated and the monodromy matrix was obtained for two different values of the proportional gain *kp*. At a point where a subharmonic regime emerges, one of the eigenvalues is equal to −1. Figure 6 shows the Floquet multipliers loci in the complex plane when the quasi-steady-state duty cycle varies. The duty cycle *D* was varied by varying the voltage reference between 0 and its maximum values giving rise to *D* ∈ (0.5, 0.68). As it can be observed from Figure 6a, for *k<sup>p</sup>* = 0.2 all the eigenvalues remain inside the unit circle for the full considered range of the duty cycle. Then, the gain *k<sup>p</sup>* was fixed at *k<sup>p</sup>* = 0.24 then the reference voltage was varied in the same range as before and the results are depicted in Figure 6b. It can be observed that one of the eigenvalues of the monodromy matrix crosses the unit circle from the point (−1, 0) in the complex plane indicating SO at a certain value of *v*ref very close to its maximum value. The critical value of *k<sup>p</sup>* at which this starts taking place is *k<sup>p</sup>* ≈ 0.22 which is in a remarkable agreement with the time-domain numerical simulations presented in Section 3.

(**a**) *<sup>V</sup>*ref <sup>∈</sup> (0, 230<sup>√</sup> 2) V (*D* ∈ (0.5, 0.68)) and *k<sup>p</sup>* = 0.20.

**Figure 6.** *Cont.*

(**b**) *<sup>V</sup>*ref <sup>∈</sup> (0, 230<sup>√</sup> 2) V (*D* ∈ (0.5, 0.68)) and *k<sup>p</sup>* = 0.24.

**Figure 6.** Floquet multipliers loci by varying the quasi-steady-state duty cycle *D* for two different values of the proportional gain *kp*.

#### **6. Stability Boundaries in the Parameter Space**

If SO boundary is of concern, the expression of the characteristic equation det(**M** − *λ***I**) = 0 can be used by imposing that an eigenvalue *λ* = −1 and solving the resulting equation in a suitable projection of the parametric space. Therefore, to determine the boundary of SO, the following equation is solved for a certain system parameter after fixing the other ones

$$\det(\mathbf{M} + \mathbf{I}) = 0 \tag{25}$$

The great advantage of using (25) is that only this equation has to be solved without the need of computing all eigenvalues of **M** explicitly. Therefore, instead of solving for all eigenvalues of **M**, only (25) is solved, hence, the saving of computational load is significant when the stability boundary is to be determined.

Figure 7 shows the stability boundary resulted from solving (25) with respect to the proportional gain *k<sup>p</sup>* for values of the duty cycle within the operating range (0.5, 0.68) and for a value of the ramp compensator amplitude *V<sup>M</sup>* = 2 V. Within one sinewave signal one has 2000 switching cycles. Therefore, the plot was generated using 1000 values of the duty cycles and the critical values of *k<sup>p</sup>* were registered in terms of *D*. In particular, for *V<sup>M</sup>* = 2 V, the critical value of the proportional gain guaranteeing that all the eigenvalues lie inside the unit circle for all values of the operating duty cycle is about 0.2. This is in perfect agreement with the numerical simulations presented in Section 3. If *V<sup>M</sup>* is increased, the critical value of the proportional gain also increases and the stability region gets wider as depicted in Figure 8. In particular, for *V<sup>M</sup>* = 3 V, the critical value of the proportional gain is about 0.73, for *V<sup>M</sup>* = 4 V, is about 1.28 and for *V<sup>M</sup>* = 5 V, it is about 1.82. Notice that for a fixed switching period *T*, changing the ramp amplitude is equivalent to changing its slope.

**Figure 7.** Stability boundaries in terms of the proportional gain *k<sup>p</sup>* and the quasi-steady-state duty cycle *D* and for *V<sup>M</sup>* = 2 V.

**Figure 8.** Stability boundaries in terms of the proportional gain *k<sup>p</sup>* and the quasi-steady-state duty cycle *D* for different values of the ramp amplitude *VM*.

As stated previously, in DC-AC inverters, the reference voltage is a time varying sinusoidal signal and accordingly the steady-state quasi-static duty cycle *D* is given by (8). In such a situation, the phase *ϕ* is a quasi-static parameter like *D*. Solving (9) in terms of the phase angle *ϕ*, one gets two critical values of the phase angle that can be expressed as follows

$$\varphi\_1 = \quad \sin^{-1}(\frac{V\_\mathcal{S}(2D-1)}{V\_{\text{ref}}D(1-D)}) \tag{26}$$

$$\varphi\_2 = \pi - \sin^{-1}(\frac{V\_\mathcal{S}(2D-1)}{V\_{\text{ref}}D(1-D)}) \tag{27}$$

These closed expressions for the critical phase angles at which SO develops explain the observation made in Section 3. In terms of the inverter gain *M*(*D*) and its maximum value *M*max, the expressions of the phase angles are given by

$$\varphi\_1 \quad = \quad \sin^{-1}(\frac{M(D)}{M\_{\text{max}}}) \tag{28}$$

$$\varphi\_2 = -\pi - \sin^{-1}(\frac{M(D)}{M\_{\text{max}}}) \tag{29}$$

The stability boundary of the system is plotted in Figure 9, in terms of the proportional gain *k<sup>p</sup>* of the voltage controller and the phase angle *ϕ* ∈ (0, *π*). Vertical dashed lines in Figure 9 indicate this theoretical critical value for the set of parameter values shown in Table 1. For each specific union of *ϕ*<sup>1</sup> and *ϕ*<sup>2</sup> curves, it can be noted that there is a turning point at the left side of the union. The system will be stable at the left of the turning point and will exhibit an SO phenomenon at its right side. For instance, let *k<sup>p</sup>* = 0.2; the system is stable during the entire sinewave cycle as already observed in Figure 5a. When the proportional gain *k<sup>p</sup>* is increased beyond its critical value, SO takes place within a certain phase interval, the length of which is determined by the intersection points between vertical lines corresponding to specific values of *k<sup>p</sup>* and the two curves of *ϕ*<sup>1</sup> and *ϕ*2. Notice that the length of the SO interval gets larger when the proportional gain increases. For instance, for *k<sup>p</sup>* = 0.4, it is expected from Figure 9 that the system will exhibit SO in the phase interval (*ϕ*1, *ϕ*2) = (46◦ , 134◦ ) which is in close agreement with the numerical simulation depicted in Figure 5b. For *k<sup>p</sup>* = 0.6, the expected SO interval is (*ϕ*1, *ϕ*2) = (24◦ , 156◦ ) which is in close agreement with Figure 5c and for *k<sup>p</sup>* = 0.8, the expected SO interval is (*ϕ*1, *ϕ*2) = (7 ◦ , 173◦ ) which is in close agreement with Figure 5d.

**Figure 9.** Critical phase angles in [◦ ] defining the SO interval in terms of the proportional gain *kp*.

The estimated values of the critical phase angles from Figure 9 defining the SO interval differ slightly from the numerical simulation result in Figure 5. The discrepancies between the theoretically predicted values in Figure 9 and the ones obtained from numerical simulations depicted in Figure 5 can be attributed to two main factors. The first one is the use of the quasi-static approximation. The second one is the fact that at the point where bubbling develops its amplitude is extremely small making it invisible in

the scale used for representing the complete waveforms of the duty cycle during one entire sinewave cycle. By zooming close the critical values of *ϕ*, more accurate data can be obtained and discrepancies decrease significantly.

As has been shown in Figure 8, the maximal value of the proportional gain *k<sup>p</sup>* guaranteeing stability during the entire the sinewave cycle depends on the ramp amplitude *VM*. Therefore, the critical phase angle curves depicted in Figure 9 are also obtained for different values of *V<sup>M</sup>* and the results are depicted in Figure 10. For each ramp amplitude *VM*, a value of the proportional gain *k<sup>p</sup>* selected at the left of the corresponding turning point will guarantee no presence of SO during the entire sinewave cycle. Note that as the ramp amplitude *V<sup>M</sup>* increases the maximal value allowed for the proportional gain *k<sup>p</sup>* also increases.

**Figure 10.** Critical phase angles in [◦ ] defining the SO interval in terms of the proportional gain *k<sup>p</sup>* for different values of the ramp amplitude *VM*.

#### **7. Conclusions**

This paper has focused on the subharmonic oscillation boundary leading to bubbling phenomenon in a single-phase DC-AC differential boost inverter with a linear resistive load. This work has provided a comprehensive study of the system and stability problems of the system were discussed in order to determine stabilizing parameter space. This facilitates convenient selection of parameter values to avoid distortion due to subharmonic oscillation instability in some intervals of the sinewave voltage reference. Therefore, the results are useful for practical design of DC-AC inverters to ensure a stable operation and hence maintain a high power quality and ensuring low and acceptable values of THD. By using time domain waveforms computed from the circuit-level switched model of the system, it was shown that the differential boost inverter could exhibit subharmonic oscillation instabilities at the fast switching scale. Stable and unstable zones of operation, critical parameter values and stability boundaries have been determined. Floquet theory combined with quasi-static approximation has been used resulting in accurately locating the critical values of the system parameters. The theoretical predictions are in perfect agreement with the results obtained from numerical simulations performed on the circuit-level switched model of the inverter. The methodology presented in this study can be applied to other inverter topologies.

**Author Contributions:** Conceptualization, A.E.A.; methodology, A.E.A. software, A.E.A.; validation, M.A.-N.; formal analysis, A.E.A.; investigation, A.E.A.; resources, M.A.-N.; data curation, R.H.; writing—original draft preparation, A.E.A.; writing—review and editing, M.A.-N. and M.H.; visualization, M.A.-N., R.H. and M.H.; supervision, M.A.-N.; funding acquisition, M.A.-N. All authors have read and agreed to the published version of the manuscript.

**Funding:** This work has been sponsored by the Spanish Agencia Estatal de Investigación (AEI) and the Fondo Europeo de Desarrollo Regional (FEDER) under grants DPI2017-84572-C2-1-R. A. El Aroudi and M. Al-Numay acknowledge financial support from the Researchers Supporting Project number (RSP-2020/150), King Saud University, Riyadh, Saudi Arabia.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **Abbreviations**

The following abbreviations are used in this manuscript:


#### **References**




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