**Demonstration of AlGaN**/**GaN MISHEMT on Si with Low-Temperature Epitaxy Grown AlN Dielectric Gate**

**Matthew Whiteside 1,\* , Subramaniam Arulkumaran <sup>2</sup> , Yilmaz Dikme <sup>3</sup> , Abhinay Sandupatla <sup>1</sup> and Geok Ing Ng 1,2,\***


Received: 11 October 2020; Accepted: 3 November 2020; Published: 5 November 2020

**Abstract:** AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MISHEMT) with a low-temperature epitaxy (LTE)-grown single crystalline AlN gate dielectric were demonstrated for the first time and the post-gate annealing effects at 400 ◦C were studied. The as-deposited LTE-AlN MISHEMT showed a maximum drain current (IDmax) of 708 mA/mm at a gate bias of 4 V and a maximum extrinsic transconductance (gmmax) of 129 mS/mm. The 400 ◦C annealed MISHEMT exhibited an increase of 15% in gmmax, an order of magnitude reduction in reverse gate leakage and about a 3% suppression of drain current (ID) collapse. The increase of gmmax by post-gate annealing is consistent with the increase of 2DEG mobility. The suppression of I<sup>D</sup> collapse and the reduction of gate leakage current is attributed to the reduction of interface state density (5.0 <sup>×</sup> <sup>10</sup><sup>11</sup> cm−<sup>2</sup> eV−<sup>1</sup> ) between the AlN/GaN interface after post-gate annealing at 400 ◦C. This study demonstrates that LTE grown AlN is a promising alternate material as gate dielectric for GaN-based MISHEMT application.

**Keywords:** LTE; AlN; AlGaN/GaN; interface state density; conductance-frequency; MISHEMT

#### **1. Introduction**

AlGaN/GaN based high-electron-mobility transistors (HEMTs) have demonstrated excellent high-frequency and high-power performance owing to their excellent material properties, such as large breakdown field, wide band gap and high electron mobility [1–4]. However, two of the major limiting factors that conventional GaN HEMTs with Schottky metal gates suffer from are a high gate leakage current, and current collapse [5]. The high gate-leakage occurs due to the Schottky metal contact, while current collapse is caused by charge trapping at the surface states present on the AlGaN surface. To solve these issues, various materials such as Al2O<sup>3</sup> [6,7], HfO<sup>2</sup> [8] or ZrO<sup>2</sup> [9] have been used as both a passivation layer and gate dielectrics. Among non-oxide insulators, AlN is an attractive high-k dielectric material for III–N metal-insulator-semiconductor high-electron-mobility transistors (MISHEMTs) due to its high breakdown field and high dielectric constant [10,11]. In addition, AlN is of interest due to its high thermal conductivity (200 WK−1m−<sup>1</sup> ), which makes it suitable for use as a passivation layer to suppress the self-heating [12]. AlN has also been reported to help reduce current collapse [13]. There are two main methods used for the deposition of AlN namely metal-organic chemical vapor deposition [14] (MOCVD) and plasma-enhanced atomic layer deposition [15,16] (PEALD). However, the growth temperature of MOCVD (>600 ◦C) is not desirable for the fabrication of AlGaN/GaN HEMTs. Furthermore, using a lower growth temperature also has the advantage of preventing tensile strain-induced cracking of AlN layer in AlN based MIS-HEMTs [17,18]. PEALD is a different approach to grow AlN films which can form a better interface with GaN at 350 ◦C but with a low deposition rate [19]. Recently, Dikme et al. [20] realized thick single crystalline AlN layers on Si and sapphire substrates at 200 ◦C using a novel technique called low-temperature epitaxy (LTE). In this technique, AlN is deposited as a combination of physical vapor deposition (PVD) and chemical vapor deposition (CVD). LTE also allows for thick (~1 µm) crystalline films to be grown at low-temperatures which is compatible with III-V device processing. We have recently reported the properties of interface states for AlGaN/GaN metal-insulator-semiconductor diodes (MIS-diodes) using the LTE grown AlN [21,22] So far, no reports have discussed the AlGaN/GaN MISHEMTs with LTE-AlN and its post-gate annealing effects. In this paper, we report AlGaN/GaN MISHEMTs on Si substrate with LTE grown AlN through DC, pulsed I-V and interface trap characterization and analysis.

#### **2. Materials and Methods**

The AlGaN/GaN HEMT structure on Si (111) substrate was grown by MOCVD. It consists of i-GaN (2 nm) cap layer, i-Al0.27Ga0.73N (18 nm) barrier layer, i-GaN (800 nm) buffer layer and transition layer (1400 nm). The resistivity of the Si substrate is >10,000 Ω.cm. Hall samples of (i) as-grown HEMT without LTE-AlN, (ii) HEMT with as-deposited ~8 nm LTE-AlN, (iii) HEMT with LTE-AlN annealed at 400 ◦C and (iv) HEMT with LTE-AlN annealed at 450 ◦C were prepared and their results at room temperature are summarized in Table 1. The MISHEMT fabrication process started with mesa isolation by reactive ion etching (RIE) using a Cl2/BCl<sup>3</sup> mixture. The ohmic contacts consisting of Ti/Al/Ni/Au (20/120/40/50 nm) was deposited followed by rapid thermal annealing at 825 ◦C for 30 s in an N2 atmosphere. Transmission line measurements showed a contact resistance of 0.4 Ω mm. Next, the gate dielectric layer using single crystalline AlN with a thickness of ~8 nm was deposited at 200 ◦C by LTE. The thickness of the deposited LTE-AlN has previously been confirmed by TEM and is reported elsewhere [22]. The novel growth method combines physical vapor deposition (PVD) and chemical vapor deposition (CVD). The Al source is solid Al with a purity of 5N, while the N source is N<sup>2</sup> gas with purity of 5N8. The N was activated by a linear ion gun close to the sample surface and the Al was sputtered in a way that its beam overlaps with the ion gun beam. The substrate temperature was in the range of 200–225 ◦C and the deposition pressure was in the upper 10−<sup>3</sup> mbar range with a total power density of around 5–7 W/cm<sup>2</sup> . Before the deposition, the sample was cleaned with a weak Ar/H<sup>2</sup> plasma to remove the native oxide. More details of the growth conditions can be found in the paper by Dikme et al. [20,21].


**Table 1.** 2DEGproperties of AlGaN/GaN with and without AlN and its post deposition annealing at 400 ◦C and 450 ◦C for 300 s in N<sup>2</sup> .

The gate metal stack Ni/Au (50/200 nm) was subsequently formed on the LTE grown AlN by electron beam evaporation. Finally, metal thickening (Ti/Au 10/400 nm) was also performed after AlN etching by Cl2/BCl3/Ar (40/20/10 sccm) plasma. The inset of Figure 1a shows the cross-sectional schematic diagram of the fabricated MISHEMTs with LTE-grown AlN. For this study, we have used device dimensions of Lg/Lsg/Lgd/W<sup>g</sup> = 2/2/2/(2 <sup>×</sup> 100) <sup>µ</sup>m. To study the post-gate annealing effects a MISHEMT sample with ~8 nm of LTE-AlN were annealed at 400 ◦C in a N<sup>2</sup> atmosphere using rapid thermal annealing process. A post-gate annealing temperature of 400 ◦C was chosen as there

was minimal changes to the Hall parameters after post deposition annealing at 450 ◦C (see Table 1). A lower temperature is also beneficial, as higher temperatures have previously been shown to cause degradation of Ni/Au gates [23,24].

#### **3. Results and Discussion**

Figure 1 shows (a) the capacitance-voltage (C-V) and (b) gate leakage current (Igleak) characteristics of Schottky diode (MS-diode), LTE-AlN MIS-diode with and without post-gate annealing. At zero-bias, the capacitance density of 373 nF/cm<sup>2</sup> and 302 nF/cm<sup>2</sup> for 200 µm diameter conventional Schottky diode and MIS-diode were obtained, respectively. After annealing, there is no significant change in capacitance density at 0 V. With reference to Schottky diode, the LTE-AlN MIS-diode exhibited 2 orders of magnitude lower Igleak at −20 V (Figure 1b). After post-gate annealing at 400 ◦C, MIS-diodes exhibited about an order of magnitude further reduction in Igleak. The improvement in Igleak is attributed to the improvement of interface properties of LTE-AlN on GaN/AlGaN after the 400 ◦C annealing.

Figure 2 shows (a) current–voltage (Ids-Vds) and (b) transfer characteristics of LTE-AlN/AlGaN/GaN MISHEMTs without and with post-gate annealing at 400 ◦C. The as-deposited AlN MISHEMT showed a maximum drain current (IDmax) of 708 mA/mm at a gate bias of 4 V and a maximum extrinsic transconductance (gmmax) of 129 mS/mm. After annealing, MISHEMT exhibited IDmax of 684 mA/mm at a gate bias of 4 V and gmmax of 148 mS/mm. The decrease in IDmax after annealing originates from a change in two-dimensional electron gas (2DEG) carrier concentration (ns), as I<sup>D</sup> ∝ ns. As shown in Table 1, after annealing at 400 ◦C, n<sup>s</sup> was found to decrease by 9% (from 9.89 <sup>×</sup> <sup>10</sup><sup>12</sup> cm−<sup>2</sup> to 9.02 <sup>×</sup> <sup>10</sup><sup>12</sup> cm−<sup>2</sup> ) which results in the 9% reduction in IDmax. Similarly, the 15% improvement of gmmax after post-gate annealing is attributed to an increase in electron mobility as well as a reduction of interface states [25]. This is attributed to a reduction in Coulomb scattering from the dielectric layer near the AlGaN/GaN interface [26]. The enhanced mobility was confirmed by Hall measurements, which shows an ~10% improvement (from 1210 cm2V −1 s −1 to 1330 cm2V −1 s −1 ) in 2DEG Hall mobility (µn), as seen in Table 1. From the Figure 2b, it is clear that AlN MISHEMT exhibited an order of magnitude improvement in the device ION/IOFF ratio after the post-gate annealing at 400 ◦C, which is due to the reduction of drain current at OFF-state. This is possibly caused by a reduction on traps at the AlN/GaN interface reducing the available leakage current conduction paths. The threshold voltages (Vth) of the devices were measured at −3.95 V and −3.8 V for as-deposited MISHET and post-gate annealed MISHEMT at 400 ◦C, respectively. Vth can be expressed as

$$\mathbf{V\_{th}} = \mathbf{V\_{th0}} - \frac{\mathbf{Q\_{it}}}{\mathbf{C\_{AlN}}} \tag{1}$$

where Vth0 is the threshold voltages without any interface states, Qit is the interface-trapped charge density and CAlN is the capacitance of the AlN layer. After annealing at 400 ◦C there is a minimal positive shift in threshold voltage which could be caused by a slight reduction of interface traps at LTE-AlN/GaN interface. This is verified by the frequency-dependent conductance measurements discussed in the later section. A similar occurrence was also reported after post-gate annealing by Zhou et al. for Al2O<sup>3</sup> and Shih et al. for HfO<sup>2</sup> [8,25]. In these cases, it was postulated that the positive Vth shift was caused by a reduction in positively charged traps and interface traps or positive fixed/mobile charges, and was confirmed by a reduction in calculated interface states after annealing. A benchmarking table between these devices and those published elsewhere can be seen in Table 2 [15,27–29].

**Figure 1.** (**a**) C-V characteristics and (**b**) two terminal Igleak-V<sup>g</sup> (200 um diameter diodes) characteristics of Ni/AlGaN/GaN Schottky diode, as-deposited LTE-AlN/AlGaN/GaN metal-insulator-semiconductor diode [22] and post-gate annealed MIS-diode at 400 ◦C. Inset: Schematic cross-sectional diagram of fabricated AlGaN/GaN MISHEMTs with LTE grown AlN on Si substrate.

**Figure 2.** (**a**) DC IDS-VDS and (**b**) transfer characteristics of as-deposited LTE-AlN/AlGaN/GaN MISHEMT and post-gate annealed MISHEMT at 400 ◦C.



− − − − Figure 3 shows pulsed ID-V<sup>D</sup> characteristics of (a) as-deposited MISHEMTs with LTE-AlN and (b) MISHEMTs with post-gate annealing at 400 ◦C. The devices were subjected to the pulse width/period of 100 <sup>µ</sup>s/10ms and quiescent biases of (Vgs0, Vds0) = (0, 0) and (−6, 20) V was used for the pulsed I-V measurements. The as-deposited LTE-AlN MISHEMT exhibited a ID/IDmax ratio of 0.91 for both quiescent biases (Vgs0, Vds0) <sup>=</sup> (0, 0) and (−6, 20). This indicates that the devices exhibited around 9% drain current (ID) collapse. After annealing at 400 ◦C, the ID/IDmax ratio of MISHEMT increases to 0.94. Therefore, about 3% I<sup>D</sup> collapse was suppressed after post-gate annealing at 400 ◦C. The improvement in current collapse in 400 ◦C annealed MISHEMT is attributed to the reduction of interface states at the AlN/GaN interface.

− − − **Figure 3.** Pulsed IDS-VDS characteristics at quiescent bias points of (Vgs0, Vds0) = (0, 0), (−6, 20) for (**a**) LTE-AlN MISHEMTs, (**b**) 400 ◦C annealed MISHEMTs and (**c**) normalized I<sup>D</sup> with IDmax for as-deposited LTE-AlN/AlGaN/GaN MISEMT and annealed MISHEMT at 400 ◦C vs. the quiescent bias points (Vgs0, Vds0) <sup>=</sup> (0, 0), (−6, 0), (−6, 20) V.

τ ω ω − − ω − − − − In order to quantify the amount of interface states at the LTE-AlN/GaN interfaces, frequencydependent conductance measurements were performed at selected biases to estimate the density of interface states (Dit) and trap time constant (τit). The frequency was varied from 1 kHz to 5 MHz over a wide range of gate voltages (Vg). Figure 4a shows the typical Gp/ω versus ω graph of LTE-AlN MISHEMT with post-gate annealed at 400 ◦C measured at different V<sup>g</sup> values between −4.1 V to −3.5 V. The Dit calculations were performed using the conductance-frequency method, which is widely used for interface calculations [21,30,31]. The two peak regions in the Gp/ω plots correspondingly indicate the presence of both low frequency (slow traps) and high frequency (fast traps). The exhibited fast traps are associated interface traps of the AlGaN/GaN hetero-interface [15,32], while the observed slow traps are associated with the AlN/GaN interface. The estimated Dit is shown in Figure 4b for the as-deposited LTE-AlN MIS-diode, as well as the MIS-diodes with post-gate annealing at 400 ◦C. The minimum Dit were estimated as 7.6 <sup>×</sup> <sup>10</sup><sup>11</sup> cm−<sup>2</sup> eV−<sup>1</sup> and 5.0 <sup>×</sup> <sup>10</sup><sup>11</sup> cm−<sup>2</sup> eV−<sup>1</sup> for the as-deposited MIS-diode and MIS-diode with post-gate annealing at 400 ◦C, respectively. With reference to as-deposited MIS-diode, a reduction of Dit (24%) has been observed in the MIS-diode after post-gate annealing at 400 ◦C. This reduction of interface traps can be associated with the suppression of I<sup>D</sup> collapse. Annealing at 400 ◦C helps to reduce the slow deep level traps thus reducing the remote Coulomb scattering from the AlN layer and improving the mobility.

ω **Figure 4.** (**a**) Gp/ω versus radial frequency plot for different gate voltages of post-gate annealed LTE-AlN MIS-diode at 400 ◦C (solid lines are fitting curves). (**b**) Distribution of interface state density as a function of the gate voltage of as-deposited LTE-AlN MIS-diodes [22] and post-gate annealed MIS-diodes at 400 ◦C.

#### **4. Conclusions**

In summary, AlGaN/GaN MISHEMTs on Si has been demonstrated for the first time with LTE grown AlN as a dielectric layer. The influence of post-gate annealing at 400 ◦C was also studied using DC, pulsed I-V and interface state characteristics. After the LTE-AlN deposition the LTE-AlN MISHEMT showed a maximum drain current (IDmax) of 708 mA/mm at a gate bias of 4 V and a maximum extrinsic transconductance (gmmax) of 129 mS/mm. By employing a post-gate annealing scheme at 400 ◦C in an N<sup>2</sup> atmosphere there was about a 15% of increase in gmmax and an order of magnitude reduction of gate leakage. About a 3% improvement of I<sup>D</sup> collapse suppression was also observed after post-gate annealing at 400 ◦C. The reduction of Igleak and I<sup>D</sup> collapse could be due to the reduction of interface state density of about 25%. This study indicates that the optimized post-gate annealing, which in our case is at 400 ◦C, is a viable way to have improved device characteristics in AlGaN/GaN MISHEMTs with LTE grown AlN.

**Author Contributions:** Conceptualization, M.W., S.A. and G.I.N.; methodology, M.W. and Y.D.; formal analysis, M.W. and A.S.; investigation, M.W.; resources, Y.D., S.A. and G.I.N.; data curation, M.W. and A.S.; writing—original draft preparation, M.W.; writing—review and editing, S.A., and G.I.N.; visualization, M.W.; supervision, G.I.N.; project administration, G.I.N. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research received no external funding.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


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## *Article* **Characterization of Self-Heating Process in GaN-Based HEMTs**

#### **Daniel Gryglewski <sup>1</sup> , Wojciech Wojtasiak 1,\* , Eliana Kami ´nska 2,\* and Anna Piotrowska 3,\***


Received: 21 July 2020; Accepted: 10 August 2020; Published: 13 August 2020

**Abstract:** Thermal characterization of modern microwave power transistors such as high electron-mobility transistors based on gallium nitride (GaN-based HEMTs) is a critical challenge for the development of high-performance new generation wireless communication systems (LTE-A, 5G) and advanced radars (active electronically scanned array (AESA)). This is especially true for systems operating with variable-envelope signals where accurate determination of self-heating effects resulting from strong- and fast-changing power dissipated inside transistor is crucial. In this work, we have developed an advanced measurement system based on DeltaVGS method with implemented software enabling accurate determination of device channel temperature and thermal resistance. The methodology accounts for MIL-STD-750-3 standard but takes into account appropriate specific bias and timing conditions. Three types of GaN-based HEMTs were taken into consideration, namely commercially available GaN-on-SiC (CGH27015F and TGF2023-2-01) and GaN-on-Si (NPT2022) devices, as well as model GaN-on-GaN HEMT (T8). Their characteristics of thermal impedance, thermal time constants and thermal equivalent circuits were presented. Knowledge of thermal equivalent circuits and electro–thermal models can lead to improved design of GaN HEMT high-power amplifiers with account of instantaneous temperature variations for systems using variable-envelope signals. It can also expand their range of application.

**Keywords:** GaN HEMT; self-heating effect; microwave power amplifier; thermal impedance; thermal time constant; thermal equivalent circuit

#### **1. Introduction**

It is now commonly accepted that high electron-mobility transistors based on gallium nitride (GaN HEMT) are the best choice for high-frequency and high-power devices, such as high-power amplifiers (HPAs) used in new generation radars, including active electronically scanned array (AESA), and modern wireless communication systems, i.e., LTE-A and 5G radios [1–4]. Due to the large complexity of signals applied in modern radars and new radios, power amplifiers have to meet stringent requirements concerning not only their linearity, output power level and efficiency but also appropriate heat management [5]. This is because both kinds of mentioned systems are operated by variable-envelope signals.

In AESA radar pulses, the signals are not only frequency-modulated but can be also modulated both in phase and amplitude [6,7]. The same concerns high-speed wireless networks which use quadrature amplitude modulation (QAM) with a large peak-to-average power ratio (PAPR). For instance, the PARP is 8.5–10 dB for LTE-A and more than 13 dB for 5G [8]. Such high variations in output power result in large changes of power dissipated in a transistor of HPA and thereby temperature variations in an active area of transistor. In addition, the transistors in transmitting amplifiers are often operated under fast-changing thermal conditions as response to quick and large signal envelope changes in time, e.g., during RF pulse or pulse-to-pulse [9], as well as the LTE-A signal.

It is obvious that temperature fluctuations cause changes in the transistor's electrical characteristics. This is a serious problem for the variable-envelope signals which are particularly sensitive to distortions caused by HPAs as a result of nonlinearity and self-heating effect of transistor. The impact both effects and discloses itself in the form of amplifier transmittance changes in time [10]. In the case of power amplifiers for wireless networks, parameters such as AM-AM and AM-PM conversions are often used to describe the effect of transistor nonlinearity. However, these are static parameters that do not show the instantaneous variations in signal amplitude and phase.

We think that the impact of transistor self-heating effect on its performances should be determined by the time-dependent transmittance changes, showing separately the changes in amplitude and phase.

Transistor nonlinearities have been quite thoroughly described and implemented in popular large-signal models, e.g., Angelov's HEMT model [11]. In contrast, the thermal effect in the transistor, especially GaN HEMT is not so widely recognized and is usually modeled using either *Rth* under static conditions or a simple 1-section low-pass (parallel *Rth*-*Cth*) circuit as in the microwave transistor models provide by e.g., Wolfspeed (Durham, NC, USA), MACOM (Lowell, MA, USA), Modelithics (Tampa, FL, USA). This approach is not satisfying for fast-changing variable-envelope excitations. Therefore, we propose to describe self-heating effect in transistor by means of transient thermal impedance *Zth*(*t*) and more complex, multi-section, equivalent thermal circuit of transistor.

The paper presents our own approach to the thermal characterization of GaN HEMTs using thermal impedance measurements *Zth*(*t*) correlated with the solution of heat conduction equation in the GaN HEMT structure by means of FDTD method [12]. As a result that GaN-based epi-structures for HEMTs are grown on various substrates, namely on SiC, Si and GaN and consist of several epi-layers, each with different thermal properties. The results of simulations and measurements enable the thermal time constants appearing in the transistor structure to be identified.

#### **2. Scope of the Research**

#### *2.1. Samples*

The following GaN-based HEMTs have been a test subject in our study: commercially available GaN-on-SiC HEMTs CGH27015F (packaged) from Wolfspeed, and TGF2023-2-01 (die) from Qorvo (Greensboro, NC, USA), GaN-on-Si HEMT NPT2022 (packaged) from MACOM and GaN-on-GaN HEMT (marked T8) fabricated within PolHEMT project [13,14]. The T8 transistor was made on epitaxial layers grown on a truly bulk monocrystalline semi-insulating GaN. Testing was performed on two gates of 0.8 µm length and 500 µm width structure. The dies were mounted to the plate in test board using EPO-TEK H20E glue approx. 0.025 mm. Typical performance and electrical characteristics of the selected GaN HEMTs are given in Table 1 (manufacturer's data).


**Table 1.** Typical performance and application information of high electron-mobility transistors based on gallium nitride (GaN HEMT) samples.

#### *2.2. Electrical Characterization of Thermal Properties*

In general terms we follow the well-known DeltaVGS measurement technique at the constant current of forward-biased gate-to-source diode in MESFET or HEMT (MIL-STD-750D-3 standard, method 3104) [15,16]. However, our approach is different from the previous ones by specific bias and timing conditions of the transistor during the measurements.

The knowledge of thermal impedance *Zth*(*t*) allows calculating the channel temperature *T<sup>j</sup>* (*t*) for any shape of dissipated power *Pd*(*t*) as follows [17]:

$$T\_{\dot{f}}(t) = T\_0 + \int\_0^t P\_d \times Z\_{th}'(t-\tau)d\tau \tag{1}$$

where:

. . . . *Tj* (*t*)—channel temperature response; *T*0—ambient temperature (heatsink); *Z* ′ *th*(*t*)—time derivative of *Zth(t)*; *P<sup>d</sup>* (*t*)—dissipated power.

*τ τ τ τ* The thermal impedance *Zth*(*t*) of different elements is often modeled, through the electro–thermal analogy, by lumped electrical equivalent circuit which contains a number of thermal resistances *Rth* and thermal capacitances *Cth* connected in an appropriate way. Typically, in simplified terms, the thermal equivalent circuit consists of several parallel *Rth-Cth* circuits connected in series [18]. Each of the low-pass circuits *Rthi*-*Cthi* corresponds to a thermal time constant τ*<sup>i</sup>* in an exponential approximation of thermal impedance *Zth*(*t*) characteristic. Such a lumped electrical model can be used to calculate the channel temperature using one of popular circuit simulators like ADS or SPICE. That approach is very convenient, because the temperature of active area of transistors can be simulated using the tool applied anyway for analysis of electrical parameters.

Δ Δ Δ Δ As previously mentioned the developed system of thermal impedance *Zth*(*t*) measurement was inspired by the method 3104 from MIL-STD-750D-3 standard which uses the effect of the voltage drop ∆*VGS(t)* at a forward–biased junction as a sensor of the temperature. Furthermore, the temperature values of the gate-source diode and the transistor channel are identical. The basic formula for that measurement technique was derived from the Schottky's diode equation and is expressed as follows:

$$V\_{GS} = n \times V\_b - \frac{n \times k \times T\_j}{q} \left[ 2ln(T\_j) - ln\left(\frac{I\_G}{\mathbf{A} \mathbf{A}^W}\right) \right] \tag{2}$$

where:

*IG*—junction forward current; *A*—effective Richardson constant; *W*—the junction surface; *q*—charge of the electron; *k*—Boltzmann constant; *n*—ideality factor; *Vb*—built-in barrier voltage.

At the constant gate current *IG*, the voltage drop ∆*VGS* across the source—gate junction decreases almost linearly with the rise of temperature and is given by: Δ

$$
\Delta V\_{\rm GS} = \mathbf{K} \times \Delta T\_{\rm j} \tag{3}
$$

where: *K*—constant.

The *Zth*(*t*) measurement procedure consists of the following steps:


Examples of test boards for packaged transistors and chips measurements are presented in Figure 1a,b, respectively. The test board consists of a printed board circuits (PCB) placed on a thick metal base plate (usually made of copper) which should be characterized by high thermal inertia. The transistor bottom is thermally connected to this plate. The temperature at the bottom of the transistor (*T*0) must be constant during the *VGS*(*t*) recording. Otherwise the *T*<sup>0</sup> temperature changes must be taken into account in the last step of the procedure i.e., thermal impedance *Zth*(*t*) calculation. The transistor can be biased in active state in heating phase of the *VGS*(*t*) recording procedure. Since the GaN HEMTs are generally potentially unstable the stabilizing circuits are required on the PCB to protect the transistor against damage.

**Figure 1.** The outline of the test boards: (**a**) packaged transistor and (**b**) die (chip).

The simplified block diagram of the proposed *Zth*(*t*) measurement system with the timing diagram of *VGS*(*t*) recording procedure is shown in Figure 2. In the methods based on the MIL-STD-750D-3 standard the gate-to-source diode is forward-biased all the time and the operating point of the transistor

≤

during the heating phase is placed in "on" region of the DC I-V output characteristic i.e., with relatively low *VDS* DC voltage (*VDS* ≤ *Vknee*) and high *I<sup>D</sup>* drain current. In that conditions the power dissipated in transistors is significantly lower and hence the *Rth* value is also smaller than in the case of normal transistor operation in transmitter's amplifier when RF signal is amplified i.e., the average value of the drain current is higher than at the quiescent operating point (without RF power, as in classes AB, B and C). Therefore, in our thermal measurements, the operating point of the tested transistor is selected so that it corresponds to the expected maximum power from the amplifier, especially when typical *VDS* bias voltage for power GaN HEMTs is over a 28 V to 50 V voltage range. −

**Figure 2.** (**a**) Simplified block diagram of thermal impedance *Zth(t)* measurement system; (**b**) DUT biasing circuit; (**c**) timing diagram of *VGS(t)* recording procedure.

Information on the influence of *VDS* voltage on thermal resistance *Rth* is scarce and ambiguous. From one side strong thermal resistance *Rth* changes versus *VDS* voltage for GaAs MESFET transistors (the constant level of power was dissipated in transistors during the tests) was observed [15]. On the other hand weak dependence of *Zt*h(*t*) or *Rth* for GaAs (no more than 10%) [19] and GaN (no more

6%) [20,21] transistors for *VDS* change was demonstrated. As reported in [22–24], the *Zth*(*t*) changes mainly follow dependence of thermal conductivity of GaN HEMT layers on temperature.

Our test setup (Figure 2) was designed to be very flexible, and it allows setting wide range *VDS* bias voltages and *I<sup>D</sup>* current during the heating phase. It includes extra *K*2, *K*<sup>3</sup> switches and controlled *<sup>V</sup>GS*<sup>0</sup> voltage source. The *<sup>V</sup>GS*<sup>0</sup> setting range is −6–0 V and *<sup>V</sup>DS* from 0 V to <sup>+</sup>50 V. The control range of current source *I<sup>G</sup>* is 0.1–10 mA. The proposed *VGS*(*t*) recording procedure (Figure 2c) is also different from the method based on MIL-STD-750D-3 standard.

At the beginning the keys are set up in the following positions: *K*1, *K*<sup>3</sup> position "1", *K*<sup>2</sup> position "0" and the transistor is biased at the chosen operating point and heated by DC power dissipated therein. After the heating pulse the keys *K*1, *K*<sup>2</sup> and *K*<sup>3</sup> are switched to the positions 0 and 1, respectively. This is the start of *VGS*(*t*) sampling during the cooling phase of the DUT. The forward gate current remains constant and it equal to *I<sup>G</sup>* after the heating time while the drain-source voltage source *VDS* circuit is open i.e., drain current is 0. The switching time of *K*1, *K*<sup>2</sup> and *K*<sup>3</sup> keys is less than 10 ns but in practice, the total switching time between heating end and the start of recording phase *t<sup>D</sup>* is less than 100 ns. In the commercially available measurement systems that time is close to 5 µs [25]. The *t<sup>D</sup>* time depends on input capacitance *Cgs* of transistor and *I<sup>G</sup>* value. Therefore, gate current *I<sup>G</sup>* value should be as high as possible. The forward gate current is limited by the maximum allowed level specified for the transistor. Furthermore, time delay is also determined by bias and stabilization circuits. In MIL-STD-750D standard the *VGS* voltage is only measured in two-time moments: before heating and as quick as possible after heating. These two *VGS* values allow calculating only the thermal resistance *Rth*. This is the main purpose of MIL-STD-750D-3 standard as it is clearly indicated in description. Therefore, this method is aimed at the testing transistors in packages, especially die attachment quality [15].

As shown in Figure 2a, the *VGS(t)* sampling is performed by means the recording block and digital part of the system. The recording time *tREC* as well as the sampling frequency *f* <sup>s</sup> can be changed. At the beginning of the recoding phase *f* <sup>s</sup> achieves 100 MHz and after 1 s drops to 10 Hz. The recording is continued up to the moment when the lack is significant changes of *VGS*(*t*). The maximum recording time of *VGS*(*t*) is 90 s. This ploy enables significantly reducing the amount of *VGS*(*t*) recorded data. The *VGS*(*t*) and *Zth*(*t*) characteristics are similar to the response of low pass filter. Therefore, there is no need to record of *VGS*(*t*) samples with the maximum sampling frequency up to end of measurement procedure.

After *VGS*(*t*) recording, the calibration is needed to calculate *K* factor values. The DUT is placed in a thermal test chamber and the *VGS* voltages across the forward-biased gate-to-source Schottky junction for a number of different temperatures are stationary measured. The *I<sup>G</sup>* value is constant and the same as during in *VGS*(*t*)

recording. The concept of *K* factor measurement is presented in Figure 3.

**Figure 3.** The concept of *K* factor measurement.

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The last step of the measurement procedure is channel temperature *T<sup>j</sup>* (*t*) and thermal impedance calculation *Zth*(*t*). The channel temperature *T<sup>j</sup>* (*t*) of transistor is given by following formula:

$$
\Delta T\_j(t) = T\_0 + K \times V\_{GS}(t) \tag{4}
$$

As shown in Figure 2c the *VGS*(*t*) is acquired during the transistor cooling. Under these conditions, as shown in Figure 2c, the thermal impedance *Zth*(*t*) can be calculated as follows:

$$Z\_{th}(t) = \frac{T\_j(0) - T\_j(t)}{P\_{dc}} \tag{5}$$

where:

*Tj* (*0*)—calculated channel temperature at the beginning of the *VGS*(*t*) recording; *PDC*—dissipated power in transistor during heating phase. ;

The *Zth*(*t*) measurement system consists of the hardware (microcontroller and FPGA), firmware and PC software. The FPGA block controls the *K*1*–K*<sup>3</sup> switches, acquires and stores the *VGS*(*t*) data from A/D converter. The communication between hardware and PC is realized by microcontroller (MCU) using USB standard. The *VGS*(*t*) data from FPGA is transferred to PC via MCU. The MCU controls the components of the recording block and the *VGSO*, *VDS* voltage sources. All parameters of *VGS*(*t*) recording procedure (Figure 2b,c) can be set using PC software. The PC software also allows pre-processing of the received data, calculation of *Zth*(*t*) impedance and finally visualization of the results. The graphical user interface of the PC software is presented in Figure 4a. The *Zth*(*t*) measurement results can be exported to text file in \*.csf format. The PC software has been written in Java using the Eclipse environment. The photo of hardware of the *Zth*(*t*) measurement system is shown in Figure 4b.

**Figure 4.** (**a**) Graphical user interface (GUI); (**b**) photo of *Zth*(*t*) measurement system hardware. (1—A/D converter, 2—VGA, 3—MCU, 4—USART/USB converter, 5—*VDS* voltage regulator, 6—*K*<sup>1</sup> switch, 7—*K*<sup>2</sup> switch, 8—*I<sup>G</sup>* current source, 9—*VGS* voltage regulator, 10—*VGS*<sup>0</sup> adjusting, 11—MCU programing connector, 12—FPGA located at bottom side, 13—DUT biasing circuit, 14—recording block, 15—digital part of the system).

#### **3. Results**

The*Zth*(*t*) and *T<sup>j</sup>* (*t*) of CGH27015 and T8 are presented in Figure 5a–d, respectively. The GaN-on-SiC HEMT CGH27015F was mounted in the test board shown in Figure 1a. During the heating phase the CGH27015F was biased as follows: *VDS* = 28 V (*P<sup>D</sup>* = 14 W) and *VDS* = 15 V (*P<sup>D</sup>* = 7 W) at the same current *I<sup>D</sup>* = ~0.5 A.

**Figure 5.** GaN-on-SiC CGH27015F and GaN-on-GaN HEMT T8 (**a,c**) thermal impedance *Zth*(*t*) and (**b**,**d**) channel temperature *T<sup>j</sup>* (*t*) measurements, respectively.

During the heating phase the T8 was biased: *VDS* = 28 V (*P<sup>D</sup>* = 1.96 W), *VDS* = 15 V (*P<sup>D</sup>* = 1.05 W) and *VDS* = 10 V (*P<sup>D</sup>* = 0.7 W) with the same drain current of 70 mA. The next results of T8 and GaN-on-SiC TGF2023-2-01 measurements presented in Figure 6 were performed under modified conditions i.e., the same power level was dissipated inside dies during heating phase of measurement procedure. In this phase, dissipated power level inside T8 was *P<sup>D</sup>* = 0.75 W and voltage *VDS* = 5 V, 10 V, 15 V, 20 V and 28 V (Figure 6a,b). The *Zth(t*) and the *T<sup>j</sup>* (*t*) of TGF2023-2-01 are shown in Figure 6c. In this case the dissipated power level was *P<sup>D</sup>* = 2.5 W and the *VDS* = 5 V, 10 V, 15 V, 20 V and 28 V.

The *Zth*(*t*) changes (T8) shown in Figure 5c, when different power levels were dissipated in GaN HEMTs, are bigger in comparison to *Zth*(*t*) changes indicated in Figure 6c for the same power dissipated in transistors and different drain-to-source voltages. The impact of Ga-on-Si HEMT NPT2022 voltage *VDS* on the *Zth*(*t*) characteristics, as shown Figure 7a, is slightly larger to similar *Zth*(*t*) characteristics of GaN-on-SiC HEMT TGF2023-2-01 (Figure 6a). Generally, obtained results confirm the lack of significant dependence of impedance *Zth*(*t*) on GaN HEMT bias voltage.

**Figure 6.** Thermal impedance *Zth*(*t*) and channel temperature *T<sup>j</sup>* (*t*) measurements for the same power level dissipated inside dies during the heating phase: (**a**,**b**) GaN-on-SiC TGF2023-2-01 (Qorvo), (**c**,**d**) GaN-on-GaN HEMT T8, respectively.

**Figure 7.** GaN-on-Si HEMT NPT2022 (MACOM) (**a**) thermal impedance *Zth*(*t*) and (**b**) channel temperature *T<sup>j</sup>* (*t*) measurements.

The "tank" and "filter" configurations of *Rth-Cth* thermal model are considered [18]. These configurations are also known as Cauer and Foster. Both models are capable to quite accurately fit the thermal impedance *Zth(t)* characteristics. The "tank" circuit consists of a chain of parallel circuits *Rth-Cth* which is simple to mathematical description. We have developed the automatic routine of "tank" model fitting in Mathcad software. The input data for this software are the *Zth*(*t*) measurement

results stored in text format file (\*.csf). For assumed number of *Rth-Cth* cells, the software allows calculating maximum error of fitting curve.

The thermal "tank" models of selected HEMTs were calculated at following bias points: CGH27015F—*VDS* = 28 V, *I<sup>D</sup>* = 0.5 A, T8—*VDS* = 28 V, *I<sup>D</sup>* = 72 mA, TGF2023-2-01—*VDS* = 28 V, *I<sup>D</sup>* = 90 mA, NPT2022*—VDS* = 48 V, *I<sup>D</sup>* = 1.5 A. These operating points correspond to output power levels close to the maximum for each transistor. The *Zth*(*t*) characteristics were fitted to measurements with the error lower than 1% and are shown in Figure 8.

**Figure 8.** (**a**) CGH27015F (Wolspeed), (**b**) T8 PolHEMT, (**c**) TGF2023-2-01 (Qorvo), (**d**) NPT2022 (MACOM) thermal GaN HEMT models.

As shown in Figure 8, the thermal models of packaged devices CGH27015F and NPT2022 are more complicated than T8 and TGF2023-2-01 die models. The last thermal cell in CGH27015F and NPT2022 models correspond to flange (or package) and thermal attachment to the cooling plate. Thermal time constants referred to individual epi-layers of GaN HEMT and depend on the sizes and material properties. However, it is rather impossible to identify in such a way physical properties of GaN-based epi-layers as the 3-D thermal problem has been reduced to the equivalent of a lumped element.

To verify thermal impedance measurements the transistor T8 was thermal modeled using 3-dimensional equation of heat conduction which is solved by means of FDTD method [12–26]. The T8 die modeled GaN HEMT structure and the assumed heat model flow are shown in Figure 9a,b, respectively. The heating area was located under the top transistor metallization, marked "red" in Figure 9. The constant heat density across all heating areas was assumed. The thermal parameters of transistor materials were constant and temperature independent too. Their values are shown in the transistor heat model flow. To reduce the simulation time the adoptive mesh was applied. The minimal mesh size was 1 µm and it was at the top of thermal structure. The calculations were performed in MATLAB. Due to the very time-consuming calculations the thermal plate size was reduced. The simulation of T8 thermal impedance *Zth(t)* take about 24 h on PC equipped with i7 Intel processor and 16 GB RAM. The simulations and measurements of thermal impedance *Zth*(*t*) of GaN HEMT T8 are shown in Figure 10.

**Figure 9.** (**a**) GaN-on-GaN HEMT T8 structure; (**b**) T8 thermal model for FDTD simulation.

As shown in Figure 10, the *Zth*(*t*) calculations and measurements are consistent. The highest difference is at the beginning of *Zth*(*t*) characteristic and it is probably caused by the too large mesh of 1µm. The HEMT heating area thickness across vertical direction is much smaller.

→∞ Good compliance of the thermal measurements with the manufacturer's data was also achieved. For example, the thermal resistance measurement of CGH27015F is *Zth*(*t*→∞) = 7 ◦C/W (Figure 5a) while *Rth* value given in the datasheet is 8 ◦C/W in the section "absolute maximum ratings" [27]. *Rth* values given by manufacturers are usually the "worst case" across the production.

1×10<sup>1</sup> 1×10-7 1×10-6 1×10-5 1×10-4 1×10-3 1×10-2 1×10-1 1×10<sup>0</sup>

( <sup>o</sup>C/W)

0 5 10

15 20 25

30 35

(s)

SiN<sup>x</sup> Ni/Au Ni/Au Ni/Au

3000 µm

λ α

→∞

A A

λ α

λ α

λ α 25 µm

3000 µm

1×10<sup>1</sup> 1×10-7 1×10-6 1×10-5 1×10-4 1×10-3 1×10-2 1×10-1 1×10<sup>0</sup> **Figure 10.** Calculated and measured thermal impedance *Zth(t)* of GaN-on-GaN HEMT T8.

Analyzing thermal characteristics (Figures 5 and 7) and thermal models shown in Figure 8a,d of packaged transistors CGH27015F and NPT2022 a significant difference in thermal resistance of GaN HEMTs on SiC and Si substrates may be observed. Considering only semiconductor structure (without flange) of both HEMTs with scaling factor ca. 5 (as output power ratio with correction for size of chip and package) GaN-on-Si HEMT NPT2022 *Rth* exceeds 9 while for GaN-on-SiC HEMT *Rth* is approx. 4.5 ◦C/W. This fact has been confirmed during measurements of the L-band 100 W amplifier with NPT2022 under pulse and CW (continuous wave) operation conditions. In case CW amplifier excitation, far below maximal output power obtained at the pulse operation, both output power and gain dropped sharply [28]. Moreover, the case temperature increased rapidly above recommended value by manufacturer. To correctly compare thermal properties of GaN-on-SiC HEMT (Quorvo TGF2023-2-01) and GaN-on-GaN (T8 HEMT) their size ought to be normalized, i.e., the size of TGF2023-2-01 scaled down to the size of T8 structure. Taking into consideration that GF2023-2-01 is ten-gates structure of 0.3 µm length and 1.25 mm width while T8 HEMT is two-gates of 0.8 µm length and 500 µm width and that the thickness of SiC substrate stands for 90% of the total thickness of GF2023-2-01 HEMT while T8 consists of lattice-matched GaN-based structure one would expect two times higher thermal resistance of GaN-on-GaN HEMT while in reality it is only 30% higher. The reason for that is boundary-effect leading to additional thermal boundary resistance at the interface of SiC substrate and GaN-based epi-structure in GaN-on-SiC HEMT [29,30].

#### **4. Conclusions**

Novel approach to characterizing self-heating process in GaN-based HEMTs has been proposed. It relies on measuring thermal impedance *Zth*(*t*) basing on MIL-STD-750D-3 standard and followed by solving 3-D heat conduction equation by means of FDTD. The thermal impedance *Zth*(*t*) of the GaN HEMT is calculated from the gate-to-source voltage measurements of the forward biased diode during cooling time after the heating pulse. A characteristic feature of our method is that during the heating phase the HEMT is biased at the operating point in which it will operate during its normal use in the transmitter's amplifiers of modern radar and wireless communication systems. Furthermore, the time delay between the heating end and the start of monitoring of *VGS* samples is less than 100 ns while the commercial measurement systems typically have delays as long as 5 µs. The *Zth*(*t*) characteristics enable the thermal time constants to be calculated.

The above procedures have been successfully applied to characterization of various commercial GaN HEMTs, namely CGH27015F (Wolfspeed) and TGF2023-2-01 (Qorvo) on SiC substrate, and NPT2022 (MACOM) on Si substrate as well as with T8 laboratory GaN-on-Ammono GaN HEMT.

The value of thermal resistance *Rth* values calculated using thermal measurements for commercially available GaN-on-SiC HEMTS are consistent with manufacturer's data. The impact of material substrate on thermal features of GaN-based transistors is clearly visible. Specifically, GaN-on-Si HEMTs show much worse thermal parameters than GaN-on-SiC. The thermal characteristics of dies i.e., TGF2023-2-01 and T8 are very similar.

The main advantage of the proposed approach is that it allows taking into account the self-heating effect of transistors during design of microwave devices. That kind of knowledge can be very important in the design of high-power amplifiers for systems using variable-envelope signals such as LTE-A and 5G radios. In addition, our method enables the thermal time constants referred to the individual GaN HEMT layers to be identified. The obtained multi-section thermal equivalent circuit of transistor and resulting thermal model may be included in GaN HEMT electrical models which are implemented in popular RF and microwave simulators. Since the GaN HEMT consists of several layers, each with different thermal properties, our measurements allow evaluating heat flow across the structure as well as determining an attachment quality die to flange or package. This is especially important when designing amplifiers with transistor chips or transistors in housing for soldering on printed board circuits (PCB).

**Author Contributions:** Conceptualization, D.G. and W.W. concept and implementation of modified DeltaVGS measurement system, E.K. and A.P.; GaN-on-SI Ammono GaN HEMTs, conceiving building blocks and process flow of device structures, methodology, D.G. and W.W.; GaN HEMT thermal impedance measurements, software, D.G. and W.W.; software development, calculation of parameters of GaN HEMT thermal equivalent circuits, simulations of GaN HEMT thermal characteristics using 3-D FDTD method, validation, D.G., W.W. and A.P.; formal analysis, W.W.; investigation, D.G., W.W., E.K. and A.P.; resources, D.G., W.W., E.K. and A.P.; original draft preparation, W.W.; manuscript review and editing, E.K. and A.P.; visualization, D.G. and W.W.; supervision, W.W. and A.P.; project administration, A.P.; funding acquisition, W.W. All authors have read and agreed to the published version of the manuscript.

**Funding:** The research was partly supported by the National Centre for Research and Development, PolHEMT Project, Contract No. PBS1/A3/9/2012 and Project "Technologies of semiconductor materials for high power and high frequency electronics" Contract No. TECHMATSTRATEG1/346922/4/NCBR/2017.

**Acknowledgments:** The authors highly appreciate valuable input to the development of GaN-based HEMTs done by Marek Ekielski, Maciej Kozubal, and Andrzej Taube from the LRN-ITE.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


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