*Article* **Novel Program Scheme of Vertical NAND Flash Memory for Reduction of Z-Interference**

**Su-in Yi 1,2 and Jungsik Kim 3,4,\***


**Abstract:** Minimizing the variation in threshold voltage (*Vt*) of programmed cells is required to the extreme level for realizing multi-level-cells; as many as even 5 bits per cell recently. In this work, a recent program scheme to write the cells from the top, for instance the 170th layer, to the bottom, the 1st layer, (T-B scheme) in vertical NAND (VNAND) Flash Memory, is investigated to minimize *Vt* variation by reducing Z-interference. With the aid of Technology Computer Aided Design (TCAD) the Z-Interference for T-B (84 mV) is found to be better than B-T (105 mV). Moreover, under scaled cell dimensions (e.g., *Lg*: 31→24 nm), the improvement becomes protruding (T-B: 126 mV and B-T: 162 mV), emphasizing the significance of the T-B program scheme for the next generation VNAND products with the higher bit density.

**Keywords:** NAND flash memory; interference; Technology Computer Aided Design (TCAD) simulation; disturbance; program; non-volatile memory (NVM)
