*4.1. Challenges of Fabricating GaN-on-Diamond Wafers*

The deposition of diamond films on the back of GaN wafers has been routinely performed by Element Six for more than 10 years. The fabrication of GaN-on-diamond wafers involves the deposition of 100 µm-thick diamond films at temperatures higher than 700 ◦C. The large deposition temperatures induce a large residual stress at the GaN/diamond interface that may cause the bowing of the wafer and the cracking of the GaN layers. In addition, the *TBR*GaN/diamond and the low quality of the initial layers of the deposited diamond films are currently the bottleneck of the heat extraction. Each of these issues will be discussed in detail in the following paragraphs.

#### 4.1.1. Decreasing Thermal Stress

One of the biggest issues of this approach is related with the high diamond deposition temperature (>700 ◦C) which induces a large residual stress at the GaN/diamond interface because of the mismatch between the *CTE*s of both materials [159,160]. The residual stress depends on the GaN thickness, on the diamond growth temperature, and on the sacrificial carrier wafer [91,92]. Residual stresses larger than 1 GPa at the free surface of the GaN have been reported [93]; these elevated stress conditions induce layer cracking and wafer bow, and impact the electrical performance of the devices [161–164]. A large thermal stress at the GaN-diamond interface causes a significant reliability concern when considering the function and lifetime of GaN-on-diamond devices.

To avoid the issues related with the residual stress, a slightly modified approach has been recently proposed [94]. The GaN was initially grown on an AlN nucleation layer deposited on a Si substrate. The Si substrate was selectively etched, leaving behind 0.5 mm-diameter GaN membranes with the AlN nucleation layer exposed onto which 50 µm-thick diamond films were further grown. The high quality diamond/AlN interface showed no visible voids or cracks, confirming the strong bond between both materials. This approach presents no technological barrier to the incorporation of an AlN "initiation" layer into the GaN buffer close to the device channel; however, due to the low thickness of the GaN membranes and the simultaneously high temperatures required for diamond growth, the bowing of the membranes during the diamond deposition step cannot be neglected. This phenomenon was recently analyzed in detail in [95] using commercial GaN-on-Si wafers as the starting material. The processing steps are described in Figure 19a. The GaN membrane diameter was shown to impact the maximum displacement from the original plane (bowing) before and after diamond deposition, as well as the membrane stress. The 5 mm-diameter membranes allowed a larger displacement with a subsequent lower stress value, however the larger bowing "pushed" the GaN surface further into the plasma during diamond deposition, exposing it to high temperatures and resulting in thermal runaway and damage to the GaN/III-N film—Figure 19b. In addition, the large membrane bows present a big challenge for device manufacturing using contact lithography. A possible way to prevent the bowing would be the use of pre-stressed GaN-on-Si wafers as the starting material. stress value, however the larger bowing "pushed" the GaN surface fur —

**Figure 19.** (**a**) Fabrication steps of a GaN-on-diamond membrane. (**b**) Image of the 5 mm-diameter membrane inside the MPCVD system and corresponding thermally-induced mechanical displacement (reprinted from [95]; permission conveyed through CCBY 4.0: https://creativecommons.org/ licenses/by/4.0/ (accessed on 7 October 2021)).

Following a radically different approach, represented in Figure 20, Jia et al. [96] reported a low stress GaN-on-diamond wafer fabricated by dual sided deposition of diamond. In this process, the temporary carrier represented in Figure 2 was a 2 µm-thick Si layer followed by 100 µm of low-quality PCD deposited by CVD. A thin SiN layer was deposited on the surface after the substrate removal, followed by high-quality PCD. The final free-standing GaN-on-diamond wafer was obtained by removing the low-quality PCD and Si layers. The surface and quality of the GaN layer after the etching of the low quality PCD and Si layers remained the same while the stress was reduced to 0.5 GPa. However, it should be mentioned that the AlN buffer layer was not removed and this may have helped to reduce the internal stress caused by diamond growth.

stress value, however the larger bowing "pushed" the GaN surface fur

—

**Figure 20.** Fabrication of GaN-on-diamond wafers by dual-sided diamond deposition.

#### 4.1.2. Optimizing the Thermal Barrier Resistance at the Diamond/GaN Interface

The minimization of the *TBR*GaN/diamond will have a positive impact on the thermal performance and reliability of GaN-on-diamond HEMTs. In theory this can be achieved by reducing the thickness of dielectric layer, thereby reducing its bulk *R*th, or by improving the interface between GaN/dielectric and dielectric/diamond to reduce the interface effects. As an example, for a particular GaN-on-diamond HEMT, the reduction in the *TBR*GaN/diamond related with the SiN layer from 13 to 3 m<sup>2</sup> ·K/GW would reduce the total *R*th of the device from 2.8 to 1.9 K·mm/W, which corresponds to a 35% decrease in the peak operating temperature rise at a given power level [73]. However, one should also keep in mind that, despite smoother GaN/SiN/diamond interfaces lead to lower *TBR*GaN/diamond, they also show reduced interfacial fracture toughness, in comparison with rougher interfaces [99], which could negatively impact the devices reliability.

The standard fabrication of GaN-on-diamond wafers requires a 30 nm-thick SiN layer to protect the surface of the GaN from the diamond deposition conditions. Despite its low thickness, this layer may contribute with a *TBR* of <sup>≈</sup>30 m<sup>2</sup> ·K/GW, adding more than 20% to the total device *R*th [74]. Some groups decreased the thickness of the SiN layer to 5 nm and obtained *TBR* values of 9.5 and 6.5 m<sup>2</sup> ·K/GW [10,82] (close to the theoretical minimum of 5.5 m<sup>2</sup> ·K/GW calculated by the diffuse mismatch model [82]).

An apparently simple way of decreasing *TBR*GaN/diamond would be to remove the SiN layer. However, depositing diamond directly onto GaN is not a straightforward task. At typical diamond CVD temperatures (700 ◦C and above), the atomic hydrogen (H) can etch the surface of the GaN substrate (forming NH<sup>3</sup> and liquid gallium (Ga)). This etching can be prevented if the density of diamond seeds on the GaN surface is so high that the lateral diamond growth rate exceeds the GaN etching rate. In this case, a protective diamond layer grows to cover the GaN surface before significant etching can occur. However, even under these conditions the interface between GaN and diamond is rather weak because Ga does not form a carbide. This means the diamond adheres to the GaN surface mainly via weak VdW interactions, rather than by strong covalent bonds. This becomes a serious problem when the coated samples are cooled down to RT due to the difference in the *CTE*s of both materials, which causes compressive stress to accumulate in the diamond layer and can lead to delamination of the entire diamond layer [75].

Despite these difficulties, different groups have reported direct growth of diamond films on GaN [10,82], however the experimental values of *TBR*GaN/diamond are higher than the ones obtained with SiN (41/30 against 9.5/5.5 m<sup>2</sup> ·K/GW, respectively [10,82]) and significantly larger than the minimum theoretical value for the GaN/diamond interface (3 m<sup>2</sup> ·K/GW [82]). During the diamond deposition extensive deterioration of the GaN surface occurs, which results in the appearance of voids measuring up to 50 nm. This results in an extremely rough surface that increases the scattering of the phonons. Smith et al. [76] and Waller et al. [74] reported *TBR*GaN/diamond as high as 220 m<sup>2</sup> ·K/GW. In both works the GaN surface was seeded using a two-step electrostatic spray technique (see more details in Section 4.1.3.1).

A different possibility is to replace the SiN layer with a layer of material with higher κ, such as AlN [10,82] (30 [46] against 285 W/(m·K) [165], respectively, in crystalline forms). However, AlN thin films decompose in hydrogen (H2) and H2/CH<sup>4</sup> plasmas at low pressures (25–5 Torr) and high temperatures (650–1070 ◦C) [166], and direct growth of diamond has proven to be very difficult. A possible solution would be the pre-treatment of the AlN surface, prior to exposure to CVD diamond growth conditions. Previous exposure of the AlN substrates to carbon tetrafluoride (CF4) plasma allowed increasing the seeding density by nearly 3 orders of magnitude in comparison with untreated substrates [167]. Mandal et al. [84] reported that exposure of the AlN surface to H2/nitrogen (N2) plasma was necessary for the deposition of thick (>100 µm) and adherent diamond layers. However, the real usefulness of replacing SiN with AlN is doubtful, since AlN and SiN thin films are amorphous and feature similar κ values (≈1–5 nm) [82]. In fact, two different groups reported higher values of *TBR*GaN/diamond obtained with 5 nm-thick AlN layers than with similar SiN layers (18.2/9.5 against 15.9/6.5 m<sup>2</sup> ·K/GW, respectively [10,82]). In both works this difference was attributed to discontinuities in the AlN layer itself which resulted in the etching of the GaN surface (Figure 21); however it is not clear if the as-deposited AlN layer was discontinuous or if it was etched during the deposition of diamond. Jia et. al [83] observed the same tendency with thicker dielectric layers: the *TBR* obtained with 100 nm-thick AlN layers and SiN layers was 56.4 and 38.5 m<sup>2</sup> ·K/GW, respectively. 

 eprinted with permission from Y. Zhou et al., "Barrier diamond device cooling," **Figure 21.** TEM cross-sections of GaN/diamond interfaces with a 5 nm-thick barrier layer of (**a**) SiN and (**b**) AlN. Uniform and smooth GaN/dielectric and dielectric/diamond interfaces are obtained with the SiN layer. With AlN, some regions (A) show smooth interfaces, however in other regions (B) ≈60 nm of GaN has been etched away (reprinted with permission from Y. Zhou et al., "Barrier layer optimization for enhanced GaN-on-diamond device cooling," ACS Appl. Mater. Interfaces, vol. 9, no. 39, pp. 34416–34422, 2017 [82]. Copyright 2017 American Chemical Society).

> – Seeding the pre-treated AlN surfaces with H-terminated detonation nanodiamond (DND) seeds resulted in an average *TBR* of 16 m<sup>2</sup> ·K/GW. A breakthrough was recently reported by Smith and co-workers [76], who used a two-step electrostatic spray technique to seed 130 nm-thick AlN films deposited on Si substrates. Using this method the experimental *TBR* was as low as 1.47 m<sup>2</sup> ·K/GW, close to 0.8 m<sup>2</sup> ·K/GW, the theoretical minimum *TBR* achievable at the AlN−diamond interface from a diffuse mismatch model, relying only upon the density of states in these two materials [84] (see more details in Section 4.1.3.1).

 achievable at the AlN−diamond interface from a dif It should be mentioned that in the experiments by Mandal et al. [84] and Smith et al. [76] the *TBR* values refer to the interface between the diamond and the AlN substrate: as a consequence, no direct comparison can be made with the *TBR*GaN/diamond previously reported by other groups (which includes the interfaces GaN/dielectric layer and dielectric layer/diamond, as well as the *R*th of the dielectric layer itself). Nevertheless, the replace-

ment of the low κ amorphous SiN layer with crystalline AlN is a promising approach. Ideally, the AlN layer should be integrated just below the GaN channel. This layer would act as an etch stop during the device epitaxy, as well as a seed layer for the diamond growth [168]. This is the approach proposed by Field and co-workers [106]; since integrating a thin AlN or high Al content AlGaN layers at this point in the epitaxy is challenging because of alloying with surrounding layers, they used a relatively low Al content crystalline Al0.32Ga0.68N layer as the etch stop and interlayer and grew diamond following the same procedure as in [84]. Due to the sample layout, a 10 nm-thick SiC layer was formed between the Al0.32Ga0.68N/diamond interface, which improved the heat transport across the two materials. A *TBR* of 30 m<sup>2</sup> ·K/GW was measured, a value still much higher than the theoretical minimum of 4 m<sup>2</sup> ·K/GW obtained for this interface [106].
