**4. Nitride-Based Dielectrics**

Despite the potentiality of Al2O<sup>3</sup> and Al2O3-based dielectric materials, other insulators have emerged as suitable candidates for insulated-gate GaN-based transistors [1,29]. Among them, nitride-based dielectrics are of particular interest compared to oxide-based insulators because of the suppression of the Ga-O bonds that tend to induce interface traps [187].

SiN<sup>x</sup> deposited by in situ MOCVD or LPCVD has been widely demonstrated to be very promising both as a gate dielectric and a surface passivation [29,49]. In particular, in situ SiN<sup>x</sup> enables the dielectric deposition without exposing the (Al)GaN surface to air, which prevents the oxidation of the surface and passivates the surface states, possibly reducing the interface traps. Ogawa et al. [193] demonstrated that the in situ process of SiN<sup>x</sup> can realize an oxide free SiNx/AlGaN interface. Takizawa et al. [194] reported high-resolution TEM analysis revealing abrupt interfaces between SiN<sup>x</sup> and AlGaN. Jiang et al. [78] systematically investigated MIS structures and MIS-HEMTs using in situ MOCVD-SiN<sup>x</sup> as a gate dielectric. A Dit in the range of 2–3 <sup>×</sup> <sup>10</sup><sup>12</sup> cm−<sup>2</sup> eV−<sup>1</sup> was obtained, which resulted in a stable Vth under gate bias and thermal stress. Derluyn et al. [195] reported that the reduction of surface states with in situ SiN<sup>x</sup> passivation of HEMT structures led to higher 2DEG density and lower current collapse. Moens et al. [196] even reported on MIS-HEMTs for 650 V applications with excellent interface quality and dielectric reliability using MOCVD-grown in situ SiNx, which demonstrated a maximum gate voltage of ~3.1 V at 10 years for a 100 ppm failure rate. LPCVD-SiN has the advantages of a large conduction band offset to GaN (~2.3 eV), a relatively high dielectric constant (~7) and a low defects density enabled by the high deposition temperature. Moreover, compared to plasma-enhanced chemical vapor deposition (PECVD)-SiNx, LPCVD-SiN<sup>x</sup> is free of plasma-induced damage and exhibits low oxygen contamination. In this regard, Hua et al. [197] reported on the superior properties of LPCVD-SiN<sup>x</sup> in terms of the leakage currents, breakdown field and TDDB lifetime. Similar investigations were performed by Jauss et al. [198], who predicted a 20-year 100 ppm lifetime at 130 ◦C for a gate voltage of 10.1 V. However, the high deposition temperature of more than 700 ◦C for LPCVD-SiN<sup>x</sup> can instead degrade the GaN surface in recessed-gate structures employed for normally off operations [48]. To overcome this issue, Hua et al. [48] successfully employed an interface protection technique consisting of a SiN<sup>x</sup> interface layer deposited by PECVD prior to the high-temperature deposition process of LPCVD-SiNx. With this approach, normally off hybrid MIS-FETs using highquality LPCVD-SiN<sup>x</sup> with a gate breakdown voltage of 21 V, a maximum gate bias of 11 V at failure rate of 63.2% for a 10-year lifetime, a stable Vth and a small current collapse were demonstrated. A similar approach has been also applied by Jiang et al. [78], who instead used in situ SiN<sup>x</sup> in conjunction with PECVD SiN<sup>x</sup> as a passivation scheme to effectively suppress the current collapse in MIS-HEMTs. Finally, it is worth mentioning that for normally off hybrid MIS-FETs, Hue et al. [42] recently developed another promising technique to protect the etched-GaN surface during the LPCVD-SiN<sup>x</sup> high temperature deposition. This is based on an oxygen-plasma treatment followed by in situ annealing prior to the LPCVD to form a sharp and stable crystalline oxidation interlayer (COIL) protecting the surface. LPCVD-SiNx-gated hybrid MIS-FETs with a COIL revealed a stable Vth and a highly reliable gate dielectric.

AlN is another promising nitride-based material which is attractive as a gate dielectric for insulated-gate GaN-based transistors due to its large bandgap, resulting in a high breakdown field, high permittivity and small mismatch to GaN, which might reduce the trap states at the AlN/(Al)GaN interface. AlN is mainly grown by MOCVD or PEALD techniques [199]. Hashizume et al. [200] were the first to report the low values of Dit in the range of 1 <sup>×</sup> <sup>10</sup><sup>11</sup> cm−<sup>2</sup> eV−<sup>1</sup> at the MOCVD-AlN/GaN interface. Huang et al. [81] revealed an atomically sharp interface between the PEALD-AlN and AlGaN. They also demonstrated that polarization charges in the monocrystal-like AlN used as a passivation layer can effectively compensate the interface traps at the AlN/(Al)GaN interface, significantly reducing current collapse and the on-resistance degradation in ALD-AlN-passivated

AlGaN/GaN HEMTs. Polarization charges in monocrystalline thin AlN layers have also been reported to affect the Vth of hybrid MIS-FETs [79]. The high thermal conductivity of AlN has been also shown to be beneficial to suppress the self-heating of AlN-passivated HEMTs, thus improving the device performance [80]. AlN as passivation layer has also been demonstrated to improve the breakdown voltage of AlGaN/GaN HEMTs compared to SiN-passivated devices [201]. Very recently, Hwang et al. [202] reported a sharp interface between the GaN and PEALD-AlN. With the PEALD-AlN used as interfacial layer, they also successfully suppressed the surface oxidation of the GaN, which resulted in the improved C–V characteristics of AlN/GaN structures. AlGaN/GaN MIS-HEMTs and MIS structures using AlN deposited by a novel technique called low-temperature epitaxy (LTE) have been also recently investigated [199,203,204].

#### **5. Summary**

In this paper, we have summarized the most relevant challenges and recent progress on the development of a gate dielectric technology for insulated-gate GaN-based devices for high-frequency and high-power applications. Specifically, we first pointed out the important physical properties of the insulators which need to be considered for designing a MIS gate structure which delivers improved energy efficiency and reliable device performance. Afterwards, we highlighted that, regardless of the GaN transistor concept and the design, one of the major challenges arising from the insertion of a dielectric on (Al)GaN is represented by the trap states located at the dielectric/(Al)GaN interface or within the bulk dielectric. These trap states strongly affect the performance and the reliability of the device and need to be minimized to ensure high energy efficiency, safe operation and the long-term lifetime of the insulated-gate GaN-based transistors.

Among the various dielectrics, we focused our attention on Al2O3, which is one of the most promising dielectric materials due to its large bandgap and conduction band offset to (Al)GaN, its relatively high dielectric constant, its high breakdown electric field and its thermal and chemical stability against (Al)GaN. In particular, we pointed out that despite the technological progress in the ALD process, enabling the fabrication of high-quality Al2O<sup>3</sup> films and of Al2O3-gated devices with improved and reliable performance, a large amount of defects and trap states at the Al2O3/(Al)GaN interface is still present and still degrades the device performance. In this regard, the main results obtained in the literature of the interface state density distribution at the Al2O3/(Al)GaN interface are presented and discussed in detail, and the recent progress in the performance of the Al2O3-gated MIS-HEMTs are reviewed.

Finally, novel Al2O3-based dielectric or compound materials and interface engineering approaches involving the use of Al2O3, which have been exploited to improve the quality and electrical performance of Al2O3-gate MIS structures, have been presented. Among them, AlON, or the use of nitride-based interface control layers have been demonstrated to be the most promising techniques. In addition to that, nitride-based dielectric materials have also been briefly presented as promising candidates, especially driven by their potential to function both as a gate dielectric as well as a passivation layer.

The insights of this paper help to understand the current status and the recent progress of the Al2O<sup>3</sup> gate dielectric technology for insulated-gate GaN-based transistors. It also highlights that the current state of the art has made great advancements, but still requires remarkable progress in terms of gate dielectric, gate stack engineering and interface control technology. Focused efforts are still needed in order to ensure a low interface and bulk trap density, thus enabling a robust reliability under stringent and dynamic electrical stresses. Further advances in the gate dielectric technologies are necessary to overcome these obstacles and to pave the way for the massive advent of insulated-gate GaN-based technologies in the electronic market.

**Funding:** This research received no external funding.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** No new data were created or analyzed in this study.

**Acknowledgments:** Anthony Calzolaro acknowledges financial support from DFG (project no. 405782347).

**Conflicts of Interest:** The authors declare no conflict of interest.
