**1. Introduction**

A central challenge of power electronics today is to address the continuously rising demands for safe and reliable control, conversion and distribution of energy, while maximizing the efficiency. Switched-mode power conversion strategies, with myriad applications [1–5], are now universally preferred over the simpler linear conversion methods due to the advantages of better flexibility, safety, and importantly, higher efficiency. The core requirement for efficient power conversion thus translates directly to highly efficient power transistors that can sustain repeated OFF/ON switching transitions with minimal switching and resistive losses. Higher operational frequencies are desirable, since they reduce the amount of energy transferred/cycle, which in turn reduces the size of the passive circuit components in the converters. Since higher frequencies will inevitably correspond to increased switching losses, the upper limit on the operational frequency (currently, in the MHz range) is majorly determined by the switching capabilities of the available power transistors.

**Citation:** Mukherjee, K.; De Santi, C.; Borga, M.; Geens, K.; You, S.; Bakeroot, B.; Decoutere, S.; Diehle, P.; Hübner, S.; Altmann, F.; et al. Challenges and Perspectives for Vertical GaN-on-Si Trench MOS Reliability: From Leakage Current Analysis to Gate Stack Optimization. *Materials* **2021**, *14*, 2316. https:// doi.org/10.3390/ma14092316

Academic Editor: Fabrizio Roccaforte

Received: 23 March 2021 Accepted: 27 April 2021 Published: 29 April 2021

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**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

Silicon-based transistors have evolved over the years to meet the market needs; however further optimization is now bounded by the theoretical limits of Si. In this regard, wide-bandgap (WBG) semiconductors have found great consensus in being promising substitutes to Si transistors, derived from their superior figures of merit (FOMs). According to Baliga's FOM (BFOM) (= *εµE* 3 *G* , *V* 2 *BR Ron* ) [6], materials such as GaN and SiC present comprehensive improvements in the breakdown voltage (*VBR*) vs. on-resistance (*Ron*) tradeoff. Comparing other FOMs provide easy estimations of the relevant metrics (a) conduction and switching losses from the on-resistance × output capacitance product (*Ron* × *Coss*) [7] and (b) power density from √ 1 *QgRonApackageRth* [8] where *Apackage* is the package size and *Rth* is the thermal resistance. The gate charge *Q<sup>g</sup>* represents the switching loss incurred by the charging and discharging cycles of the gate terminal. Here too, GaN emerges as the dominant choice over Si, as reviewed by Vecchia et al., in [1].

Thus, combining the improved transport, breakdown and thermal properties, the use of WBG materials enables cost and size-effective power transistors (converters) operating at high voltages and temperatures with higher speeds (lower switching losses), and with higher overall efficiency (lower conduction and switching losses).

Although GaN (BFOM = 3175 [9]) is superior to SiC (BFOM = 840 [9]) in most material properties, SiC has better thermal conductivity and is generally considered to be more relevant to the high voltage (>1200 V) application domain, while the commercial marketability of GaN is usually assumed to be in the low to mid voltage ≤650 V (power capability ≈ kW) domain [1,9,10]. This is primarily because of the current and voltage limitations [1,9,11] of the lateral configuration initially adopted for design of GaN power transistors. These devices were built to capitalize on the high-mobility high-density 2DEG formed at the AlGaN/GaN hetero-interface and indeed, several works on lateral GaN transistors have displayed impressive performances in the mid-voltage range [12–14], as a result of revolutionary improvements in GaN epitaxy and design over the last couple of decades.

However, to establish GaN power transistors as serious contenders in application markets such as Electric Vehicle/Hybrid Electric Vehicle (EV/HEV) [4] or power grids, voltage capabilities up to 1700–1800 V are required. To this aim, the research focus is now shifting to vertical GaN structures [2,3,15]. In addition to better heat management and normally off capabilities, vertical architectures overcome the breakdown voltage vs. device area tradeoff of lateral devices. With proper optimization, vertical transistors are also expected to present better reliability performance, since the electric field is moved within the bulk, eliminating surface issues.

Fully vertical GaN-on-GaN diode and transistor demonstrators have reported excellent performances (up to 3-4 kV capability [16–24]). However, GaN substrates are small and expensive, with wafer costs per unit area for GaN-on-GaN ranging up to \$ 100/cm<sup>2</sup> for 2-inch wafers [25,26]. Thus, currently these devices have limited commercial viability. Economically, the GaN-on-Si technology appears to be the most worthwhile for further development, with 8-inch wafers costing only \$1 per unit area, potentially lowering wafer costs by 100 times. [25,26]. However, owing to the mismatches in lattice constant and thermal expansion coefficient between GaN and Si, the growth of thick GaN layers on Si are subject to high dislocation/defect densities, which makes the epitaxy especially challenging. Although some innovative techniques have been successful in fabricating fully vertical GaN-on-Si diodes [27–31], and a fully vertical GaN-on-Si power transistor (*VBR* = 520 V, *Ron* = 5 mΩ.cm<sup>2</sup> ) was recently demonstrated by Khadar et al. in [32] using substrate removal techniques, fully vertical GaN-on-Si technology is still in a very nascent stage. Recent results demonstrate the possibility of using engineered substrates (QST®), with a matched coefficient of thermal expansion, to enable low-cost vertical GaN FETs on large diameter wafers (8–12 inch) [33].

For the development of the gate module and for the optimization of the drift region of vertical GaN devices, an important step is the development of quasi-vertical GaN-on-Si devices [3,27,34–36], based on the idea of maintaining the source and drain electrodes on

the same side of the wafer. This approach allows us to understand, study and overcome the challenges related to the development of vertical GaN transistors, before moving to the full vertical layout. Quasi-vertical structures can build on the recent advancements into GaN-on-Si epitaxy achieved during research into lateral GaN devices, while providing better field management due to the vertical stack. Among the several available quasivertical configurations such as CAVETs [24,37], OG-FETs [38,39] or Fin FETs [22,40], the trench MOSFET [2,3,32,34,41–46] is a popular choice with high cell density. It is inherently a normally off device with low *Ron*, and needs no regrowth of AlGaN/GaN channels. Figure 1 presents the schematic of a typical quasi-vertical GaN-on-Si trench MOSFET.

**Figure 1.** Schematic of a quasi-vertical n + -p + -n −-n <sup>+</sup> GaN-on-Si trench MOS device.

In the ON-state, the current in the quasi-vertical structure is sourced from the top n + layer, and conducted vertically through the p <sup>+</sup> GaN layer along the gate trench sidewalls. The current is then collected laterally through the bottom n + layer, before being transported back to the surface through the drain metallization. A high doping of the n + currentspreading layer ensures better current distribution, to minimize current crowding around the contact in the ON-state.

To design a reliable GaN-on-Si trench MOSFET, careful optimization of several interlinked physical parameters is required. As discussed earlier, the first design consideration, as for any power transistor, is to achieve a high *VBR* and low *Ron* simultaneously. In this regard, the thickness and doping of the p-body and drift layer are the central constraints. The parameters need to be carefully engineered to ensure good reverse blocking capability in the OFF-state in addition to forward conduction in the ON-state. Regarding the M-O-S stack, gate design parameters such as dielectric composition and thickness are important in controlling the threshold voltage, leakage and gate capacitance of the device. The dielectric choice, in addition to structural optimization of the trench to minimize field crowding, controls the gate breakdown capability. Finally, the leakage and trapping needs to be minimized throughout the quasi-vertical stack.In this work, we will discuss recent case studies that address the impacts of different design choices on the performance of quasi-vertical trench MOSFETs, while demonstrating testing strategies used to identify and compare degradation mechanisms in such devices. In Section 2, p + -n −-n <sup>+</sup> diode test structures are characterized; leakage modeling is used to identify the dominant mechanisms under reverse bias, and technology computer-aided design (TCAD) simulations are employed to compare the effects of high vs. low p-body doping, to present a trade-off useful for breakdown optimization. In Section 3, the optimization of the gate stack through the use of a bilayer dielectric is discussed. Specifically, the trapping and breakdown performance of bilayer (SiO<sup>2</sup> + Al2O3) vs. unilayer (Al2O3) dielectrics are compared, and the effects of trench optimization are visualized by scanning electron microscopy (SEM) and transmission electron microscopy (TEM) analysis. In Section 4, methodologies for the assessment of the dynamic performance of the devices are presented. In addition, light-assisted experimental techniques are discussed, which improve the detection and understanding of trapping phenomena under low and high positive gate stresses.
