**2. Materials and Methods**

Several different compliance substrates have been realized to improve the quality of the heteroepitaxial growth.

Inverted silicon pyramids (ISP) were fabricated on (001) Si wafers by deep UV lithography. The structures consisted of 700 nm-wide square geometries with a 1.4 µm pitch. A thin layer of stoichiometric silicon nitride deposited by LPCVD with a thin buffer layer of thermal silicon dioxide was used as a hard mask. The layer was etched by a fluorine-based plasma and the silicon substrate was etched by a 45 wt.% KOH @ 70 ◦C solution.

In the second compliance substrate, the samples consist of a silicon (0 0 1) substrate with 2 µm of Si1−xGe<sup>x</sup> grown on top and a cap of 10 nm or 20 nm thick Si. From simulations [28], the ideal value of [Ge] for the lattice match was calculated to be around 12%. In our studies, three germanium concentrations were used at 10%, 12%, and 15% The heteroepitaxial growth of the 3C-SiC films on the ISP and Si-Ge buffer substrates was realized using a chemical vapor deposition process by NOVASiC in a horizontal hot-wall reactor operating with standard silane/propane/hydrogen chemistry [29].

In the third compliance substrate, the Si(111) substrates were patterned into hexagonal arrays of pillars on 100 mm wafers. The standard Bosch process in the shape of hexagonal prisms 8 µm deep and 2 or 5 µm wide that were separated by 2 or 3 µm trenches was applied to fabricate the pillars. The pillars had 100 µm hexagonal patches separated by 5 µm trenches to avoid their contact and reduce substrate bowing. To further improve the pillars' properties, a three-step procedure was used: (i) a vertical Bosch process was first applied to dig the pillars; (ii) one isotropic dry carving was next applied to create the under etching and necking; and (iii) some oxidation-stripping cycles were used to finally smooth the sidewalls and reduce the top layer thickness of the pillars. The heteroepitaxial growth was realized in a LPE M10 reactor using a trichlorosilane–ethylene hydrogen chemistry [6].

For the bulk growth, 3C-SiC seeds were realized on Si (100) substrates using a chemicalvapor deposition process in a horizontal hot-wall reactor (LPE M-10, Catania, Italy). The silicon and carbon precursors were trichlorosilane (SiHCl<sup>3</sup> or TCS) and ethylene (C2H4) using hydrogen (H2) as a gas carrier. The process was implemented in a low-pressure regime (100 mbar), wherein the epitaxy started at 3 µm/h, then increased to 6 µm/h, and finally further increased to 30 µm/h. This process resulted in a thick layer of about 70 µm. In the next step, the temperature was increased above the melting point of silicon. This resulted

in the Si substrate being fully melted inside the CVD reactor. The remaining freestanding SiC layer was used as a seed layer for the following homoepitaxial growth which used low-pressure regime at different temperatures (between 1600 and 1700 ◦C). A growth rate of 60 µm/h was used to increase the substrate thickness for two hours [6]. The first 20 microns of the 30 µm layer were highly doped and the last 10 microns were low doped for device realization. Nitrogen was used for n+ and n-type layer formation. The total thickness of the 3C-SiC homoepitaxial samples was about 200 µm (confirmed by SEM analysis).

Another approach for the bulk growth is to use enhanced sublimation epitaxy (ESE), which is a modified physical vapor transport (PVT) growth technique originating from a patent-protected epitaxial SiC growth method [30] developed by researchers at the Linköping University. A typical ESE growth setup is shown in Figure 1. The exclusiveness of the ESE is the distance between the source and the substrate, as well as the character of the source material itself. In a standard PVT setup, the distance between the source and the substrate is more than 10 mm, while in the ESE it typically varies between 0.5 and 2 mm. Such a distance is sufficient to create a large enough temperature gradient, which is the main driving force for the growth. In addition, compared to PVT, such a short distance allows for the more direct transfer of SiC vapor species from the source to the substrate, with a much lower interaction with the graphite walls. In PVT, the source material is a polycrystalline SiC powder, while in the ESE, the powder is replaced by a polycrystalline SiC plate. Furthermore, tantalum (Ta) foil is inserted into the graphite crucible. At growth temperatures, it reacts with carbon-bearing species and forms TaC. In this way, the vaporphase composition inside the crucible is enriched with Si, which is beneficial for the enhancement of 3C-SiC stability. The combination of the short distance, Si-enriched growth ambience, and stochiometric monolithic source makes ESE an excellent technique for the growth of high-quality SiC layers in a vacuum (1 <sup>×</sup> <sup>10</sup>−<sup>4</sup> mbar) at temperatures below 2000 ◦C. Such growth conditions are favorable to induce SiC conversion from hexagonal to cubic polytypes, which are known to be more stable at temperatures below 2000 ◦C.

Using a transfer process developed at FAU Erlangen-Nurnberg [31], growth of the bulk 3C-SiC with reasonable dimensions and thicknesses was demonstrated using such seeding material and the approach of closed space PVT (CSPVT), [26,32], in its original concept also known as Sublimation epitaxy (SE), was utilized.

**Figure 1.** (**a**) PVT reactor used for the sublimation growth and hot zone consisting of a tantalum foil to acquire carbon, the source material, a spacer to separate the source and seed, and the manufactured seeding stack. (**b**) Schematic of the seed manufacturing process. Starting from 3C grown by CVD on a silicon substrate, the silicon is removed by chemical wet etching and subsequently the thin freestanding 3C layer is merged to a polycrystalline SiC carrier for mechanical stabilization and backside protection (see Reference [32]).

Starting from 3C-on-Si material grown by CVD (LPE M10, Catania, Italy), hightemperature stable seeds for bulk growth in a PVT setup can be fabricated according to Figure 1b. First, the CVD seeds are cut to get the desired dimensions. At the start of the project, a diamond wire saw was used. However, the size of the samples that could be prepared was limited to approximately 12.5 <sup>×</sup> 12.5 mm<sup>2</sup> , as the sawing process induced cracks along the <110> direction in the 3C layer due to the applied mechanical force [33]. Therefore, a change to a multipulse-laser ablation technique [34,35] was made. As the melting point of silicon (1419 ◦C) is well below the required temperatures for PVT growth (<1800 ◦C), a removal of the silicon substrate is necessary. Otherwise, the molten silicon would immediately react to silicon carbide with the graphite crucible and graphite isolations used in PVT setups [24]. Therefore, after the cutting of the samples, a wet-chemical etching of the silicon substrate with HNA (HF: HNO3: H2O) was performed [36,37], resulting in a thin (typically between 20 and 50 µm) free-standing 3C-SiC layer. The etched layers featured a high-quality growth front as well as a defect-rich backside associated with the former transition area between Si and 3C-SiC. Subsequently, the layers were merged to a polycrystalline SiC-carrier with the high-quality growth front facing up. This step is necessary for the mechanical stabilization of the thin 3C layers and to prevent a backside sublimation during the sublimation growth. For the merging, a carbon glue with the main component of 1-Methoxy-2-propanol acetate [31] was used and both a combined heat and pressure treatment was applied. After the merging, residues of the carbon glue that could remain on top of the growth caused by an overflow of the glue were removed to maintain a high-quality starting point for the sublimation growth [38].
