*4.3. MOSFET*

Early 3C-SiC power devices were predominantly demonstrated via heteroepitaxial 3C-SiC grown by chemical vapour deposition (CVD) above silicon substrates in addition to free-standing wafers, provided by HOYA Advanced Semiconductor Technologies Co Ltd. [50,74,97,98]. Power devices were based on diode and MOSFET (lateral and vertical) architectures. Devices demonstrated by 3C-SiC CVD grown on undulant-silicon substrates suffered from premature breakdown voltage and high leakage currents due to APBs and SF inherent within the epitaxial layer of the device [99,100].

Typical characteristics showed that achieving breakdown voltages in excess of 600 V was challenging since the leakage current emanating from the formerly mentioned p-n junction SFs degraded performance in a terminal manner [100]. High current cellular vertical 3C-SiC MOSFETs were demonstrated by Abe et al. [74]. This device achieved an impressive 1220 A/cm<sup>2</sup> current density based on a single cell. This corresponds to a current carrying capability of 41–132 A for a 3 <sup>×</sup> 3 mm<sup>2</sup> , 600 V chip. SF-induced leakage current hampered the off-state performance of this MOSFET. CVD deposited gates produced 600 V-MOSFETs with a high channel mobility of 200 cm2/Vs [101]. The high channel mobility and low specific on-state resistance of 5–7 mΩcm<sup>2</sup> were brought about by a specific activation anneal of 1600 ◦C in argon (Ar), in order to realise a smooth 3C-SiC surface prior to deposition of the gate oxide. They used 600 V DMOSFETs to show that material quality has a strong influence on the blocking behaviour. In contrast, the on-state electrical characteristics were unaffected [102]. A 200V reduction in breakdown voltage was observed for DMOSFETs with a high crystal defect density.

Due to the lower interface trap density at the 3C-SiC/SiO<sup>2</sup> interface compared with 4H-SiC, MOSFETs are the most studied 3C-SiC devices, targeting for lower on-resistance than 4H-SiC MOSFETs in medium voltage applications (600–1200V). High field-effect mobility values were demonstrated by fabricating 3C-SiC MOSFETs with a high current density of 1220 A/cm<sup>2</sup> and encouraging scaling features were shown in 1 mm <sup>×</sup> 1 mm and 3 mm × 3 mm devices [74]. In addition, it is shown in [65,68] that by removing the rapid thermal anneal for the ohmic contact, the field-effect mobility can be further improved. Despite the achievements made in forward conditions, reaching blocking ability (BV) close to the theoretical values is still a challenge, mainly because of the high leakage current induced by crystal defects such as SFs [97]. By reducing stacking faults to ~90 cm−<sup>1</sup> , the device blocking ability (5 <sup>×</sup> <sup>10</sup><sup>15</sup> cm−<sup>3</sup> doped drift region) can be significantly improved to 600 V [50], close to the unipolar limit. Table 6 is a summary of the recent literature results for 3C-SiC MOSFET fabrication.


**Table 6.** A summary of literature data on the forward and reverse performance of 3C-SiC MOSFETs.
