*Review* **Challenges and Perspectives for Vertical GaN-on-Si Trench MOS Reliability: From Leakage Current Analysis to Gate Stack Optimization**

**Kalparupa Mukherjee 1,\*, Carlo De Santi <sup>1</sup> , Matteo Borga <sup>2</sup> , Karen Geens <sup>2</sup> , Shuzhen You <sup>2</sup> , Benoit Bakeroot <sup>3</sup> , Stefaan Decoutere <sup>2</sup> , Patrick Diehle <sup>4</sup> , Susanne Hübner <sup>4</sup> , Frank Altmann <sup>4</sup> , Matteo Buffolo <sup>1</sup> , Gaudenzio Meneghesso <sup>1</sup> , Enrico Zanoni <sup>1</sup> and Matteo Meneghini <sup>1</sup>**


**Abstract:** The vertical Gallium Nitride-on-Silicon (GaN-on-Si) trench metal-oxide-semiconductor field effect transistor (MOSFET) is a promising architecture for the development of efficient GaNbased power transistors on foreign substrates for power conversion applications. This work presents an overview of recent case studies, to discuss the most relevant challenges related to the development of reliable vertical GaN-on-Si trench MOSFETs. The focus lies on strategies to identify and tackle the most relevant reliability issues. First, we describe leakage and doping considerations, which must be considered to design vertical GaN-on-Si stacks with high breakdown voltage. Next, we describe gate design techniques to improve breakdown performance, through variation of dielectric composition coupled with optimization of the trench structure. Finally, we describe how to identify and compare trapping effects with the help of pulsed techniques, combined with light-assisted de-trapping analyses, in order to assess the dynamic performance of the devices.

**Keywords:** vertical GaN; quasi-vertical GaN; reliability; trapping; degradation; MOS; trench MOS; threshold voltage
