**4. ON-State-Light Assisted Analysis of Trapping Mechanisms in Quasi-Vertical MOSFETs from IMEC, Leuven, Belgium**

For reliable ON-state operation of GaN MOSFETs, it is fundamental to understand and minimize the trapping states for the insulator/GaN interface. Since III-V semiconductors have no native oxides, developing high quality oxide films on GaN is difficult. The progress in the application of the atomic layer deposition technique has allowed the successful deposition of low-defect Al2O<sup>3</sup> films on GaN, improving the performances of MOS structures. However, identifying relevant trapping sites and the induced threshold voltage Vth instabilities [44,89,106,107,110,111] due to limited controllability of the GaN surface potential continues to be a primary task to the adoption of GaN vertical MOSFETs in real applications.

In Section 3.1, the trap impacts on threshold voltage were found to be comparable between bilayer and unilayer dielectric cases, indicating that states at or near the GaN/Al2O<sup>3</sup> interface are presumably the major contributing factor to bias threshold instability (BTI) observations.

In this section, we focus on unilayer Al2O3-only trench MOSFET devices with an average Vth of 2 V, with device structure similar to Figure 1, to understand the trapping

mechanisms through characterization of induced Vth shifts [44]. Within the Al2O3/GaN system, three fundamental trapping locations have been identified [106,107]. Trap states within the bulk dielectric and near-interface or border sites depend strongly on the properties of the deposited Al2O3, while the states along the Al2O3/GaN interface (quantified by the interface state density Dit ) correlate to the quality of the dielectric/semiconductor boundary, and of the process. For a wide band-gap material such as GaN, it is often difficult to isolate the effects of energetically deep trap states. This is where light energy, and especially the application of UV light with energies approaching/higher than the GaN band-gap, is valuable. In the following results, we investigated Vth shifts under positive gate stress, by combining analytical techniques to identify trap processes and associated recovery dynamics. In each case, light energy is used to support the analyses, and provide further insight into the physical origin of the trap states.

The first set of measurements to test the dynamic performance of the devices, as summarized in Figure 11, are double pulsed measurements. The double pulse measurement system is a powerful high voltage, high speed setup to analyze the dynamic performance of devices by synchronously pulsing the gate and drain voltages. The pulsing setup switches between the quiescent (stress conditions) and measurement phases within relatively short time scales (µs). The V<sup>G</sup> stress settings are incremented from VG,Stress = 0 V to 5 V, VD,Stress = 0 V for a quiescent time of t<sup>Q</sup> = 100 µs, and the ID-V<sup>G</sup> measurement settings were VGS = −1 to 7 V, VDS = 8 V for a measurement time tmeas = 1 µs. In Figure 11a, the measurements were performed in dark conditions, displaying a positive shift in Vth (PBTI) of 1.2 V for Q (5,0) (Vth calculated as the voltage intercept at I<sup>D</sup> = 5 mA/mm). The Vth shift can be attributed to the fast-pulsed stressing configuration, with no recovery intervals between the progressively stronger stress conditions.

Δ **Figure 11.** Double pulsed characteristics; (**a**) Measurements under dark conditions show a ∆Vth = 1.2 V and very little recovery in the measured IDVG, 5 min after the stress at Q (5,0); (**b**) Comparison of current level shifts measured under no light and UV light. Under UV illumination, shifts are lower under during stress conditions, and post-stress recovery is faster.

Δ After a rest period of 5 min following the positive gate stress at Q (5,0), the ID-V<sup>G</sup> measured for Q (0,0) condition still showed substantial degradation from the initial ID-V<sup>G</sup> characteristic at Q (0,0), indicating semi-permanent trapping processes. This can also be visualized by plotting the ∆ID/ID, max ratio in Figure 11b for the high stress Q (5,0) condition.

– The shift in the current levels under stress was 30% of the pre-stressed current maximum, while 5 min of recovery reduced it to 25–27%. On the other hand, repeating the same stress-recovery cycles as in Figure 11a, but under the presence of UV light displayed substantial improvement. As highlighted in Figure 11b, under UV light, for the highest stress condition of Q (5,0), the shift in the current levels was less than 10%. Furthermore,

at Q (0,0) was found to be negligible (ΔI ≈ 2–

– measurements of 10 μs each are

transients in the 10 μs–

letting the device recover for 5 min thereafter, the deviation in the ID-V<sup>G</sup> at Q (0,0) from the unstressed initial ID-V<sup>G</sup> at Q (0,0) was found to be negligible (∆ID/ID, max <sup>≈</sup> 2–3%, not shown).

Based on these observations, a powerful transient setup was employed to take a closer look at the evolution of induced Vth shifts under longer gate stress durations, in the presence of different monochromatic light energies. This versatile setup accurately evaluates Vth transients in the 10 µs–100 s range where a typical measurement consists of 100 s of stress and 100 s of recovery. Twenty-two fast ID–V<sup>G</sup> measurements of 10 µs each are performed during the stress/recovery phases to compare the evolution of Vth. During initial measurements using this technique, small negative Vth shifts were observed at low stress voltages [89,112], and high positive Vth shifts were observed for gate stresses of 4 V and higher [44]. To investigate the effects of light-assisted de-trapping, the recovery was repeated under different wavelengths of light, following 100 s of trap filling at VG,Stress = 5 V, and VD,Stress= 0 V.

Figure 12 presents the results of the light-assisted Vth transient technique. In Figure 12a, a positive Vth shift of 0.75 V is seen after 100 s of stress at VG,Stress = 5 V. The recovery transient (at VG,Rec = 0 V and VD,Rec = 0 V) in response to this stress, was measured under dark and under monochromatic light energies from 1.6 eV to 3.1 eV, as illustrated in Figure 12b,c. Under dark conditions, the recovery is slow and hence incomplete [113] at the end of the 100 s of recovery phase. For low photon energies, such as 760 nm, only 50% (0.35 V) of the stress-induced PBTI was recoverable within 100 s. For higher photon energies, de-trapping was found to be gradually accelerated. The threshold energy (associated to the lowest energetic position of deep bulk states) for improved de-trapping was identified to be 2.95 eV (420 nm), while complete recovery of the 0.75 V of positive Vth shift was observed within the 100 s window for the 3.1 eV (395 nm) case. As can be noticed in Figure 12b, all photon energies below 2.7 eV did not induce any significant changes, with small/negligible recovery. Small variations observed below this threshold in Figure 12c may be ascribed to small (5–10%) measurement inconsistencies and/or noise.

**Figure 12.** Vth transient measurements (**a**) Shift in Vth (Vth−Vth@10 <sup>µ</sup><sup>s</sup> ) during stress phase of 100 s at VG,Stress = 5 V. (**b**) Vth evolution during recovery phase of 100 s at VG,Stress = 0 V under varying light wavelengths from 760 nm to 395 nm, following equivalent stress phases as described in (**a**), (**c**) absolute Vth shift during recovery (Vth@100s−Vth@10µ<sup>s</sup> during recovery) versus the light energy.

A direct takeaway from this would be the presence of trap states located energetically between 2.9 eV and 3.1 eV from the conduction band of the oxide, which equates to 0.8 to 1.0 eV from the conduction band of the semiconductor, considering a conduction band offset of 2.16 eV [86] at the Al2O3/GaN interface.

The final light-assisted technique to identify trap distributions is the photo assisted CV method [44,114]. This measurement approach evaluates the distribution of interface states located along the gate dielectric interface to GaN. In this method, capacitance-voltage measurements, obtained under a photo-assisted de-trapped condition and a bias-induced trapped condition, are compared to quantify the interface state density. The use of UV light allows us to empty all defects at the interface (when the device is in depletion) to probe interface states deep within the bandgap. The results of the photo-assisted CV experiment are displayed in Figure 13.

**Figure 13.** Photoassisted CV method for Dit extraction; (**a**) Capacitance-time transient during exposure to UV light at V<sup>G</sup> = 0 V; (**b**) Capacitance-time transient during filling of traps at V<sup>G</sup> = 5 V. (**c**) C-V comparison between detrapped (after UV light) and trapped state. (inset) Electron Dit vs. EG.

The devices are biased in depletion condition for a short time and then exposed to UV light in order to empty all traps at the interface, as shown in Figure 13a. In the presence of UV light, electron-hole pairs are generated, accompanied by an increasing capacitance transient due to the release of trapped charge inside the depleted region. The duration of UV exposure is 50 s, until the capacitance level saturates. This is followed by a longer time interval in the dark (500 s) to allow enough time for the excess photo-generated carriers to leave the system and reach thermal equilibrium. Then, the de-trapped capacitance-voltage curve from depletion to accumulation is measured from V<sup>G</sup> = 0 V to 5 V (see Figure 13c). Bias at the end voltage (5 V) is maintained for a moderate filling time (80 s), to induce charge trapping at insulator and interface states, as shown in Figure 13b. Finally, the second C-V curve of the trapped device is measured from accumulation to depletion. The difference in C-V slope of the trapped and de-trapped curves allows the extraction of Dit versus energy, while the fixed shift in the curves is proportional to the amount of charge trapped in the bulk of the oxide and/or in near-interfacial or border traps. The Dit profile (inset of Figure 13c) reveals shallow traps located around 0.3 eV from the conduction band.

Based on the observations in Section 4, the following inferences regarding relevant trapping mechanisms under forward gate stress can be drawn, as also summarized in Figure 14.

**Figure 14.** Energy band diagrams illustrating trapping locations in the Metal/Al2O3/GaN system (**a**) mechanisms activated at low V<sup>G</sup> stress. M1: negative ∆Vth due to detrapped electrons from oxide towards metal. M2\_VLOW: moderate and recoverable positive ∆Vth due to injection of electrons from GaN accumulation into the border oxide traps; (**b**) mechanisms strengthened at high gate stress, M2\_VHIGH: strong positive ∆Vth due to electrons injection into energetically deeper interface traps or bulk states in the dielectric. M2\_VHIGH causes semi-permanent trapping which requires external light energy (inducing de-trapping) for achieving fast recovery of Vth [44].

The small NBTI observed during Vth transients at low gate stresses (≤2 V) is attributed to de-trapping of electrons within the gate oxide to the metal (M1 in Figure 14). When medium gate stresses are applied (≈3–4 V), small amounts of PBTI can be attributed to electron trapping from the semiconductor towards border states in the dielectric (M2\_VLOW in Figure 14). Vth shifts owing to this process are recoverable once stress is removed and the Fermi level is restored, even under dark conditions if enough recovery time is provided. For high gate stresses (≥4V), strong PBTI is induced, and this contribution suffers from low recovery under dark conditions, even for long recovery times (~ days). The mechanism

responsible for this semi-permanent Vth degradation (M2\_VHIGH in Figure 14) is due to the worsening of M2 under high fields, resulting in electron transport from the channel to energetically deeper trap states along the interface, or further within the bulk of the dielectric. To enable de-trapping from these deeper trap states, light energy ≥2.9 eV is required.
