*4.1. Binary High-κ Oxides in 4H-SiC MOSFETs*

κ Since the band gap for SiC is three times larger than that for Si, the band offset at the SiO2/SiC interface is smaller than that in the SiO2/Si system. Hence, in SiC MOS-based systems, a higher tunnelling current than in Si is expected for a given oxide thickness [8].

κ *κ* Because of its high permittivity (20), hafnium oxide (HfO2) has been widely used in Si technology. Hence, this material has attracted also the attention of the SiC scientific community. In particular, the investigation started by studying the electronic structure of the HfO2/SiC interface [101]. However, it was clear that HfO<sup>2</sup> alone is not suitable for SiC because of the low conduction band offset (in the range 0.5–0.7 eV)) at the HfO2/SiC interface, which may not provide an adequate barrier height for electron injection from the substrate [101,102]. Because of the intrinsic limitation of the band alignment, attention moved to the study of the HfO2/SiO2/SiC system [102].

Moreover, other high-κ binary oxides with larger band gaps and more favourable band alignment with SiC, such as Al2O<sup>3</sup> [101], La2O<sup>3</sup> [59,103], and ZrO<sup>2</sup> [104,105], have been investigated.

In general, in order to mitigate the fundamental limitations of high-κ binary oxides, the introduction of a SiO<sup>2</sup> interlayer between the high-κ material and SiC is often adopted [58,102].

A good survey of the literature on high-κ dielectrics for SiC was recently reported by Siddiqui et al. [106].

κ As described before, using high-κ dielectrics in 4H-SiC MOS-based devices can be beneficial to fully exploit the properties of the material and reduce the device's on-resistance. However, combined interaction with the SiOx layer can give further improvements. As an example, high channel mobility in 4H-SiC MOSFETs with Al2O<sup>3</sup> gate insulators fabricated at low temperatures by MOCVD (64 cm2V −1 s −1 ) can be obtained when the Al2O<sup>3</sup> gate insulator is deposited at 190 ◦C. According to Hino et al. [107], this result could be further improved up to an extremely high field-effect mobility of 284 cm2V −1 s <sup>−</sup><sup>1</sup> when the 4H-SiC MOSFET was fabricated with an ultrathin thermally grown SiOx layer inserted between the Al2O<sup>3</sup> and SiC interface [107].

κ κ κ On this particular aspect, the impact of a thin SiO<sup>2</sup> layer thickness inserted between Al2O<sup>3</sup> and SiC on the channel mobility in Al2O3/SiC MOSFETs was investigated by Hatayama et al. [108]. They demonstrated that the peak value of the field-effect mobility in Al2O3/SiO2/SiC MOSFETs could reach 300 cm2V −1 s −1 for an SiO<sup>2</sup> thickness of 1 nm. On the other hand, when the SiO<sup>2</sup> layer increased up to 2 nm, the field-effect mobility drastically reduced to 40 cm2V −1 s −1 [108], as illustrated in Figure 10.

κ Another possible approach is employing a semiconductor surface treatment prior to gate insulator deposition. Lichtenwalner et al. [43] reported the use of a NO annealing at

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1175 or 1100 ◦C for 20 min of a 4H-SiC semiconductor in an attempt to control the interface state density Dit. This procedure allowed obtaining a peak field-effect mobility in 4H-SiC MOSFETs of 106 cm2V −1 s <sup>−</sup><sup>1</sup> using an Al2O<sup>3</sup> film deposited by ALD as gate dielectric with postdeposition annealing at 400 ◦C for 30 s. − − − −

**Figure 10.** (**a**) Comparison between the field-effect mobility obtained in 4H-MOSFETs fabricated using Al2O<sup>3</sup> insulators with and without an ultrathin thermally grown SiOx layer inserted between the Al2O<sup>3</sup> and SiC interface. (**b**) Peak value of the field-effect mobility obtained using SiOx layers with different thicknesses. The data are taken from [107,108].

− − However, a key aspect is the channel mobility at the operative gate bias. In fact, the remarkable peak values of the field-effect mobility are often accompanied by a rapid decrease due to an increase in the gate bias close to the value at which the device should operate. This particular phenomenon can be understood analysing the single components limiting the channel mobility. As an example, a rapid decrease in the field-effect mobility is associated with a dominant phonon-scattering mechanism, while a smooth decrease with an increase in the gate bias is associated with coulombic scattering [109,110]. In particular, Arith et al. [111] demonstrated a process for forming aluminium oxide (by ALD) as a gate insulator in 4H-SiC MOSFET that did not involve the insertion or formation of SiO<sup>2</sup> at the interface, eliminating traps that may be present in SiO2. This was achieved with hydrogen plasma pre-treatment followed by annealing in forming gas. Hydrogen treatment was effective at reducing Dit at the interface of aluminium oxide and SiC without a SiO<sup>2</sup> interlayer.

<sup>−</sup> <sup>−</sup> − − − Clearly, because of the large differences in the mobility behaviour of the MOSFETs processed under different conditions, this topic has been strongly debated. In particular, Yoshioka et al. [47] demonstrated optimization of the interface of aluminium oxide and SiC without a SiO<sup>2</sup> interlayer, resulting in a low Dit for the metal oxide semiconductor (MOS) capacitor of 1.7 <sup>×</sup> <sup>10</sup><sup>12</sup> cm−<sup>2</sup> eV−<sup>1</sup> at E<sup>C</sup> <sup>−</sup> <sup>E</sup><sup>t</sup> = 0.2 eV and a peak field-effect mobility of 57 cm2V −1 s −1 that was quite constant with the variation of the gate bias. Other works have tried to figure out the right combination of semiconductor surface pre-treatments and postdeposition annealing in order to improve the electrical properties of Al2O3/SiC interfaces [41,46].

Other processing steps have been explored to improve the performance of 4H-SiC MOSFETs, e.g., by appropriate manipulation of the SiO2/SiC interface. In particular, Yang et al. [112] deposited 30 nm of SiO<sup>2</sup> by ALD and subsequently performed a postdeposition annealing (PDA) in a nitrous oxide (N2O) ambient. The highest electron mobility of 26 cm2V −1 s <sup>−</sup><sup>1</sup> was achieved by performing PDA at 1100 ◦C for 40 s. The gate oxide could withstand effective fields up to 6 MV/cm within a leakage current range of 1 <sup>×</sup> <sup>10</sup>−<sup>7</sup> A/cm<sup>2</sup> . This value of maximum electric field was small compared to that of thermally grown SiO2, which can typically withstand up to 10 MV/cm. In another work, Yang et al. [113] inserted 1 nm of lanthanum silicate (LaSiOx) between ALD-deposited SiO<sup>2</sup> and 4*H*-SiC to form a gate stack. Peak mobility of 132.6 cm2V −1 s <sup>−</sup><sup>1</sup> was found, with three times larger current

capability compared to gate oxide without La2O3, but no field oxide data were given. Figure 11 shows a summary of the discussed results.

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κ

**Figure 11.** (**a**) Comparison between the field-effect mobility obtained in 4H-MOSFETs fabricated using Al2O<sup>3</sup> insulators with the insertion of ultrathin thermally grown or nitridated SiO<sup>2</sup> layers. (**b**) Comparison between the field-effect mobility obtained in 4H-SiC MOSFETs fabricated using SiO<sup>2</sup> insulators with the insertion of ultrathin La2O<sup>3</sup> layer. The data are taken from Refs. [43,111,113].

It has to be mentioned that ternary insulators have also been investigated for MOSFET application in 4H-SiC. In particular, AlON films provided interesting and reliable results both in MOS and MOSFET applications [114–116]. However, ternary elements are not the focus of this review.

Very recently, Jayawardhena et al. [117] pointed out the relevance of the appropriate pre-treatment of the semiconductor to achieve reliable and stable electric characteristics by employing ALD Al2O<sup>3</sup> films directly in contact to the bare 4H-SiC surface with no interlayers. In particular, their best results were obtained with the preparation of a nitrided surface via NO annealing, i.e., a process known to passivate surface defects, and a hydrogen exposure followed by Al2O<sup>3</sup> deposition on the bare 4H-SiC surface [117].

A summary of the most relevant 4H-SiC MOSFETs with different high-κ gate dielectrics is reported in Table 4.


**Table 4.** Survey of literature data on 4H-SiC MOSFETs with different high-κ gate dielectrics.
