*3.13. Stress in 3C-SiC*

Another aspect that is crucial in the development of the 3C-SiC material is stress. In this case, we have essentially two different components of the stress:. The first one is called intrinsic stress, related to the different lattice constant between 3C-SiC and the silicon that produces a high concentration of defects at the interface. These defects produce a high level of stress essentially in the first microns of the growth. For thick layers, we observe a reduction of this intrinsic stress and for very thick layers, this component of the stress is close to zero. For the intrinsic stress, it has been observed through using MEMS devices that the reduction of the stress follows an exponential low that is very close to the exponential decrease of the SFs' density vs. thickness [9]. This stress is generally compressive in 3C-SiC (100) while it is tensile in 3C-SiC (111).

The second component of the stress is the "thermal stress", related essentially to the different thermal coefficients between silicon carbide and silicon. In fact, the growth occurs at high temperatures (1350–1390 ◦C) and the two materials (SiC and Si) decrease their lattice constants in different ways, moving from the growth temperature to room temperature. This component of the stress is always tensile and then reduces the stress or even changes the sign of the stress in the (100) material, while considerably increasing the total stress in the case of the (111) 3C-SiC. For this reason, it is extremely difficult to grow a thick layer of 3C-SiC on the (111) Si without cracking the film or even the substrate during the ramping down of the temperature in the reactor.

In the CHALLENGE project, we used two different approaches to try to solve this problem. The first approach has been described in Section 3.2. In fact, using the pillars' structures, it is possible to considerably reduce the thermal stress with the deflections of the pillars on the edge of different patches (see Figure 7). In this way, it was possible to obtain thick (111) 3C-SiC layers' wafers with a low bow.

The other approach that we used in this project will be described later in Section 3.15. In this approach, after a thick growth (60–90 µm), the silicon substrate was melted inside the reaction chamber and then removed one of the sources of the thermal stress.

Obviously, this process does not remove the intrinsic stress due to the defects at the 3C-SiC/Si interface. Using the SiGe buffer layer approach described in Section 3.3, it is possible to decrease the intrinsic stress but further experiments should be done to completely remove this component.
