*3.2. Ion Implantation and Activation*

High impurity doping is necessary for low ohmic contact and sheet resistance in 3C-SiC power devices. The most commonly used dopants for 3C-SiC are nitrogen or phosphorus for n-type, and mainly aluminium for p-type.

The low diffusivity of typical dopants in SiC below 1800 ◦C [32] means that highly doped selective regions of SiC power devices are often achieved by ion implantation. As implanted dopant species are nearly always interstitial (not chemically bonded), they are therefore electrically inert. Therefore, an extra post implant annealing (PIA) step is typically deployed to repair the lattice damage and place the implanted dopants into their correct substitutional positions. This is referred to as 'activation'. Extremely high temperatures are required for the SiC PIA; above 1400 ◦C [33,34] is common for n-type SiC and higher still (>1600 ◦C) for p-type [35–37]. The higher p-type PIA temperature is required because acceptors sit deeper in the band gap than donors, and are consequently more challenging to activate. Regarding 3C-SiC, the most common form is grown heteroepitaxially on Si. As a consequence, these activation annealing temperatures are often limited to 1412 ◦C (Si melting point). Performing the ion implantation at a higher temperature helps to reduce the induced lattice damage; thus, it is often applied for high dose implantations. Since the ion implantation induced lattice damage increases with the number of dopants per unit volume (namely the dose), hot implants are almost mandatory when the implant concentration goes above 10<sup>19</sup> cm−<sup>3</sup> [38].

High temperature PIA also causes a rough semiconductor surface, which is enhanced within implanted regions and can degrade the performance of critical interfaces such as Schottky contacts and MOSFET channels [39–41]. A graphite capping layer, demonstrated to be effective up to 1800 ◦C [35], is often utilised to protect the SiC surface during the PIA and reduce the resulting roughness. Comparing the few examples in the literature, n-type implanted 3C-SiC have been extensively studied for varying annealing conditions (1150 ◦C to 1400 ◦C) both with a graphite capping layer [42] and without [43,44]. It was shown that there was little advantage demonstrated when using a graphite cap, likely due to the annealing temperature (below 1400 ◦C due to the Si substrate) not being high enough to roughen the surface. In [45], it was shown that by combing the use of hot implant and pulsed excimer laser processing, which only anneals the surface region, 3C-SiC crystal damage due to implantation can be effectively repaired without degrading the surface morphology (energy density 0.2444 J/cm<sup>2</sup> at 10 Hz), thus providing an alternative solution that allows high temperature PIA to be conducted on Si substrates.

Despite resulting in a rougher surface, a higher temperature is preferred in favour of a higher dopant activation rate. Attributed to a smaller band gap, thus a shallower donor level (55 meV), the activation of n-type dopants in 3C-SiC is easier than in 4H-SiC (80–130 meV) [46]. Studies on n-type 3C-SiC suggest that nitrogen has advantages over phosphorous for use as an n-type dopant, with both fewer defects and lower resistivity achieved [42]. Compared with the N saturation density in 4H-SiC (around <sup>5</sup> <sup>×</sup> <sup>10</sup><sup>19</sup> cm−<sup>3</sup> ) [47], the level in 3C-SiC turns out to be similar at around 7 <sup>×</sup> <sup>10</sup><sup>19</sup> cm−<sup>3</sup> [48]. With the valence band aligned to other polytypes, the deep acceptor level issue still exists for 3C-SiC. Adding to the limited processing temperature, p-type implant and activation has long been an issue for 3C-SiC-on-Si [38,49]. In recent years, the developments on free standing 3C-SiC materials [50,51] make PIA temperatures above 1400 ◦C possible, thus facilitating a significant step forward in 3C-SiC power device fabrication. However, the knowledge of p-type 3C-SiC ion implantation and activation is very limited and requires further investigation. Table 3 summarises some past results published on the ion implantation and activation of dopants in 3C-SiC.


**Table 3.** A summary of literature data on the ion implantation and activation of 3C-SiC.

*3.3. Ohmic Contact*

Due to the requirement of an extra PIA process, achieving ohmic contacts on implanted regions is more difficult than on epilayers. As is the case in 4H-SiC [56], this is particularly true for p-type 3C-SiC because the acceptor levels are deeper, as previously mentioned. Attributed to a lower conduction band edge (3.8 eV from vacuum level), the theoretical SBH between 3C-SiC and commonly used metals is 0.9 eV lower than for 4H-SiC. This is convenient for n-type ohmic contact fabrication, while p-type remains as challenging as in other polytypes. Most work on SiC ohmic contacts is divided into three topics, namely surface preparation, contact metal, and post metallisation annealing (PMA).

The 3C-SiC epilayer surface roughness can vary significantly, from as low as 1 nm depending on the growth technique [43] to high values reaching tens of nm [57]. To achieve a relatively smooth semiconductor surface for ohmic contact fabrication, chemical mechanical polishing (CMP) is often used prior to any further processing. Noh et al. [58] show that the RMS surface roughness reduced from ≈20 nm to ≈7.5 nm. Consequently, the ohmic contact resistivity *<sup>ρ</sup><sup>c</sup>* was reduced by an order of magnitude, from 8.6 <sup>×</sup> <sup>10</sup>−<sup>1</sup> <sup>Ω</sup>cm<sup>2</sup> to 2.8 <sup>×</sup> <sup>10</sup>−<sup>2</sup> <sup>Ω</sup>cm<sup>2</sup> . As alluded to previously, practical device fabrication requires a high temperature (above 1400 ◦C) PIA treatment, which has been shown to degrade the

surface following initial CMP. In [43], a detailed discussion was reported around the PIA effects on 3C-SiC surface morphology and its correlation to the resulting *ρ<sup>c</sup>* values. It was communicated that although severe damage to the surface can limit performance, the *ρ<sup>c</sup>* value will not be seriously affected given that the surface roughness value remains below 10 nm.

Many metals or metal stacks, including Al [54,59–61], Ti [54,59–61], Ni [37,54,57,58,60–63], Ni/Ti [43,55,61], Au/Ti [61], Pt [63], W [37], and TiW [64], have been analysed for 3C-SiC n-type ohmic contact fabrication. It was observed that Al contacts typically display the lowest *ρc*, which was explained by the near-zero SBH between Al and 3C-SiC (∼0 eV) compared to Ti (0.4 eV) and Ni (0.55 eV) [54]. Nonetheless, both Ti and Al are readily oxidised in air, with Al characterised by a melting point below 600 ◦C. Conversely, Ni demonstrates a slow rate of oxidation at room temperature combined with a very high melting point. Although Ni reacts with SiC at temperatures higher than 500 ◦C, the Ni silicide microstructure helps to reduce the SBH. This in turn leads to a lower *ρc*. Consequently, Ni is the most commonly utilised metal contact to n-type SiC.

The effects of PMA on ohmic contacts fabricated on n-type implanted 3C-SiC (Figure 4a) shows a continuous reduction of contact resistivity with increasing annealing temperature up to 1000 ◦C, above which the resistance increases. Details of the silicide formation are shown by XRD analysis in Figure 4b. It can be inferred that between 500 ◦C and 600 ◦C, a coexistence of Ni2Si (121) and Ni31Si<sup>12</sup> (300) is present. The Ni31Si<sup>12</sup> (300) peak gradually diminishes at higher temperature, while the Ni2Si (002) becomes prominent and enhances continuously to temperatures reaching 1100 ◦C. Noting that Ni2Si (121) is readily formed at 600 ◦C, with no other noticeable phases above that temperature, the Ni2Si (002) enhanced phase could explain the contact resistance reduction from 800 ◦C to 1000 ◦C. It is worth mentioning that, due to the very low SBH of highly doped n-type 3C-SiC/metal interface, as-deposited ohmic contacts can be obtained without PMA processing [59,65]. This makes it possible to integrate SiC transistor technologies with other low temperature technologies, such as atomic layer deposited high k dielectrics (e.g., HfO<sup>2</sup> or Al2O3) with relatively low growth temperatures and classic wafer bonded or heterojunction devices.

**Figure 4.** (**a**) Specific contact resistance dependence on the PMA temperature and, (**b**) XRD measurements of metal/3C-SiC (6 <sup>×</sup> <sup>10</sup><sup>20</sup> cm−<sup>3</sup> ) interface after various PMA temperatures indicating silicide formation. Contact was fabricated by depositing (Ti30 nm/Ni100 nm) on 5 <sup>×</sup> <sup>10</sup><sup>20</sup> cm−<sup>3</sup> N implanted 3C-SiC.

Compared to n-type 3C-SiC, even less is known about p-type 3C-SiC ohmic contacts. As with 4H-SiC, Al based alloys are most commonly used for p-type ohmic contact since very often Al is also the doping species. A Ti interlayer is often applied not only to improve the adhesion, but the TiC product after PMA also helps to reduce the contact resistance [36,66].

Among the very limited data, the lowest specific contact resistances (10−5–10−<sup>4</sup> Ωcm<sup>2</sup> ) are obtained from trials made on p-type epilayers [66,67], which eliminates the issue of acceptor activation. However, when fabricating power devices such as MOSFETs, it is

crucial to obtain ohmic contacts on selective highly doped, mostly implanted p+ regions. It is reported in [38] that, on 3C-SiC with a Si substrate, a hot implant (500 ◦C) with high Al concentration (1 <sup>×</sup> <sup>10</sup><sup>20</sup> cm−<sup>3</sup> ) together with very long duration (>300 h) PIA at 1300 ◦C had to be performed to achieve ohmic contacts, and even so, the resultant *ρ<sup>c</sup>* was still high, around the 10−<sup>2</sup> Ωcm<sup>2</sup> level. More recently, p-type ohmic contacts (Figure 5a) on Al hot implanted (600 ◦C, 1 <sup>×</sup> <sup>10</sup><sup>20</sup> cm−<sup>3</sup> ) free standing 3C-SiC have been reported. By increasing the PIA temperature treatment to 1700 ◦C, a dramatic reduction in annealing time was required—down to 2 h. Even though the *ρ<sup>c</sup>* value is still relatively high ~10−<sup>3</sup> Ωcm<sup>2</sup> , it is promising since the contacts were fabricated on a very rough surface (Figure 5b), which can be further improved either by optimising the 3C-SiC growth process or additional polishing treatments. Table 4 provides a survey of the literature results for ohmic contact processing on 3C-SiC, mostly n-type.

**Figure 5.** (**a**) I-V characteristic ohmic contact (Ni/Al/Ti) fabricated on Al implanted free standing 3C-Si and, (**b**) surface morphology of the free standing 3C-SiC by AFM.


**Table 4.** A summary of literature data on the fabrication of 3C-SiC ohmic contact.


**Table 4.** *Cont.*
