*2.3. Diode Layout*

Managing the power dissipation in Schottky diodes is becoming an aspect of increasing interest, due to the need to reduce electricity consumption in modern electronic systems. In particular, a conventional Schottky diode (as that schematically depicted in Figure 1) is a majority carrier device, in which the dynamic power dissipation is negligible with respect to the conduction static power losses [52]. In such a device, the barrier height, ideality factor and reverse leakage current are important parameters affecting the static power dissipation. In particular, the conduction static power dissipation *P<sup>D</sup>* can be expressed as [53]:

$$P\_D = \%\_{\rm ON} \times (V\_F \times f\_F) + (1 - \%\_{\rm ON}) \times (V\_R \times f\_R) \tag{5}$$

where *%ON* is the ON duty cycle, *V<sup>F</sup>* and *J<sup>F</sup>* are the voltage and current density under forward bias, while *V<sup>R</sup>* and *J<sup>R</sup>* are the voltage and current density under reverse bias. Hence, considering the case of the conventional 4H-SiC Schottky diodes, the forward current-voltage behavior is described by the TE model, with the *V<sup>F</sup>* expressed as function of the forward current density *JTE* as follows, accordingly to the linear region approximation of Equation (2):

$$V\_{\rm F,TE}(f\_{\rm TE}) = n\phi\_{\rm B} + \frac{nkT}{q}\ln\left(\frac{f\_{\rm F}}{A^\*T\_f^2}\right) \tag{6}$$
 
$$\text{electric field in the space-chram domain that entails a shear band}$$

ி,்ா(்ா) = + ∗ ଶ ൰ Moreover, due to the high electric field in the space-charge region that entails a sharp band bending and thus a thin barrier, the reverse current is typically described according to the *TFE* model, with the relationship between current density *JTFE* and reverse voltage *V<sup>R</sup>* given by

$$J\_{R,TFE}(V\_R) = = A^\* T^2 \sqrt{\frac{q^2 \pi E\_{00}}{(kT)^2}} \sqrt{V\_R + \frac{\phi\_B}{\cosh^2\left(\frac{qE\_{00}}{kT}\right)}} \exp\left(-\frac{\phi\_B}{E\_0}\right) \exp\left(\frac{V\_R}{E\_1}\right) \tag{7}$$

ℎ<sup>ଶ</sup> ቀ <sup>ቁ</sup> <sup>ଵ</sup> = × ൫⁄ − ℎ(⁄ ) ൯ ିଵ where *<sup>E</sup>*<sup>1</sup> <sup>=</sup> *<sup>E</sup>*<sup>00</sup> <sup>×</sup> (*qE*00/*kT* <sup>−</sup> *tanh*(*qE*00/*kT*))−<sup>1</sup> and the other parameters of Equation (7) as described before. Hence, accordingly to Equation (5), the static power dissipation depends on the Schottky barrier height *φB*.

*Φ* Figure 5a shows the calculated conduction power loss for conventional 4H-SiC Schottky diode as a function of the barrier height, in the temperature range 25–150 ◦C. The calculation has been performed using Equations (5)–(7), assuming a duty cycle %ON = 50%, a forward current density *J<sup>F</sup>* = 100 A/cm<sup>2</sup> and reverse voltage *V<sup>R</sup>* = 650 V. As highlighted in Figure 5a, for a given temperature, a reduction of the Schottky barrier entails a reduction

of the power losses, up to a certain lower limit, where the losses show a sudden increase, due to the significant increase of the reverse leakage current with the barrier reduction, especially at higher temperatures. Evidently, based on these considerations, in power electronics applications, Schottky contacts with low barrier height are sought after, as lowering the Schottky barrier height leads to a reduction of the power consumption [48]. However, it must be considered that a lowering of the barrier *φ<sup>B</sup>* could lead to an increase of the leakage current density *J<sup>R</sup>* and thus, a good compromise between the diode forward and reverse behavior must be found for the minimization of the power dissipation *PD*. *Φ*

**Figure 5.** Schottky barrier height dependence of the static power losses for (**a**) a conventional Schottky diode and (**b**) a modern JBS diode, in the temperature range 25–150 ◦C. The curves were simulated by considering the forward electrical behavior ruled by thermionic emission model and the reverse characteristics ruled by thermionic field emission model. In the case of the JBS diode (**b**), the leakage current contribution has been neglected.

For that reason, as discussed later in this paragraph, in modern 4H-SiC-device technology, the high-reverse *TFE* leakage current, which typically characterized the conventional Schottky diodes, has been strongly reduced by acting on the device layout. In this case, the contribution of the leakage current can be neglected, and the static conduction losses decrease with a reduction of the barrier height, as shown in Figure 5b.

Since the middle of the 1990s, new diode designs have been proposed to achieve improved rectifier characteristics of semiconductor-based Schottky diodes. Mehrotra et al. [54] demonstrated that a design involving metal-oxide-semiconductor (MOS) regions, built into a trench region of the device front, was successful in pushing higher the limit given by the reverse blocking voltage, allowing the device to support larger doping of the semiconductor epitaxial layer, and thus an improvement of the on-state characteristics. A schematic view of this device is reported in Figure 6a: as can be seen, the MOS structure is formed on the bottom and sidewalls of a trench, while the Schottky contact is on the top surface. With this layout, called trench MOS barrier Schottky rectifier (TMBS), a reduced level of electrical field is achieved on the Schottky interface, producing a smaller Schottky barrier height lowering and thus a reduced leakage current level, if compared with the standard Schottky structure.

Afterward, another approach of "Schottky-pinch rectifier" was proposed by Zhang et al. [55] for 4H-SiC Schottky rectifiers. Differently from the previously discussed solution, this diode layout consisted of integrating MOS-structures (with a thermally grown oxide) together with Ni Schottky contacts on the same plane, as shown in Figure 6b. This layout, called the planar MOS Schottky diode structure (MOSSD), was able to maintain an acceptable level of forward current, up to 90% with respect to a conventional Schottky diode of the same footprint area, while reducing the leakage current by one order of magnitude.

However, these designs including MOS structures, could give some limitations, with the possible occurrence of the oxide breakdown before the 4H-SiC critical electrical field was reached. To overcome this limitation, a dual-metal-trench (DMT) device structure, implementing low and high Schottky barrier height materials (i.e., Ti and Ni metals, respectively) was suggested by Schoen et al. [56]. The device scheme is given in Figure 6c: under forward bias, the mesa was not pinched off and the electrical characteristics are given by the low barrier contact (Ti/4H-SiC). In contrast, under reverse bias, the mesa structure became fully pinched-off and the high barrier height of the Ni Schottky contact prevails, limiting the electric field. A further evolution of the DMT has been later proposed by Roccaforte et al. [57], who combined the advantages of Ni2Si and Ti in a dual-metalplanar (DMP) Schottky diode (schematically depicted in Figure 6d) which exhibited a forward voltage drop close to that of a Ti/4H-SiC diode (lower barrier) and a reverse current comparable to that of a Ni2Si/4H-SiC (higher barrier).

**Figure 6.** Different Schottky diode layouts proposed to achieve an optimal trade-off between the forward and reverse characteristics. (**a**) Trench MOS barrier Schottky (TMBS) diode. (**b**) Planar MOS Schottky diode (MOSSD). (**c**) Dual-metal-trench (DMT) Schottky diode with Ti and Ni Schottky contact. (**d**) Dual-metal-planar (DMP) Ti-Ni2Si/4H-SiC Schottky diode.

*Φ* − − The electrical behavior of the DMP structure can be explained by an equivalent system with two parallel diodes which have two different barrier heights, specifically the low barrier of the Ti layer determines the current flow under forward bias, and the high Ni2Si barrier dominates the reverse conduction by the pinch-off of the low barrier Ti regions. The DMP diode presented an ideality factor *n* = 1.25, a barrier height *φ<sup>B</sup>* = 1.23 eV (close to that of Ti contact) and leakage current at <sup>−</sup>100 V of 5.8 <sup>×</sup> <sup>10</sup>−<sup>4</sup> A/cm<sup>2</sup> , 30 times lower than the leakage current observed in the Ti/4H-SiC diode.

All the aforementioned diode layouts showed an improvement of the trade-off between the forward and reverse characteristics of the diodes.

Nowadays, the so-called junction barrier Schottky (JBS) diode is the most widely used Schottky-like architecture in SiC technology with significant improvement with respect to the standard Schottky diode [58]. This device consists in p<sup>+</sup> -type regions (usually achieved by p-type ion implantation and electrical activation) embedded within an n-type Schottky epitaxial area, as schematically shown in Figure 7 [59,60]. This layout mitigates the reverse leakage current of the Schottky diode and achieves a hard breakdown, as typical of a p-n junction [58]. Specifically, under low forward bias, the current flows in the regions between the p<sup>+</sup> -wells, exploiting the Schottky barrier characteristics given by the top metal, while under reverse bias, these regions are pinched-off and the electrical characteristics

are given by the p-n junction. The distance *d* between two adjacent p<sup>+</sup> -wells and the size *s* of p<sup>+</sup> -well are important parameters that must be carefully designed for optimizing the trade-off between forward and reverse characteristics. These parameters, together with the depletion width *WD*, defined the cell pitch *p* (*p = d + s + WD*). For instance, the on-state voltage drop decreases as the cell pitch is reduced, while the leakage current decreases as the p<sup>+</sup> -well distance is reduced for a constant value of p<sup>+</sup> -well size [61]. The schematic process flow, with the sequential steps typically adopted for JBS diode fabrication, can be found in Ref. [9]. As occurs in SBDs, in these devices the Schottky contact between the metal and the n-type epitaxial 4H-SiC is also a key part for optimizing the overall electrical performance of the device.

**Figure 7.** Schematic cross-section view of a 4H-SiC junction barrier Schottky (JBS) diode.

Beyond the diode layout with the well-established JBS design for 4H-SiC-based Schottky rectifiers, the employment of materials with low work function is of particular interest for minimizing the power dissipation of Schottky diodes and they are currently explored with promising results. This aspect will be discussed in detail in the next subsection.
