**3. OFF-State and ON-State–Optimization of the M-O-S Stack in Quasi-Vertical MOSFETs from IMEC, Leuven, Belgium**

This section describes recent results on the degradation and optimization of the MOS gate stack used for GaN-on-Si vertical MOSFETs.

The reliability of the gate stack is highly influenced by the choice of the oxide in trench MOSFETs, since the insulator is vulnerable to repeated stressing during the operation of the power devices over time [46,84,85]. Specifically, the properties of the insulator can greatly affect the leakage, breakdown and trapping performance of the M-O-S stack under positive gate stresses. One of the essential requirements for a gate oxide is to have high band offsets with GaN, which is critical to limit the leakage current [86–88]. In this regard, while materials such as silicon nitride or hafnium oxide (band offsets around 1 eV) are less favored, Al2O<sup>3</sup> [89,90] and SiO<sup>2</sup> [32,34] have emerged as popular choices with conduction band offsets (∆EC) of 2.1 and 2.5 eV, respectively. Al2O<sup>3</sup> presents good metrics [86–88]: in addition to having a high bandgap (8.9 eV), high k (dielectric constant = 9.0), and reasonably high breakdown strength (~10 MV/cm), improvements in deposition techniques now allow Al2O3/GaN interfaces to be formed with very low interface state densities [88,91,92]. SiO<sup>2</sup> also has a high bandgap (9.1 eV), and its advantage is high chemical stability, which extends to high operational stability in the devices.

Since the reliability of the MOS framework is still not completely understood, there has been limited effort in exploring alternatives to the conventional MOS structure with an unilayer dielectric. In particular, the approach of using bilayer dielectrics (with a thin interface dielectric followed by a thicker insulator), which has been found to be advantageous for Si MOSFET design, could potentially be very valuable for GaN-based MOSFETs as well. However, inherent reliability risks could be worsened with increasing complexity in the dielectric deposition process. To truly capitalize on the effects of improved dielectrics, the bulk GaN etch process, in particular the formation of the trench itself, needs to be highly optimized. The shape of the trench is usually optimized [93–97] to find the best combination of *VBR* and *Ron*; deep trenches with rounded corners have been reported to display good metrics [93,98,99]. However, for higher trench depths (over-etch) extending beyond the p-body, the peak field under the OFF-state could be aggravated [93]. The overall etching process is aimed at creating smooth sidewalls, and preventing irregularities such as pits or voids, especially at the bottom trench corners where the peak fields are expected [93–97].
