4.1.4. Optimizing the Thickness of the GaN Epilayers

 The determination of the GaN buffer layer thickness typically takes into account the electrical performance of the device and material quality requirements, instead of thermal requirements [184]. In latest generation GaN-on-diamond devices the low thermally conductive nucleation and strain relief layers are removed before the deposition of the diamond film, and as a consequence the thickness of the GaN buffer layer has a nonnegligible impact on the total *R*th of the device. In fact, in a joint work between the University of Bristol and Element Six [88], the thickness of the GaN buffer layer was reduced from 700 to 354 nm and the thickness of the dielectric layer to 17 nm, leading to a device *R*th of 9 K·mm/W, a value significantly lower than the *R*th of GaN-on-SiC devices (16 K·mm/W). Besides lowering the maximum temperature, the thinning of the GaN layer decreased self-heating, resulting in a smaller change in output conductance and providing a means to reduce the thermally-generated device non-linearities.

 Taking into account these results, it might initially be assumed that the GaN layer should be as thin as possible. If it is too thick, the *R*th associated with the GaN layer and consequently the *R*th of the device increase. However, if the GaN layer is too thin (especially when the heat source length is comparable to the device length and for small *TBR*GaN/diamond values), the concentrated heat flux coming out from the heat source reaches the GaN/diamond interface without spreading, causing the region right under the heat source to heat up significantly and leading to an increased *R*th [85]. As an example, the peak channel temperature of a 4 × 125 µm/40 µm gate pitch GaN-on-diamond HEMT dissipating 10 W/mm is shown in Figure 25 for different values of *TBR*GaN/diamond and GaN layer thicknesses (from [185]). It can be seen that thinner GaN layers may lead to lower or higher peak channel temperatures, depending on the particular value of the *TBR*GaN/diamond.

 Simulations have systematically shown that the device *R*th monotonically decreases with increasing GaN layer thickness until it reaches a minimum. The higher the κ of the diamond, the lower the *TBR*GaN/diamond [86,87,89], and the smaller the hotspot area [85], the more important this dependence becomes.

µm ( µm may result in a µm, respectively, and the minimum In 2020, Song and co-workers [90] have shown that, while the device *R*th is fairly low at a typical GaN thickness of 1 µm (≈12.9 and ≈16.4 K·mm/W for *TBR*GaN/diamond of 6.5 and 30 m<sup>2</sup> ·K/GW, respectively), a reduction in the GaN thickness below 1 µm may result in a substantial increase in the device *R*th, in particular when *TBR*GaN/diamond is high (≈31% and <sup>≈</sup>118% increase for *TBR*GaN/diamond of 6.5 and 30 m<sup>2</sup> ·K/GW, respectively, and 0.1 µm GaN thickness). For the same *TBR*GaN/diamond values, the GaN thickness that minimizes the *R*th of the device is ≈3.6 and ≈5.8 µm, respectively, and the minimum *R*th is ≈5% and ≈19% the *R*th with 1 µm of GaN.

 "Novel thermal management and its analysis in GaN electronics," Asia **Figure 25.** Peak channel temperature of a 4 × 125 µm/40 µm gate pitch GaN-on-diamond HEMT dissipating 10 W/mm for different *TBR*GaN/diamond values and GaN layer thicknesses (Copyright © 2014 IEICE. Reprinted, with permission, from M. Kuball, J. A. Calvo, R. B. Simon, and J. W. Pomeroy, "Novel thermal management and its analysis in GaN electronics," Asia-Pacific Microw. Conf., pp. 920–922, 2014 [185]).

– From what was presented above, it can easily be concluded that in order to take the most benefit of the diamond substrate, the impact of the GaN buffer layer thickness on the overall *R*th of the device should also be taken into account in the design phase, in addition to the traditionally considered electrical performance and material quality requirements.
