*3.6. Hetero-Epitaxy Process: Carbonization*

The heteroepitaxy of 3C-SiC on Si is a complex process that is realized in several steps. After the introduction in the reaction chamber, the first step is the etching of the silicon substrate in a hydrogen flux to remove the native oxide (step 1). Then, the second step is the substrate carbonization wherein a flux of the carbon precursor and carrier gas (hydrogen) is introduced in the chamber at temperatures between 900 and 1200 ◦C (step 2). Subsequently, the temperature should be increased to grow the 3C-SiC layer at temperatures close to the melting point of silicon (step 3). Finally, the temperature is decreased to room temperature (step 4). All these steps have a considerable impact on the quality of the epitaxial layer.

The most critical in the 3C-SiC/Si growth seems to be the second step: the carbonization of the Si substrate. This process is sometimes referred to as "reactive CVD" (R-CVD) because one of the components of the compound (in this case, silicon) is not supplied from the vapor phase but comes directly from the Si substrate that reacts with the gas ("vapor") species. As a result of carbonization, a thin seed of a few nanometers is formed for the subsequent CVD epitaxy process; it is sometimes denoted as the "carbonization buffer". The characteristics of this seeding layer are fundamental for the crystalline quality and the stress of the film. From previous studies, it has been observed that for given growth conditions, the morphology and thickness of the carbonization buffer depend strongly on the substrate orientation [50]. Consequently, the conditions to obtain an optimal buffer differ between orientations. For any orientation, the maximal thickness is conditioned by the nucleation density (proportional to carbon supply) and the ratio between the vertical and lateral growth rates (controlled by process pressure and temperature).

During carbonization, initial nucleation centers extend progressively, laterally, and vertically into three-dimensional 3C-SiC islands. Their temperature-dependent growth rate is proportional to the carbon flow rate but remains limited by the Si supply from the substrate; high in the initial stage when surface coverage with 3C-SiC is low, it reduces progressively to zero as the 3C-SiC islands extend, coalesce, and block the Si supply. It is important to mention that the R-CVD growth mechanism remains active until a complete coalescence of the 3C-SiC buffer is achieved, which is sometimes a long process. Consequently, in many cases, the CVD mechanism coexists (intentionally or not) with R-CVD during the initial part of step 3 of the heteroepitaxial growth.

The roughness of the carbonization layer has a large effect on the stress of the entire film: high roughness makes the relaxation of intrinsic stress during the growth easier [51]. The main process parameters that influence the roughness of the carbonization buffer are the temperature of the carbon precursor introduction and temperature of the carbonization plateau.

One of the problems related to the carbonization step is the formation of voids (also called "etch pits") in the near-interface region of the silicon substrate. These micrometric cavities form from the coalescence of silicon vacancies created in the Si substrate as a

consequence of the R-CVD growth mechanism. The major part of voids does not affect the quality of the 3C-SiC film (their presence is sometimes considered as a stress-relaxing factor), although some of them can be at the origin of surface defects in the epitaxial film. Consequently, the void formation should be reduced. This can be achieved through carbonization under a high C/H<sup>2</sup> ratio, which increases the nucleation density and favors fast-film coalescence that stops the formation of voids. In Figure 10a, the fraction in percentage of the void area with respect to the total observed area as a function of the C/H<sup>2</sup> ratio are reported. In the same figure, the density of the void as a function of the C/H<sup>2</sup> ratio is also reported. The effective void areas decreases from 11% to 5% while increasing the flux of carbon atoms. The reduction can be further enhanced by introducing the silicon precursor during the thermal ramp between the carbonization plateau (step 2) and epitaxy (step 3) to form a transition layer. Such intentional mixing of R-CVD and CVD mechanisms further improves the quality of the interface between the 3C-SiC film and Si substrate [27]. In the same paper, it has been reported that the increase of the C/H<sup>2</sup> ratio also produces an increase in the density of the layer, as well as an increase in the carbonized thickness.

**Figure 10.** The percentage of void areas occupied with respect to the total observed area (**a**) and voids' density (**b**) are reported as a function of the C/H<sup>2</sup> ratio [%] (see Reference [27]).

The growth on compliance substrates may require a modification of the carbonization step in order to fit particular substrate-related requirements. This is, for instance, the case for substrates with the Si-Ge buffer for which the carbonization temperature was reduced to below 1000 ◦C and H<sup>2</sup> etching (step 1) was excluded from the process in order to preserve a thin Si cap (10 nm or 20 nm), necessary for correct carbonization. In addition, the temperature of the CVD growth (step 3) was lowered to avoid Si-Ge melting. It is important to underline that such a "low temperature" process resulted in a higher quality of the epilayer on Si-Ge with respect to the film grown on bare silicon.

An alternative approach to the formation of the 3C-SiC seed on the Si substrate was recently proposed. Silicon substrates are "pre-carbonized", meaning that a few nm-thick amorphous carbon (a-C) film is deposited using the plasma immersion ion implantation (PIII) technique. During H<sup>2</sup> annealing (step 1), carbon reacts with silicon to form oriented 3C-SiC seeds through a solid-state epitaxy mechanism. The standard R-CVD carbonization step is no longer necessary. CVD deposition on such seeds gave satisfactory results on all studied orientations: (100), (110), (111), and (112) [52].

#### *3.7. Effect of Growth Rate: Defects and Stress*

The growth rate has a large effect on the quality of the 3C-SiC both in terms of its structural quality and stress. It has been observed in a previous paper [53] that the growth rate has a large effect on the density of twins. In fact, in decreasing the growth rate from 10 µm/h to 1 µm/h, a decrease of the twin density of almost a factor of 6 can be observed. A similar (but weaker) effect has been observed also on the rocking curve, which is more sensitive to SFs and point defects [6]. The Full Width at Half Maximum (FWHM) of the rocking curve is reduced both by reducing the growth rate and increasing the thickness.

With decreasing growth temperature, the growth rate has to be reduced or otherwise the deposition may become polycrystalline. This is particularly the case for 3C-SiC growth on the Si-Ge buffer and constitutes a potential limitation for further development of this approach.

For the 3C-SiC growth on ISP substrates, we demonstrated that the height of the void created above the vertex of the pyramid (Figure 9b) increased at higher growth rates. Consequently, the initial stage of 3C-SiC growth on ISP substrates, until reaching complete coalescence, should be performed at a low growth rate.

The growth rate has also an influence on the final stress of the 3C-SiC epilayer. Indeed, as demonstrated in [54], during the growth of the 3C-SiC layer, the intrinsic stress in the layer is continuously relaxing. For a given film thickness, by tuning the growth rate, we can adjust the duration of the relaxation (by the duration of the growth), controlling the final stress of the sample.
