*3.4. MOS Processing*

Given the superior electrical performance of SiC and its capacity to be thermally oxidised, it is not surprising that there are copious amounts of SiC MOS devices being demonstrated. The commercialised 4H-SiC polytype is naturally the most frequently reported. Numerous literature reports suggest that MOS interface traps are similar in nature for all SiC polytypes [69]. Therefore, studies relating to the 4H-SiC/SiO<sup>2</sup> interface provide insightful information with respect to the equivalent 3C-SiC system.

In [70], reporting around the possible origins of interface traps identified two primary sources; namely, carbon and oxide defects that accumulate at the MOS interface during the oxidation process. The oxide defect-induced traps (also known as "near-interface traps") have much smaller time constants compared to the carbon-clusters. Therefore, oxide defect-induced traps are also known as "fast traps" while the latter are coined "slow traps". A graphic illustration of the carbon cluster model is shown in Figure 6, including the corresponding specified energy levels of the traps. Figure 6 shows the 4H-SiC conduction band edge is overwhelmingly impacted by π-bonded clusters and carbon near-interface traps, with the latter being most dominant. Both trap forms are acceptor-like, therefore negatively charged when occupied, which explains the positive flat band voltage (*Vfb*) typically detected with respect to 4H-SiC MOS devices. In contrast, the 3C-SiC conduction band is devoid of near-interface traps due to a narrower band

gap. However, 3C-SiC is still negatively-impacted by π-bonded carbon clusters. These (carbon clusters near the 3C-SiC conduction band edge) defects are positively charged if occupied as they are donorlike, resulting in a *Vfb* that is negative. Dangling bonds augment the interface defectiveness but are negligible secondary concerns compared to the aforementioned carbon clusters. Consequently, hydrogen annealing is not as effective for SiC when compared to Si. Alternative methods have been demonstrated for high-quality SiC/SiO<sup>2</sup> interface optimisation.

**Figure 6.** Schematic representation of the "carbon cluster model". Adapted from Ref. [71] with permission from the author (R. Esteve).

Reports focussing on the improvement of the SiC/SiO<sup>2</sup> interface are mainly related to the topic of post oxidation annealing (POA). Former research literature revealed the advantages of including hydrogenation processes either during the (gate) oxidation process or subsequently, via the POA. This has the effect of decreasing the interface trap density (*Dit*) in addition to reducing positive fixed charge (*Qfc*) [68,72]. Consequently, wet oxidation in conjunction with POA is often utilised for 3C-SiC MOSFET fabrication [73,74]. Regarding the nitridation step, extra deep interface traps revealed by double peak conductance spectra were observed from fabricated MOS capacitors via direct N2O oxidation and pure O<sup>2</sup> oxidation methods on nitrogen implanted films [72,75].

Figure 7 shows the lateral MOSFET transfer curves on Al implanted 3C-SiC/Si substrates with the gate oxide grown in different atmospheres, but all at the same temperature of 1300 ◦C [76]. Due to varying oxide thicknesses, for direct comparison the gate field instead of gate voltage is plotted on the x-axis. It can be inferred that the dry oxidized device demonstrates a normally on characteristic with a gate threshold voltage approaching zero. This is in agreement with the previously introduced Carbon Cluster Model, stating that only donor-like states occupy the 3C-SiC/SiO<sup>2</sup> interface. Since these states are positively charged when vacant, these donor-like states may be responsible for the inherent negative threshold. The nitrided sample is even further shifted in the negative threshold direction due to the counter doping channel effect [77]. The wet oxidized sample has the most positive gate threshold. A combination of N2O nitridation and POA (wet) yielded an intermediate threshold field of around −2MV/cm. Clearly, the wet oxidation was successful in shifting the device threshold in a more positive manner, either by forcing a reduction in positive fixed oxide charges or via compensating them with additional negative charge. Both wet POA and oxidized processed devices have a peak field-effect mobility (*µFE*) value in the region of 60 cm2/Vs, which is the lowest compared with the dry oxidized sample (70 cm2/Vs) and the N2O nitrided sample (90 cm2/Vs).

**Figure 7.** Transfer curves of 1300 ◦C oxidized lateral MOSFET with various conditions.

As mentioned previously, the reliability of the 3C-SiC MOS system is particularly interesting, yet there has been relatively little study of this topic, mainly due to a shortage of non-defective 3C-SiC material. Figure 8 shows the critical strength (*Ec*) of SiO<sup>2</sup> layers grown on 3C-SiC/Si substrates in different atmospheres at 1300 ◦C. As can be seen, by using combined dry O<sup>2</sup> gate oxidation with an N2O POA process, the noise level was greatly reduced and the critical electric field strength was able to be kept at around 8 MV/cm, the highest value observed.

**Figure 8.** Dielectric breakdown curve of gate oxides fabricated by (**a**) 60 min 1300 ◦C O<sup>2</sup> dry oxidation, (**b**) 15 min 1300 ◦C O<sup>2</sup> wet oxidation, (**c**) 120 min 1300 ◦C N2O dry oxidation and (**d**) 30 min 1300 ◦C O<sup>2</sup> dry oxidation + 90 min 1300 ◦C N2O POA.

Recently the reliability of 3C-SiC MOS capacitors (dry oxidised and N2O POA at 1300 ◦C) has been examined at room temperature by using both v-ramp and time-dependent dielectric breakdown (TDDB) analysis. As can be seen in Figure 9a, the accumulated total failure percentage increases steadily until around 8.5 MV/cm, beyond which the failure number sharply increases to 100%. The failures at lower fields are most likely induced by crystal deficiencies in the 3C-SiC substrate that alter localised material properties. High field (>8.5 MV/cm) failures are characterized by either F-N tunnelling, observed via the increased leakage current, or electron impact ionization energy being reached within the oxide due to elevated electric fields. TDDB analysis is conducted at electric field values of 6, 7.5, 8.5, and 9 MV/cm. The Weibull distributions are displayed in Figure 9b. Even at high fields beyond 8.5 MV/cm, the slope values remain low in the region of ~1, an order of magnitude lower than reported values for 4H-SiC [78], suggesting extrinsic defects are still the dominant failure mechanism.

**Figure 9.** (**a**) Failure distribution of 3C-SiC MOS capacitors in the electric field range of 4.5–10.5 MV/cm, and (**b**) Weibull distributions of device failures at various electric fields.

Besides the application on Schottky contacts described in Section 3.1, nanoscale resolution current mapping by C-AFM can also be a powerful analysis technique for investigation of the dielectric breakdown behaviour of thin insulators. In fact, this method was recently employed by Fiorenza et al. [79] in order to explain the reasons behind the premature breakdown of thermal oxide (SiO2) grown on 3C-SiC typically observed in MOS capacitors, by stressing the oxide through the application of a bias to the C-AFM tip corresponding to an electric field of 8 MV/cm (see schematic set-up in Figure 10a).

**Figure 10.** (**a**) C-AFM set-up adopted for the electrical characterization of the SiO2/3C-SiC system; (**b**) AFM morphology and (**c**) C-AFM current map acquired under the application of an electric field of 8 MV/cm to the tip. Adapted with permission from ref. [79]. Copyright © 2021 Elsevier Ltd.

The C-AFM current map and corresponding AFM surface morphology acquired on the SiO2/SiC system are reported in Figure 10b,c, respectively. The C-AFM current map in Figure 10c reflects the breakdown distribution of an array of tip/oxide nano-MOS capacitors. Hence, the features on the surface morphology (Figure 10b) could be correlated with the position of the breakdown spots (Figure 10c), which are not randomly distributed, but preferentially appear along the APBs (dashed line in Figure 10b). Here, the straight line conductive aspects associated with SFs on the exposed 3C-SiC surface (see Figure 10c) were not visible in the presence of a thermal oxide. Based on this analysis, the premature dielectric breakdown observed in MOS capacitors could be attributed to the presence of

positively charged APBs, causing an electron injection enhancement from the 3C-SiC into the SiO2.

Table 5 is a list of recent work performed on the study of 3C-SiC MOS interface traps.

**Table 5.** A summary of literature data on the processing of 3C-SiC MOS interface and relevant information on fixed charges (*Qfc*), interface trap density (*Dit*), and oxide critical field (*Ec*), unless specified, the 3C-SiC materials listed are epilayers.


#### **4. 3C-SiC Device Prototypes**
