**1. Introduction**

Today, it is widely recognized that microelectronic devices have improved the quality of our daily lives, strongly contributing to the development of human civilization. In the 1940s–1950s, the first microelectronic devices appeared, and they were based on germanium. However, silicon (Si) gradually began to be the semiconductor of choice, driving the power electronics revolution with the introduction of the first p-n-p-n transistors in 1956 at Bell Laboratories [1,2]. About two decades later, the introduction of metal-oxide-semiconductor field-effect transistors (Si-MOSFETs) set the foundations for the development of the modern CMOS technology [3]. Hence, for about fifty years, microelectronics have been based mainly on Si semiconductors. The great success of digital technology may apparently indicate that Si is still the most suitable material for microelectronic devices. However, in other fields, such as electronic systems for power transmission or distribution (power converters, base stations, wireless connections, etc.) and optoelectronics (light emitting diodes—LEDs, lasers), the achievement of the ultimate silicon performances opened the route for the post-Si era. In this context, wide band gap (WBG) semiconductors emerged as the most suitable materials for this technological revolution, especially in high-power and high-frequency electronics [4–7].

Among the WBG semiconductors, silicon carbide (SiC) and gallium nitride (GaN) are the most attractive candidates because they already provide a good compromise between

**Citation:** Lo Nigro, R.; Fiorenza, P.; Greco, G.; Schilirò, E.; Roccaforte, F. Structural and Insulating Behaviour of High-Permittivity Binary Oxide Thin Films for Silicon Carbide and Gallium Nitride Electronic Devices. *Materials* **2022**, *15*, 830. https:// doi.org/10.3390/ ma15030830

Academic Editor: Alexander N. Obraztsov

Received: 17 December 2021 Accepted: 19 January 2022 Published: 22 January 2022

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their theoretical properties (blocking voltage capability, operation temperature, and switching frequency) and commercial availability [4–6]. Their wide band gaps result in higher breakdown voltage and operation temperature with respect to Si, so both are excellent candidates to replace Si in the next generation of high-power and high-frequency electronics. Because of their different physical and electronic properties in terms of carrier mobility and thermal conductivity [8,9], SiC and GaN will cover different market segments in the post-Si technologies [10]. In particular, SiC is more suitable for high-power applications based on vertical devices, while GaN is more efficient for high-frequency applications based on lateral transistors. In any case, both materials can provide superior performances with respect to the existing Si devices [5,6], although the different technological steps for transistor fabrication need to be appropriately integrated.

Gate insulators are certainly the most important brick for transistor operation, even in the post-Si era, since the device performances critically depend on the choice of the insulating material. However, gate insulator technology is rather different in SiC and GaN, thus leading to a variety of issues to be faced when developing devices on these two WBG semiconductors.

Traditional dielectric materials, such as silicon oxide or silicon nitride, have also been widely investigated [11–14] for applications based on WBG semiconductors. However, the performance of the ideal Si/SiO<sup>2</sup> system has been not achieved, and attention has been focused on the so-called "high-κ" oxides [15–20]. Among all the high-κ materials, some binary oxides (such as Al2O<sup>3</sup> [21,22], HfO<sup>2</sup> [22], NiO [23,24], CeO<sup>2</sup> [25], Sc2O<sup>3</sup> [26,27], La2O<sup>3</sup> [28], Gd2O<sup>3</sup> [28], Y2O<sup>3</sup> [28,29], ZrO2, [17,18], Ga2O<sup>3</sup> [30], etc.) potentially represent a suitable solution for the integration in WBG-based devices because of their higher chemical stability and/or lower fabrication cost. Some other possible materials have been studied, such as ternary oxides and nitrides, but those materials are beyond the topic of this review paper.

Table 1 shows a summary of the possible oxide candidates for the replacement of the SiO<sup>2</sup> dielectric material and their principal physical properties, such as dielectric constant values, band gaps, and crystallization temperatures.


**Table 1.** Principal physical properties of high-κ gate binary oxides.

Figure 1a reports the values of the band gaps of different insulators as a function of their relative permittivity (in units of the vacuum permittivity ε0). The general trend (highlighted by the continuous line) is a decrease in the band gap with increasing permittivity. Hence, the reduced band gap of high-permittivity oxides can represent a concern in terms of leakage current. For this reason, insulators with appropriate band alignment with the semiconductor must be preferred. In this context, Figure 1b shows the band alignment of several high-κ oxides with the semiconductor materials under consideration (i.e., Si, 4H-SiC, and GaN). The offset between the conduction bands of the semiconductors and insulators is reported in scale.

ε **Figure 1.** (**a**) Band gap values as a function of relative permittivity (in units of the vacuum permittivity ε0 ) for different insulators. The continuous line is a guide; (**b**) schematic illustration (in scale) of the band alignments of some common insulators with the semiconductor materials under consideration (i.e., silicon, 4H-SiC, and GaN). The light purple, green, and orange dotted lines indicate the conduction band edge of the Si, 4H-SiC, and GaN semiconductors, respectively.

Hence, in terms of physical properties, the guidelines for the choice of the ideal gate dielectric material are: (i) high dielectric constant value; (ii) appropriate alignment of the band gap with respect to the substrates (in particular, the band offset should be greater than 1 eV); (iii) thermal stability during the fabrication process (many steps have to be carried out at high temperatures for short periods of time) [17–19].

Moreover, since the gate oxide is directly in contact with the device channel, another important requirement is good quality of the gate oxide/semiconductor interface in terms of low roughness and low density of electronic defects [5].

These requirements could be met throughout two possible approaches, i.e., a crystalline gate oxide epitaxially grown on the semiconducting substrate or an amorphous oxide. Electronic defects can be thus minimized either by exactly or randomly saturating the dangling bonds, respectively. Generally, amorphous oxides are the preferred solution, since they possess isotropic dielectric constants due to the fluctuation of the polarized bonds and do not possess rough edges. By contrast, the advantage of the epitaxial oxides is the abruptness of the interface [17,18].

In general, as schematically illustrated in Figure 2, structural and compositional defects of binary oxides (e.g., oxygen vacancies, impurities, etc.) can generate the presence of energetic levels within the band gap or at the interface, and the trapped charges in these states are undesirable for the following reasons: (i) they are responsible for a shift in the voltage threshold of the transistor; (ii) they may change over time and determine the instability of the transistor output characteristics; (iii) they scatter the carriers in the inversion channel and, consequently, limit the channel mobility; (iv) they compromise the transistor reliability because they are the main cause of the dielectric breakdown [17,18].

κ Silicon dioxide (SiO2) [15] was considered an ideal dielectric during the Si era because it possesses a very low electronic defect density. The reason for this is the low coordination number, which guarantees the possibility to "repair" the dangling bonds. On the other hand, alternative high-κ oxides possess chemical bonds that cannot easily relax, thus inevitability leading to a higher electronic defect density. Hence, there is a need to reduce the number of electronic defects in these materials by annealing treatments or by optimizing their deposition processes.

κ **Figure 2.** Schematic representation of the main issues affecting the functionality of high-κ binary gate oxides in a transistor.

κ In this context, the important role of the growth technique for the deposition of the high-κ dielectric layers is clear. Certainly, many deposition techniques based on either physical or chemical principles are available. However, the semiconductor industry currently demands manufacturing techniques able to achieve good surface coverage on large areas, high conformity on three-dimensional structures, high growth rate, reliability, and compatibility with the thermal budget required for the device fabrication [31,32].

κ Table 2 compares the main features of the common growth techniques used [29] for the deposition of high-κ oxide thin films for microelectronics applications, considering the different deposition parameters. High deposition rates and large varieties of available materials are certainly the main advantages of molecular beam epitaxy (MBE) or chemical vapor deposition (CVD) methods. By contrast, these techniques are characterized by the need for high deposition temperatures. Physical vapor deposition (PVD)-based techniques are generally preferred for metals rather than for insulator deposition and lack uniformity over large areas.


**Table 2.** Comparison of the main features of the common deposition techniques for high-κ oxides in microelectronics [29,31,32].

However, judging from the latest industrial trends and looking forward at the nanometric-scale miniaturization process of electronic devices, the employment of deposition methods with atomic-level accuracy has become mandatory. From this perspective, atomic layer deposition (ALD) is the most promising deposition technique, and it is gradually replacing CVD and PVD techniques in many applications.

ALD is an innovative thin-film growth method that belongs to the general class of CVD techniques. As in a typical CVD process, films are deposited from gaseous chemical precursors, one for each element of the desired compound. However, unlike the traditional CVD mechanism, the ALD process is characterized by "self-limited" reactions, first between precursor and pristine surface and second on a surface saturated by one "monolayer" of precursor fragments [31]. This deposition mechanism allows subnanometer control of film thickness, conformal coating of nonplanar substrates (step coverage ~100%), and high-quality films deposited at relatively low temperatures [32]. For these reasons, the employment of ALD can give several advantages over that of either CVD or PVD. Finally, the low growth rate of the classical thermal ALD (T-ALD) process has been now significantly improved by the implementation of plasma enhanced ALD (PE-ALD). PE-ALD is an energyenhanced deposition technique based on plasma ignition to enhance the co-reactants' reactivity. The high reactivity of the plasma species produces a higher density of reactive surface sites. Consequently, higher growth rates and better properties of the resulting films in terms of density, impurity content, and electrical parameters can be obtained. Another advantage of PE-ALD is the possibility to control additional process parameters, such as the operating pressure, plasma power, and plasma exposure time. Varying the plasma parameters enable fine tuning the properties of the deposited films.

A great part of the results presented in the following Sections are related to high-κ oxides grown by ALD techniques.

#### **2. Amorphous High-**κ **Oxides on WBG Semiconductors**

Several amorphous materials have been studied in the last decades as possible high-κ gate oxides for WBG semiconductors. Among them, because of their high crystallization temperature, Al2O<sup>3</sup> thin films have certainly been the most widely investigated solution as amorphous dielectric layers. Some studies have reported on Al2O<sup>3</sup> formed by reactive ion sputtering [33–35], oxidation of Al in oxygen ambient at high temperatures [36], and a few others nonconventional techniques [37,38]. The major drawbacks of these solutions are the low breakdown fields (around 5–6 MVcm−<sup>1</sup> ) of the deposited films and their poor thickness uniformity on large areas. These limitations have been overcome by the implementation of the ALD technique, which has been the method of choice to study the potentiality of Al2O<sup>3</sup> thin films [39–44].

However, several issues still remain objects of investigation in order to optimize the quality of deposited materials and their interfaces with the WBG semiconductors. Moreover, though the growth of high-κ oxides amorphous films is generally carried out at low deposition temperatures (in the 200–300 ◦C range), some interfacial interaction could occur in SiC and GaN substrates, resulting in the presence of unwanted materials or deposition by products.

In this context, the cleaning of the substrate surface before dielectric deposition, as well as the postdeposition annealing treatments, are discussed in the next subsections, illustrating as examples some relevant case studies of amorphous high-κ oxides on SiC and GaN substrates.
