*3.1. Optimising Dielectric Composition*

This section demonstrates the advantages of employing a bilayer insulator composition in quasi-vertical MOSFETs through DC and pulsed measurements, and TCAD simulations [46]. The devices under test are GaN-on-Si trench MOSFETs, structurally similar to Figure 1. During Atomic Layer Etch (ALE) processing steps, an O<sup>2</sup> plasma is used to oxidize the GaN after which a BCl3 dry etch step is executed to remove the oxidized GaN layer. The amount of ALE cycles has been optimized to ensure a good profile of the gate trench, removing in total ~25 nm. In this section, we discuss the effects of the dielectric composition around the gate trench, as illustrated in Figure 5. The Al2O<sup>3</sup> deposition is performed using atomic layer deposition (ALD) at 300 ◦C, while the SiO<sup>2</sup> in the bi-layer is deposited using plasma-enhanced chemical vapor deposition (PECVD) at a deposition temperature of 400 ◦C. The focal idea was to compare the robustness of devices fabricated with a bilayer dielectric composed of SiO<sup>2</sup> and Al2O<sup>3</sup> to devices with a traditional unilayer dielectric of Al2O3. Effectively, the bilayer stack should combine the merits of SiO<sup>2</sup> as a bulk insulator with the ability of Al2O<sup>3</sup> to create a high-quality interface to GaN.

**Figure 5.** Dielectric composition of the devices under test. The first configuration is an unilayer of 35 nm Al2O<sup>3</sup> at the GaN interface, while the second has a bilayer composition: 35 nm of SiO<sup>2</sup> , then 2.5 nm of Al2O<sup>3</sup> at the GaN interface.

As expected, the gate-source and gate-drain diode leakage of the bilayer devices was found to be lower by a couple of orders of magnitude [46]. This is attributed to the intrinsically higher breakdown field of SiO2, as well as the additional barrier (conduction band discontinuity at the Al2O3/SiO<sup>2</sup> interface of 0.4 eV [86]) to thermionic leakage from the channel to the gate, introduced by the bilayer configuration.

To evaluate the reliability of the two stacks under the ON-state, forward gate breakdown step stress tests were performed, where the gate voltage was incremented from 0 V in steps of 3V, while VDS was constant at 1 V. Very little dispersion in breakdown voltage was observed across several devices, and the gate breakdown voltage for the unilayer and bilayer configurations were found to be 9 V and 27 V [46], the bilayer devices displaying an improvement of three times.

In Figure 6, the schematic of the simulated device (Figure 6a), and the electric field distribution within the unilayer and bilayer oxides are visualized at their respective gate breakdown voltages.

In the ON-state, the channel exists continuously along the trench sidewalls. Thus, the applied gate voltage falls entirely within the oxide layer, and the internal field grows rapidly, as illustrated in Figure 6b,c. This condition can then be used to estimate the critical electric field for the two gate dielectric compositions. From theoretical considerations, the unilayer Al2O<sup>3</sup> devices are expected to have an average critical electric field value of 2.6 MV/cm (9 V/35 nm), while the bilayer devices are estimated to have a critical electric field value of 7.5 MV/cm (26.2 V/35 nm) for the SiO<sup>2</sup> layer, and 3.2 MV/cm (0.80 V/2.5 nm) for the Al2O<sup>3</sup> layer [46]. These values are well substantiated by the simulated electric fields in Figure 6 obtained at the respective breakdown voltages.

**Figure 6.** (**a**) Schematic of the simulated quasi-vertical trench MOSFET. Electric field distribution around the trench edges at the measured ON-state breakdown voltage visualized for (**b**) unilayer: Al2O3/GaN devices and (**c**) bilayer: SiO2/Al2O3/GaN devices.

The second set of measurements were aimed at comparing OFF-state performance of the dielectric stacks. Figure 7 presents the results of drain step stress until breakdown, coupled with electroluminescence (EL) studies, performed at VGS =0 V on 35 devices from each wafer. During each stress step, an EL image was simultaneously generated with an acquisition time of 40 s [46]. In the OFF-state, the applied stress voltage is distributed across the depleted drift layer, in addition to the dielectric stack, resulting in correspondingly higher breakdown voltages for both unilayer and bilayer devices. The *VBR* distribution for the tested devices is compared in Figure 7a, wherein the bilayer emerges as clearly superior, with an average *VBR* improvement of 10 V.

**Figure 7.** OFF-state drain step stress performance at VGS = 0 V for a 35-device sample set (**a**) Comparison of the experimental breakdown values for both unilayer and bilayer cases (**b**) Localization of the failure spots along the gate finger, collected from observed EL spots (an example of an EL spot shown for reference at top) at corresponding *VBR* values.

An example of an EL spot observed along the gate finger at *VBR*, reflecting the region of breakdown in the devices, is shown in Figure 7b, along with a collated map of the breakdown spots for all tested devices, identified through EL acquisitions obtained during the step stress process, and on reaching failure. The results clearly indicate a preferential failure occurrence at the corners of the gate fingers, independent of the dielectric deposition.

The measurements displayed in Figure 7 were performed using microprobes fitted with an optimized current limiting circuit, in order to protect the failed devices from thermal runaway, and to preserve them for further post-failure analyses by TEM and Energy Dispersive X-ray Spectroscopy (EDX) [100,101] to identify the cause of breakdown [102].

Compared to the size of the original defect, an observed EL spot represents a relatively wide area in which the original defect could be present. Screening is necessary to precisely localize the defect within the observed EL spot area, which can be done by performing alternating focused ion beam (FIB) milling and SEM imaging [100]. After screening of the

defect, TEM investigations were performed at various lamella thicknesses starting from 1.5 µm down to 50 nm to search for of a particular defect. Figure 8 exemplary displays the results of a defect analysis of a stressed bilayer device at the location of a particular EL spot, with a focus on the gate trench corners.

**Figure 8.** TEM analysis of defect at gate trench of a bilayer device at the position of an EL spot (**a**,**b**) BF-TEM and (**c**) ADF-STEM images of an approx. 50 nm thin lamella.

Device failure was identified to have been caused by an electrical breakdown of the gate isolation at the bottom edges of the trench, and was correlated with the presence of several abrupt steps of the gate trench sidewall [102]. While the defect structure was found to coincide with a melted area and several voids (see Figure 8b,c) as a consequence of gate shorts [102], EDX analysis on failed devices (not shown here, but reported in [102]) revealed that the breakdown of the gate isolation resulted in minor migrations of silicon and oxygen, and a dominant migration of nitrogen into the gate oxide.

To complete the investigation into the relative merits/demerits of the bilayer composition, trapping analyses using double pulsed [44,103] and on-the-fly transient [44,104,105] measurements were performed on several devices from both wafers, as presented in Figure 9. More details on the test methods will be provided in Section 4. The shift in the threshold voltage (∆Vth) is compared for identical positive gate overdrive stresses.

**Figure 9.** Comparison of bilayer vs. unilayer Vth shifts relative to the unstressed threshold voltage using (**a**). Double pulsed characteristics and (**b**) Vth transient tests.

The Vth shifts are comparable or slightly higher for the bilayer case, which could be due to additional trapping sites generated at the additional interface within the dielectric. However, the trapping performance for both the compositions is primarily comparable, which implies that most of the trapping can be presumed to occur at the interface and/or border traps near the shared GaN/Al2O<sup>3</sup> region [44,106,107].

#### *3.2. Optimising Trench Fabrication*

In Section 3.1, the cause of breakdown was correlated to non-idealities around the trench edges. In this section, the cross-sectional analyses to identify the underlying issue, and to visualize improvements in the gate trench etch process, are summarized [102], in an effort to understand how to improve breakdown performance.

The investigated devices are GaN-on-Si trench MOSFETs with bilayer gate dielectric compositions. The fabrication process of the gate trench involved a bulk GaN etch process followed by an ALE and wet cleaning process. The first set of devices (Wafer A) are from the bilayer wafer presented in Section 3.1 (see Figure 8). The second set of devices (Wafer B) are taken from a wafer with an optimized ALE processing and wet cleaning sequence.

During the initial FIB-SEM investigation to isolate the defective/shorted gate, irregularities of the trench structure of Wafer A were observed. Hence, slice-and-view FIB-SEM analysis [100,101,108,109] was undertaken to study the trench at different locations along the gate finger, as presented in Figure 10.

**Figure 10.** Slice and View analysis by FIB-SEM along the gate finger of devices from (**a**–**c**) Wafer A and from (**d**–**f**) Wafer B. (**a**) and (**d**) SEM top view images of the devices. The positions of the cross sections are marked by colored, dashed lines. (**b**,**c**) and (**e**,**f**) SEM cross sectional images. The colored frames correspond to the colored dashed lines in (**a**) and (**d**).

Several steep steps of varying shape and length were observed at each cross section along the trench sidewalls, dominantly at the lower trench corners. Since these irregularities are associated with accelerated degradations, drawing from these observations, the ALE and wet cleaning processes were improved during the fabrication of Wafer B. As displayed in Figure 10d–f, the newly fabricated trench gates have clean sidewalls, with no observed roughness or steps. Further TEM analysis [102] also corroborated these observations.

From the results in Section 3, we can improve the general understanding of the degradation mechanisms that occur within the gate stack, when subjected to prolonged gate and drain stresses. Bilayer dielectric compositions, utilizing the good interface properties of Al2O<sup>3</sup> to GaN and the improved stability of the SiO<sup>2</sup> material, were found to be highly advantageous to breakdown performance of GaN trench MOSFETs, without significant worsening of trapping effects. However, before improving other design parameters, the fundamental GaN etch process must be robust. Microstructural defects formed during fabrication of the gate trench sidewalls can manifest in worsened reliability and faster breakdown, hence optimization techniques to minimize etch roughness are critical.
