**3. Epitaxial Growth of High-**κ **Oxides on WBG Semiconductors**

While different oxides have been studied as gate insulators on SiC and GaN [15–19], only some of them can be grown epitaxially on the WBG semiconductor single-crystal surface [23–25,80–84]. The epitaxial growth of high-κ oxides on WBG semiconductor substrates can offer some advantages. Generally, the principal improvement is related to better saturation of interface unbonded atoms. In particular, the most commonly used SiC and GaN polymorphs for microelectronics applications possess the wurtzite structure, with hexagonal surface atomic arrangements. However, though in principle this strategy can be applied to both SiC and GaN technologies, practical studies have been performed mainly on GaN-based substrates. In fact, the few studies of epitaxial high-κ materials on SiC substrates were limited to γ-Al2O<sup>3</sup> phase films [80] and direct growth of NiO thin films by metal organic chemical vapour deposition (MOCVD) [81]. The γ-Al2O<sup>3</sup> phase films were initially grown by Tanner et al. [80] by the ALD process as amorphous layers, and the epitaxy on 4H-SiC substrate was obtained under a post-annealing crystallization process at a very high (1100 ◦C) temperature. The epitaxy was observed for the alignment of the γ-Al2O<sup>3</sup> (111) planes with the (001) 4H-SiC substrate, having a lattice mismatch of about 8.8%. On the basis of the performed reflection high-energy electron diffraction analysis, the (111) γ-Al2O<sup>3</sup> oriented films showed quite good structural properties for film thickness up to 20 nm, even though some twinned grains were present. Moreover, upon increasing the film thickness, the crystallization process was no more efficient, and amorphous regions were observed under TEM investigation.

Epitaxial NiO films, by contrast, have been directly grown onto 4H-SiC epilayers at the deposition temperature of 550 ◦C [81,85]. A high-resolution TEM micrograph of the NiO/4H-SiC interface (Figure 6a) confirmed the presence of an axially-oriented (111) NiO film, but a "non-ideal" interface was observed, because a discontinuous amorphous SiO<sup>2</sup> layer was detected, probably formed during MOCVD growth. Furthermore, the presence of Moiré fringes generated by the superposition of twinned NiO grains was observed. The C–V characteristics of NiO/4H-SiC capacitors (Figure 6b) were used to calculate the dielectric constant, the value of which, at 6.2, was much lower than the theoretical 11.9. This result was justified by the presence of the discontinuous silicon oxide interfacial layer.

**Figure 6.** (**a**) High-resolution cross-section TEM image of a NiO film deposited by MOCVD on 4H-SiC at 500 ◦C; (**b**) C-V curve acquired on a NiO/4H-SiC MOS capacitor. Reproduced with permission from [81]. Copyright © 2013 Elsevier Ltd.

More studies on growing epitaxial oxides have been carried out on GaN-based materials. The materials under investigation comprise some lanthanide oxides, such as gadolinium [82], scandium [83,84], and lanthanum [83] oxides, as well as nickel [23,24,81] and cerium oxides [25,81]. The lanthanides oxides possess bixbyite symmetry, while NiO and CeO<sup>2</sup> are face cubic centred (fcc) oxides. However, the (111) planes of the latter two possess a hexagonal oxygen structure, which is suitable for epitaxy with the (0001) GaN superficial planes. Their structural and physical properties are summarized in Table 3.


**Table 3.** Physical and structural properties of high-κ oxides epitaxially grown on GaN.

The epitaxial growth of Sc2O<sup>3</sup> thin films was performed on a GaN substrate at about 700 ◦C by the pulsed laser deposition (PLD) technique [84]. Herrero et al. [84] demonstrated that the most critical deposition parameter to obtain perfectly stoichiometric and epitaxial Sc2O<sup>3</sup> thin films was the oxygen partial pressure. In particular, above 50 millitorr oxygen partial pressure, more than one preferential growth direction was observed. The epitaxial growth of Sc2O<sup>3</sup> was also evaluated by Jur et al. [83] by the MBE technique. Their investigation extended to La2O3, which in principle can provide a dielectric constant of 26 in its hexagonal structure. Nevertheless, La2O<sup>3</sup> growth was demonstrated not to be trivial, since La2O<sup>3</sup> is a hygroscopic material and tends to form an amorphous layer at the interface with the GaN substrates. Nevertheless, the authors demonstrated that it was possible to inhibit the water diffusion by the introduction of a thin Sc2O<sup>3</sup> layer between GaN and the growing La2O<sup>3</sup> films. The MBE technique was also used for the growth of Gd2O<sup>3</sup> epitaxial gate oxide on an AlGaN/GaN heterostructure [82]. Sakar et al. [82] showed the impact of a Gd2O<sup>3</sup> epitaxial oxide layer on the electrical performance of an HEMT device. Gd2O<sup>3</sup> films were deposited at 650 ◦C. The authors demonstrated that the Gd2O<sup>3</sup> layer underwent phase transition upon increasing its film thickness. The first layers, up to about 3 nm, possessed hexagonal structure, which changed to monoclinic phase when the thickness of 15 nm was reached. This phase transformation had a great impact on the electrical

properties, especially in terms of interface trap density, which showed a minimum value of 2.98 <sup>×</sup> <sup>10</sup><sup>12</sup> cm−<sup>2</sup> eV−<sup>1</sup> in Gd2O<sup>3</sup> film 2.8 nm thick. The authors' conclusion was that the epitaxial lattice strain also positively affected the two-dimensional electron gas density at the AlGaN/GaN interface by about 40%.

− −

Nickel and cerium oxides (NiO and CeO2) have also been deposited onto AlGaN/GaN systems. The first report on NiO-oriented film as a gate insulating layer in AlGaN/GaN devices was related to thermal oxidation of Ni metal layers [86]. In particular, the fabrication process relied on a heating treatment, in the 300–600 ◦C temperature range for 5 min in air ambient, of a 10 nm-thick Ni metal layer. Besides the observation of a colour change from the dark Ni metal layer to the transparent NiO film, no details were provided on the structural or compositional characteristics of the formed NiO layers. Generally, the thermal oxidation of Ni metal layers can lead to the formation of voids in the oxide layer and/or of randomly oriented films, since the process initiates at the grain boundaries and then expands in all directions. The growth kinetics of NiO film seem to depend on the texture and crystallite size of the initial Ni metallic layer [87]. It has been shown that the strong (111) texture of the Ni layer results in slow NiO growth. These slow oxidation kinetics are related to the stronger resistance to oxidation of the Ni (111) planes [88]. Therefore, the NiO growth proceeds mainly from other crystallographic planes, mostly located at the grain boundaries. Indeed, most of the Ni grains have a (111) texture. This nonuniform growth results in increased surface roughness after oxidation.

The growth of NiO and CeO<sup>2</sup> thin films on AlGaN/GaN heterostructures was carried out by MOCVD at 500 ◦C [23–25]. TEM analysis demonstrated the formation of 16 nm-thick NiO (Figure 7a,b) and 20 nm-thick CeO<sup>2</sup> (Figure 7c,d), both compact and uniform films. Since no intermediate layers were visible at the interface, the occurrence of any interaction and/or oxidation of the substrate during the growth process was ruled out. Moreover, the (111) NiO planes were perfectly parallel to the (0001) planes of the AlGaN/GaN substrate.

**Figure 7.** High-magnification cross-section TEM images (**a**) and in-plane SAED patterns (**b**) of NiO thin film deposited by MOCVD on AlGaN/GaN heterostructure at 500 ◦C. High-magnification cross-section TEM image (**c**) and in-plane SAED patterns (**d**) of CeO<sup>2</sup> thin film deposited by MOCVD on AlGaN/GaN heterostructure at 500 ◦C. Panel (**a**): reproduced with permission from [23]. Copyright © 2012 AIP Publishing; Panel (**d**): reproduced with permission from [25]. Copyright © 2013 AIP Publishing.

The selected area electron diffraction (SAED) pattern (Figure 7b) indicated that the external spots related to the NiO were perfectly aligned to the internal ones from the AlGaN. In particular, the white spots at 2.77 Å and 1.59 Å plane distances could be related to the (100) and (110) AlGaN/GaN planes and represented the typical 0001 zone axis pattern for a hexagonal single crystal, while the red spots forming the hexagonal pattern at 1.47 Å can be related to the (220) NiO plane; thus, only the 111 NiO zone axis is visible. The NiO spots are perfectly aligned to the AlGaN/GaN spots at 1.59 Å. Hence, it is possible to conclude that an epitaxial growth of the (111) NiO planes on the (0001) substrate plane occurred. The occurrence of the epitaxial growth can be explained by considering the threefold symmetry of the (111) NiO, which makes possible an epitaxial relationship between the hexagonal (0001) planes from the AlGaN substrate and the (111) planes of the NiO film. In particular, the lattice mismatch between the two hexagonal arrangements from the NiO and AlGaN, calculated from the electron diffraction images, was about 5%. Moreover, it is worth noting that the XRD peak position of the NiO (111) reflection was very close to that of bulk NiO, thus indicating that relaxed NiO thin films with strong diffraction intensity could be obtained under the described operating conditions. Hence, it can be concluded that NiO deposited samples were epitaxial and stress-free films and possessed excellent interface quality. TEM analysis also defined the structural relationship between the deposited CeO<sup>2</sup> films and the AlGaN/GaN substrate. A TEM cross-section image showed the formation of 20 nm-thick CeO<sup>2</sup> film and an almost perfect film/substrate interface (Figure 7c). The presence of differently oriented grains is evident, as can be deduced by the appearance of Moiré fringes. In-plane SAED was also recorded, and diffraction patterns of three different zone axes were visible. The 0001 zone axis pattern of the substrate is represented by the white circles in Figure 7d. The CeO<sup>2</sup> SAED pattern demonstrated that the CeO<sup>2</sup> film grew along two different orientations, namely, the (111) and (100) directions. In fact, the 111 zone axis pattern is represented by the red spots lying at 1.93 Å plane distances, and the 100 zone axis pattern is represented by dots lying at the vertex and at the centre of each side of the yellow squares at 1.93 Å and 2.70 Å plane distances, respectively. The 100 CeO<sup>2</sup> zone axis is represented by three equivalent configurations 30◦ rotated in the plane.

Hence, the NiO films (111) epitaxially grew on (0001) AlGaN/GaN substrate, while the CeO<sup>2</sup> film was not a single crystal epitaxial layer but formed by two sets of differently oriented grains (namely, (111)-oriented and (100)-oriented grains) aligned in the (0001) substrate plane of AlGaN.

The electrical characteristics of the oriented NiO and CeO<sup>2</sup> thin films allowed determining their experimental permittivity values. In fact, from the analysis of the C–V curves, it was possible to estimate permittivity values of 11.7 and 26 for NiO and CeO<sup>2</sup> films, respectively. These values were very close to those of the NiO and CeO<sup>2</sup> bulk permittivity (11.9 and 26) and properly higher than that of AlGaN alloys. These good values were probably due the oriented growth of the two films, which represented almost an "ideal" bulk system, in contrast to amorphous and/or polycrystalline films, which generally show lower values with respect the bulk materials.

Another key parameter to be considered in dielectric material integration onto WBG semiconductors is the effective density of the trapping states. The maximum of the trapping states determined in the AlGaN/GaN metal insulator semiconductor (MIS) diodes were <sup>5</sup> <sup>×</sup> <sup>10</sup><sup>12</sup> cm−<sup>2</sup> eV−<sup>1</sup> for the CeO<sup>2</sup> films and 6 <sup>×</sup> <sup>10</sup><sup>11</sup> cm−<sup>2</sup> eV−<sup>1</sup> for the NiO films. The trapping states of the CeO<sup>2</sup> were higher than those of the NiO, which could be attributed to the better structural characteristics of the NiO/AlGaN interface. While (111) NiO thin insulating layers seem to be an appealing choice as an epitaxial gate oxide, their integration into a real transistor has not been attempted yet.

#### **4. Application of High-**κ **Oxides as Gate Dielectrics in SiC and GaN Transistors**

As already mentioned in the introduction, most powered electronic devices based on silicon have used silicon dioxide (SiO2) as a gate dielectric. However, the use of SiO<sup>2</sup> in modern devices based on WBG semiconductors can be a bottleneck for the full exploitation

κ κ

**κ**

of the intrinsic properties of these materials because of the low value of the dielectric permittivity of SiO2.

Figure 8 shows the schematics of common insulated gate transistors based on wide band gap semiconductors (SiC and GaN), i.e., a 4H-SiC metal oxide semiconductor field effect transistor (MOSFET) (Figure 8a), an AlGaN/GaN metal insulator semiconductor high electron mobility transistor (MISHEMT) (Figure 8b), and a recessed gate hybrid AlGaN/GaN MISHEMT (Figure 8c).

**Figure 8.** Schematic cross section of (**a**) a 4H-SiC power MOSFET, (**b**) an AlGaN/GaN MISHEMT, and (**c**) a recessed gate hybrid MISHEMT.

κ A first advantage of using a high-κ dielectric in a power device is related to the distribution of the electric field at the gate dielectric region. In particular, according to Gauss's law, the electric field in a gate dielectric Eins that is placed on a semiconductor substrate, e.g., in the gate of a transistor, is given as:

$$\mathbf{E\_{ins}} = \frac{\kappa\_{\mathbf{s}}}{\kappa\_{\rm ins}} \mathbf{E\_{s}} \tag{1}$$

E୧୬ୱ = κୱ κ୧୬ୱ Eୱ where κ<sup>s</sup> and κins are the relative dielectric permittivity values of the semiconductor and insulator, respectively, and E<sup>s</sup> is the electric field in the semiconductor [89].

κ Considering as an example that the relative dielectric permittivity of 4H-SiC is 9.7 while that for SiO<sup>2</sup> is 3.9, according to Equation (1), the electric field in the gate oxide is about a factor of 2.5 times that in the semiconductor. Hence, when the critical electric field of 4H-SiC is reached, the maximum electric field in the oxide exceeds 9 MV/cm, thus meaning that the insulator is subjected to a significant stress, and the device reliability is penalized. In recognition of this problem, it has been proposed to replace the conventional SiO<sup>2</sup> gate dielectric by a high-κ insulator, with a permittivity comparable to that of SiC, so that the electric field in the gate dielectric would become closer to that in the semiconductor. In this way, the maximum electric field in the gate dielectric could be reduced, which should be satisfactory for reliable device operation. Moreover, the changes in the electric field distribution have a strong impact on the drift layer thickness required to sustain the targeted drain bias. In fact, using a high-permittivity gate dielectric allows using the optimal semiconductor drift region for the targeted breakdown, thus minimizing the specific on-resistance of the device.

Moreover, considering always the case of a SiC MOSFET (Figure 8a), the total specific on-resistance Ron,sp of the device is given by the sum of different contributions [89]:

$$\mathbf{R\_{on,sp}} = \mathbf{R\_{ch}} + \mathbf{R\_{a}} + \mathbf{R\_{JFET}} + \mathbf{R\_{drift}} + \mathbf{R\_{sub}} \tag{2}$$

where Rch is the channel resistance, R<sup>a</sup> is the accumulation region resistance, RJFET is the resistance of the JFET region, Rdrift is the resistance of the drift region after the current spreading from the JFET region, and Rsub is the resistance of the n-type doped substrate.

R<sup>a</sup> and RJFET can be minimized by appropriately scaling the device layout, and Rsub can be reduced by thinning the substrate. Hence, the control of the channel resistance contribution Rch is a critical point in 4H-SiC MOSFET fabrication. In particular, the channel resistance contribution Rch is given by:

$$\mathbf{R\_{ch}} = \frac{(\mathbf{L\_{ch}} \cdot \mathbf{p})}{\mu\_{\text{inv}} \mathbf{C\_{ox}} (\mathbf{V\_G} - \mathbf{V\_{th}})} \tag{3}$$

where p is the pitch of the MOSFET elementary cell, Lch is the channel length, µinv is the mobility for electrons in the channel (inversion layer), Cox is the specific capacitance of the gate oxide, Vth is the threshold voltage, and V<sup>G</sup> is the applied gate bias. The gate oxide capacitance term Cox increases with the insulator permittivity. Hence, it has a direct impact on the channel resistance and ultimately on the device's total resistance.

As pointed out by theoretical works [89,90], the use of high-κ is ideally desirable for future application in trench MOSFET technology [91].

One of the interesting features of the GaN semiconductor and its related AlGaN alloys is the possibility of growing AlGaN/GaN heterostructures. AlGaN/GaN heterostructures are characterized by the presence of a two-dimensional electron gas (2DEG) formed at the interface and possessing a high sheet charge density (in the order of 10<sup>13</sup> cm−<sup>2</sup> ) and a high mobility (above 1000 cm2V −1 s −1 ) [92,93]. Moreover, GaN-based materials have a high critical electric field (above 3 MV/cm). Thanks to these unique properties, high-electron mobility transistors (HEMTs) based on AlGaN/GaN heterostructures with excellent performances have been demonstrated in recent years and are suitable candidates for high-frequency applications [94,95]. These devices are based on a Schottky barrier at the gate electrode to modulate the channel current. However, particularly for high-voltage applications in which the gate electrode is strongly reverse biased with respect to the drain, a high gate leakage current at the Schottky junction can limit the performance of these transistors [96]. Hence, a dielectric must be introduced under the gate in order to reduce the leakage current, creating a metal–insulator–semiconductor high-electron mobility transistor (MISHEMT), as schematically shown in Figure 8b. In this case, however, the choice of the gate dielectric represents a key issue for improving device performance [21,97,98] and optimizing the parasitic capacitance and the gate leakage current [19,99].

Similarly, the benefits of using high-κ materials on the characteristics of insulated gate transistors in SiC and GaN can be understood from the theoretical calculations shown in Figure 9a,b. In particular, Figure 9a shows our calculation of the threshold voltage as a function of the thickness of different high-κ dielectrics for 4H-SiC MOSFETs. As the gate dielectric thickness is increased to reduce the gate leakage current, the threshold voltage of the device (Vth) also increases. Hence, while an improvement in the off-state characteristics of the MOSFET is achieved, this is accompanied by a degradation in the onstate performance. However, using high-κ dielectrics as insulating gate materials instead of the conventional SiO2, the rate of increase in the threshold voltage with the dielectric thickness is reduced. In this way, the leakage can be reduced, with a minor side effect on the output current.

Figure 9b shows the calculation of the threshold voltage of a GaN-based MISHEMT as a function of the gate dielectric layer thickness of different high-κ insulators. In this case, the Vth of the device is negative because of the inherent normally-on nature of these devices [92]. The negative value of Vth increases with increasing thickness of the gate insulator. However, the rate of this negative shift is reduced with increasing dielectric permittivity [100]. Hence, the use of high-κ gate insulators in GaN-based MISHEMTs is beneficial for reducing the power consumption of the devices.

κ **Figure 9.** Calculated threshold voltage of SiC MOSFETs (**a**) and AlGaN/GaN MISHEMTs (**b**) as a function of the gate insulator layer thickness for different high-κ materials. Panel (**b**): reproduced with permission from [100]. Copyright © 2014 WILEY-VCH Verlag GmbH & Co. KGaA.
