**2. OFF-State-Leakage and Doping Constraints of Quasi-Vertical GaN-on-Si Diodes from IMEC, Leuven, Belgium**

In this section, we discuss the factors influencing the leakage current and the breakdown voltage of vertical GaN-on-Si stack, specifically designed for vertical trench-MOSFETs.

The growth of thick, mostly insulating GaN drift layers on Si was made possible during the last years thanks to the intense research on lateral power GaN devices; the main goal has been to improve the OFF-state blocking capability. For the move into vertical GaN devices, the drift layer modulation needs to be more rigorous, since in addition to sustaining high reverse biases in the OFF-state, it also needs to have a low resistivity in the ON-state. The ideal drift layer is thick, to sustain a large breakdown voltage, lightly doped, to ensure high mobility, thus allowing a good ON/OFF ratio, and has a low defect density, to minimize the defect-related leakage components [3]. Unintentionally doped drift layers are weakly n-type (10 16 carriers/cm<sup>3</sup> or above, [3,47,48]), due to residual impurities introduced during the growth process, such as silicon and oxygen [3,47–52].

In a vertical trench-MOSFET, the n − drift region is in direct contact with the p-body, that may have Mg concentrations in excess of 10 <sup>18</sup>–10 19 cm−<sup>3</sup> . To optimize the breakdown voltage of vertical power FETs, it is therefore important to minimize both the leakage through the drift region, and to ensure that the p-body/drift region junction can sustain the high vertical field when the device is in the OFF-state [3,31,53–55].

Magnesium doping in GaN has been reported to form acceptor states located 0.16 eV above the valence band [56,57]. This relatively deep energy level results in incomplete thermal ionization of Mg acceptors at room temperature. Since the presence of hydrogen during MOCVD growth of p-type GaN can passivate the Mg-dopant through the formation of Mg-H bonds [58], a post-growth annealing treatment (while ensuring energies are lower than the threshold to create native defects) is necessary to ensure a high conductivity and hole density.

There are several possible leakage paths in the OFF-state [53,59,60]. In the quasivertical layout, parasitic leakage along the etch sidewalls and the bulk regions might be dominant and needs to be minimized. Other leakage paths may be present along the passivation layers, or vertically along the entire stack, reaching the substrate. To minimize the vertical leakage, the prevalent leakage mechanisms among different technology variations need to be understood, to enable directed improvements.

In performing leakage analysis of reverse biased p <sup>+</sup>n diodes, the conduction mechanisms through dielectrics subjected to high electric fields have been found to be applicable [53,59,61]. For low to medium reverse bias, the relevant mechanisms are usually electrode-limited related to the quality of the metal-semiconductor contacts. However, these mechanisms are usually not relevant in good vertical designs. As such, bulk conduction mechanisms are more relevant, in particular, variable range hopping (VRH) [54,55,59,62–71], Poole-Frenkel emission [59,63–69,72–78], and space charge limited conduction (SCLC) [31,47,53,79].

For investigating the doping and leakage issues under OFF-state within the vertical stack, it is useful to consider the simpler quasi-vertical diode structures, which form the fundamental block of the full MOSFET. The test vehicles used for the following study were aimed at understanding the p + -n −-n + stack; the schematic is presented in Figure 2. Fabricated on a 200 mm Si substrate, the diodes have Mg doping with N<sup>A</sup> = 6 × 10 19 cm−<sup>3</sup> within the p + layer, and a weakly n-type drift layer with n = 4 × 10 16 cm−<sup>3</sup> . The cathode is at the buried n + layer below the n drift region. The reverse breakdown voltage was measured to be 170 V on these specific structures, having a drift layer thickness equal to 750 nm [45,55].

**Figure 2.** Schematic of the quasi-vertical p + -n GaN-on-Si diodes.
