*3.1. Design*

*Vin* depends on the available input power source. For the buck mode of operation, *Vin* must be greater than open circuit battery voltage, *Vbat*. For maximum control flexibility, the duty cycle is 50% and *Vin* can be selected based on (2).

$$V\_{in} = 2V\_{bat\\_n} \tag{2}$$

where, *Vbat*\_*<sup>n</sup>* is the nominal battery voltage from datasheet.

*Rin* depends on the value of DC load current in mode 3. For maximum control flexibility, *Rin* can be selected by (3).

$$R\_{in} = \frac{V\_{in}}{i\_{rin}} = \frac{V\_{in}}{I\_{in\\_dc}} = \frac{2V\_{bat\\_n}}{I\_{dc}/2} = \frac{4V\_{bat\\_n}}{I\_{dc}}\tag{3}$$

The input capacitor should be capable to store the charge and energy for half cycle of the injected AC current and discharge in rest of the half cycle. The value of *Cin* is determined based on the allowable input ripple voltage Δ*vcin* and the magnitude, *Im*, and frequency, *ω*, of AC current. The charge storage, sinusoidal ripple current, and ripple voltage across input capacitor is depicted in Figure 5. *Cin* is used to bypass most of the AC current. Therefore, AC current through *Rin* and *Vin* should be negligible. Input capacitor current, *icin*, can be represented by (4).

$$i\_{\rm circ} \approx I\_{\rm IN} \sin(\omega t) \tag{4}$$

**Figure 5.** AC states at input capacitor: current, charge, and voltage.

The voltage and the charge of the input capacitor is determined based on the initial conditions and AC current. The charge of the input capacitor, *qcin*, can be presented by (5).

$$q\_{cin} = q\_{in} + \int i\_{cin}dt\tag{5}$$

where, *qin* is the steady state stored charge in capacitor. The designed nominal input voltage, *Vin* can be considered is initial condition for capacitor voltage, *vcin*. Therefore, *vcin* can be represented by (6).

$$
\upsilon\_{\rm cin} = V\_{\rm in} + \Delta \upsilon\_{\rm cin} \sin(\omega t + \pi/2) \tag{6}
$$

By the definition of capacitance, the relationship between voltage and charge can be presented by (7).

$$i\_{\rm cin} = \frac{dq\_{\rm cin}}{dt} = \mathbb{C}\_{\rm in} \frac{dv\_{\rm cin}}{dt} \tag{7}$$

Equation (7) can be rewritten as (8) by linearization. The linearization is shown in Figure 5.

$$\frac{\Delta q\_{\rm cin}}{\Delta t} = \mathcal{C}\_{\rm in} \frac{\Delta v\_{\rm cin}}{\Delta t} \tag{8}$$

For 1/4th of the period, Δ*qcin* is determined by (9).

$$\frac{\Delta q\_{cin}}{\Delta t} = \frac{\int\_0^{T/4} i\_{cin} dt}{T/4} = \frac{\int\_0^{T/4} I\_m \sin(\omega t) dt}{T/4} = \frac{I\_m}{8\pi} \tag{9}$$

where, *T* is period. Therefore, (8) can be represented by (10).

$$\mathbf{C}\_{\rm in} \frac{\Delta v\_{\rm cin}}{T/4} = \frac{I\_m}{8\pi} \tag{10}$$

Rearranging (10), *Cin* can be calculated from (11).

$$C\_{\rm in} = \frac{I\_{\rm m}T}{32\pi\Delta v\_{\rm cin}} = \frac{I\_{\rm m}}{32\pi f \Delta v\_{\rm cin}} = \frac{I\_{\rm m}}{16\omega \Delta v\_{\rm cin}}\tag{11}$$

where, *f* is the frequency of the AC current and *ω* = 2*π f* .

The output inductor, *L*, is selected based on the standard design as in (12) [18].

$$L = \frac{V\_{out} \times (V\_{in} - V\_{out})}{\Delta I\_L \times f\_{SW} \times V\_{in}} \tag{12}$$

where, Δ*IL* is the allowable inductor switching ripple current, and *fSW* is the pulse width modulation switching frequency. Switching ripple current, Δ*IL*, is different than controlled AC injection current. The frequency of Δ*IL*, is much higher than AC injection current and the magnitude should be almost negligible. A larger inductor gives better attenuation to switching ripple current. However, it reduces the control bandwidth. Considering (2) and control bandwidth, the design guideline for *L* can be presented in (13).

$$L = \frac{V\_{\text{bat\\_n}} \times (2V\_{\text{bat\\_n}} - V\_{\text{bat\\_n}})}{\Delta I\_L \times f\_{\text{SW}} \times 2V\_{\text{bat\\_n}}} = \frac{V\_{\text{bat\\_n}}}{2 \times \Delta I\_L \times f\_{\text{SW}}} \tag{13}$$

The output capacitor, *C*, reduces the switching ripple voltage. *C* can be selected by the standard design as in (14) [18].

$$C = \frac{\Delta I\_L}{8 \times f\_{SW} \times \Delta V\_{out}} \tag{14}$$

A higher value of *C* provides lower switching ripple. However, the battery itself has very high capacitance. Therefore, a smaller value of *C* can be used.

The passive components for the topologies are calculated using (2), (3), (11), (13), and (14) considering *Vbat*\_*<sup>n</sup>* = 13.8 V, *Im* = 5 A, and *f* = 20 Hz, *fSW* = 100 kHz, Δ*Vout* = 7.5 mV, and Δ*IL* is 5% i of *Im*. Available standard components are selected for experiments. The calculated and selected value of components are in Table 2.

**Table 2.** Passive Components for Topologies.


*3.2. Modulation*

The midpoint voltage, *Vmid*, is the voltage across *L* and *C* shown in Figures 3 and 4. *Vmid* determines the direction and magnitude of output current *Iout*. *Vmid* is controlled by pulse width modultion (PWM) of the gate driver signal. The output voltage, *Vout*, depends on internal impedance, *Z*, output current, *Iout* and open circuit battery voltage, *Vbat* as in (15).

$$V\_{\text{out}} = V\_{\text{bat}} + I\_{\text{out}}Z \tag{15}$$

The PWM signals to drive the MOSFETs are shown in Figure 6. The gating signal and midpoint voltage for synchronous buck converter is in Figure 6a. *Q*<sup>1</sup> and *Q*<sup>2</sup> are complementary. Deadtime is considered between on states of *Q*<sup>1</sup> and *Q*2. The estimated average midpoint voltage is expressed by (16).

$$
\overline{V\_{mid}} \approx dV\_{in} \approx \overline{V\_{out}} \tag{16}
$$

where, *d* is the duty cycle. The effect of synchronous operation and deadtime are excluded from calculation in (16).

**Figure 6.** Gate driver PWM signal for power converters: (**a**) synchronous buck (**b**) H-bridge with unipolar switching (**c**) H-bridge with bi-polar switching.

The unipolar PWM signal for H-bridge topology is shown in Figure 6b. *Vout* is always positive. Therefore, *Q*<sup>3</sup> is always off and *Q*<sup>4</sup> is always on for unipolar switching. *Q*<sup>1</sup> and *Q*<sup>2</sup> are complementary with deadtime. The estimated average voltage for unipolar switching is approximately the same as the synchronous buck converter in (16).

$$
\overline{V\_{mid}} \approx d\_{\rm uni} \, V\_{in} \approx \overline{V\_{out}} \tag{17}
$$

where, *duni* is the duty cycle of *Q*<sup>1</sup> for unipolar PWM. The relationship between *duni* and *d* is represented by (18).

$$d\_{uni} = d \tag{18}$$

The bipolar PWM signal for the H-bridge is in Figure 6c. The estimated average midpoint voltage for bipolar PWM is expressed by (19).

$$
\overline{V\_{mid}} \approx d\_{bi} V\_{in} - (1 - d\_{bi}) V\_{in} \approx \overline{V\_{out}} \tag{19}
$$

where, *dbi* is the duty cycle of *Q*<sup>1</sup> for bipolar switching. 1 − *dbi* is applied to *Q*3. *Q*<sup>1</sup> and *Q*<sup>2</sup> are complementary with deadtime. *Q*<sup>3</sup> and *Q*<sup>4</sup> are also complementary. *dbiVin* represents positive parts of *Vmid* and (1 − *dbi*)*Vin* represents the negative part. *Vout* is always positive, therefore *dbiVin* is always significantly higher than (1 − *dbi*)*Vin*. The relationship between *dbi* and *d* is represented by (20)–(22).

$$d = d\_{bi} - (1 - d\_{bi}) \tag{20}$$

$$d\_{l\dot{l}} = \frac{1}{2} + \frac{d}{2} \tag{21}$$

$$1 - d\_{\rm bi} = \frac{1}{2} - \frac{d}{2} \tag{22}$$

PWM techniques are selected based on the topologies used to inject AC current injection. Regardless of the topology chosen, *Vmid* is controlled by the duty cycle, *d*. *d* is converted to *duni* and *dbi* for the H-bridge using unipolar and bi-polar switching. For both topologies anti-parallel diode ensures the reverse current flow i.e., discharging condition of the battery.
