*3.4. Solid-State Circuit Breaker*

The base design of the SSCBs that were developed to investigate non-unit protection schemes is shown in Figure 6. To interrupt the various short-circuit faults, two anti-series SiC (Cree C3M0065090D) switches are used for both the positive pole and the neutral. Furthermore, to prevent an avalanche breakdown of the switches and overvoltages in the grid, Metal Oxide Varistors (MOVs) are used to clamp the voltage. The design parameters of the SSCB are given in Table 1.

**Figure 6.** Base design of the solid-state circuit breakers that are used in this paper.

**Table 1.** Design parameters of the solid-state circuit breaker.


The SSCB measures the current via a high bandwidth hall-sensor, and the current rate-of-change (di/dt) via the voltage across the current limiting inductor. Using analog comparators, logical gates, and a latch circuit, the switches are turned off when the current through the SSCB or the voltage across the inductor exceed their set thresholds. It will be shown that it is able to detect and open its switches within 1 μs after its thresholds are exceeded. For illustrative purposes, a picture of the SSCB's hardware realization is shown in Figure 7.

**Figure 7.** Hardware realization of the solid-state circuit breaker.

## *3.5. Experimental Validation of the SSCB*

To validate the operation of the developed SSCB, one side is connected to a voltage source of 350 V while a short-circuit is induced at the other side using a mechanical relay and a variable resistor, much like the circuit shown in Figure 1. For the experiments, the thresholds for the overcurrent and inductor voltage (di/dt) detection are set to 21 A and 20 V (20 MA/s) respectively. For these experiments thresholds can be chosen arbirarily, but guidelines for determining appropriate thresholds will be given in Section 5.

To show the correct operation of the overcurrent detection, the SSCB is short-circuited at its terminal with a relatively high fault resistance and low inductance (8 Ω and 0 μH respectively). The fault current *IF* and the voltage over the current limiting inductor *UL* for this experiment are shown in Figure 8. At the fault occurrence the di/dt is high, but because the analog detection circuits use small filter capacitors and the system's time constant is low (due to the large fault resistance), the voltage over the inductor does not exceed its 20 V threshold long enough to trip the di/dt detection circuit. However, when the fault current exceeds the 21 A threshold, overcurrent is detected by the analog control logics and the switches are opened within 1 μs.

**Figure 8.** Experimental results when the SSCB is short-circuited with a high fault resistance resulting in the overcurrent detection being triggered when the current exceeds 21 A.

To show the adequacy of the di/dt detection, the experiment is repeated with relatively low fault resistance (2 Ω). The results for this experiment are shown in Figure 9. Because the system's time constant is lower, the voltage over the inductor remains above the threshold significantly longer. Therefore, the analog di/dt detection is triggered and the fault is cleared within 400 ns of its occurrence.

**Figure 9.** Experimental results when the SSCB is short-circuited with a low fault resistance resulting in the di/dt detection being triggered when the 20 V (20 MA/s) threshold is exceeded for a longer time.

From these two experiments it can be concluded that both the overcurrent and di/dt detection circuits operate adequately, and the SSCB clears faults within 1 μs. In the remainder of this paper three of these SSCBs will be used to experimentally validate the theory presented in this paper.
