**2. Hardware Description**

The designed converter is based on the FNA41560 IC (Integrated Circuit) produced by Fairchild Semiconductor's. This Insulated Gate Bipolar Transistor (IGBT) module is designed for low-power AC (Alternating Current) motor drive applications, cooler and air conditioning. The device responsible for the data acquisition, processing and execution of the vector control algorithm is the C2000 Delfino MCU TMS320F28379D LaunchPad microprocessor from Texas Instruments.

Figure 1 presents the system built to perform the experimental tests.

**Figure 1.** Experimental bench built.

The experimental bench is composed of:


There are two basic types of inverters, Voltage Source Inverter (VSI), powered by a voltage source, and Current Source Inverters (CSI) powered by a current source. VSI topology is more common and synthesizes a well-defined voltage in the machine terminals while CSI provides a current signal in the machine terminals [5].

Figure 2 presents the simplified schematic diagram of a VSI. This setting uses a rectifier to transform the AC input signal into DC. After rectification, the signal is filtered by the DC link to obtain a signal without oscillations. Next, the DC signal is applied to the threephase IGBT bridge with the sole purpose of creating an alternating signal at the output by switching the semiconductor frequently defined by the modulation technique employed.

**Figure 2.** Diagram of a voltage inverter.

#### *2.1. Digital Signal Processor*

The TMS320F28379D microcontroller is designed for application in control systems, drive drivers, signal detection and processing. The DSP has two Central Processing Units (CPU), two Control Law Accelerator (CLA) and a maximum adjustable clock of 200 MHz [25,26].

LaunchPad features 32-bit architecture, 1 MB of flash memory, 204 kB of RAM, 14 analog-to-digital conversion channels (ADC) with 16/12-bit resolution and 14 channels designated for PWM function [25,27,28].

### *2.2. Rectifier*

Rectifiers can be classified according to the number of phases of the input AC voltage source, i.e., single-phase or three-phase. Depending on the semiconductors used, they can be classified as uncontrolled, semi-controlled, or fully controlled. Also, concerning topology, they can be classified as half-wave or full-wave rectifiers [29]. The three-phase uncontrolled full-wave rectifier topology is common in converter drive applications because it uses diodes as the rectifying element, connected in a full-bridge arrangement.

In this configuration, the entire cycle of the alternating voltage of the power supply is rectified, providing in the voltage output a constant average value and with smaller oscillations [29]. For this work, the full-wave bridge rectifier configuration encapsulated in the KBPC3510 IC is used. This rectifier allows a maximum current of 10 A, enough to supply the consumption of the three-phase induction motor used.

#### *2.3. DC Link*

The design of the DC link capacitors considers the power of the converter load, the maximum permissible voltage variation, and the hold-up time of the load, which is defined as the time that the output voltage should remain constant in the event of a momentary fault in the capacitor bank's input voltage. The Equation (1) is used to design the capacitor bank, given by

$$C\_o = \frac{2P\_{rated}t\_H}{0.19V\_{rated}^2} \tag{1}$$

where *Prated*, *tH*, *Vrated* represent the rated power, hold-up time, and rated feed voltage of the machine, respectively. The variation of the output voltage was defined at 10% and the hold-up time of 8.33 ms, that is, a half cycle of the nominal frequency of the load. Thus, the capacitance value of the projected DC link is 4.4 mF, in which a total of eight EPCOS

B43845 capacitors of 2200 μF and voltage of 200 *Vdc* were used. The designed DC link can work with voltages up to 400 *Vdc*, enabling AC voltage connection at the rectifier input of 127 *Vrms* or 220 *Vrms*.

The DC link also contains pre-charge and bank discharge resistors. The pre-charge resistor is responsible for preventing a high in-rush current from flowing through the converter elements and damaging the components when the rectifier's AC supply circuit breaker is tripped. The single-phase variable autotransformer at the input of the rectifier circuit was also employed for this purpose, allowing the input AC voltage to rise gradually to the value of 220 *Vrms*.

The discharge resistor has the function of draining the energy stored in the capacitors when the converter is switched off, ensuring that the voltage reduces to zero slowly, also avoiding accidents. Another function of the discharge resistor is to work as a braking resistor when the machine starts to work as a generator due to the type of load it drives. In this context, the DC link voltage tends to rise due to the reverse power flow. Figure 3 illustrates the simplified DC link circuit with the pre-charge (*Rpc*) and discharge (*Rd*) resistors.

**Figure 3.** DC link with pre-charge and discharge resistors [30].

The AC voltage at the input of the rectifier circuit is 220 *Vrms*. Thus, the DC voltage at the output of the rectifier corresponds to the maximum value of the input voltage, i.e., 311 *Vdc*. The pre-charge resistor was chosen so that the link voltage reaches the maximum value (311 *Vdc*) in 5 s, while the discharge resistor was chosen so that the bank voltage is zero in 132 s. The *Ch*<sup>1</sup> switch is open only at the beginning of bank charging, and after the bank voltage stabilizes the switch is closed since the pre-charge resistor is no longer needed. Similarly, the switch (*Ch*2) is closed when the converter is switched off, allowing the stored energy in the bank to be drained, and when in the normal operation of the converter, *Ch*<sup>2</sup> is open.

#### *2.4. Power Module*

The choice of Fairchild Semiconductor's FNA41560 driver is a consequence of the need for a compact and high-performance solution for the frequency inverter. The chip features optimized circuit protection and a combined IGBT drive to reduce losses. The module is also equipped with overcurrent protection, under-voltage interlocks, temperature monitoring output, bootstrap diodes and features gate drive circuits and internal dead-time.

The FNA41560 must be powered with a voltage of 15 *Vdc*, supports 600 *Vdc* (drainsource voltage) in the IGBT while dissipating 41 W of power in each semiconductor. The module operates with a maximum switching frequency of 20 kHz, a maximum current of 15 A at 25 ◦C, an insulation rating of 2000 *Vrms*/min and terminals for individual current monitoring of each phase [31].

The power module has six PWM outputs to drive the IGBTs, which can be controlled by the DSP via optocoupler ICs. The PWM modules of the DSP have complementary outputs and internal dead-time production. However, a gate drive circuit was designed to receive the command signals from the upper switches of the three-phase IGBT bridge and, from these, the command signals of the lower switches and the dead-time between the switches of the same arm are produced via hardware. In this way, configuration errors of the PWM channels and dead-time of the DSP that could damage the FNA41560 are avoided. Figure 4 illustrates the dead-time generation circuit for the U-arm of the three-phase IGBT bridge.

**Figure 4.** Circuit to generate the complementary PWM and dead-time signals [30].

From Figure 4 it is noted that the circuit to generate the complementary signals has a resistor (*Rdt*) and a capacitor (*Cdt*) to generate the dead-time between the switches of the same arm along with AND and NOR logic gates. The switching frequency chosen is 10 kHz, within the operating range of the FNA41560. Thus, the resistor and capacitor were set to guarantee a dead-time of 1 μs equivalent to 1% of the switching period.

The designed PCB of the IGBT module contains three dead-time generation circuits and complementary signals. Looking at Figure 4, when applying a high logic level signal to the *UH*<sup>2</sup> input of the first arm, the *UHIGH* output also assumes high logic level. However, the *ULOW* output, which drives the lower IGBT, has a low logic level with the addition of the time delay, preventing simultaneous driving of the switches. The same principle is extended to the switches of the V and W arms of the three-phase IGBT bridge.

In addition, to drive the module's switches, optical isolation circuits or optocoupler circuits were used. These are circuits used with the purpose of electrical decoupling, the PWM channels of the DSP do not have a direct electrical connection with the inputs of the FNA41560. Its working principle is based on a Light Emitting Diode (LED) that, when energized, emits a light that puts a phototransistor in a conduction state [32].

The necessity for electrical isolation comes from the fact that there are voltages and currents in the power stage that could cause damage to the control and data acquisition circuits. For this reason, the reference of the power module is different from the reference of the DSP and the data acquisition boards, ensuring the isolation of the control and measurement circuits from the power circuits.

For this project, it was chosen to use optocouplers of the HCPL2630 type. These ICs work with Transistor-Transistor Logic (TTL) logic level, considerable electrical isolation, 12 ns delay time and have two independent channels in the same encapsulation [33].

Figure 5 illustrates the circuit developed to isolate PWM signals from the DSP to the FNA41560 driver.

The PWM signals coming from the DSP have as reference *GND*1, while at the output of the optocouplers (power stage), the reference is *GND*2. At the output of the isolation circuit, the PWM signals are injected into the dead-time circuits and there is the generation of the complementary PWM to drive the IGBTs of the power module.

**Figure 5.** PWM signal isolation circuit [30].

To monitor the temperature of the power module, a voltage comparator circuit with a variable resistor was designed to adjust the maximum temperature limit of the FNA41560. The IGBT module has an internal thermistor that changes its resistance according to the temperature change. If the module temperature exceeds the set limit, the circuit containing the operational amplifier LM2904 changes the state of the output from logic level low to high. In this context, the signal at a logic high level triggers an LED as a visual alert, in addition to sending a pulse to the DSP to interrupt the PWM signals from the IGBTs.

Figure 6 presents the circuit used for under-voltage blocking recommended by the FNA41560 manufacturer. Also, a 4N25 optocoupler and a voltage divider circuit were used to transmit the signal to the DSP.

**Figure 6.** FNA41560 under-voltage detection circuit [30].

The resistors RPF, RS and the capacitors CPF, CBPF are defined according to the module datasheet. The resistor *R*<sup>1</sup> is used to limit the current of the optocoupler LED, the resistors *R*<sup>2</sup> and *R*<sup>3</sup> are the voltage divider resistors. The values of 200 Ω, 10 kΩ and 20 kΩ respectively have been set. The terminals "A" and "K" of the 4N24 IC indicate the Anode and Cathode terminals of the LED. The terminals "C", "B" and "E" represents the collector, base and emitter terminals of the phototransistor, respectively.

Short-circuit current detection of the FNA41560 is provided by a shunt resistor located at the source terminals of the lower IGBTs of the three-phase bridge. If the voltage across the resistor exceeds the short-circuit threshold voltage trip level (0.5 *Vdc*) at the *Csc* input of the module, a fault signal is assigned and the lower arm IGBTs are turned off [34].

The protection circuit contains a low-pass filter, formed by resistors *Rf* and capacitor *Csc*. The module manufacturer suggests values for these components in such a way that the time constant is between 1 μs and 2 μs. A 15 Ω resistor and 100 nF capacitor were used, i.e., filter time constant of 1.5 μs. A shunt resistor with a value of 0.1 Ω was sized. Thus, for the protection to operate, a current greater than or equal to 5 A circulating through the module is required.

### *2.5. Current Measurement*

The current measurement of the converter was made using the LA 55-P Hall-effect sensor from the LEM manufacturer. Table 1 presents the characteristics of the transducer.

**Table 1.** LA 55-P sensor characteristics [35].


When an electrical current circulates through the primary winding (*Ip*) of the current sensor, a current also circulates in the secondary (*Is*) proportional to the conversion ratio of the transducer. The current in the secondary in turn produces a voltage (*Vin*) on the shunt resistor *Rm* and thus this voltage signal is fed into the non-inverting adder circuit. In the design of the current acquisition circuit, it was chosen to use the TL084 operational amplifier and the *Rm* resistor was set to a value of 100 Ω. The current conditioning circuit is shown in Figure 7.

**Figure 7.** Current signal conditioning circuit.

The voltage signal *Vref* is responsible for adding an offset voltage to the signal. Since the analog-to-digital conversion channels of the DSP operate with input voltages between 0 and 3 *Vdc*, an offset voltage must be added to the input signal such that this voltage represents the null measurements of the sensor, while voltages above the offset value represent positive measurements of the sensor and voltages below the offset voltage represent negative measurements. The Equation (2) presents the relationship between output voltage *Vout*<sup>1</sup> with inputs *Vref* and *Vin*, given by

$$V\_{out1} = \frac{V\_{in}}{2} + \frac{V\_{ref}}{2} \tag{2}$$

Therefore, the output voltage is given by half of the reference voltage and half of the input voltage. The output signal of the non-inverting adder circuit passes through a clipper circuit, composed of two diodes and a resistor, whose function is to limit the output voltage of the operational amplifier between 0 and 3 *Vdc*.

A simulation was developed to evaluate the operation of the current conditioning circuit. Considering a current in the secondary of the transducer of 10 mA and reference voltage of 3 *Vdc*, i.e., offset voltage of 1.65 *Vdc* to ensure that the post-processing signal remains in the middle of the reading range. In addition, a signal with a frequency of 10 kHz and amplitude of 0.05 V was added to the input signal to represent the noise present in the current measurement as a function of power module switching.

Figure 8 shows the result of the current conditioning circuit simulation.

**Figure 8.** Simulation of the conditioning circuit of the current sensor.

By inspecting Figure 8, it is possible note that the *Vout*<sup>1</sup> voltage signal oscillates over the offset voltage value and remains between 0 and 3 *Vdc*. However, the voltage signal representing the current is not exclusively sinusoidal, it contains a high-frequency component, coming from the switching of the power module. Thus, it is desirable to remove the ripple caused by switching. The RC loop consisting of *Rf* and *Cf* , operating as a passive anti-aliasing low-pass filter was inserted into the output of the conditioning circuit, as presented in Figure 7. The Equation (3) is used to calculate the filter cutoff frequency, given by

$$f\_c = \frac{1}{2 \cdot \pi \cdot \mathcal{R}\_f \cdot \mathcal{C}\_f} \tag{3}$$

A cutoff frequency of 2.4 kHz was adopted for the filter and, thus, the value of the resistor used was 2 kΩ and the capacitor of 33 nF. Figure 9 shows the comparison between the input voltage signal and the voltage signal after the low-pass filter.

**Figure 9.** Simulation of the RC anti-aliasing filter.

From Figure 9 it is noted that the ripple caused by switching has been considerably attenuated by the filter used. It can also be seen that a delay has been incorporated into the signal, but not very significantly.

#### *2.6. Voltage Measurement*

The LV 20-P voltage transducer from the manufacturer LEM was used for voltage measurement. Table 2 shows the characteristics of the sensor.

**Table 2.** LV 20-P sensor characteristics [36].


When applying a voltage to the sensor measuring terminals, a current (*Ip*) is produced in the primary winding. Thus, in the secondary, the current (*Is*) is produced due to the transducer conversion ratio. In turn, the current in the secondary produces a voltage on the shunt resistor (*Rm*) which reflects the voltage applied to the primary of the sensor.

The voltage conditioning circuit is like the current conditioning circuit, shown in Figure 10.

From Figure 10 it is noted the presence of resistors on the primary side of the voltage sensor. The function of this resistor is to limit the transducer primary current according to the information presented in Table 2. Thus, it was adopted for the *R*<sup>1</sup> resistor a value of 75 kΩ, enabling the measurement of voltages up to 500 V. For the shunt resistor *Rm* a value of 100 Ω was adopted.
