*3.1. External-Biasing Topology*

To verify the effectiveness of the flicker noise reduction phenomenon, in the initial study, the gate bias of the MOS device was externally applied [32,40,41]. Similarly, the switched-biasing technique can be implemented by externally controlling the gate bias of the current source of the VCO. In addition, the efficiency of the flicker noise reduction by the switched-biasing technique can be significantly improved in the VCO because the external signal generator can be optimally designed with the modulation frequency, amplitude, waveform including the duty cycle, and DC bias voltage.

Yoshida et al. proposed a structure that digitally controls the current source of a ringtype VCO using a switched-bias circuit (SBC), which is depicted in Figure 4 [50]. As shown in Figure 4b, the SBC is composed of two-level shifters and two identical bias branches (BC1 and BC2) and is configured to operate alternately according to the clock (CK) signal applied from the outside. In the VCO core shown in Figure 4a, current sources divided into three bits are placed on each side of the delay cell, and their gate bias is switched to a modulated signal (Vcp and Vcn) formed through the SBC. In addition, all current sources are biased to perform a triode operation because the probability of trap −detrap is less than that of the saturation operation and less flicker noise is generated [55]. The clock frequency of the SBC was set to 10 MHz. The purpose is to suppress spurious occurrences at the switching frequency despite the simulation result that noise reduction below 100 kHz is independent of the clock frequency. Effectively utilizing the SBC, the ring VCO improves the noise performance by 3 dB at 100 kHz [50].

**Figure 4.** Ring VCO based on a switched-bias circuit (SBC): (**a**) block diagram of the ring VCO and schematic of the delay cell in the VCO; (**b**) schematic of SBC for current source modulation (reproduced with permission from the author, Low-voltage, low-phase-noise ring voltage-controlled oscillator using 1/f-noise reduction techniques; published by The Japan Society of Applied Physics, 2007) [50].

#### *3.2. Self-Biasing Topology with the Fixed DC Voltage*

A fully on-chip-type circuit cannot be configured by externally applying the modulation signal, and the design of the switched-bias technique is complicated because of the spurious dependence of the modulation frequency [50,56]. Although the external-biasing topology can supply the optimal modulation signal to the current source, the modulation signal correlated with the oscillation signal cannot be guaranteed to have an additional current injection at the time with the minimum sensitivity to the phase shift, as shown in Figure 3b. The phase noise of the oscillator can be further reduced by driving the current source modulated with the frequency which is the same as the oscillation frequency [34,47].

Jeong and Yoo proposed a method of applying switched-biasing to the current sources of each *gm* stage and the coupled input stage in a CMOS quadrature-VCO (QVCO), as presented in Figure 5 [57]. When applied to a conventional current source coupled QVCO, the switched-biasing technique can be applied to the current source shared by the coupled input stage and the *gm* stage. However, when the *gm* stage and the coupled input stage share a current source, the oscillation waveform and the common source node waveform are misaligned because of the resistance in the transistor triode region and parasitic capacitances in the common source node (shown as Vs in Figure 5a). In this design, the source nodes of the cross-coupled pair and the coupled-input pair are separated for optimal alignment, and the QVCO waveform is shown in Figure 5b. As a result, the oscillation amplitude increased by 0.3 V (peak-to-peak) compared to the structure that shared the current source. Compared to the constant bias current and shared-current source method, phase noise improvements of 17 dB and 10 dB were shown in the simulation, respectively. In the measurement results, an improvement in the performance of 10 dB by the switched-biasing technique was verified, compared to that of the shared-current source method [57].

**Figure 5.** CMOS quadrature-VCO (QVCO) with separate current sources based on the switched-biasing technique: (**a**) schematic of the QVCO; (**b**) simulation waveforms at the outputs of the quadrature channel and the common node (reproduced with permission from the author, Low-phase-noise CMOS quadrature VCO; published by IEEE, 2006) [57].

Musa applied switched-biasing to the current source of a VCO operating near millimeterwave, as shown in Figure 6 [51]. Unlike the CMOS structure, as it is an NMOS-only structure, an additional bias path (as shown in VBias of Figure 6a) for setting an appropriate DC bias level and a capacitor (as shown in *CF* of Figure 6a) for coupling with the oscillation node are added. As depicted in Figure 6b, based on the ISF theory, the phase noise was improved through optimal current injection (i.e., the zero crossing point of the ISF) [47]. In addition, as the size of the feedback capacitance *CF* determines the modulation signal amplitude, the capacitance was determined as an optimal value considering the trade-off between phase noise improvement and power consumption [51].

**Figure 6.** Millimeter-wave NMOS VCO using the switched-biasing technique: (**a**) schematic of the VCO; (**b**) waveform analysis of the VCO based on the ISF theory (reproduced with permission from the author, a low phase noise quadrature injection locked frequency synthesizer for mm-wave applications; published by IEEE, 2011) [51].

Huang and Kim proposed a self-biasing QVCO using the current source splitting (CSS) method, as illustrated in Figure 7a [52]. Unlike the conventional method of sharing a current source, it is designed to separate and deliver current to each cross-coupled transistor. This method has the advantage of being able to ignore noise caused by parasitic capacitance appearing at the common source node of a cross-coupled pair through separation of the corresponding node. In addition, the current source (NM5−<sup>6</sup> in Figure 7a) and the crosscoupled pair (NM1−<sup>2</sup> in Figure 7a) act as two cascode cross-coupled pairs, creating an effective negative resistance. As mentioned in Section 2 and as shown in Figure 7b, the longterm memory effect was eliminated by maximizing the modulation amplitude (i.e., VCO in the voltage-limited region), thus increasing the flicker noise reduction effect of the current source. To prove this, the result of the circuit simulation with which the flicker noise factor of the MOSFET was removed as compared to the measurement result of the fabricated QVCO, and similar phase noise improvement was confirmed [52].

**Figure 7.** CMOS QVCO with split current sources: (**a**) schematic of the QVCO; (**b**) simulated waveforms at the drain–source and gate-source voltages of NM5 (top) and NM1 (bottom) (reproduced with permission from the author, Low phase noise self-switched biasing CMOS LC Quadrature VCO; published by IEEE, 2009) [52].

Chen et al. proposed a method to suppress the flicker noise generated from crosscoupled pairs by adding a source degeneration capacitor, as depicted in Figure 8a [58]. The degeneration capacitor (*CD* in Figure 8a) is set to have a low impedance at the fundamental frequency and high impedance at a low frequency (i.e., flicker noise), as presented in Figure 8b [59]. In addition, using a filtering capacitor (as shown in *Cf* of Figure 8a), a low pass filter was constructed to remove noise from the bias path. In the simulation results, the closed-in phase noise of the VCO was improved by 2 dB using the current source modulation, but the structure using the degeneration capacitor improved 4, 11, and 7.5 dB at 10 kHz, 100 kHz, and 1 MHz, respectively [58].

**Figure 8.** CMOS VCO including degeneration and filter capacitors: (**a**) schematic of the VCO; (**b**) current flows depending on the capacitance of CD—the usage of the optimal capacitance can divide the current into two paths, as shown in the middle case (reproduced with permission from the author, Reduction of 1/f<sup>3</sup> phase noise in LC oscillator with improved self-switched biasing; published by Springer, 2015) [58].

> Hsieh and Lin proposed adding a passive network between the current source and the VCO core to suppress the up-conversion of the second harmonic noise, as shown in Figure 9a [53]. As the second harmonic current of the common source node of the crosscoupled pair is up-converted and acts as noise, *C*1, shown in Figure 9a, is connected in parallel with the current source to filter the second harmonic thermal noise [27]. Moreover,as the quality-factor (Q-factor) of the LC tank decreases during the period when the crosscoupled pair transistor operates in the triode, *L*1 is added to increase the impedance of the common source node. As shown in Figure 9b, it was verified that the closed-in phase noise (100 kHz−1 MHz) characteristic improved to 3 dB when the passive network was added basedonthesameswitched-biasingtechnique[53].

Based on the ISF theory, Mostajeran et al. proposed the ISF manipulation technique to reduce the flicker noise contribution by reducing the effective ISF of the tail current source, as shown in Figure 10 [60]. Considering that the ISF in the current source, it is necessary to implement two turn-offs during one oscillation period, and a separated current source structure was adopted in a similar manner to previous studies. By deep triode operation of the PMOS transistor as a current source, a low impedance path to the ground is formed so that less noise generated from the tail flows into the tank. Owing to switched biasing and the operation of the triode region of the PMOS, it can be observed that the effective ISF of the current source is reduced compared to the conventional NMOS current source, as depicted in Figure 10b. The measurement indicated an improvement of 17 dB in phase noise at 10 kHz and 8.2 dB at 1 MHz compared to phase noise with the structure using

the conventional NMOS current source, and a very low flicker corner frequency of 10 kHz was confirmed [60].

**Figure 9.** CMOS VCO with improved phase noise characteristics by adding a passive network: (**a**) schematic of the VCO; (**b**) phase noise of the VCO with the current source modulation and the noise filter (displayed as "proposed VCO"), the VCO using only the current source modulation (displayed as "without noise filter"), and the VCO using the constant bias voltage without the filter (displayed as "without switched biasing") (reproduced with permission from the author, A 0.7-mW LC voltage-controlled oscillator leveraging switched biasing technique for low phase noise; published by IEEE, 2019) [53].

**Figure 10.** CMOS VCO based on the ISF manipulation technique: (**a**) schematic of the VCO including current sources using PMOS transistors; (**b**) waveforms of the effective tail ISF amplitude for the conventional current source using NMOS and the proposed current source using PMOS (reproduced with permission from the author, a 2.4 GHz VCO with FOM of 190dBc/Hz at 10 kHz-to-2 MHz offset frequencies in 0.13 μm CMOS using an ISF manipulation technique; published by IEEE, 2015) [60].

Shasidharan et al. proposed a structure in which the switched-biasing technique is applied to a Class-C CMOS VCO, as shown in Figure 11 [54]. In this design, a source degeneration capacitor to suppress flicker noise of a cross-coupled pair and an auxiliary −*gm* stage to compensate for insufficient negative *gm* were constructed. A current source using PMOS transistors was used to make a low impedance path, and an effective switching

operation was achieved by the biasing at the sub-threshold voltage. Moreover, by adjusting the size of the current source appropriately, the parasitic capacitance *Cin* was designed to be an even-mode harmonic filter of the common node (VCM1−<sup>2</sup> in Figure 11b). As it was designed to have a narrow conduction angle of 0.31π through simulation, the phase noise characteristic shows an improvement of 14 dB in the performance at 1 MHz offset compared to the case where the switched-biasing technique was not applied [54].

**Figure 11.** Class-C CMOS VCO using the switched-biasing technique: (**a**) schematic of the VCO; (**b**) bias conduction at the sub-threshold operation of the split current sources implemented by PMOS transistors (reproduced with permission from the author, A 2.2 to 2.9 GHz complementary class-C VCO with PMOS tail-current-source feedback achieving—120 dBc/Hz phase noise at 1 MHz offset; published by IEEE, 2019) [54].

Lee and Im applied the switched-biasing technique in a simple inverter delay cell based ring oscillator, which is depicted in Figure 12 [61]. As shown in Figure 12b, by selfbiasing the current source of the CMOS inverter, the slope of the output waveform increases, and, as a result, the flicker noise is reduced and the oscillation swing is improved [62]. Compared to the topology without self-biasing, an improvement of 7 dB at 100 kHz and 11.5 dB at 1 MHz was verified through simulation [61].

**Figure 12.** Ring VCO using the switched-biasing technique: (**a**) schematic; (**b**) simulated waveforms of the VCO output (top), bias voltage of the current source (middle), and tail current of the inverter cell (bottom) (reproduced with permission from the author, Low phase noise ring VCO employing input-coupled dynamic current source; published by IET, 2020) [61].

As the self-bias topology is coupled from the oscillation node, there is the advantage that an external modulation signal is not required. In addition, because it is implemented in the design of the VCO alone, the noise design can be controlled differently from the case of external bias. However, in some studies, the DC bias level is set near the threshold voltage of the current source for a proper switching effect **[53,54,63]**. Unsurprisingly, switching of the current source occurs after oscillation has begun, and, hence, an excessively low DC bias may not provide adequate starting conditions.

#### *3.3. Self-Biased Topology with the Adaptive DC Voltage*

To solve the start-up issue of the general self-bias topology, a method of adaptively adjusting the DC bias level of the current source according to the oscillation amplitude can be used. As mentioned in Section 2, because the current efficiency can be improved by reducing the conduction angle, a narrow conduction angle can be implemented by lowering the DC bias level as it approaches the steady state.

Min et al. suggested that the DC bias level of the current source can be adaptively adjusted according to the VCO oscillation amplitude by adding an auxiliary peak detector to the existing self-biasing topology, as shown in Figure 13 [63]. In this design, referring to Figure 13b, a separate cross-coupled pair (depicted in M5− M6 of Figure 13a) detects the negative peak of the oscillation waveform and induces charging to the capacitor (as shown in *C*1 in Figure 13a). The charged voltage ( *Vk*) changes the DC bias level of the current source, solving the start-up issue of the oscillator, and simultaneously reducing the oscillator amplitude variability, mainly due to the Q-factor change of the capacitor bank within the tuning range and the process, voltage, and temperature (PVT) variation of the circuit. The phase noise using the switched-biasing technique was improved to approximately 6 dB at 100 kHz in the simulation, compared to that using the constantbiasing technique [63].

**Figure 13.** VCO using self-biasing with the adaptive DC voltage: (**a**) schematic; (**b**) operation of the self-biasing with the adaptive DC voltage from peak tracking at the oscillator outputs (reproduced with permission from the author, Low voltage CMOS LC VCO with switched self-biasing; published by Wiley, 2009) [63].

Narayanan and Okada presented the VCO architecture using a synchronized pulse generator to inject pulse-shaped waveforms into each current source, as shown in Figure 14 [64]. Unlike the self-biasing with the fixed DC voltage in which a modulation signal is injected directly through a capacitor, a rail-to-rail waveform is implemented using a two-stage inverter to narrow the conduction angle. As an additional method to reduce the conduction angle, an envelope tracking scheme called conduction angle control, shown in Figure 14a, was used. It lowers the DC bias level applied to the current source as the VCO oscillates,

as indicated in Figure 14b, so that the conduction angle decreases as the VCO reaches a steady state. As the DC bias is approximated to the supply voltage when the current source supplies current, the triode operation is possible; thus, the noise generation of the current source is reduced compared to the case of the saturation operating point. Because of this design method, this VCO lowered the flicker noise corner to 700 Hz, and thus obtained the result of having a flattened figure-of-merit (FoM) in the range of 1 kHz−10 MHz. However, the intrinsic delay of the pulse generator clarifies the limitations of this method, as shown in Figure 14c. For proper current bias based on the ISF theory, a positive peak voltage must be delivered to the current source at the point where the ISF is zero crossing, but an indispensable mismatch occurs because of the corresponding delay. The result is shown in detail in Figure 14d. By adjusting the delay of the pulse waveform modeled with Verilog-A, when the delay exceeds 8/<sup>π</sup>, the phase noise degradation occurs rapidly, and even when it reaches 4/<sup>π</sup>, it can be observed that oscillation does not occur [64].

**Figure 14.** VCO employing the pulse generator that supplies pulse waveforms and the adaptive DC bias voltage: (**a**) schematic; (**b**) conceptual diagram of the VCO including the pulse generator operation; (**c**) intrinsic delay of the pulse generator; (**d**) simulated phase noise degradation with increasing the delay of the pulse generator (reproduced with permission from the author, A pulse-tail-feedback LC-VCO with 700 Hz flicker noise corner and −195dBc FoM; published by IEICE, 2019) [64].
