*3.5. Parasitic Capacitances*

The most important parasitic elements of the MOSFET are the capacitances due to the inherent field-effect operation of this transistor. The oxide and p-n junction capacitances are responsible for limitations of the frequency response which generates poles and zeros which are frequently analyzed to determine the stability of the device and the dominant bandwidth of the system. Three capacitances are considered in the conceptual design modeling:

i. "Oxide capacitance" is formed by the SiO2 between the gate terminal and the channel formed from drain to source. This capacitance is given by the gate oxide capacitance as follows.

$$\mathcal{L}\_{\mathcal{J}} = \mathcal{W}L\mathcal{L}\_{ox} = \mathcal{W}L\varepsilon\_{ox}/t\_{ox} \tag{11}$$

where εox is the oxide dielectric constant and *tox* is the oxide thickness.

ii. "P-N junction capacitances" due to the reverse bias of the p-n junctions formed between drain/source to the substrate/bulk terminals of the device. This capacitance is evaluated using the built-in potential *ϕ<sup>B</sup>*, built-in zero-bias junction capacitance *Cj*0, and the built-in junction capacitance *Cj*as follows.

$$\varphi\_B = V\_l \ln \left( \frac{N\_A N\_D}{n\_i^2} \right) \tag{12}$$

$$C\_{j0} = \sqrt{\frac{\epsilon\_{Si} q N\_A}{2 \varrho\_B}}\tag{13}$$

$$\mathcal{C}\_{\dot{j}} = \frac{\mathcal{C}\_{\dot{j}0}}{\left(1 - \frac{V\_{\dot{j}}}{\mathcal{C}\_{B}}\right)^{\text{ur}}} \tag{14}$$

where *ni* is the intrinsic carrier concentration in silicon, *NA/ND* are numbers of acceptor/donor atom concentrations per volume in material, *εSi* is the silicon dielectric constant, and *Vj* is the reverse bias voltage applied.

## *3.6. Passive Components*

In microelectronic conceptual design, the passive components provide additional versatility in the consolidation and refinement of many integrated circuits that require compensation, parasitic element adjustment, antenna integration, and other possible maneuvers. For the conceptual modeling using the Excel methodologies, this paper considers only resistor and capacitor implementations. To implement resistances, Table 3 shows the values for sheet and contact resistances in the C5 ON-SEMI process [15] described by wafer runs from the corresponding foundry.

**Table 3.** Resistance process parameters for CMOS 0.5 μm process used in ON-SEMI wafer runs [13].


From Table 3, N+ and P+ are the n-type and p-type doped active silicon materials, respectively; POLY, POLY2, and POLY2\_HR are polysilicon, polysilicon-2, and polysilicon2-high-resistivity materials, respectively; NWELL corresponds to the n-type well (where P-Type transistors are located); M1, M2, and M3 are metal-1, metal-2, and metal-3 layers, respectively, where the component connections are implemented inside the chip.

To implement capacitances, Table 4 shows the values for area, fringe and overlap capacitances in C5 ON-SEMI process [15]. The area capacitances for substrate, N+ active, P+ active, POLY, POLY2, M1 and M2 have units of aF/μ2, while the fringe and overlap capacitances are given in units of aF/μ. Parameters from table IV are very important in the compensation of analog integrated circuits that are used in instrumentation channels for processing signals coming from sensors and transducers.


**Table 4.** Capacitance process parameters for CMOS 0.5 μm process used in ON-SEMI wafer runs [15].

The equations to implement passive components are given as follows. Resistances made in Nwell, N+, P+, POLY, POLY2 and POLY2\_HR:

$$R\_T = \begin{bmatrix} \text{Short Resistance Parameter} \end{bmatrix} \times \text{L/W} \tag{15}$$

Capacitances made by POLY-POLY or POLY-Metal:

$$C\_T = \begin{bmatrix} \text{Capacitance Parameter} \end{bmatrix} \times \text{WL} \tag{16}$$

Now that the model equations have been presented, the following sections will discuss the methodology used to describe the conceptual model for the CMOS microelectronic circuit.

#### **4. Excel Methods for CMOS Design**

Conceptual design involves the use of parameters and constants to compute and size values of components and electrical variables [16,17]. However, sometimes the number of specifications given is larger than the number of degrees of freedom available to the designer trying to comply and fulfill them [3,4,27–29]. Therefore, in the design process, a series of decision points is necessary to iterate the processing flow before obtaining the final solution. Several trials are necessary and sometimes, intermediate simulations are required to analyze different alternative solutions. In this case, the use of Excel methods is convenient while advancing in the design process. There are three sorts of recommended methods:


#### *4.1. Single Straight Processing Excel Method*

In the single straight processing, the method proceeds in a horizontal fashion with the CMOS technology parameters in the first block of columns. Then, the processing flow continues sequentially, column by column, until the final desired calculation values are obtained. If several conditions are considered, then a row repetition is developed accordingly. Figure 4 shows single straight processing to design resistances using active p+, active n+, polysilicon and polysilicon-2 CMOS elements with their respective contact resistances and varying W and L sizes. Figures 5 and 6 show the CMOS 500 nm IC layouts of 3.5 K and 1.5 K resistors, obtained from Electric-VLSI. The artwork was developed once the Excel method was used to calculate the number of sheets or squares required by the conceptual design.


**Figure 4.** Single straight method to design CMOS resistances.

**Figure 5.** CMOS IC layout active p+ resistor design, 3.5 K, from Electric-VLSI.

**Figure 6.** CMOS IC layout polysilicon resistor, 1.5 K, from Electric-VLSI.

#### *4.2. Tabular Straight Processing Excel Method*

In the tabular processing, the method proceeds as usual, in a horizontal fashion to evaluate the design instance with the CMOS technology parameters in the first block of columns. However, this evaluation is repeated for a multiple number of instances while varying one or two specifications or parameters. Then, the processing flow continues sequentially, row by row, until the final desired instance is terminated. Each instance considered will be evaluated over a single row. Figure 7 and Figure 8 show tabular processing

to design capacitances using poly-poly-2 CMOS 500 nm technology. Figure 5 starts with the value of the capacitance and ends up with squared plates in Poly-Poly to design the capacitance. Figure 7 starts with L/2 feature size (300 nm in this case) X-Y rectangular dimensions to obtain the effective capacitance value. Figures 9 and 10 show the CMOS 500 nm IC layouts of 2 pF and 10 pF capacitances, obtained from Electric-VLSI. The artwork was also developed once the Excel methodology was used to evaluate the conceptual design. Capacitors from Figures 8 and 9 are used for operational transconductance amplifier (OTA) compensation later in this paper.


**Figure 7.** Tabular method to design CMOS capacitances. This Excel goes from capacitance value to X-Y dimensions.

#### *4.3. Two-Dimensional Processing Excel Method*

In two-dimensional processing, the method proceeds with the horizontal first row having the specifications and CMOS technology parameters of the conceptual design. Each row will define a step in the processing design flow such that the Excel will progress down and away from the first cell of the spreadsheet. The evaluations are arranged such that intermediate calculations follow a slope down from the early decisions all the way to the last decision. Usually, an iterative process is necessary to comply with two or three specifications with a single degree of freedom. For instance, with the bias current, ISS, of a differential amplifier, can fulfill expectations for Slew Rate (SR), Output Resistance (Rout), and Power dissipation (Pdiss) in the conceptual design of a CMOS differential amplifier. Figure 11 illustrates the Excel method to develop the conceptual design for a CMOS differential amplifier. The method illustrates the step-by-step evaluation and decision-making process downward, and the CMOS technology specifications are shown rightwards as shown in Figure 11. The CMOS Technology characteristics flow horizontally to the right and the CMOS design equations, from (5) to (10), flow downwards illustrating the step-by-by step procedure. The evaluation of CMOS transistor size, W/L, goes along to fulfill the required specification. However, if a particular spec does not convince the design engineer, the processing flow can be stopped, and a recalculation with a different spec or different decision making is readily possible at every row. The processing flow continues row/column by row/column until the final step and size selection is terminated.


**Figure 8.** Tabular method to design CMOS capacitances. This Excel sheet goes from X-Y dimensions to capacitance value.

**Figure 10.** CMOS IC poly-poly 10 pF capacitance with rectangular X-Y layout from Electric-VLSI.


**Figure 11.** Two-dimensional processing method to design a differential amplifier. From the initial cell (top-left), the conceptual design progress downward, step by step, and to the right to size each transistor.

Figure 12 shows the schematic from Electric-VLSI of a differential amplifier using results from the Excel two-dimensional method. In this case, every value sizing the MOSFETs means L/2 times or half the feature size of the technology. For instance, the middle twin transistors have a size of W = 120 × (0.5/2) = 30 μm by L = 2 × (0.5/2) = 0.5 μm. Furthermore, the SPICE code to perform DC and AC testing in this conceptual design of the device is shown in Figure 12. Once this schematic circuit model is tested, the next step is developing the layout. Differential amplifiers are the core of every instrumentation amplifier and their layout must be considered very carefully. Figure 13 shows the strategy recommended by J. Baker [4] to develop a common centroid layout.

With careful development by considering the DRC (direct rule checking) from Electric-VLSI CMOS 500 nm kit, the layout shown in Figure 14 is developed by using the evaluations and conceptual model obtained from the Excel two-dimensional method.

**Figure 12.** A differential amplifier schematic using CMOS 500 nm technology.

**Figure 13.** Common centroid layout recommended for big matched differential pair transistors [3,4].

**Figure 14.** Conceptual design layout (using Electric-VLSI) of a differential amplifier from an Excel method.

#### **5. Methodologies for Complete Amplifier Design**

The Excel methodologies shown previously can be applied to develop conceptual designs of complete functional blocks such as a cascode amplifier with its bias circuit, and a two-stage operational transconductance amplifiers (OTA). The OTA amplifier includes a compensation capacitance which is necessary to ensure stability and reliable operation for the required frequency response. Even though the following design examples are not very specialized, the literature shows many examples of more specialized conceptual designs where microelectronic design has been extended [30–33]. The design flow that students

must follow to perform the conceptual design of the microelectronic device is given as follows:

	- I. The characterization of the microelectronic device is the initial fundamental step in the analysis and design of the multi-stage amplifier.
	- II. Ideal analysis provides the first insight to the circuit operation by performing circuit analysis over the external components.
	- III. Practical models of the op-amp include static and dynamic parameters.
	- IV. The Excel method helps in developing the overall step-by-step procedure which accounts for all the requirements and specifications
	- V. The design of multi-stage devices involves the following boundary conditions and requirements:
		- a. Boundary conditions: CMOS technology, process specs (*VT0, Cox, K'*), supply voltage and current range (*VDD, VSS, ISS*), operating temperature (*To*) and range.
		- b. Requirements: Gain (*Av*, *Ai*), gain bandwidth (*GB*), settling time (*Ts*), slew rate (*SR*), input common mode range (*ICMR*), common mode rejection ratio (CMRR), power supply rejection ratio (*PSRR*), output voltage swing *(vout (max), vout (min)*), output resistance (*Rout*), offset voltage (*VOS*), noise (*eout 2*), layout area.
		- c. Verify that intermediate stages couple correctly without causing instabilities such as the influence of mirror poles in the transfer function. The Excel method can be used to revise and iterate the process in search of a robust device.
	- VI. Compensation techniques involve: Miller, feed-forward, and selfcompensation schemes.

#### *5.1. Cascode Amplifier with Bias Source*

The cascode amplifier obtains a higher gain and output resistance than the traditional inverting amplifier stages. Typical design parameters are slew rate (SR), output swing, and power dissipation for a simple cascode stage. Figure 15 illustrates the Excel method to develop the conceptual design for a cascode amplifier. As mentioned before, the method illustrates the step-by-step evaluation and decision-making process downwards and the processing flow goes rightwards. Again, the CMOS Technology characteristics and specifications flow horizontally to the right and the CMOS design equations, from (5) to (10), flow downwards illustrating the step-by-by step procedure. The evaluation of CMOS transistor size, W/L, goes along to fulfill the required specification.


**Figure 15.** Two-dimensional processing method to design a CMOS cascode amplifier.

> Figure 16 shows the schematic from Electric-VLSI of the conceptual design of the cascode amplifier which includes the bias network on the left of the stacked three MOSFET from the right. The bias circuit was implemented and evaluated in a separate analysis using the guidelines from J. Baker [4]. Once this schematic circuit model is tested, the next step is to develop the layout.

**Figure 16.** A three stack cascode amplifier schematic using CMOS 500 nm technology.

The layout is developed using Electric-VLSI and includes both the bias circuit and the three stacked transistors as shown previously in Figure 16. Figure 17 illustrates the layout design with the corresponding Vdd = 5 V and Vss = 0 (ground). This layout shows the transistors in horizontal layouts where the lower two levels include N-type transistors, and the upper level includes the P-type transistors which appear in the circuit schematic

from Figure 16. The layout also shows the p-well and n-well over the lower two N-channel transistor levels and the upper P-channel transistor level, respectively.

**Figure 17.** Conceptual design layout (using Electric-VLSI) of a three stage cascode from an Excel method.

#### *5.2. OTA with Miller Compensation*

The development of a conceptual model for an operational transconductance amplifier with Miller compensation has an additional complexity of calculating the feedback capacitance that operates the amplifier in a stable and reliable regime. The phase margin PM > 50◦ and the sizing of more than 10 transistors make the Excel method larger. Figure 18 shows the Excel spreadsheet workout with the evaluation of transistor sizes and dominant pole calculations.

Again, the procedure shows the conceptual design strategy mentioned before, the CMOS technology characteristics and specifications flow horizontally to the right and the CMOS design equations, from (5) to (10), flows downwards illustrating the step-by-by step procedure. In this case, Figure 18 has two downward decision flows. The first one evaluates the design with the sole calculation of the Miller compensation capacitance to provide the required phase margin and stability criteria [3,4,17,27]. The second design decision flow determines the size of a transistor to locate a right-hand side pole (RHP) exactly to cancel the second pole. This way the dominant pole will be extremely alone well inside the gain bandwidth and the amplifier will have, even higher, phase margin PM. Figure 19 shows the Electric-VLSI layout schematic of the conceptual design obtained for the 500 nm CMOS technology. Figure 20 illustrates the layout of the OTA amplifier with the area dominance of the compensation capacitance Cc = 3 pF. Those capacitances are extremely large and, in this case, the layout generated has a squared shape, like the ones developed with a single straight Excel methodology for capacitors. The layout shows also the common centroid differential amplifier stage developed before and the big, 125 μm/1 μm, p-channel MOSFET transistor right above the output voltage of the amplifier.


**Figure 18.** Conceptual OTA design with two downward decision flows.

**Figure 20.** Electric-VLSI layout of the CMOS OTA with RHP-zero compensation.

#### *5.3. Performance Simulation Tests*

The Excel methods are used to synthesize the conceptual designs of integrated circuits and devices to teach and develop successful strategies that can be repeated for different CMOS technologies. This section will compare the expected specifications defined initially with the schematic and layout results from SPICE simulations run by Electric-VLSI using the LTSpice program as a kernel.

Four conceptual design cases are analyzed which are part of a formal course in microelectronics [28]. The design problems are:


The differential amplifier results are summarized in Table 5. This amplifier stage is shown in Figures 11 and 13 and resolved using the two-dimensional processing method from the Excel methodology illustrated in Figure 10. The results comply with all the specifications established for the conceptual model using the CMOS 500 nm technology as illustrated in Table 5. Some parameters differ slightly because of the iterative nature of the design decision flow in which the number of requirements is higher than the number of degrees of freedom available: three transistor sizes (W/L) and the operating Q point of the current-sinking at the lower transistor in Figure 13.

**Table 5.** Specifications and measured values from simulation tests in the CMOS Differential amplifier.


Note: Differences are between accepted tolerances of +/−10% for the conceptual model development.

Table 6 illustrates the results for the cascode amplifier conceptual model developed using the Excel method shown in Figure 14. Again, this amplifier stage, shown in Figures 15 and 16, describes the fulfillment of all the specifications established for the conceptual model using the CMOS 500 nm technology. The power dissipation shown for this amplifier includes the three stack of transistors and the bias reference network shown in Figures 15 and 16. Again the number of requirements is higher than the number of degrees of freedom available: three transistor sizes (W/L) and the operating Q point of the current-sinking at the lower transistor in Figure 16. The two previous amplifiers, differential, and cascode are not used as independent amplifiers, but they are part of a larger multistage amplifier or microelectronics functional block. Therefore, the conceptual models for a highly specialized microelectronic device contain 2, 3, or more of those primitive amplifiers described previously. Now we will present results for the conceptual model of a two-stage OTA and of a three-stage operational amplifier. Table 7 shows results for the conceptual model of a two-stage OTA that includes a differential amplifier and an inverting amplifier that drives the load. This was the amplifier illustrated by Figures 18 and 19 and developed using the methodology of Figure 17. This OTA conceptual design includes additional specifications such as offset voltage, output swing, phase margin, power supply rejection ratio (PSRR), gain-bandwidth GB, and settling time. This is a preview of the project that the students in the microelectronics course develop at the end of the semester.


**Table 6.** Specifications and measured values from simulation tests in the CMOS cascode amplifier using using 0.5 μ porocess.

Note: Differences are between accepted tolerances of +/−10% for the conceptual model development.

**Table 7.** Specifications and measured values from simulation tests in the CMOS 2-stage OTA using 0.5 μ process.


Note: Power dissipation includes the bias current for both stages.

Finally, Table 8 illustrates the results obtained from a conceptual design of a 3-stage op-amp using an additional third stage with a shunt feedback scheme to reduce the output resistance of the device. The results are good with a low value with the negative slew-rate (SR) of −9 V/μs which needs to be improved from this conceptual design developed using the methodologies discussed in this paper.

**Table 8.** Specifications and measured values from simulation tests in the CMOS 3-stage op-amp using 0.5 μ process.


Note: Power dissipation includes the bias current for the three stages.

The schematic of the three-stage op-amp conceptual design is shown in Figure 21. This figure illustrates the main sub-components of the device: bias and reference voltage circuit, first stage differential amplifier, Miller and right-hand plane zero (RHP) compensation for maximum stability, inverting amplifier second stage, and the output push/pull with shunt feedback differential amplifier that provides a lower output resistance in the device.

**Figure 21.** Electric-VLSI schematic of the 3-stage CMOS op-amp with RHP-zero compensation.

The conceptual design developed in this paper shows one of the major steps in designing analog integrated circuits (IC) for electronic instrumentation devices required by electronics, biomedical, robotics, and computer engineering majors. In analog IC design, a good combination of function or application with IC technology is necessary to obtain a successful solution. The Excel methodologies are an additional tool to validate and verify the conceptual model required before the device is sent to the foundry facility. Analog IC design consists of three major steps [3]: electric design, physical design (layout), and test design (testing). Engineers and designers must be flexible, use techniques such as the Excel methods, and have a skill set that allows them to simplify and understand a complex conceptual design problem. In microelectronics, device IC design is driven by improving technologies rather than new technologies [3]. The engineer should be aware that sometimes analog systems applications, where speed, area, or power, have certain advantages over the digital approach. Even using Excel methods, deep-submicron (DSM) technologies offer grea<sup>t</sup> challenges to the creativity of engineers and designers of IC microelectronic devices.

#### **6. Analysis of Results**

To further increase the potential of using Excel methods in developing instrumentation amplifiers for biomedical applications, we examined a project case study using the methodology to design a 3-stage amplifier having a low voltage and low power operation in the strong inversion zone. Undergraduate students during the spring semester of 2021 in the microelectronics course at Tecnológico de Monterrey developed a project where they used the methods learned in class [34]. This design was going to be used as a subsystem of a bioinstrumentation amplifier required in sensor signal conditioning applications.

The project consisted of the development of a three-element instrumentation amplifier for biomedical applications. Figure 22 illustrates the basic scheme where two op-amps receive the differential mode input signals, and a third op-amp changes the signal from differential mode to single-ended mode referenced to ground.

**Figure 22.** Classic topology for the instrumentation amplifier used in biomedical applications.

In Figure 22, each op-amp (OA1, OA2, and OA3) must be selected from possible topologies seen in class to achieve certain performance characteristics. Those op-amps have the following components:


Figure 23 shows a block diagram of each op-amp with all the functional parts of the system. For the power source, the students have the option of developing a highperformance bandgap reference source that is stable with respect to variations in supply voltage, temperature, and noise.

**Figure 23.** Overall block diagram of each operational amplifier.

The requirements and specifications provided in Table 9 are to be met for each of the op-amp blocks.


**Table 9.** Proposed specifications for the op-amp design for biomedical applications.

The students began with a literature survey before selecting the device to develop from the conceptual requirements, theoretical development, schematic development, and layout implementation using Electric\_VLSI [35–38]. Instead of adding a third stage at the output of the two-stage OTA device, they added a second stage differential-amplifier with compensation between the first differential stage and the output stage. This results in improving the frequency response and sacrificing some gain and having a better phase margin for even robust design. Even with this modification, the simulations show an increase in the overall gain compared to the last three stage designs (Section 5). The compensation capacitor *Cc* and *Rz* are kept for both differential stages, and the output terminals of both compensation elements are connected all the way to the output of the circuit. The methodology generates the transistor dimensions and capacitor values illustrated in Tables 10 and 11.


**Table 10.** Transistor dimensions for the new three-stage conceptual design.

**Table 11.** Capacitors and resistors for the new three-stage conceptual design.


Considering the transistor dimensions for this new three stage amplifier design, the first cut expected parameters are calculated as follows, assuming long channel models.

1. Slew rate.

$$\text{LSR} = \frac{I\_5}{\text{C}\_c} = \frac{10\mu}{0.5p} = 20\,\text{V/}\mu\text{s}\tag{17}$$

2. Estimated amplifier gain.

$$A\_{v0} = \left(\frac{\mathcal{G}\_{m2}}{\mathcal{g}\_{m2} + \mathcal{g}\_{m4}}\right)^2 \cdot \frac{\mathcal{G}\_{m6}}{\mathcal{g}\_{ds6} + \mathcal{g}\_{ds7}} = \left(\frac{\mathcal{G}\_{m2}}{I\_5/2(\lambda\_2 + \lambda\_4)}\right)^2 \cdot \frac{\mathcal{G}\_{m6}}{I\_6(\lambda\_6 + \lambda\_7)}\tag{18}$$

$$g\_{m2} = \sqrt{2\beta\_2 I\_2} = \sqrt{2 \times 115.6 \mu \times 8 \times 5 \mu} = 96.17 \text{ }\mu\text{S} \tag{19}$$

$$g\_{m6} = 942.5 \,\upmu\text{S} \tag{20}$$

$$A\_{\rm r0} = = \left(\frac{96.16\mu}{5\mu(0.04 + 0.05)}\right)^2 \cdot \frac{942.5\mu}{92.14\mu(0.04 + 0.05)} = 134.3\text{ dB} \tag{21}$$

3. Power dissipation.

$$P\_{\rm diss} = (2I\_5 + I\_7)(V\_{dd} + |V\_{ss}|) = (2 \times 10\mu + 92.14\mu)(2 \times 1.8) = 403.7\,\upmu\text{W} \tag{22}$$

4. Output swing.

$$V\_{\rm out}(\min) = V\_{\rm ss} - V\_{\rm DS7}(\rm sat) = -1.8 + \sqrt{\frac{2I\_7}{k\_N(\mathcal{W}/L)\_7}} = 1.8 + \sqrt{\frac{2 \times 92.14\mu}{115.6\mu \times 22.5}} = -1.53\,\text{V} \tag{23}$$

$$V\_{out}(\max) = V\_{dd} - V\_{SDb}(\text{sat}) = 1.8 - \sqrt{\frac{2I\_6}{k\_P(W/L)\_6}} = \sqrt{\frac{2 \times 92.14 \mu}{37.8 \mu \times 130}} = 1.607 \tag{24}$$

5. Input common mode range, ICMR.

$$(W/L)\_5 = \frac{2I\_5}{k\_N V\_{DS} \text{(sat)}^2} = \frac{2 \times 10\mu}{k\_N \left(-V\_{ss} + I\text{CMR}^- - \sqrt{\frac{k}{\beta\_1}} - V\_{T1} \text{(max)}\right)^2} \tag{25}$$

$$I\text{\textdegree}MR^{-}=-0.93V\tag{26}$$

$$\left( \left( W/L \right)\_3 = \frac{I\_5}{k\_P \left( V\_{dd} + I \text{CMR}^+ - |V\_{T3}| \left( \max \right) + V\_{T1} \left( \min \right) \right)^2} \tag{27}$$

$$ICMR^{+} = 1.69V \tag{28}$$

6. Output resistance.

$$R\_{\rm out} = \frac{1}{\mathcal{g}\_{ds6} + \mathcal{g}\_{ds7}} = \frac{1}{I\_6(\lambda\_N + \lambda\_P)} = \frac{1}{92.14\mu(0.04 + 0.05)} = 120.5 \text{ K}\Omega \tag{29}$$

Afterward, the circuit schematic and layout are developed in Electric VLSI to perform simulations tests. The compensation capacitor is designed as a poly-poly2 capacitor. The area for the capacitor is 78 by 78 lambda, with a 47 fF parasitic capacitance. Figure 24 shows the Excel first cut approximation used for the first part of the conceptual design.


**Figure 24.** Excel methodology for the first part two-stage OTA conceptual design, before connecting the third stage to achieve higher gain and robust conceptual design.

The Excel design spreadsheet shown in Figure 24 replicates the strategy which has been proposed in this article. The CMOS technology characteristics and specifications flow horizontally to the right and the CMOS design equations, from (5) to (10), Tables 1 and 2, flow downwards illustrating the step-by-by step procedure. Figures 25 and 26 illustrate the schematic and layout diagrams for the three-stage amplifier designed using the methodology shown and initiating with the conceptual design equations coming from the long channel model.

**Figure 25.** Schematic diagram from Electric\_VLSI for the three-stage low-power high-gain operational amplifier.

**Figure 26.** Layout diagram from Electric\_VLSI for the three-stage low-power high-gain operational amplifier.

The output simulation runs show results that comply with the major specifications required by the design. Figure 27 illustrates the layout frequency sweep where the dB gain, gain bandwidth, and the phase margin are displayed. The DC gain obtained is 91.7 dB, the gain bandwidth GB is 46 MH and the phase margin is now close to 94◦, which makes a very robust device.

**Figure 27.** Frequency sweep using. AC analysis in SPICE for the three-stage low-power high-gain op-amp Layout.

Figure 28 shows the time domain simulation to verify the slew rate response. The graph shows *SR*<sup>+</sup> = 21.47 V/μs and *SR*− = −19.35 V/μs which is much more than the required response.

**Figure 28.** Time domain response using transient analysis in SPICE for the three-stage low-power high-gain op-amp layout.

To summarize the complete results for all the theoretical and expected parameters, Table 12 compares:


**Table 12.** Comparison of specification, theoretical, schematic and layout results for the three-stage, low-power high-gain operational amplifier conceptual design.


(\*) no anticipated calculations were made for those parameters.

The results compare well to the specified requirements except for the maximum positive swing of the output signal which does not reach the specified value of 1.4 V. Furthermore, the power dissipation is slightly higher than anticipated by the theoretical calculations of 0.403 mW. However, very good results are obtained in gain bandwidth (GB), CMRR, PSRR, phase margin PM, and noise. The requirements for slew rate (SR) and DC gain (*Av*0) are barely achieved. Some of those specifications could have been obtained with additional calibration and refinements in the final conceptual design.

The student team [34] decided to compare the conceptual design of this low-power operational amplifier with one that appears in the literature with similar characteristics and is used in similar biomedical applications [35]. Table 13 shows this comparison where the supply voltage and the power consumption appear higher in our design. The load capacitance was a specification given by the instructor. Slew rate and bandwidth show a significantly higher performance in our design; however, those were parameters also required by the instructor. The chip area is twice in our design, however, in this case, the instructor did not have any restrictions here and no optimization was performed to reduce the layout artwork whatsoever. Table 13 results, however, illustrate comparisons under different specifications such as the load capacitance and voltage supply. Reference [35] used *CL* = 30 pF and ±1.65 V, whereas our example used *CL* = 2 pF and ±1.8 V, respectively. Some of those conditions were imposed by the course instructor. These changes produced large differences in closed-loop bandwidth and slew rate (SR) as seen by Table 11 results. Furthermore, the power dissipation and chip area obtained here are twice the values obtained by reference [35]. Another way to reduce the power dissipation and voltage supply could have been if they have designed the amplifier to operate in the subthreshold zone. However, the model equations in the Excel method would need to be changed to include the subthreshold model whatsoever. This comparison is an excellent way to encourage confidence in students about the design of integrated circuits at the nanoscale level [36].

**Table 13.** Comparison of the three-stage op-amp conceptual design with <sup>L</sup>ópes-Martin´s design [35] which appears in the technical literature using CMOS 500 nm technology.


A system simulation test was performed by students with an instrumentation amplifier working with a gain of 60 dB or 1000 *v/v* using the traditional three op-amp topology. Figure 29 shows the Icon-View of the simulation experiment having three op-amps (3S\_OA) and the required resistors to provide the gain factor and the bias of the device. The figure shows on the left-hand side the SPICE code to run the frequency domain test (.ac dec 100 0.1 1 G). Furthermore, the MOSFET models command < include C5\_models.txt> describes the 500 nm technology used in this case.

The frequency-domain tests show a DC gain very close to the required for this instrumentation amplifier. Figure 30 shows the output voltage graph with a measured gain of 59.7 dB, approximately 966 V/V, which shows less than 5 % error with respect to the required 1000 V/V gain. This gain goes along to up to 10 KH in bandwidth.

Finally, a time-domain system test for the instrumentation amplifier was developed to find the maximum output symmetrical swing for the device when amplifying the biomedical sensor signal. This transient test was performed with a 1.8 mV amplitude at 1000 H differential mode signal (V2-V1) at the input. Figure 31 shows the output signal with a+1.7323 V to −1.735 V swing which also shows the gain of 966 *v/v* for the instrumentation amplifier configuration.

**Figure 29.** Instrumentation amplifier system simulation test using icon-view with Electric\_VLSI.

**Figure 30.** SPICE AC frequency domain test for the instrumentation amplifier.

**Figure 31.** Time domain test for the instrumentation amplifier, where the maximum rail to rail swing is shown.

The designed operational amplifier and the instrumentational amplifier have good features for biomedical portable sensor conditioning applications. ECG and EEG biopotentials can be processed, and a good front device can be implemented using the conceptual design generated using these methods. The design of micro-power-operational amplifiers to fulfill biomedical instrumentation characteristics has become a huge ye<sup>t</sup> complicated research task with grea<sup>t</sup> opportunity areas for improvement and innovation. The design proposed by the students offers further improvement opportunities (like reducing output resistance) ye<sup>t</sup> possesses interesting features that would hopefully serve for its application in sensor signal conditioning in biomedical instrumentation.

Another application of the low power operational amplifier is to perform signal conditioning in signals coming from CMOS-MEMS sensors [39–42] where the CMOS amplifiers are used as the standard electronic system maneuvering platform. For instance, in [42] the low power operational amplifier is used as a high input impedance instrumentation amplifier to condition signals coming from a micro-hotplate in either Pirani, Temperature, or Gas CMOS-compatible MEMS sensors. Three operational amplifiers, designed in this paper, are set up as instrumentation amplifiers like the one shown in Figure 29. This configuration is ideal for this multifunctional sensor platform application, particularly for the results obtained by the temperature sensor as shown in Figure 32. Figure 33 shows the new instrumentation amplifier configuration used to condition the signal coming from the multiplatform temperature sensor [42] to obtain the results shown in Table 14. Figure 34 illustrates the linear conditioning performed by the instrumentation amplifier designed using the low power OTA developed by the students.

**Figure 32.** Output voltage for a CMOS MEMS temperature sensor with suspended gap from reference [42].



**Figure 33.** Instrumentation amplifier to condition the output from the temperature sensor described by the multiplatform of reference [42].

**Figure 34.** The linear signal conditioning performed by the instrumentation amplifier on signals coming from the CMOS-MEMS Temp Sensor Multiplatform [42].

The results obtained in this CMOS-MEMS sensor application confirm the possibility of using the EXCEL methods to perform first cut front end device design and testing. In

teaching microelectronics, sometimes the use of high-performance software tools deviates attention toward the final objective and competence development for electronics engineers. The analysis of results from the previous two examples shows that the use of EXCEL methods provides a fertile background to start conceptual design processes without requiring complex or expensive software which is not readily available in many universities around the globe. Finally, to account for parasitic capacitances and temperature effects over the operating point of the amplifiers, Appendix A provides additional equations that can be added to the Excel method to find those fluctuations when using Spice simulations of the device. Appendix A.1 shows the parasitic capacitance modeling and Appendix A.2 illustrates the temperature model of this technology.
