**3. Circuit Implementation**

Figures 2 and 3 show the schematic diagram and detailed timing diagram of the proposed pixel-level ADC, respectively. Since a microbolometer has a high bias current compared to its signal current, bias-current suppression is used [6]. Using the accurate bias-current suppression, the integration time can be increased to improve the SNR and the resolution required for A/D conversion can be reduced. Additionally, fixed-pattern noise (FPN), which is produced by the non-uniform IRFPA response, can be lowered to reduce the burden on non-uniformity correction [6,18]. The responsivity of the microbolometer is highly dependent on the bias voltage *VB*, hence, maintaining a stable bias voltage is crucial in microbolometer applications [19]. Therefore, a capacitive transimpedance amplifier (CTIA) is used for current integration even though it has a high-power consumption.

**Figure 2.** Schematic diagram of the proposed ADC: (**a**) overall unit cell circuit; (**b**) one-bit latch used in unit cell circuit.

**Figure 3.** Timing diagram of the proposed ADC shown in Figure 2.

First, the current input *ISIG* is integrated with the integrator and the value of *V*(*CINT*) is compared with the value of *VTH* using the comparator. Here, *φSW* and *φRST* are control signals for determining the integration time and reset control signals for the integrator, respectively. The *CCDS* is the capacitor required for correlated double sampling (CDS) operation [20], reducing FPN and low-frequency noise and compensating for the offset voltage of the comparator and integrator. To completely eliminate all FPNs and non-uniformities in IRFPA and ROIC, an additional calibration process is required. The comparison result is transferred and stored in a one-bit latch according to the *φEN\_C* signal. The result of the comparison is a logic 0', the output of the one-bit latch *Lout* is a logic 0', and the constant charge is removed from the integrator to the DAC according to the control signals of *φ*1 and *φ*2. The one-bit latch is then reset according to the *φL\_RST* signal for the next comparison cycle. The inversion signal of *Lout* is used as a clock signal of a six-bit counter, through which the digital value of the upper six bits for the current input is determined. *φC\_RST* is used for the reset control signal of the six-bit counter.

After completing the integration and A/D conversion of the upper six bits, the *V*(*CINT*) value is held by using *φSW*, and the digital values stored in the counter are sequentially transferred to the column multiplexer outside the array. A/D conversion of the lower six bits is implemented as a single-slope A/D conversion method for the residual *V*(*CINT*). First, the six-bit counter is reset using the *φC\_RST*, and the *VTH* value changes from *VRST* to 0.5( *VRST* + *VSAT*) in the form of a ramp signal. When the value of *VTH* is less than the value of *V*(*CINT*), the input of one-bit latch is logic 1', and the *Lout* changes periodically by *φEN\_C* and *φL\_RST*. Therefore, the digital value of the six-bit counter increases until the *VTH* exceeds *V*(*CINT*), and the final digital data stored in the counter is the lower six-bit digital data for the current input. Finally, the six-bit digital data is sequentially transferred once again to the column multiplexer outside the array.

Figure 4 shows a one-bit counter used in the unit cell circuit in Figure 2. It is a simple structure using three logic inverters, and it can be easily applied to the pixel-level ADC. *XIN* and *XOUT* are clock and output, respectively, and *XOUT* turns into the logic value of *vy* when *XIN* changes from logic 1' to 0'. Due to the delay time between *XIN* and *XOUT* signals, *vy* is not affected by changes in *XOUT* signal at this moment. Subsequently, when *XIN* changes from logic 0' to 1', *vy* changes to the inversion of *XOUT*. The final six-bit counter is configured as an asynchronous ripple counter using six one-bit counters in Figure 4.

**Figure 4.** One-bit counter used in the unit cell circuit of Figure 2: (**a**) schematic diagram; (**b**) timing diagram.

Figure 5 shows the overall arrangemen<sup>t</sup> of the proposed ROIC. The unit circuit in Figure 2 has a simple configuration. However, it is difficult to implement the proposed unit circuit in one pixel of 40 μm × 40 μm. Thus, as shown in Figure 5, four adjacent (2 × 2 array) bolometers share one unit circuit in Figure 2 in a time-dividing manner. The size of the bolometer array is 640 × 512, and the unit circuit has an array of 320 × 256. The temperature sensor detects the substrate temperature, and the dark sensor obtains the

reference value of the bias current. The suppression circuit and 12-bit ADC/DAC blocks are used to control the bias current of the bolometer array [6]. Timing circuit, row scan, and ramp signal generator are required to control the unit circuit, and column multiplexer is required to transfer digital data outside.

**Figure 5.** Block diagram of the overall arrangemen<sup>t</sup> of the proposed readout integrated circuit (ROIC).
