*3.2. Active Diode*

One of the main challenges on the rectifier circuit is to avoid the reverse leakage current by controlling the operation of transistor M5. Therefore, an active diode controlled with a threshold cancellation circuit can regulate the work behavior of this device depending on the voltage potential between the input and output. The deployed threshold cancellation circuit controls the gate potential of the MOSFET M5 by comparing the input/output voltage conditions. Additionally, the width of M5 has a large influence on the performance of this rectifier because the voltage drop is mainly affected by this parameter due to the internal on-resistance. Consequently, since the gate capacitance of M5 depends on the width, the turn on/off time of the transistor will also be affected by this parameter. In addition, the DSB technique, composed of M6 and M8, is deployed to reduce the leakage current through the bulk terminal of M5 by connecting it to the higher potential (*Vnvc* or *Vrec*). Another advantage of this technique is eliminating the body effect of M5, which reduces the rectifier voltage drop. Both M6 and M8 can be small in size since only a very low current flows through them during the start-up phase.

To assure a safe start-up of M5, a bypass PMOS diode (M10) was connected in parallel. This transistor makes the active diode more robust by preventing it from leakage current in the subtraction that induces latch-up. After the start-up phase, the bypass diode always operates in the cut-off region.

#### *3.3. Threshold Cancellation Circuit*

In order to reduce the threshold voltage effect on M5, a bootstrap technique is used by attaching the capacitor *C*1 to the output terminal. When the *VNVC* is higher than the output voltage *Vrec*, M5 is turned ON, since *VSG*5 is no longer lower than *VTH*5, and thus it can be defined in (1). Nevertheless, because M5 is operating in the deep-triode region due to *VSD*5 <sup>2</sup>·(*VSG*<sup>5</sup> − |*VTH*5|), *VSG*5 can also be defined according to the on-resistance equation, see (2).

$$V\_{\rm SG5} = V\_{\rm NVC} - V\_{\rm CAP} \tag{1}$$

$$V\_{SG5} = \frac{1}{\mu\_p \cdot \mathbb{C}\_{ox} \cdot \mathcal{W}\_5 / L\_5 \cdot \mathbb{R}\_{SD5}} + |V\_{TH5}| \tag{2}$$

Here, *μp* is the carrier mobility, *Cox* is the oxide capacitance, *W*5/*L*5 is the aspect ratio of transistor M5, and *VTH*5 is its respective threshold voltage.

The bootstrapping capacitor (*C*1) is charged up through an auxiliary diode-connected PMOS transistor M7, and it maintains a value when the rectifier is under the steady-state regime. At this time, because *C*1 is discharging, *VCAP* is one diode forward-bias voltage (*VTH*7) bellow *Vrec* due to M7 is being in the saturation region. Thus, the voltage held on the bootstrapping capacitor can be defined as:

$$V\_{CAP} = V\_{rc} - \left| V\_{TH7} \right| \tag{3}$$

*VSG*5 and *VCAP* from (2) and (3), respectively, can be replaced in (1), which means that *Vrec* can now be defined according to the following equation:

$$V\_{\rm rec} = V\_{\rm NVC} - \left( |V\_{TH5}| - |V\_{TH7}| \right) - \frac{1}{\mu\_P \cdot \mathbb{C}\_{ox} \cdot W\_5 / L\_5 \cdot R\_{SD5}} \tag{4}$$

According to (4), the rectified signal is highly influenced by the size of M5 and the threshold voltage of both M5 and M7, and thus it is vital to manage these parameters to enhance the output signal voltage. The implemented threshold cancellation circuit reduces the voltage drop of the main pass transistor M5 by lowering the threshold voltage effect. Additionally, the size of the bootstrap capacitor is an important design concern for the implementation of the proposed rectifier. Integrated capacitors consume a large area on the chip when standard CMOS processes are used [24]. Therefore, *C*1 was set at 200 fF not only to reduce the correspondent area on the die but also to have a faster charging/discharging time. Consequently, this low bootstrap capacitance allows a lower gate voltage of M5 at the ON state. Due to the reduction of its internal source to drain resistance, the voltage drop is decreased. The reverse leakage current during the OFF state will be avoided because *VSG*5 is reduced. Moreover, it is necessary to have an auxiliary circuit to hold the *VCAP* node when M5 is OFF, and to discharge it at the opposite state.

The bootstrapping capacitor is used to reduce the threshold voltage effect of M5. However, an increase in its on-resistance can be noticed due to the reduction of *VSG*5. Thus, a conduction path needs to be generated to discharge the gate of M5 during the ON state, which will lead to a further increase of *VSG*5. The proposed AVC is composed of NMOS M9 and a comparator CMP that drives its gate. When *VNVC* is higher than the output voltage *Vrec*, the comparator CMP should immediately turn on M9 to provide a discharge path of the *VCAP* node. Consequently, it will turn on the main pass transistor M5 with a low on-resistance. Because the large size of M5 increases the gate capacitance, the AVC must have a faster bias signal control to switch the discharge path of the gate node ( *VCAP*). Thus, the comparator must be designed to attend to these demands.

Figure 2 shows the proposed two-input common gate comparator. This comparator is composed of a current mirror stage to make the comparison, plus an inverter block to bias the gate of M9. Even if the transistor of the current mirror should be as small as possible to reduce the current consumption of the comparator, the size of M12 and M15 must be carefully chosen to manage the delay, and consequently, the reverse leakage current in M5. These two transistors cannot have the same W/L ratio as M11 and M14. Otherwise, this would generate a delay caused by the inverter's gate capacitance's low charging/discharging time. Additionally, they cannot be much larger than the other transistors because of the reduced time that M5 would be ON, which would lead to a PCE reduction. Therefore, M12 and M15 only need to be slightly higher to provide the required charging/discharging time to reduce the delay of the overall comparator. Table 1 summarizes the dimension values of the proposed rectifier circuit.

**Figure 2.** Schematic of the two-input common gate comparator CMP.

**Table 1.** Circuit transistor sizes.


#### **4. Results and Discussion**

The simulation experiments were carried out using Cadence Virtuoso Analog Design Environment with a 130 nm CMOS process. The respective physical layout of the CMOS rectifier is presented in Figure 3. To replicate the output behavior of the energy harvester, the default input sinusoidal voltage amplitude and frequency used in the simulations were 600 mV and 3.2 kHz, respectively. Throughout most of the tests, *CLOAD* and *RLOAD*

were set at 2 μF and 5.5 kΩ to simulate the capacitance of the storing capacitor and the impedance of the electronics to be powered, respectively.

**Figure 3.** Physical layout of the proposed CMOS rectifier.
