**1. Introduction**

Infrared cameras, which detect objects by infrared rays in a situation where they cannot be observed by human eyes, are widely used in military, medical, and commercial fields. In recent years, there has been an increase in the demand for compact and power efficient portable infrared cameras, especially in the private sector for medical devices and security cameras. Therefore, significant research has been conducted on microbolometers, which are uncooled-infrared detectors that do not require a cryogenic cooling system [1–4].

While designing a readout integrated circuit (ROIC) for infrared focal plane array (IRFPA), noise performance is of crucial concern. The dominant noise sources in a microbolometer are the Johnson noise and 1/f noise, which can be decreased by increasing the integration time [5]. Therefore, it is necessary to use a pixel-level readout architecture with a large integration capacitor to obtain a long integration time. However, a microbolometer has a high bias current compared to its signal current. Hence, it is hard to locate a large integration capacitor in the pixel because of area limitation. To effectively overcome this problem, a bias-current skimming technique can be used [6]. In addition to noise performance, the dynamic range (DR), which is defined as the ratio of the maximum allowable signal to the minimum detectable signal, is also an important factor. In many applications, either the frame rate is very slow or the target temperature varies over a wide range. Hence, it is necessary to consider both the noise performance and the charge handling capacity of the ROIC.

A monolithic analog-to-digital converter (ADC) is essential for compact and powerefficient portable infrared cameras. Information can be transported with a high signalto-noise ratio (SNR) in a more power efficient manner in the digital domain using a monolithic ADC, and on-chip signal processing for system-on-chip (SoC) can be made available. Monolithic ADCs can be implemented at the chip level by employing a single high-speed ADC [7], at the column level by using multiple lower speed ADCs [8,9] or at the pixel level by using very low speed ADCs [10–14]. A pixel-level ADC has many advantages

**Citation:** Lee, J.; Nam, I.; Woo, D. Current Input Pixel-Level ADC with High SNR and Wide Dynamic Range for a Microbolometer. *Sensors* **2021**, *21*, 2354. https://doi.org/10.3390/ s21072354

Academic Editor: Roman Sotner

Received: 17 February 2021 Accepted: 24 March 2021 Published: 28 March 2021

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**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

over chip and column level ADCs. These include low noise, low power dissipation, and the ability to continuously observe the pixel outputs for long time [14,15].

Although the pixel-level ADC has many advantages, conventional ADC architectures are not easily implemented in IRFPAs because a low-power, high-resolution ADC with small size is required. Since a single-slope ADC (SS-ADC) has a very simple structure, a pixel-level ADC can be easily implemented using this method [10]. However, since analogto-digital (A/D) conversion is performed after integration, SNR and DR cannot be improved. In addition, a large number of comparisons are required to implement a highresolution SS-ADC, which significantly increases power consumption.

Another method to implement a pixel-level ADC is based on the time-to-digital (TTD) ADC, also known as the time-to-first spike ADC [11]. While integrating the input current, it detects the time at which the integral signal reaches the reference voltage. Properly modifying the reference voltage can improve the DR characteristics. However, since the integration time varies depending on the input current, it is difficult to obtain a good SNR or a suitable digital resolution for a large input current.

Studies have been conducted that implement pixel-level ADC using pulse frequency modulation (PFM) method [12,13]. While integrating the input current, the integral signal is reset when the integral signal reaches the reference voltage, and A/D conversion is performed using the reset number. Since sufficient integration time and charge handling capacity can be obtained, SNR and DR characteristics can be improved. However, the PFM-based implementation requires many reset pulses to obtain a high-resolution ADC. Therefore, it has high power consumption and is disadvantageous for fast operation. To overcome these problems, the two-stage method can be a good solution [16]. However, since accuracy and linearity are affected by the reset interval, A/D conversion performance may be poor depending on the characteristics of the comparator. In addition, it is still difficult to reduce power consumption since the comparator is always on as the asynchronous method is used.

In the proposed readout circuit, current-input pixel-level ADC using a synchronous two-stage A/D conversion is efficiently performed during the integration, and the characteristics of power consumption, SNR, and DR are improved with high resolution.

#### **2. Basic Concepts of the Proposed ADC**

The current input pixel-level ADC proposed in this paper uses a synchronous twostage A/D conversion to reduce power consumption and improve SNR and DR characteristics. The basic concepts of the proposed ADC are explained in the timing diagram shown in Figure 1. First, the current input is integrated and converted into a voltage *V*(*CINT*), and it is compared with the reference voltage ( *VTH*) at regular time intervals. *VRST* and *VSAT* denote the reset voltage and the maximum allowable voltage of *V*(*CINT*), respectively, and *VTH* is equal to 0.5( *VRST* + *VSAT*). If the value of *V*(*CINT*) is greater than the value of *VTH* at the comparison point, the constant voltage of 0.5( *VSAT* – *VRST*) is removed from *V(CINT*). This process is repeated periodically during the integration of the current input. The digital information *DOUT* on the current input *ISIG* is obtained by counting the number of removals and is expressed by

$$D\_{OUT} = \left[\frac{2T\_{INT}I\_{SIG}}{\mathbb{C}\_{INT}(V\_{SAT} - V\_{RST})}\right] \tag{1}$$

where *TINT* is the integration time, *CINT* the integration capacitor, and the square bracket [] represents the function of digitization. This method is based on first-order incremental ADC [17]. Using this method, A/D conversion is efficiently performed during integration and a sufficient integration time and large charge-handling capacity is obtained. The maximum charge-handling capacity *Q M* is expressed by

$$Q\_M = 2^{M-1} \mathcal{C}\_{INT} (V\_{SAT} - V\_{RST}) \tag{2}$$

where *M* is the resolution of the A/D conversion. Since a synchronized method is used where comparing *V*(*CINT*) and *VTH*, power consumption of the comparator is minimized.

**Figure 1.** Basic concepts of the proposed pixel-level analog-to-digital converter (ADC).

In a typical application for medium wavelength infrared (MWIR) microbolometer, even if the current input is integrated after removing the bias current, the ADC of the readout circuit must have a resolution of 12-bit or more [12,14]. To implement a 12-bit resolution using only the first-order incremental ADC, 2<sup>12</sup> comparison cycles are required, which is a grea<sup>t</sup> burden in terms of speed and power consumption. To solve these problems, a two-stage A/D conversion is used as shown in Figure 1. In the first period, A/D conversion for the upper six-bit is performed during the integration as described above. After the integration, the residual voltage of *V*(*CINT*) is held and the lower six-bit is determined by additional single-slope A/D conversion. In this case, since the number of the comparison cycles for implementing a 12-bit ADC is reduced to 27 (2<sup>6</sup> + 26) times, a compact and low-power design is possible, which can be easily implemented as a pixel-level ADC. The circuits for the upper and lower six-bit A/D conversion are shared by dividing the time, so that the conversion result for the upper six-bit should be read out of the array before the lower six-bit conversion.
