**3. Design Implementation**

Regarding the inherent output characteristics of the piezoelectric transducer, the proposed CMOS rectifier was mainly designed to achieve a high PCE for wide low input voltage and frequency conditions. Therefore, the operational voltage ranges from 0.4 V to 1 V, and the working frequency varies from hundreds of Hz to a few kHz. In addition, the output impedance of the energy harvester is not considered in this design because the matching impedance process is performed before this rectification stage in the PMC. Thus, the main goal of this work is to reduce the voltage drop across the structure by applying a threshold cancellation technique that will further enhance the power converted to the ohmic load. These improvements will overcome the drawbacks of previous work by mitigating the reverse leakage current, and thus enhancing the PCE for a low input voltage range.

Figure 1 shows the simplified schematic of the proposed active rectifier. It consists of an NVC and an active diode biased by a threshold cancellation circuit. The first stage is set to perform the signal full-wave rectification. However, because this passive stage cannot control the reverse current from the load capacitor when the output voltage is higher than the input, a second stage active diode (M5) is needed. This active stage is composed of a PMOS controlled by a threshold cancellation circuit with a bootstrapping capacitor to reduce the effective threshold of the active diode, and an adaptive voltage controller (AVC) to adjust the gate voltage of M5 by controlling the charging/discharging cycle of the bootstrapping capacitor. To perform it, a two-input common gate comparator and an NMOS transistor are used. Besides these stages, a dynamic switching bulk (DSB) technique was used to control the bulk voltage of the active diode PMOS.

**Figure 1.** Schematic of the proposed active rectifier composed by a NVC and an active diode controlled by a threshold cancellation circuit.

#### *3.1. Negative Voltage Converter*

The first stage is fully passive, and it is used to perform the signal full-wave rectification by applying a fully-cross coupled configuration. During the positive half period of the input signal (*Vin*+ > *Vin*−), M1 and M3 will be conductive as soon as the input voltage gets larger than *VTHn* and *VTHp*. In this cycle, node 1 is connected to *Vin*+ and node 2 to *Vin*−. For the negative period of the sine wave, M2 and M4 are conducting while the previous two transistors are now turned off (cut-off region). Therefore, the higher voltage potential is always at *Vnvc*, whereas the lowest potential is at 0 V. The voltage drop of the NVC is given by *VDSn* + *VSDp* in each conduction path, where *VDSn* and *VSDp* are the voltage drop of NMOS transistors M2 or M3 and PMOS transistors M1 or M4, respectively.

To meet all the power restrictions related to the piezoelectric energy harvesting systems, the rectifier circuit must minimize the voltage drop across the rectification process. As less voltage drop occurs, both the VCE and the PCE of the circuit will be higher. For this stage, NVC, the main requirement is to decrease the voltage drop associated with each MOSFET by reducing their on-resistance.
