**4. Experimental Results**

The readout circuit was designed using a 0.35 μm 2-poly 4-metal CMOS process for a 640 × 512 MWIR a-Si microbolometer array with a pixel size of 40 μm × 40 μm. The design parameters of the microbolometer and readout circuit are summarized in Table 1. The fabricated unit cell circuit is 80 × 80 μm<sup>2</sup> in size because the proposed unit circuit is shared by 2 × 2 pixels. Uncooled microbolometers are difficult to operate at speeds above 60Hz. Therefore, the frame rate of IRFPA is set to 60 Hz and the sampling rate of the proposed pixel-level ADC is 240 Hz. It was tested at room temperature using the operation board shown in Figure 6.

**Table 1.** Design parameters of the microbolometer and readout circuit.


**Figure 6.** Measurement system: (**a**) operation board and fabricated chip; (**b**) mask layout of the proposed unit cell circuit for 2 × 2 bolometer array.

Figure 7 shows the operating waveforms of the proposed pixel-level ADC. The current input is integrated and converted to MSBs in the first period. Subsequently, the residual *V*(*CINT*) is held and converted to LSBs. MSBs and LSBs are estimated by counting the number of *LOUT*. Figure 7 b shows the operating waveforms of the counter output (*Q*3*Q*2*Q*1*Q*0). Only four bits are displayed among six-bit outputs, and *Q*0 represents the least significant bit. As shown in Figure 7, the range of the available current input that does not saturate during integration time is drastically improved by the current input pixel-level ADC.

**Figure 7.** Measured operating waveforms of the proposed pixel-level ADC: (**a**) current integration and A/D conversion; (**b**) counter output.

Figure 8a shows the measurement results of differential non-linearity (DNL). Figure 8b shows the integral non-linearity (INL) estimated by Figure 8a. The DNL is within about ±0.4 LSB, and the INL is within about ± 2.0 LSB. These results confirm the monotonicity of the proposed pixel-level ADC.

**Figure 8.** Measurement results of the linearity of the proposed pixel-level ADC: (**a**) differential non-linearity (DNL); (**b**) integral non-linearity (INL).

SNR and DR characteristics are important figures of merit for IRFPA applications. To estimate the SNR and DR characteristics, the readout circuit noise, i.e., the ADC noise, should be measured. First, the digital output of the ADC for a zero current input was sampled 2000 times, then the readout noise for a zero current input was estimated as the standard deviation *σ* of the sampled output. Through this process, it was confirmed that the readout noise for a zero-current input *σ*0 is close to 0 LSB. However, this method alone cannot evaluate the effect of kTC noise of the DAC on the readout noise. In order to evaluate the readout noise caused by the DAC, there must be a current input. In this case, the readout noise itself can be evaluated by eliminating the noise caused by the current input. The ADC output was sampled several times for two different current inputs, and the histograms were obtained as shown in Figure 9. Figure 9a,b are histograms obtained using a total of 2000 samples, where the number of MSBs counting is 1 and 63, respectively. Using the data in Figure 9, the noise of the current input system *σI* can be removed, and the noise equivalent to one MSB counting *σM* can be predicted as shown in following equation:

$$
\sigma\_a^2 = \sigma\_0^2 + \sigma\_I^2 + \sigma\_M^2 \tag{3}
$$

$$
\sigma\_b^2 = \sigma\_0^2 + \sigma\_I^2 + 63\sigma\_M^2 \tag{4}
$$

$$
\sigma\_M = \sqrt{\left(\sigma\_b^2 - \sigma\_d^2\right) / 62} \quad = 0.0438 \text{ [LSB]} \tag{5}
$$

where *σa* and *σb* are the *σ* of Figure 9a,b, respectively. After predicting the *σM* value from the histograms of Figure 9, the readout noise according to the current input can be evaluated and applied to the final SNR characteristic of Figure 10.

Figure 10 shows the SNR characteristics according to the current input, and the total noise is estimated from the bolometer noise, quantization noise, and the readout noise. The legend A of Figure 10 indicates the graph of the proposed pixel-level ADC with a *TINT* of 3.1 ms and a maximum *ISIG* of 20.4 nA. Legends B and C indicate the case of applying the conventional 12-bit SS-ADC after the integration time. In the case of B and C, since the charge handling capacity is limited due to the pixel area limitation, it is necessary to reduce the integration time to 98 μs for a wide current input (B) or reduce the input range to 3.0 nA for a long integration time (C). Design parameters except for *TINT* and maximum *ISIG* are the same as in Table 1 for A, B, and C. Since the charge handling capacity of the proposed ADC is appropriately extended, the integration time is maximized for a wide input range. Therefore, the proposed ADC has good SNR characteristics for a wide input range as shown in Figure 10.

**Figure 9.** Histograms of the digital output of the proposed ADC with a fixed input: (**a**) where the number of MSBs counting is 1; (**b**) where the number of MSBs counting is 63.

**Figure 10.** SNR characteristics for the three cases: (**A**) the proposed pixel-level ADC; (**B**) 12-bit SS-ADC with reduced integration time; and (**C**) 12-bit SS-ADC with reduced input range.

Table 2 shows the performance comparison between the proposed ADC and other methods. The design of the readout circuit for IRFPA is greatly dependent on the IR detector. Therefore, in the case of A, A, B, and C, the main design parameters are the same for reliable comparison. A' indicates the case of applying the proposed ADC without bias-current suppression. Since the maximum value of the bias current is about 60 nA, if the bias current is not suppressed, the integration time decreases and both charge handling capacity and SNR decrease. Without bias-current suppression, the effective signal range decreases and the burden required for non-uniformity correction is increased [12,14]. Therefore, the resolution of the ADC must be increased in the actual design. Although it is difficult to make a clear comparison, the results presented in other papers are compared Table 2. Reference [10] uses the SS-ADC for pixel-level ADC and shows very low chargehandling capacity like B and C. Since the readout circuit of the reference [10] is for a cooled type MWIR detector, the bias current is small and the readout noise is very low. In addition, since the SNR value of A includes the noise of the detector, it is difficult to clearly compare the SNR values of A and [10]. The reference [11] uses the TTD method for pixel-level ADC, and the proposed ADC shows superior SNR characteristics. Since the readout circuit of the reference [11] is for a short wavelength infrared (SWIR) detector, an additional method is used to increase the charge handling capacity to an extreme. It can be seen from the

Table 2 that the proposed ADC shows excellent and balanced characteristics in both charge handling capacity and SNR.


**Table 2.** Performance comparison.

Figure 11 is a comparison of the results of the power consumption for the three cases, simulated using the same MOS library. The three cases are designed based on the same microbolometer shown in Table 1, and the bias-current suppression method is applied to all three circuits. Legend A indicates the power consumption of the proposed ADC, and D indicates the case of applying a PFM-based method to the A/D conversion for the upper six bits. Legend E indicates a case where the entire A/D conversion is implemented with only first-order incremental ADC. Considering the characteristics of the comparator and the maximum integration time, only 10-bit conversion is applied instead of 12 bits in the case of legend E. Since the comparator is always on as the asynchronous method is used in the case of D, it is still difficult to reduce power consumption. The 1st-order incremental ADC requires many comparison cycles to obtain a high-resolution ADC. Therefore, it has high power consumption. The proposed ADC can expect the lowest power consumption among the three methods as shown in Figure 11.

**Figure 11.** Power consumption for the three cases: (**A**) the proposed pixel-level ADC; (**D**) pulse frequency modulation (PFM)-based two-stage analog-to-digital (A/D) conversion; (**E**) 1st-order incremental ADC.
