**1. Introduction**

Currently, we have high-capacity technology of analog and digital electronic devices due to the micro-components that are increasingly becoming smaller in scale. In fact, in 1965, Gordon E. Moore predicted (Moore's law) that every 2 years the number of transistors in a microprocessor would double. This law worked for the first 10 years [1]; then it became a joke between engineers who said that "now people predict that the end of Moore's law doubles every 2 years." Since then, transistor integration has been observed as illustrated in Figure 1, where Moore's law was in force for a long time. However, the limits towards a scale in nanotechnology have shown that although Moore's law no longer applies, significant efforts are still being made to continue reducing the size of the micro and nano components. For example, recently design and process in semiconductors have been done with the development of the world's first chip with 2 nanometers (nm) nanosheet technology [2].

 Dieck-Assad, G.; Rodríguez-Delgado, J.M.; González Peña, O.I. Excel Methods to Design and Validate in Microelectronics (Complementary Metal–Oxide– Semiconductor, CMOS) for Biomedical Instrumentation Application. *Sensors* **2021**, *21*, 7486. https://doi.org/10.3390/s21227486

**Citation:**

Academic Editors: Jong-Ryul Yang and Seong-Tae Han

Received: 25 September 2021 Accepted: 30 October 2021 Published: 11 November 2021

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**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

**Figure 1.** Behavior of the technological development for the small-scale design of transistors on microchips doubling every two years (Moore's law) [1].

Therefore, with this context in which the microchip technology is reducing in size over time, college students with different science and engineering majors need to understand the "know-how" of designing circuits that integrate microchips. Unfortunately, often this knowledge is taught with specialized complex (and expensive) software, which is sometimes not readily available in many universities around the world.

Analog and digital integrated circuit design has emphasized a good understanding of analog and digital electronic circuits to model, simplify, analyze, and simulate microelectronic devices before developing layouts and sending devices to IC fabrication foundry consortiums. Design engineers find SPICE simulations useful to validate "thinking models" [3,4] to verify cause–effect relationships and to ensure that assumptions made are appropriate in the design process. Microelectronics courses and specialized workshops (and webinars) teach conceptual design where the following concepts are emphasized.


IC design is important in device development for microelectronics engineering innovation and is embedded into the design flow which may have continuous iterations to optimize designs by decision refinements. In the process of CMOS microelectronics conceptual design [5–7], the electrical device specification requires active and passive models for creating, verifying, and determining the robustness of the design. This process involves the selection of a conceptual circuit, the analysis of the selected circuit, the possibility of a modification to the circuit, and the verification of the circuit solution. The physical electronics design process [8–10] consists of representing the electrical device in a 2D layout consisting of many different geometrical rectangles at various levels (layers). This layout is then used to implement a 3D integrated circuit during the fabrication process. The device conceptual model follows a process to obtain a layout. This process includes [3,4]:


This process is depicted in the flow diagram shown below in Figure 2.

**Figure 2.** Block diagram showing the design procedure to reach the Layout conceptual model.

Once the first approach to design is terminated, the process continues with design testing which consists of coordinating, planning, and implementing the measurement of the integrated circuit performance. The objective is to compare the experimental performance with the specifications and/or simulation results. Several tests are available, e.g., functional: verification of the nominal specifications; parametric: verification of the characteristics to within a specified tolerance, verification of the static (AC and DC) characteristics of the circuit or system, and verification of the dynamic (transient) characteristics of a circuit or system. Additional testing could include device testing performed at the wafer level or package level and detailed testing that removes the influence of measurement system in the device performance.

The conceptual design of analog integrated circuits in new devices is now shaped by rules such as: consumers generate a need for new integrated circuits, design engineers have an open possibility of participating in designs, time to develop a product is reduced, profit in products and prototypes are not readily necessary, and the new concept of "crowd designing" [3] plays an important role in device development. This article discusses Excel methods to perform "paper and pencil" calculations ("thinking model") in the conceptual design of CMOS analog integrated circuits which are validated using ELECTRIC-LTSpice to

provide the initial characteristics of the device. Several methodologies have been developed for CMOS device design and testing but most of them are very specific to the final prototype or experimental application [11–17]. The Excel methods analyzed in this study focus on providing didactic instruction in microelectronics for undergraduate and graduate students. Therefore, it seeks to focus learning by referring to world trends in conducting open science, providing the social appropriation of knowledge. The forefront is didactic managemen<sup>t</sup> whose central axis is the catalyst of open innovation processes that have proven to be very successful disruptive models in open laboratories, universities, research centers, industry, and governmen<sup>t</sup> for the development of emerging economies and public policies [18–26].

As a result, this study describes a method that uses an Excel spreadsheet to start the conceptual design from the point of view of the "thinking model" or the first cut evaluation of the design with "paper and pencil". In addition, several contributions stand out:

The Excel methods discussed here focus on microelectronics education for undergraduate and graduate students. The article describes a simple method using an Excel spreadsheet to initiate conceptual design from the standpoint of "thinking model" or "paper and pencil" first cut evaluation of the design. Furthermore, several contributions are emphasized:


This manuscript is organized as follows. Section 2 briefly describes device modeling to represent transistors using first principle equations that predict their behavior in different regimes and operating conditions. Section 3 provides the basic MOSFET modeling equations, starting with the threshold voltage calculations, the transconductance equations for the ohmic (sub-saturation), active (saturation), and subthreshold conditions, both for long channel and short channel devices. Section 3 also gives the typical MOSFET parameters for 0.5 mm CMOS technology, the small-signal model parameter equations, and useful resistance and capacitance calculations using the foundry process parameters for the technology. Section 4 describes the Excel methods that students use to develop their first cut approximations in conceptual designs of CMOS devices and before testing schematic simulations and layouts. This section explains three Excel methodologies: single straight, tabular straight, and two-dimensional processing methods to perform the evaluation of the device's conceptual design. This section also discusses resistance, capacitance, and differential amplifier conceptual designs as specific examples to apply the Excel methods. Section 5 discusses the Excel methods applied for complete amplifier design. Here the cascode amplifier and the OTA (Operational Transconductance Amplifier) are used as examples of how students use the basic two-dimensional Excel methodology to solve CMOS microelectronic conceptual design devices. Section 6 illustrates a complete case study, developed by students and wrapped up by their instructor, of a low-power high-gain operational amplifier for biomedical applications. In this section, comparison of the design is performed with respect to a particular device appearing in the technical literature and

an application of a CMOS-MEMS signal conditioning is developed considering the requirement of conditioning a differential mode temperature sensor´s output to obtain a readily available low voltage representation of the temperature of a micro hotplate multisensor platform. Finally, Section 7 wraps up the paper with illustrative conclusions about how these Excel methods have provided extraordinary insights to undergraduate students in their effort to consolidate a good understanding of microelectronics conceptual integrated circuit (IC) design.

#### **2. Materials and Methods—Device Modeling**

The process of device modeling consists of representing the electrical properties of devices using mathematical equations, circuits, graphs, correlations, and energy conservation laws. Models allow predictions and validation of circuit performance with uncertainties coming from no-idealities and non-linear behaviors in electronic components. Typical equations and conservation laws are Ohm´s law, large- and small-signal models of MOS-FET transistors, VTC curves, and I-V curves of diodes. The final goals are to simplify the cause–effect relationships allowing the engineer to understand and consider decisions that increase performance in the circuit.

Analog integrated circuits in microelectronic conceptual design are developed using a non-hierarchical structure where the use of repeated blocks is only possible in few devices, and therefore the design process is complex and challenging. To handle this, design engineers use hierarchy whenever possible, use good organization techniques, efficiently document the design, provide reasonable and reliable assumptions and simplifications, and eventually validate the conceptual designs using simulation experiments. Assumptions and simplifications are used to emphasize the essential characteristics by neglecting the nondominant effects in the design. The challenge of teaching microelectronics is to develop an insight into the design process without requiring specialized professional software which is not readily available in many universities around the world. Figure 3 shows the microelectronics design process, on the left side, with the insight given on the right side, using Excel methods and other simulation techniques which are readily available to universities.

**Figure 3.** The CMOS microelectronics design process and the insight provided by the Excel methods in the quest to teach microelectronics design with simple tools.

Analog integrated circuit design and device evaluation have reached a level of maturity in established applications such as digital to analog and analog to digital conversion systems, front end signal conditioning devices, instrumentation channel devices, bandgap reference sources, DC to DC power conversion drives, and other important microelectronic circuits [3]. Finally, analog circuit conceptual designs have significant applications in devices where speed and power have an overwhelming advantage over digital devices. This paper reviews the long and short channel models for CMOS devices and further application of long channel equations using Excel methods for first cut approximations before computer simulations and layout development. Those approximation models can be found in many CMOS microelectronics specialized textbooks [3,4,7,27–29] and they are summarized here for completeness in this discussion.

#### **3. Results—Transistor Models for Analog Conceptual Design**

#### *3.1. Threshold Voltage Calculation*

The evaluation of threshold voltage, *VT*, is fundamental in the development of CMOS microtechnology because gives the necessary condition for allowing operation of the transistors in the right zone.

$$V\_T = \left[V\_{T0}\right] + \gamma \left(\sqrt{|2\varrho\_F| + V\_{SB}} - \sqrt{|2\varrho\_F|}\right) \tag{1}$$

where *γ* is the body factor, 2*ϕF* is the Fermi potential, *VT*0 is the zero bias threshold voltage, and *VSB* is the potential difference between source and bulk of the device.

#### *3.2. Current Equations for Long Channel Devices*

The drain-source current equations for the MOSFET long channel device are given below for *VGS* ≥ *VT* and *k = μCox(W/L)*:

Saturation zone: *VDS* ≥ *VGS* − *VT*

$$\dot{q}\_D = \frac{k}{2} [V\_{GS} - V\_T]^2 (1 + \lambda V\_{DS}) \tag{2}$$

Ohmic zone: *VDS* ≤ *VGS* − *VT*

$$
\dot{q}\_D = \frac{k}{2} [2(V\_{GS} - V\_T) - V\_{DS}] V\_{DS} \tag{3}
$$

For *VGS* ≤ *VT* the transistor plays in the subthreshold zone with the following exponential behavior, like the bipolar junction transistor:

$$\dot{\mu}\_D = I\_t \frac{\mathcal{W}}{L} \mathcal{e}^{\frac{(V\_{GS} - V\_T)}{nV\_t}} \tag{4}$$

where the nomenclature and parameters of the model are as follows: *iD* is the drain to source current flowing in the MOSFET, *μ* is the charge carrier mobility, *Cox* is the SiO2 oxide capacitance, *(W/L)* is the width/length transistor ratio, *VGS* is the gate to source potential differences, *VDS* is the drain to source potential differences, *λ* is the transistor´s channel modulation parameter, *It* is the subthreshold saturation current (<1 μA), *Vt* is the thermal voltage (~26 mV at 25 ◦C), and n is a subthreshold constant (~1 to 2).

#### *3.3. Velocity Saturation and Effective Mobility in Current Equations of Short Channel Devices*

To consider velocity saturation and effective mobility in short channel MOSFETs adjustments are made in the model equations presented above. This is particularly important in the saturated and ohmic regions of operation. The drain-source current equations for the MOSFET short channel device are given below for *VGS* ≥ *VT*, having saturation velocity *vsat = μe Ec/2*, where *μe* is now the effective mobility of charge carriers and *Ec* is the critical field for which the carrier saturation occurs.

Saturation zone:

$$V\_{DS}(sat) = \frac{(V\_{GS} - V\_T)E\_cL}{(V\_{GS} - V\_T) + E\_cL} \tag{5}$$

$$\dot{m}\_D = \frac{W\mu\_\text{c}\mathbb{C}\_{\text{ox}}E\_\text{c}}{2} \left[ \frac{\left(V\_{GS} - V\_T\right)^2}{\left(V\_{GS} - V\_T\right) + E\_\text{c}L} \right] \tag{6}$$

Ohmic zone:

$$V\_{DS}(olmic - limit) = V\_{DS}(sat) = \frac{(V\_{GS} - V\_T)E\_\mathrm{c}L}{(V\_{GS} - V\_T) + E\_\mathrm{c}L} \tag{7}$$

$$i\_D = \frac{\mathcal{W}\mu\_c \mathcal{C}\_{vx} E\_c}{(E\_c L + V\_{DS})} \left[ (V\_{GS} - V\_T)V\_{DS} - \frac{V\_{DS}}{2} \right] V\_{DS} \tag{8}$$

If we summarize the SPICE-level I models of the MOSFET transistors to be used in conceptual CMOS designs, Table 1 describes the equations considering the ohmic and saturation regions in the so-called strong inversion regime.



Moreover, for "paper and pencil" calculations ("Thinking Modeling") the parameters used for 0.5 μm CMOS technology are described in Table 2.

**Table 2.** MOSFET parameters for CMOS 0.5 μm process (C5\_models) obtained in ON-SEMI Wafer Runs [6].


#### *3.4. Small-Signal Model of Devices*

The useful small-signal equations for MOSFET transistors correspond to the saturation zone of the device. The two most important parameters are *gm*, transconductance gain, and *gds*, output conductance of the device which provides its output resistance [3,4]. The equations for those parameters are described as follows.

$$\log\_{\mathfrak{M}} = \frac{d i\_{DS}}{d V\_{GS}} \Big|\_{Q} = \sqrt{2\beta I\_D (1 + \lambda V\_{DS})} \cong \sqrt{2\beta I\_{DS}} \tag{9}$$

$$\left. g\_{ds} = \frac{d i\_{DS}}{dV\_{DS}} \right|\_{\mathbb{Q}} = \frac{\lambda I\_{DS}}{1 + \lambda V\_{DS}} \cong \lambda I\_{DS} \tag{10}$$

From those expressions, λ is the channel modulation parameter shown in Table 2 and *β =k= μCox(W/L)* which was defined earlier for the large-signal model. These parameters are evaluated at the quiescent Q point where the device operates and the small-signal ignites.
