**Appendix A**

#### *Appendix A.1. Parasitic Capacitances Modeling*

In the analysis of parasitics inside the CMOS transistor, we can identify three types of capacitances. First, the thin oxide capacitance between the gate and the other terminals of the transistor that depends on the operating zone with an approximate value of

$$\mathsf{C}\_{\mathfrak{F}} = W L \mathsf{C}\_{\text{ox}} \tag{A1}$$

In the accumulation zone and factionary values of *Cg* of depletion, saturation, and linear zones of operation. The second type of parasitic capacitance inside the CMOS transistor is the PN junctions capacitors formed between the material P and N in the channel and substrate and sidewall capacitances. This is given by,

$$C\_j \cong \frac{C\_{jb}(A\_b + A\_{\rm sw})}{\left(1 - \frac{v\_j}{q\_B}\right)}\tag{A2}$$

The third type of parasitic capacitance inside a CMOS transistor is the Overlap capacitance that can be from the overlap of gates due to lateral diffusion (Cov) and fringing effects (Cf).

$$\mathbb{C}\_{\text{ov}} = \mathbb{C}\_{\text{ox}} \times L\_D \tag{A3}$$

$$C\_f = \frac{2\varepsilon\_{ox}}{\pi} \ln\left(1 + \frac{T\_{poly}}{t\_{ox}}\right) \tag{A4}$$

$$\mathbb{C}\_{ol} = \mathbb{C}\_{ov} + \mathbb{C}\_{f} \tag{A5}$$

Table A1 illustrates the summary of the parasitic capacitances in a MOSFET at different operating zones. Moreover, Figure A1 depicts graphically the parasitic capacitance model of the CMOS devices.



**Figure A1.** The parasitic capacitance model of the CMOS transistors.

#### *Appendix A.2. Temperature Model and the Influence of Temperature in the Conceptual Design*

In CMOS technology the influence of temperature in device conceptual designs is reflected mainly in the transconductance parameter and the threshold voltage, which can be evaluated using the Excel methods and validated using the ".temp" command in SPICE. The transconductance parameter changes with temperature as follows:

$$k(T) = k(T\_0)[T/T\_0]^{-1.5} \tag{A6}$$

The threshold voltage changes with temperature as follows:

$$V\_T(T) \cong V\_T(T\_0) + \infty \ (T - T\_0) \tag{A7}$$

Typically for NMOS transistors, <sup>∝</sup>*NMOS* varies from − 2 mV/◦C to − 3 mV/◦C from 200 ◦K to 400 ◦K and for PMOS transistors the sign is reversed as one may expect. Therefore, the overall evaluations and calculations performed using the Excel method at room temperature would need to be re-calculated to account for the temperature range of operation. This can be validated using SPICE simulation as mentioned above.

For example, assume that we want to determine how the drain-source operating current of a CMOS 0.500 μm NMOS transistor varies from 27 ◦C to 100 ◦C. The device has *W*/*L* = 5 μ/1 μ, *k*(*<sup>T</sup>*0) = 117 μA/V2, *VGS* = 2 V, *VT*(*<sup>T</sup>*0) = 0.8 and *T*0 = 27 ◦C. The following calculations are performed:

(a) At room temperature:

$$I\_{DS}(27^{\circ}\text{C}) = \frac{117\mu\text{A}/\text{V}^{2}\cdot5\mu}{2\cdot1\mu}(2 - 0.8)^{2} = 421.2\text{ }\mu\text{A}$$

(b) At 100 ◦C (373 ◦K):

$$k(100 \, ^\circ \text{C}) = 117 \mu \text{A} / V^2 (373/300)^{-1.5} = 84.39 \, \mu\text{A} / \text{V}^2$$

$$V\_T (100 \, ^\circ \text{C}) = 0.8 - 0.002 (73 \, ^\circ \text{C}) = 0.654 \, \text{V}$$

$$I\_{DS} (100 \, ^\circ \text{C}) = \frac{84.39 \, \mu\text{A} / \text{V}^2 \cdot 5 \mu}{2 \cdot 1 \, \mu} (2 - 0.654)^2 = 382.23 \, \mu\text{A}$$

The previous example illustrates that a change of +73 ◦C in temperature produces a drop of 9.3% in the operating drain-source current of this device. Those calculations can be developed in the Excel methods to find the influence of temperature in the amplifier design. Those changes can also be verified by SPICE simulation using the temperature sweep accordingly.
