**4. Conclusions**

A CMOS detector with concurrent in-phase coupling was proposed to achieve highquality images using THz imaging systems. The cross-capacitor structure possessed two detecting operations in a common source and a drain input structure while considering

general amplifier analysis. The simulation results demonstrated that the proposed detector exhibits higher detection performance than the previously studied detector topology using gate-drain capacitors. At the output stage, the detector performance with regard to phase coupling was improved by 1.5–3 times higher than that of the previous detector core based on the input power. The detector, manufactured by a TSMC 0.25 μm CMOS process, comprised a differential folded dipole antenna, as the proposed core was connected by cross-coupled capacitors, a pre-amplifier, and a low-gain voltage buffer amplifier. The values of *RV* and *NEP* at 200 GHz were 14.13 MV/W and 34.42 pW/ √Hz, respectively, at a gate bias of 150 mV. In contrast to the previous detector studies, the proposed detector structure has a smaller detector IC area with higher detection performance. At 200 GHz, the measurements of a THz imaging system using samples of copper foil tape attached to Styrofoam substrates demonstrated that the proposed detector can resolve wavelengths (approximately 200 GHz) of 2-mm thickness with a high correlation coefficient. The proposed detector demonstrated an improved correlation of 59.37% with the actual sample, 1.4 times higher than the previous detector under identical conditions, except for the circuit structure. The image SNR, which indicates the image quality, was 49 dB, which was 9 dB higher than that obtained using the model capacitor of the process. The THz image quality was improved using the proposed concurrent-mode CMOS detector without the need for an additional circuit.

**Author Contributions:** Conceptualization, J.-R.Y.; methodology, M.-J.L., G.-E.L. and J.-R.Y.; software, M.-J.L. and H.-N.L.; validation, M.-J.L. and J.-R.Y.; formal analysis, M.-J.L. and J.-R.Y.; investigation, M.-J.L.; resources, S.-T.H. and J.-R.Y.; data curation, M.-J.L. and J.-R.Y.; writing—original draft preparation, M.-J.L., H.-N.L., G.-E.L. and J.-R.Y.; writing—review and editing, M.-J.L., S.-T.H. and J.-R.Y.; visualization, M.-J.L.; supervision, J.-R.Y.; project administration, J.-R.Y. All authors have read and agreed to the published version of the manuscript.

**Funding:** This work was partly supported by the National Research Foundation of Korea gran<sup>t</sup> funded by the Korea governmen<sup>t</sup> (MSIT) (No. 2021R1A2C2004356) and Institute of Information & Communications Technology Planning & Evaluation gran<sup>t</sup> funded by the Korea governmen<sup>t</sup> (MSIT) (No. 2018-0-00711).

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** The data presented in this study are available on request from the corresponding author. The data are not publicly available due to the regulation of the project.

**Acknowledgments:** The chip fabrication and EDA tool usage were partly supported by the IC Design Education Center (IDEC), Korea.

**Conflicts of Interest:** The authors declare no conflict of interest.
