**7. Conclusions**

In this work, an MLP architecture design at the hardware level was presented, using base neurons at the circuit level as its building blocks. Neuron weights and bias were optimized off-line using n-dimensional objective functions through the gradient descent method. The hardware architecture of the base neuron was designed on a CMOS operational amplifier in 1.2-micron technology. The total power consumption was 46 mW. The 5-3-1 ANN architecture was designed with nine neurons, using 36 op-amps, demonstrating its electronic performance in the practical case shown in Section 5.

The application developed with the implementation of the base neuron circuits showed optimal results in detecting the pattern. Starting with the supervised learning algorithm and based on the gradient descent method to obtain the synaptic weights and bias for the neural architecture, the responses shown in Figure 8 and Table 7 were appropriate to the electrical behavior. The MLP architecture presented an efficiency of 99 %. We might sugges<sup>t</sup> other applications, but in the first instance, we determined that solving this problem was an adequate choice to show the efficiency of the MLP system. Other applications could be proposed, but that remains as future work; for example, we are currently working on image recognition to classify agricultural products and on data processing of hypertensive and diabetic patients. As part of the future work, we have the design and implementation of neural network circuits based on the optimization of objective functions. Besides, we can use other tools, such as Verilog-AMS or VHDL-AMS, as alternatives to simulate the results presented in this work. Another future work is trying other meta-heuristic optimization methods to obtain better ANN training results. We consider that the application of the proposed method was optimal but not without leaving a possibility of applying another meta-heuristic method in the short term.

The advantage of our development with respect to other works cited in Table 8, can be observed, mainly, in the following improvements: power dissipation, number of transistors, and probably, the dimension in area of the integrated circuit. It is likely that one of the disadvantages of our implementation is the speed of response, but that is compensated by the fact that this is a design containing just what is necessary for the application, without an excessive amount of resources.

**Author Contributions:** Conceptualization, A.M.-S., C.A.H.-G., L.A.M.-R. and I.A.-B.; methodology, A.M.-S., C.A.H.-G., L.A.M.-R. and I.A.-B.; software, A.M.-S., M.A.G. and J.A.O.T.; validation, A.M.-S., I.A.-B. and M.A.G.; formal analysis, A.M.-S. and L.A.M.-R.; investigation, A.M.-S., C.A.H.-G., L.A.M.- R. and I.A.-B.; resources, A.M.-S., C.A.H.G., L.A.M.-R., I.A.-B., M.A.G. and J.A.O.T.; writing—original draft preparation, A.M.-S., I.A.-B., L.A.M.-R. and C.A.H.-G.; writing—review and editing, A.M.-S., C.A.H.-G., L.A.M.-R. and I.A.-B.; visualization, C.A.H.-G. and J.A.O.T.; supervision, L.A.M.-R. and A.M.-S. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by the Mexican National Council for Science and Technology (CONACYT) through the Research Projects 882, 278, and 613.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** Not applicable.

**Conflicts of Interest:** The authors declare no conflict of interest. The funders had no role in the study's design, in the collection, analyses, or interpretation of data, in the writing of the manuscript, or in the decision to publish the results.
