*2.3. Experimental Results*

The system was designed in 65 nm low-Vt CMOS technology, as shown in Figure 7. The entire area was 0.28 µm<sup>2</sup> . The CPs had an *N* of 20 and a *C* of 15 pF. The LV-CP had an *N* of six and a *C* of 3 pF to generate the supply current of 10 µA at 1 V, which was sufficiently high for the following circuits while keeping *γ* < 0.2.

**Figure 7.** Die photo.

The input terminal was connected to an equivalent circuit of the TEG with *VOC* and *RTEG*. A *CDD* of 300 nF and a *CPP* of 1 nF were connected to the input and output terminals of the CP system, respectively. Since the system did not work at a *VOC* of 0.6 V probably because the V*TH* of MOSFETs was close to the slow corner while the simulation was performed at the typical corner, the experiments were performed at *VOC* of 0.8 V. Figure 8

shows *IPP*, *IDD*, *VDD*, and *PPP* as a function of *VPP* where *VPP* was varied by varying the load resistance. All the simulations were performed with the slow-corner model. The measured results were matched with the simulated ones with an error of about 10%. *VPP* was regulated at 2.5 V when *IPP* was 25 µA or lower. The average *VDD* was 0.6 V or higher when *VPP* was regulated.

**Figure 8.** (**a**) *IPP*, (**b**) *IDD*, (**c**) *VDD*, and (**d**) *PPP* as a function of *VPP.*

To see the dynamic response of *VPP* and *VDD* against *VOC*, *VOC* was made to go up and down between 0.5 V and 1 V in 200 µs, as shown in Figure 9. A signal EN was also monitored using a buffer whose supply voltage was *V*1V. In the period T1, because *VDD* was lower than *VDDT*, EN stayed low. In the period T2, because *VDD* was higher than *VDDT*, but *VPP* was lower than *VPPT*, EN stayed high. Once *VPP* reached *VPPT*, in the period T3, the system stayed in the steady state where the *TON*/*TOFF* operation was repeated to keep *VPP* and *VDD* at *VPPT* and *VDDT*, respectively.

**Figure 9.** Dynamic behavior of *VPP* and *VDD* against *VOC*.

The system was also tested with the TEG using a thermal source, as shown in Figure 10. The TEG was based on carbon nanotubes [18]. The TEG module was built to fit with a pipe, which flowed hot liquid or gas. Because the TEG module had an *RTEG* of 1.4 kΩ, *VOC* needed to be set at a higher voltage of 1.1 V with a temperature difference of 66 K to enable the fabricated converter system to be functional, as shown in Figure 11.

**Figure 10. The** TEG module (**a**) and experimental setup with the TEG (**b**).

**Figure 11.** *VOC* vs. ∆*T* (**a**) and *IDD* vs. *VDD* at ∆*T* of 66 K (**b**).

Figure 12 shows *IPP*, *IDD*, *VDD*, *PPP*, *ηSYS*, and *ηCP* as a function of *VPP*. *ηSYS* and *ηCP* are defined by (*VPP* ×*IPP*)/(*VOC*×*IDD*) and (*VPP*×*IPP*)/(*VDD*×*IDD*), respectively. The *VPP* regulation point was different by 0.3 V between measured and simulated, but the electric values except for it were in good agreement. It was confirmed that the converter system with the TEG module under the experimental condition could supply power of 30 µW at 2.5 V to the following sensor ICs. The overall power conversion efficiency *ηSYS* was hit at about 7% against a theoretical limit with no loss of 50%. The power conversion efficiency of the converter system *ηCP* was 15% when *VDD* was 0.55 V at *VPP* of 2.5 V, i.e., a voltage ratio (*VPP*/*VDD*) of 4.5. For comparison, *ηCP* of 20%, 32%, and 45% was realized with a *VDD* of 0.1 V, 0.2 V, and 0.3 V at a *VPP* of 0.5 V, respectively, in [10]. Thus, the *ηCP* of the proposed converter system was a little lower than that of [10] at the voltage ratio of 4.5. The design optimization may need to be improved to increase power conversion efficiency by including the TEG electrical parameters in the design parameters.

**Figure 12.** (**a**) *IPP*, (**b**) *IDD*, (**c**) *VDD*, (**d**) *PPP*, (**e**) *ηSYS*, and (**f**) *ηCP* as a function of *VPP.*
