**2. Circuit Design**

*2.1. System Design*

Figure 3 illustrates the proposed CP system to extract power from the TEG with high-output impedance and to drive the following sensor ICs. Table 2 shows the condition to resume or suspend CP operation. A detector DETi monitors *VDD* and outputs ENi. A detector DETo monitors *VPP* and outputs ENo. Only when both signals become high, an oscillator OSC outputs a clock to drive the CP. Otherwise, the OSC stops working to not drive the CP. The third detector DETpp generates a signal VPP\_OK to let the sensor ICs know the supply voltage is sufficiently high to work.

**Figure 3.** Building blocks of the proposed CP circuit system.

**Table 2.** Operation condition of the main CP against *VDD* and *VPP.*


Figure 4 shows two operation phases in steady state. In Phase (a), the CP inputs the current mainly from *CDD*. Even though *RTEG* is much larger than the input impedance of CP, *VDD* can be controlled to be higher than *VDD\_MIN*. Phase (a) starts with EN high when *VPP* hits *VPPM = VPPT*, where *VPPM* and *VPPT* are the minimum voltage of *VPP* and the target voltage of *VPP*, respectively. *VPP* increases while *VDD* decreases due to CP operation. EN goes low when (1) ENo goes low or (2) ENi goes low. In the case of (1), the ripple △*VPP* is determined by the loop response from the output node of the CP to EN. *VDDM* must be higher than *VDDT*. In the case of (2), *VDDM* is equal to *VDDT*. In Phase (b), *VDD* increases with the charging current from the TEG, while *VPP* decreases with the discharging load current. The input impedance of the CP becomes very large because the main charge pump CP is suspended with EN low, even though a small amount of current flows into small building blocks such as LV-CP. Thus, even though the TEG has high-output impedance, the system controls the input voltage to keep it higher than the minimum operating voltage by

modulating the input impedance of the charge pump using two-phase operation with lowand high-input impedance modes. The average input impedance can be matched with the output impedance of the TEG. On the other hand, such an operation is not required when the output impedance of TEGs such as the bulk-type is much lower than the input impedance of the CP in operation. The operating point approaches *VOC*, but the system can work as long as *VOC* is higher than the minimum operating voltage.

**Figure 4.** Two phases of the circuit operation. (**a**) Low and (**b**) high input impedance modes

The following equations hold among *TON*, *TOFF*, ∆*VPP* and ∆*VDD*, where it is assumed that *IPP* and *IDD* are the steady-state currents and can be treated as constant when ∆*VPP* << *VPP*, ∆*VDD* << *VDD*, and *ITEG* << *IDD*.

$$T\_{ON} = \frac{\mathcal{C}\_{DD} \,\Delta V\_{DD}}{I\_{DD}} = \frac{\mathcal{C}\_{PP} \,\Delta V\_{PP}}{I\_{PP} - I\_{LOAD}} \tag{1}$$

$$T\_{\rm OFF} = R\_{\rm TEG} \complement \text{DDI} \ln \frac{V\_{\rm OC} - V\_{\rm DDM}}{V\_{\rm OC} - V\_{\rm DDM} - \Delta V\_{\rm DD}} = \frac{\mathcal{C}\_{\rm PP} \Delta V\_{\rm PP}}{I\_{\rm LOAD}} \tag{2}$$

*IPP* and *ILOAD* are related as Equation (3).

$$I\_{LOAD} = \frac{T\_{ON}}{\mathbf{T}} I\_{PP} \tag{3}$$

When one can regard *ITEG* as constant in the case of ∆*VDD* << *VDD*, *IDD* and *ITEG* are related as Equation (4).

$$I\_{TEG} = \frac{T\_{ON}}{\mathbf{T}} I\_{DD} \tag{4}$$
