**3. Implementation of the Control Unit**

The control circuit of the proposed storage unit, composed of comparators, logic gates and power switches, is depicted in Figure 4. The power switches are implemented with 10,000 um/0.30 um 3.3 V PMOS transistors, which present low on-resistance and sufficient response time. The power switch's length is set to a minimum in order to present a small layout area. A bulk regulation circuit is added on S1 and S2 switches to prevent supercapacitors from discharging towards the input. To supervise the voltage levels of the storage media, low-power comparators are designed, utilizing resistive MOSFETs and nA bias current (Figure 4). The topology of the used comparator [19] creates a hysteresis window (∆V) which can be implemented by adjusting the cross-coupled (M5, M6) and diode-connected (M3, M4) transistors aspect ratio as follows:

$$
\Delta V = \pm \frac{1 - \sqrt{(W/L)\_{5,6} / (W/L)\_{3,4}}}{\sqrt{1 + (W/L)\_{5,6} / (W/L)\_{3,4}}} V\_{\text{ov}\_{diffpair}} \tag{1}
$$

where *W* is the width of each transistor, *L* is the length of each transistor and *Vovdiffpair* is the overdrive voltage of the differential pair of the comparator. Thus, by properly selecting the values of the transistors' widths, the desired hysteresis window can be achieved. Specifically:

**Figure 4.** Control logic and comparator design.

For SCsmall, a comparator with a 50 mV hysteresis window (comp1) is designed. It controls the charging and discharging mode of the supercapacitor through switches S1 and S1\_load respectively. This small hysteresis window provides regulated supply voltage for the internal circuits of the harvesting system, with low voltage ripple as well as protection from excessive switching. Additionally, pin en1 is available for external control of the load connection via the S1\_load switch (Vout1).

The SCbig charging mode is also supervised by a 50 mV hysteresis window comparator (comp2). Additionally, a 200 mV hysteresis window comparator (comp3) controls the SCbig discharging, via the output switch, S2\_load. Since two different comparators are used for the charging and discharging mode of SCbig, the output voltage window (Vout2) can be adjusted to the load needs, with a minimum ∆V<sup>2</sup> of 200 mV. For a 5 F capacitor and 100 mA load current the frequency of the voltage ripple is extremely low (<1 mHz). This supply voltage ripple is acceptable for many off-the-shelf components (e.g., MSP430i204x MCU, etc.). As external control is offered (pins en1 and en2), the supply of the loads can be enabled or disabled as needed. Otherwise, the enable pins can be tied to low (inactive) or high (active) potential.

Two additional comparators (comp4 and comp5), monitor VSCsmall and VSCbig voltage levels and activate the battery support if one or both supercapacitors are critically discharged. The S4 switch closes, and the battery provides energy to the supercapacitor in need. The bleeder mode (switch S3) is triggered only in case that both supercapacitors are fully charged.

The combination of the comparators signals along with the external enable signals, is implemented with digital logic circuits (NAND, AND, NOT gates) which are also customdesigned with resistive transistors, to further decrease the power consumption of the control unit.

The voltage thresholds are determined by external voltage divider networks (Figure 4), with multiple voltage tapping points. A fraction of VSCsmall or VSCbig is compared with a stable voltage reference. Since bandgap voltage references are too power-demanding for low-power applications, a 1.08 V voltage reference circuit was implemented, which is based on the circuit presented in [20], with pW power consumption.
