*2.4. Built-In Power-On Reset (POR)*

After the transducer starts generating power, VDD is gradually increased from 0 V. Every building block has its own minimum operating VDD. If pull-down (PD) is enabled below the minimum VDD, the system is latched in that state and therefore VDD should no longer be increased. Power-on reset (POR) aims to remove such misbehavior. Additional low-power POR requires more silicon area and more power. As a result, we simply added a blocking PMOS (PPD), which has a standard threshold voltage in the pull-down path, as shown in Figure 2. As shown in Figure 6a, while VDD is low, VREF can be also lower than VDD/2 because of the misbehavior of the OPAMPs. In that case, the gate voltage V<sup>G</sup> of the pull-down NMOS (NPD) stays high. Even in such a case, PPD disconnects the path from VDD to ground. The necessary condition for normal operation is that PPD starts conducting after VREF > VDD/2. Figure 6b shows the simulated waveform of the entire system to verify the normal operation during power-up.
