*2.2. Building Blocks' Design*

B1: Main charge pump

The given design parameters are the minimum open-circuit voltage of the TEG (*VOCMIN*), *RTEG*, *VPPT*. The number of stages *N* was designed to maximize *IPP* at *VPPT* when the circuit area is given. Based on [15], *N* is given by Equation (5).

$$N = \left[1.7 \times N\_{MIN}\right] = \left[1.7 \times \frac{V\_{PP} - V\_{DD} + V\_{TH}^{EFF}}{V\_{DD}/(1 + \mathfrak{a}\_T) - V\_{TH}^{EFF}}\right] \tag{5}$$

where [*x*] indicates the floor function of *x*, *NMIN* is the minimum number of stages to barely generate *VPP*, and *V EFF TH* is an effective threshold voltage of switching transistors, which were called ultra-low power diodes in [16]. The capacitance of each stage capacitor *C* is related with *IPP* and *IDD* as Equations (6) and (7), where the clock frequency *f* is determined to maximize *IPP*.

$$I\_{PP} = \frac{f\mathcal{C}(1+\mathfrak{a}\_T)}{N} \left[ \left(\frac{N}{1+\mathfrak{a}\_T} + 1\right) V\_{DD} - (N+1)V\_{TH}^{EFF} - V\_{PP} \right] \tag{6}$$

$$I\_{DD} = \left(\frac{N}{1+\mathfrak{a}\_T} + 1\right) I\_{PP} + \left(\frac{\mathfrak{a}\_T}{1+\mathfrak{a}\_T} + \mathfrak{a}\_B\right) fN\mathcal{C}V\_{DD} + I\_{CTRL} \tag{7}$$

where *α<sup>T</sup>* and *α<sup>B</sup>* are the ratios of the top (*CTOP*) and bottom plate parasitic capacitance (*CBTM*) to *C*, *CTOP*/*C* and *CBTM*/*C,* respectively. Note that *CBTM* includes the parasitic capacitance of an oscillator to drive the main CP. *ICTRL* is the input current for the control circuits, which was assumed to be *βIDD* using the design parameter *β* (<1) in this paper because the auxiliary circuits assumed in this paper as shown later steadily ran regardless of *TON. IDD* is also given by Equation (8) at the extreme case of *TON* = *T* and *TOFF* = 0.

$$I\_{DD} = \frac{V\_{OC} - V\_{DD}}{R\_{TEG}}\tag{8}$$

From Equations (6)–(8), the minimum C needs to meet Equation (9).

$$C = \frac{(1 - \beta)N(V\_{\rm OC} - V\_{\rm DD})}{fR\_{\rm TEG}\left[ (N + 1 + a\_T) \left\{ \left(\frac{N}{1 + a\_T} + 1\right)V\_{\rm DD} - (N + 1)V\_{\rm TH}^{\rm EFF} - V\_{\rm PP} \right\} + \left(\frac{a\_T}{1 + a\_T} + a\_B\right)N^2V\_{DD} \right]} \tag{9}$$

To have a duty ratio of *TON/T* smaller than a factor of *γ*, the C to be designed must be increased by a factor of 1/*γ*.

The parameters shown in Table 3 were used for design demonstration. *VDDMIN* was mainly determined by the technology used to design, e.g., the availability of low-Vt CMOS and circuits used in the system. As will be shown later, it was limited by an oscillator to generate a clock with 10 MHz. Such a moderate frequency was required to have a sufficiently small circuit system built in the same sensor ICs. From Equations (5) and (9), N and C were calculated to be 19 and 4.8 pF at *VDDT* = 0.5 V, respectively. Figure 5 shows *PPP* and CP area *NC/γ* as a function of *VDD*.

**Table 3.** Design parameters used in this work.

**Figure 5.** (**a**) *PPP* vs. *VDD*; (**b**) CP area *NC/γ* vs. *VDD.*

B2: Auxiliary circuits

As illustrated in Figure 3, the detectors compare *VDD* and *VPP* with a reference voltage *VREF* generated by bandgap reference BGR [17]. To provide a supply voltage *V*1V~1 V to the BGR, another small CP (LV-CP) was implemented. The LV-CP is operated in open loop not to affect the *VDDMIN* of the system. A dedicated oscillator starts running without any input signal other than *VDD*. When LV-CP converts power to the output terminal and *V*1V reaches about 1 V, a clamping circuit CLAMP with NMOSFETs connected in series with the output terminal clamps the output voltage. *V*1V is also used as the supply voltage of all the logic gates and the detectors. Figure 6 shows a simulated result of the BGR. *VREF* is saturated when *V*1V > 0.8 V.

**Figure 6.** *VREF* vs. *VDD.*
