5.1.1. Tracking Performance Analysis of the Proposed Controller

The results obtained for both the controllers tracking performance analysis are depicted in Figures 7 and 8. To test the tracking performance of the controller's real power, references were varied between 0 MW and 0.1 MW (PV output is non-linear), whereas reactive power references were changed between 0 MVar and 0.02 MVar, respectively.

**Figure 7.** Real power tracking performance of (**a**) FLDPC method and (**b**) dq CCS-based power controller with PLL.

From Figure 7a, it is seen that, initially, real power reference was set to 0 MW, which was increased from 0 MW to 0.05 MW after 1 s. Then, it was set to 0.1 MW between 2.97 and 4.969 s, and the final reference was set to 0 MW again, between 4.97 and 7 s. For all the real power references, it was observed that the PV-VSI output real power, controlled by the proposed PVMT-based FLDPC, was tracking the real power references accurately. On the other hand, though from Figure 7b it seems that the conventional dq CCS-based power controller also tracked the reference powers, from the zoomed portion it is clear to see that the tracking speed of the proposed PLL-less PVMT-based FLDPC method is 0.03 s. This was 0.19 s faster than that of the conventional dq CCS-based power control method, whose real power reference tracking speed was 0.22 s. For reactive power, the reference power was kept to 0 MVar, initially, which increased to 0.01 MVar and 0.02 MVar at 1 s and 3 s, respectively. Finally, at 1 s reference reactive power decreased to 0 MVar. It can

be observed from Figure 8a that the VSI output reactive power controlled by the PVMTbased FLDPC method was following the reference reactive power accurately at different time intervals. In addition, the proposed PVMT-based FLDPC showed better tracking performance than that of CCS-based power controller, though the conventional CCS-based controller was able to track the reference reactive power, as shown in Figure 8b. According to the zoomed portion of Figure 8a,b, the time taken to reach a steady-state of reactive power by the proposed PVMT-based FLDPC was 0.03 s, where the conventional CCS-based power controller tracked it at 0.23 s. This was 0.20 s slower than the proposed controller.

**Figure 8.** Reactive power tracking performance of (**a**) FLDPC method and (**b**) dq CCS based power controller with PLL.

5.1.2. Proposed Controller Steady-State Performance Analysis

In this section, the steady-state performance of the proposed PVMT-based FLDPC method is validated. From the results shown in Figures 9 and 10, it is clear that due to the use of the proposed PVMT-based FLDPC method, the ripples at VSI output power were significantly reduced. The time range considered for viewing the ripples in VSI output real and reactive power was 2.88–5 s. From Figure 9a, it can be observed that for the proposed PVMT-based FLDPC, very low ripple existed in the VSI real power output. However, a higher ripple was observed in the VSI real power output for the conventional PLL-based power controller, which ranged between 0.0984 and 0.1006 MW. Real power also did not follow the reference accurately, as seen from Figure 9b. For reactive power, it can be seen from Figure 10b that the ripple was very high for the conventional CCS-based power controller and it ranged from 0.019 to 0.0208 MVar. On the other hand, for the proposed PVMT-based FLDPC method, reactive power also had very low power ripple, as shown in Figure 10a.

**Figure 9.** Real power steady-state performance of (**a**) FLDPC and (**b**) dq CCS-based power control method with PLL.

**Figure 10.** Reactive power steady-state performance of (**a**) FLDPC and (**b**) dq CCS-based power control method with PLL.

In Figures 11 and 12, the waveforms of the PV-VSI's output current and voltage are presented for both the controllers. From Figures 11a and 12a, it can be seen that for PLL-less PVMT-based FLDPC, the PV-VSI output voltage and current were sinusoidal in shape, and had negligible noises. In comparison, even though the PV-VSI output voltage and current for PLL-integrated CCS-based power controller were sinusoidal in shape, large distortion was observed, as shown in Figures 11b and 12b.

Further from Figure 13, it was observed that for both the controllers, the THD of the PV-VSI currents was less than 5%, which is in line with the IEC standard [44]; however, the current THD (4.967%) obtained by the PLL-CCS-based power control method was very high, compared with the PVMT-based FLDPC method's current THD (1.59%). As a result, oscillations in PV-VSI output power and current during steady-state were very low for PLL-less PVMT-based FLDPC, compared with the power control method based on PLL-integrated dq CCS.

**Figure 11.** PV-VSI output voltage for (**a**) FLDPC method and (**b**) dq CCS-based power controller with PLL.

**Figure 12.** PV-VSI output current for (**a**) FLDPC method and (**b**) dq CCS-based power controller with PLL.

**Figure 13.** VSI output current THD for FLDPC and dq CCS-based power control method.
