*Article* **Improving Performance Estimation for Design Space Exploration for Convolutional Neural Network Accelerators †**

**Martin Ferianc 1,\* ,‡, Hongxiang Fan 2,‡, Divyansh Manocha <sup>3</sup> , Hongyu Zhou <sup>4</sup> , Shuanglong Liu <sup>5</sup> , Xinyu Niu <sup>6</sup> and Wayne Luk <sup>2</sup>**


**Abstract:** Contemporary advances in neural networks (NNs) have demonstrated their potential in different applications such as in image classification, object detection or natural language processing. In particular, reconfigurable accelerators have been widely used for the acceleration of NNs due to their reconfigurability and efficiency in specific application instances. To determine the configuration of the accelerator, it is necessary to conduct design space exploration to optimize the performance. However, the process of design space exploration is time consuming because of the slow performance evaluation for different configurations. Therefore, there is a demand for an accurate and fast performance prediction method to speed up design space exploration. This work introduces a novel method for fast and accurate estimation of different metrics that are of importance when performing design space exploration. The method is based on a Gaussian process regression model parametrised by the features of the accelerator and the target NN to be accelerated. We evaluate the proposed method together with other popular machine learning based methods in estimating the latency and energy consumption of our implemented accelerator on two different hardware platforms targeting convolutional neural networks. We demonstrate improvements in estimation accuracy, without the need for significant implementation effort or tuning.

**Keywords:** field-programmable gate array; deep learning; neural network; performance estimation; Gaussian process
