**1. Introduction**

Three-dimensional (3D) integration of silicon dies or wafers has received considerable attention in the past decade, due to its advantages of higher I/O density, lower RC delay, capability of heterogeneous integration, and footprint shrinking. Microbumps containing solder alloys have been deployed for establishing electrical and mechanical connection between vertically stacked chips [1,2]. Although similar in principle to the well-developed flip-chip technology, the interconnections using microbumps are still subjected to process adaptations. Therefore, solder joint reliability plays a vital role in the quality of electronic products.

Among all reliability issues, drop impact reliability of a solder joint, in particular, is of great importance and has attracted many researchers. For ball grid array (BGA) level solder joints typically 200–500 µm in size, the main failure mode during drop impact loading is manifested as cracking along the interface of solder bump and the intermetallic compounds (IMCs) formed by soldering [3,4], and the joint at the outermost corner is found as the most critical, which fails along the solder–pad interface [5,6]. F. X. Che et al. found that

**Citation:** Liu, Z.; Fang, M.; Shi, L.; Gu, Y.; Chen, Z.; Zhu, W. Characteristics of Cracking Failure in Microbump Joints for 3D Chip-on-Chip Interconnections under Drop Impact. *Micromachines* **2022**, *13*, 281. https://doi.org/10.3390/ mi13020281

Academic Editor: Seonho Seok

Received: 7 January 2022 Accepted: 5 February 2022 Published: 10 February 2022

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the constitutive model of solder used in the input-G simulation has a major impact on the stress and strain in a solder joint and on the hardening effect of bulk solder under a high strain rate during drop impact, which prevents the drop impact energy from dissipating through the bulk solder and accounts for the interface cracking [7]. However, downsizing of the interconnection joint size entails the reconsideration of a failure mechanism and characteristics of the micro-interconnections, as the joints in a chip-on-chip stacking scenario could use little of the previous studies at a larger scale as direct reference. Therefore, recent research of drop reliability also focuses on the 3D die-stacking structure. This includes the study by Chen et al. who determined that the critical position under the board-level drop impact is the corner of bottom layer of copper via [8], and the reliability improvement with a thinner IMC layer was revealed by Hsien-Chie Cheng et al. [9,10]. They also found that the interconnects under the drop test would exhibit a cohesive fracture inside the solder, which is different from the BGA cases studied by Suh [6,11]. M. O. Alam studied the parameters of stress intensity factors (SIF, *K*<sup>I</sup> and *K*II) around predefined cracks in the IMC layer of a solder butt joint by using linear elastic fracture mechanics (LEFM) and found that the SIF values increase sharply when the placement of the crack approaches near the interface. In summary, the reliability of microbumps for 3D integration under drop impact draws increasing concerns in interfacial fracture mechanics, as the cracking is strongly affected by the interfacial mechanical mismatch, and the propagation path will be complexly determined by both the interface feature and the solder matrix. Some research works have involved the path selection of the crack near the interface [12], but there is no description of the dynamic process of crack propagation near the interface.

In this study, we first observed the crack failure of a microbump joint in a chip-on-chip (CoC) test vehicle under drop test conditions and found that the crack formed at the edge of the soldering interface, propagated along the interface for a certain length, and deflected into the solder layer, eventually causing failure of the joint. To elucidate this phenomenon, a finite-element model was constructed to investigate the crack propagation behavior, based on basic fracture mechanics theories. The stress intensity factor of the crack tip at the interface between the IMC and solder is calculated by the contour integral method, and the propagation path of the solder joint interface crack is studied by using the criterion of energy release rate versus the fracture toughness in both the original and the deflected propagation path. Experimental tests for the joints of different solder thicknesses were carried out and compared with the numerical calculations to validate the model. Finally, the experimental observations revealed how the grain structure of the solder layer may affect the actual cracking path and drop lifetime.

#### **2. Setup for Drop Experiment**

Figure 1 shows the schematic diagram of the drop experiment. A Chip-on-chip test vehicle was used, which consisted of a 6 × 6 × 0.5 mm top chip, and a 12 × 12 × 0.5 mm bottom chip. Both the top chip and bottom chip had a microbump array fabricated on the surface through a standard lithography–etching–electroplating bumping process. Each microbump consisted of a Cu pillar, a Ni barrier layer, and a SnAg cap. The two chips were bonded through a flip-chip thermo compression process by an Athlete CB-600 flip-chip bonder with an alignment accuracy of ±1 µm. The temperatures of the bonding head and bottom suction tool were set at 340 and 100 ◦C to obtain a peak temperature of 260 ◦C at the soldering interface, and the bonding pressure was 0.06 N per bump. Target temperature and pressure were applied for 30 s. The 5 µm Cu traces on both chips linked each bump to form two daisy chains, each comprising 24 pair of bumps.

A JEDEC-compliant Salon Teknopajia drop tester executed the drop experiments. The CoC module was firmly assembled on the center of test board where the impact-induced distortion is highest. The dimension of the test board also complies with the JEDEC standard, although only the 1-chip arrangement was used. A daisy chain in the module was electrically connected to a high speed data acquisition circuit to allow for transient resistance recording in real-time during drop test. The test board was then fastened onto the base plate by four screws. For each drop, the base plate was raised to the height specified in JEDEC standard and dropped on the strike surface with the acceleration G measured to follow the curve shown in Figure 2. For the observation of microstructure evolution, CoC modules after certain numbers of drops were cross-sectioned and examined under a field-emission scanning electron microscope (FE-SEM) working at the backscattered electron imaging mode.

**Figure 1.** The schematic diagram of drop test and the cross-section images of the unit of the daisy chain.

**Figure 2.** Impact acceleration of test results.

#### **3. Set up for Simulation and Experiment**

A finite-element (FE) code that employs transient dynamics was applied to investigate the mechanical response of the bump joint structure in a mechanical simulation for the drop test related above. The material properties in the model are all linear elastic models, as shown in Table 1. Von Mises stress distribution in the whole model at the moment of highest impact acceleration is shown in Figure 3a. According to the literature, in the board-level drop test of BGA, the failure of solder balls was mainly due to peel stress [13]. Here, the reliability of the microbumps is likewise focused by simulating the stress built in the joints between top and bottom chips. For the outer corner joints, which were subjected to highest impact stress, the maximum peeling stress is shown in Figure 3b. In the top-side, IMC was 75.8 MPa, while in the bottom, IMC of the same joints was 91.4 MPa. Therefore,

the applied load was set from 10 to 90 MPa in the following FE model for the analysis of interfacial cracking behavior.


**Table 1.** Material properties of the main parts modeled as linearly elastic [14].

**Figure 3.** (**a**) Von Mises stress distribution of solder joint; (**b**) maximum peeling stress curves in a microbump joint during the impact load.

Because the solder joint has a cylindrical symmetry, the model for the calculation of the stress intensity factor at the crack tip is a two-dimensional model based on plane strain (Figure 1), which has an Sn-3.0Ag-0.5Cu solder(SAC305)–IMC–Ni sandwich configuration with dimensions of 100 × 20 µm, 100 × 1 µm, and 100 × 2 µm, respectively. A zerothickness crack is preset at the interface between the IMC and solder layers, and the crack length is variable. The method of presetting the zero-thickness crack is the common point method. The surface morphology of IMC is ignored, and the interface between IMC and the solder is assumed to be flat. With an IMC thickness of only 1 µm, the possible void formation around the IMC layer was ignored, and the Ni–IMC interface was considered as ideal. The bottom of the copper pad is a fixed end, and a static-type tensile load is uniformly applied on the upper surface of the solder.

The interaction integral method is used to solve the stress intensity factor at the crack tip. Because the crack in the model is on the interface between the IMC and the solder, the elasticity of the material on each side is different; thus, discontinuity appears on the interface. To ensure the calculation accuracy, the integral path of the contour is processed in sections. The mesh of the model adopts the region division method, and the smaller mesh size is used at the crack tip to ensure the solution accuracy, as shown in Figure 4. Affected by the thickness of the IMC, the mesh quality of the grid in the crack tip decreases sharply from the first to the fourth layer. Therefore, the average stress intensity factor calculated by taking the four integral contours at the innermost layer in the crack tip is utilized as the stress intensity factor around the crack tip.

**Figure 4.** Model for calculating the stress intensity factor under different crack lengths.

#### **4. Results and Discussion**

#### *4.1. Failure Mode and Mechanism of Microbumps*

In order to determine the failure characteristics of microbump interconnections under drop impact, first, the recording of the transient resistance of the daisy chain was plotted against the drop counts, as shown in Figure 5. The resistance change contains three distinct stages. Stage I denotes the period in which resistance value *R* remained unchanged; this stage typically lasts for the first 60 drops. Then, in several tens of following drops, denoted as stage II, fluctuation of R is detected, with the peak value not exceeding 120% of the original value. Later, R experiences a period of drastic fluctuation that it increases to far more than the initial value, and the daisy chain becomes completely open in less than 80 drop counts. In order to further explore the crack propagation mechanism, the drop samples were sliced and analyzed at different stages of circuit damage during continuous drop test. Figure 6a is a cross-sectional SEM of the sample without a drop test, and it can be seen from the figure that the IMC interface formed under the hot pressing bonding conditions used in the experiment is of good quality. As shown in Figure 6b,c, after the first 50 drops, a micro-crack was visible at the end of the IMC–solder interface of the bottom chip side. After the circuit was completely disconnected, a through crack could be observed. It can be concluded that the solder joint accelerated failure after crack propagation and deflection. Therefore, the resistance change pattern can be used to estimate the extent to which the structural damage of a critical microbump has progressed. It can also be seen that the joint degradation accelerated after the crack deflection since a significant spurt of resistance corresponds to the rapid shrinking of the residual joint area in this stage.

**Figure 5.** Typical resistance curves of daisy chains under drop test.

**Figure 6.** Cross-sectional SEM of the microbumps at different stages of drop impact. (**a**) Crosssectional SEM of the sample without drop test; (**b**) after 50 drops; (**c**) after the circuit is completely disconnected.
