**About the Editors**

**Francesc Serra-Graells** received his PhD degree in Electronics Engineering at the Universitat Politecnica de Catalunya, Spain, in 2001. He is currently Associate Professor at the Department of ` Microelectronics and Electronic Systems of the Universitat Autonoma de Barcelona, Spain. Since ` 1994, he is also with the Integrated Circuits and Systems group of the Institut de Microelectronica de ` Barcelona, Centro Nacional de Microelectronica, IMB-CNM(CSIC), Spain. His research interests are ´ very low-power, both low-voltage and low-current, design techniques for analog and mixed-signal CMOS circuits, like programmable amplifiers with automatic gain control, phase-locked loops, analog-to-digital and digital-to-analog data converters, oscillators and power managmen<sup>t</sup> units, among others. The results of his research activities are application-specific integrated circuits (ASICs) and intellectual-property (IP) cores targeting smart sensing systems, like hearing aids, IR and X-ray imagers, NEMS interfaces, chemical sensors and biosensors, space instrumentation and neural recording systems. He is co-author of more than 60 publications and has participated in more than 30 research and industrial ASIC projects.

**Michele Dei** received the Laurea degree cum Laude in Electronic Engineering and the Ph.D degree in Information Engineering at the University of Pisa (Italy) in 2007 and 2010, respectively, working on the design of smart sensors for detection of physical quantities. He is currently working at the Information Engineering Department of the University of Pisa (Italy), through of a Marie Skłodowska-Curie Individual Fellowship contract (H2020-MSCA-IF-2019/893544) as Principal Investigator of the SWeaT project regarding wearable electro-chemical instrumentation. Previously he worked within the IMB-CNM (Barcelona, Spain) and with the School of Information and Communication Technology at KTH (Stockholm, Sweden). His engineering background involves low-power analog-mixed signal integrated circuit for sensor interfacing, data converters in the context of a number of high-impact research and industrial projects.

**Kyoungrok Cho** received a B.S. degree in Electronic Engineering from Kyoungpook National University, Taegu, Korea, in 1977, and an M.S. and Ph.D. degree in Electrical Engineering from the University of Tokyo, Japan, in 1989 and 1992, respectively. From 1979 to 1986, he was with TV research center of LG Electronics in Korea. He is currently a Distinguished Professor at the College of Electrical and Computer Eng. of Chungbuk National University, Korea. His research interests are in the field of high-speed and low-power circuit design, SoC and platform design for the communication system, and prospective IOT sensor networks. He has been a director of a regional center of IDEC(IC Design Education Center) in Korea covering Chungcheong provinces and Taejon city from January 2004. In 1999 and again in 2006, he spent a year at Oregon State University, USA, as a visiting scholar.

## **Preface to "Integrated Circuits and Systems for Smart Sensory Applications"**

Connected intelligent sensing reshapes our society by empowering people with increasing new forms of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in some cases, even self-powered smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required intelligence and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power managemen<sup>t</sup> strategies, low-range wireless communications, and integration with sensing devices. In this Special Issue, recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications are presented via the following five emerging topics:


**Dedicated short-range communications** (DSRC) services designate one-way or two-way wireless communication for automotive use involving vehicle-to-vehicle and vehicle-to-infrastructure communications. In 2020, The United States Federal Communications Commission (FCC) allocated the 5.895-5.925 GHz band for Intelligent Transportation System (ITS) services. Equipment in the DSRC Service comprises On-Board Units (OBUs) and Roadside Units (RSUs). An OBU is a transceiver (which is normally battery operated) fitted inside the vehicle. In such scenarios, a high-speed reliable radio link need to be established under power-constrained requirements. Ali et al. [1] presents a new wake-up receiver (WuRx) to support he main RF receiver of the OBU by providing wake-up detection to exit the OBU hibernation state. The proposed ASIC features an intelligent digital controller (IDC) for improving WuRx reliability and for replacing complex and power-hungry analog blocks such as band-pass filters and frequency detectors. The IDC implements a number of smart power-managemen<sup>t</sup> techniques such as: (i) self-hibernation of the IDC and range communication (RC) oscillator; (ii) digital hysteresis for accommodating wake-up signal frequency variation and enhancing WuRx accuracy; (iii) a watch-dog timer for IDC self-recovery to avoid uncertain conditions during poor and false wake-up; (iv) configurable wake-up signal cycles before enabling a power-hungry RF transceiver. The IDC prototype in 130 nm CMOS technology occupies a modest silicon area (94 × 82 µm<sup>2</sup>). The resulting WuRx shows comparable sensitivity (−46 dBm) with the state-of-the-art, while outperforming it in terms of power consumption (2.48 µW), thus demonstrating the effectiveness of the proposed IDC. DSRC transceivers also comprise analog-todigital converters

(ADC) to allow the transceiver to communicate with the digital base-band electronics, with speed and resolution requirements of few tens of MS/s and 10 bits, respectively. To meet these requirements, Shehzad at al. [6] proposed a 12 bit 20 MS/s successive approximation register (SAR) ADC fabricated in 65 nm CMOS with an active area of 0.14 mm2, performing a SNDR of 65.44 dB while consuming only 472.2 µW with 1 V power supply. Low-power operation has been achieved employing various circuital techniques such as specific capacitor-switching strategy, asynchronous control logic, and custom modification of the dynamic-latch comparator.

**Digital smart sensors** are at the heart of IoT development, ranging fromconsumer gadgets, sensor networks, and image sensors to biomedical instruments, thanks to their digital-ready output and their added functionalities over classical analog-domain transducers, with almost zero impact on the device cost. Such added functionalities comprise sensor compensation, trimming and/or full-digital CMOS implementation for rapid IP embedding on complex system on chips (SoC). Ali et al. [2] propose polynomial-based adaptive digital temperature compensation for piezoresistive-type (PRT) pressure sensors. Such sensors have gained attention in a variety of applications due to their simplicity, low cost, miniature size, and ruggedness; however, their electrical behavior is temperature dependent and highly nonlinear. To avoid severe impairment of measurement accuracy, the authors propose an ASIC fabricated in 180 nm CMOS technology, delivering compensation accuracy within ±0.068% of full scale when temperature varies from −40 to +150 °C. On the other hand, low-cost and low-power temperature sensors, often targeting challenging requirements in terms of accuracy, precision, and linearity, are ubiquitously demanded. When cost per unit is considered, higher accuracy for a thermal sensor is based on a trade-off between the production costs for calibration and the required precision. Vasile et al. [5] show a trimmed digital sensor with a +1.5/−1.0 °C inaccuracy in the temperature range of −20 to +125 °C using a 180-nm CMOS EEPROM process by one-point calibration. Finally, Cicalini et al [10] show the implementation of an innovative, all-digital 180 nm CMOS capacitive-to-digital converter adequate for medium-low resolution body sweat-flow rate in wearable applications. They demonstrate the operation of 10.3 effective-number-of-bits resolution readout interface at 0.9 V-supply for a 0–250 pF input capacitance featuring ≥ 1.884 nJ/conversion, excellent linearity and robustness against process/temperature corners, while using only 0.0192 mm<sup>2</sup> of silicon area.

**Implantable neural interfaces** concern multi-electrode systems routinely designed as Application Specific Integrated Circuits (ASIC), which comprise hundreds or thousands of recording amplifiers on a single chip. To this aim, the signal recording chain must be very carefully designed so as to operate in low power and low latency, while enhancing the probability of correct event detection. High-fidelity recording of neuronal signals, comprising the action potentials (AP) range (300 Hz–10 kHz) and the local field potential (LFP) (1–300 Hz) range, requires strict noise (>10 µVRMS) and a total harmonic distortion (THD) (>2%) specifications, when dealing with signals up to 10 mVpp. Minimization of the dissipated power and silicon area is also critical for the design of neuronal interfaces with a very large number of recording channels. The large DC voltage at the input of the amplifier results from electrochemical interactions between the electrode and the tissue. The recording circuit must cut off this DC electrode voltage with high-pass filter (i.e., AC coupling) with a lower cutoff frequency, typically in the order of 1 Hz, and amplify the remaining AC signals with a gain in the order of 40 dB. Ranjandish and Schmid [3] report the latest advances in closed-loop implantable electronics for epilepsy control, focusing on both implantable and external commercial systems and pointing out the following research challenges: (i) size and weight; (ii)

power consumption and temperature elevation; (iii) battery powering and rechargeability; (iv) the biocompatibility of the package and enclosure; (v) data compression and storage. Trzpil-Jurgielewicz [7] propose a linearity-enhancing circuital technique for AC-coupled neural amplifiers to remove the electrode DC voltage. A prototype preamplifier fabricated in 180 nm CMOS technology shows THD values are below 1.17% for signal frequencies 1 Hz–10 kHz and signal amplitudes up to 10 mV peak to peak. While using only 0.0046 mm<sup>2</sup> of silicon area, the prototype has an input-referred noise of 8.3 µVRMS in the 1 Hz–10 kHz range, while consuming 7.2 µW per channel.

**Power Management Strategies in wireless sensor nodes (WSN)** involves both hardware and software techniques. Smart sensor nodes perform a set of tasks, often corresponding to different load states. The predictable transition schedule allows the software to proactively reconfigure the voltage converter to supply required amount of current for various load conditions. Under varying load conditions, however, a large Switched Capacitor (SC) converter often provides poor efficiency at smaller loads. An output voltage ripple is often alleviated by having a large output capacitor and/or high switching frequency, which represents another challenge faced by modern SC converters. Arslan et al. [4] propose a voltage converter whose switching frequency and output voltage are proactively adjusted to maintain high conversion efficiency based on the schedules of load current demanded by the target load. Multiphase operation is also implemented to provide low-output ripple. The ASIC prototype, fabricated in 130 nm CMOS technology, supports a load current range between 10 µA and 10 mA for switching frequencies ranging from 100 kHz to 200 MHz, while providing an efficiency of above 80%. The area of the converter is 0.59 mm2, operating a 1.5-V supply; it delivers a tunable output voltage between 0.4 and 1.1 V with maximum ripple of 56 mV. Apart from transistor-level power optimization, software control over the operating states of WSN is important for overall power saving of the battery-constrained system. You et al. [8] proposes a novel power managemen<sup>t</sup> method (PMM) that leads to less energy consumption in an idle state than conventional PMMs. While conventional PMMs rely on operation between Sleep, Idle, and Run modes, the proposed approach splits the Sleep mode into three different modes: Deep-Sleep and Semi-Idle Sensor and Semi-Idle WuRx. The proposed PMM strategy has been tested on a gas-sensing WSN using the commercial Mica2 platform and compared to conventional PMM. The proposed approach offers power savings between 2 and 74.2% depending on event rate, thus demonstrating its effectiveness in low-event-probability WSNs.

Neuromorphic hardware systems differ from classical von Neumann processor architectures since they are naturally configured for parallel information processing. Mimicking the vastly and densely connected neurons of the human brain, neuromorphic architectures encode information in sequences of action potentials called spike trains, theoretically promising a breakthrough in energy efficiency for signal processing. In this sense, specific and power-optimized hardware implementation of such neural networks is a hot topic in this research area. Asghar et al. [9] present an CMOS implementation of a Spiking Neural Network (SNN) for real-time9×9 pixel input image for pattern recognition. Fabricated using 180 nm CMOS process, the proposed chip achieves a classification accuracy of 94.66% for the MNIST dataset while occupying 3.6 mm<sup>2</sup> chip core area and presenting an average power consumption of 1.06 mW.

## **Francesc Serra-Graells, Michele Dei, Kyoungrok Cho** *Editors*

## **A Highly Reliable, 5.8 GHz DSRC Wake-Up Receiver with an Intelligent Digital Controller for an ETC System**

#### **Imran Ali, Muhammad Asif, Muhammad Riaz Ur Rehman, Danial Khan, Huo Yingge, Sung Jin Kim, YoungGun Pu, Sang-Sun Yoo and Kang-Yoon Lee \***

College of Information and Communication Engineering, Sungkyunkwan University (SKKU), Suwon 16419, Korea; imran.ali@skku.edu (I.A.); m.asif@skku.edu (M.A.); riaz@skku.edu (M.R.U.R.); danialkhan@skku.edu (D.K.); yingge@skku.edu (H.Y.); sun107ksj@skku.edu (S.J.K.); hara1015@skku.edu (Y.P.); rapter@kaist.ac.kr (S.-S.Y.)

**\*** Correspondence: klee@skku.edu; Tel.: +82-31-299-4954

Received: 18 June 2020; Accepted: 17 July 2020; Published: 19 July 2020

**Abstract:** In this article, a highly reliable radio frequency (RF) wake-up receiver (WuRx) is presented for electronic toll collection (ETC) applications. An intelligent digital controller (IDC) is proposed as the final stage for improving WuRx reliability and replacing complex analog blocks. With IDC, high reliability and accuracy are achieved by sensing and ensuring the successive, configurable number of wake-up signal cycles before enabling power-hungry RF transceiver. The IDC and range communication (RC) oscillator current consumption is reduced by a presented self-hibernation technique during the non-wake-up period. For accommodating wake-up signal frequency variation and enhancing WuRx accuracy, a digital hysteresis is incorporated. To avoid uncertain conditions during poor and false wake-up, a watch-dog timer for IDC self-recovery is integrated. During wake-up, the digital controller consumes 34.62 nW power and draws 38.47 nA current from a 0.9 V supply. In self-hibernation mode, its current reduces to 9.7 nA. It is fully synthesizable and needs 809 gates for its implementation in a 130 nm CMOS process with a 94 × 82 μm<sup>2</sup> area. The WuRx measured power consumption is 2.48 μW, has −46 dBm sensitivity, and a 0.484 mm<sup>2</sup> chip area.

**Keywords:** wake-up receiver; digital controller; reliability; electronic toll collection (ETC) system; dedicated short range communication (DSRC)
