**1. Introduction**

Recently, the radio frequency (RF) wake-up receiver has become an attractive research area for battery-operated transceivers in a variety of applications such as electronic toll collection (ETC) systems, wireless sensor networks (WSNs), wireless body area networks (WBANs), internet-of-things (IoTs), and wearable devices [1–4]. Nowadays, the ETC system (ETCS) is rapidly being adopted as an intelligent transportation solution in automotive vehicles. It uses a 5.8-GHz dedicated short range communication (DSRC) for a high speed radio link between a road side equipment (RSE) fixed at the toll gate and on-board unit (OBU) fitted inside the vehicle [1,5–7], as shown in Figure 1. Without stopping the vehicles, the toll is paid automatically and it saves time and eliminates tra ffic congestion on the roads. In ETCS, a wake-up receiver (WuRx) is an auxiliary RF receiver, additionally to the main RF transceiver, as shown in Figure 2, and is mandated due to the battery powered OBU. The WuRx is a pure asynchronous communication scheme and it maximizes data transceiver sleep time. This not only reduces OBU energy dissipation but also diminishes network latency. Figure 3 shows the asynchronous communication between RSE and OBU with WuRx. The reliability, false wake-up, power dissipation, and sensitivity are key considerations in WuRx design. In WuRx, designed with low power dissipation

and good sensitivity, false and poor wake-up turns on main transmitter and receiver modules, which reduces battery life and degrades the overall WuRx performance. The numerous WuRx circuits have been investigated in literature to optimize power consumption, maximize sensitivity, and improve reliability [8–11]. The various WuRx architectures are summarized in Figure 4. Based on the type of the power source, the WuRx is categorized in active and passive wake-up circuits. The active WuRx circuits are powered from a battery fitted on an OBU to monitor a possible wake-up signal. The energy for the wake-up circuit is harvested from the incident RF signal in passive receivers. Mostly, the active circuits adopt either RF envelope detector (RFED) structures [1,12,13], shown in Figure 4a,b, or frequency conversion architectures [14,15], depicted in Figure 4c. The frequency conversion based wake-up receivers o ffer higher sensitivity due to RF amplification before RF envelope detection [16], or local oscillator (LO) generation for down-conversion before amplification and envelope detection at intermediate frequency (IF) [14]. These circuits dissipate more power and occupy a larger area due to a power hungry phase-locked loop (PLL) and automatic channel scanning circuits for two channel receptions [15]. The majority of wake-up circuits are implemented with RFED because of its low power consumption using Schottky diodes [12,13] or metal–oxide–semiconductor field-e ffect transistor (MOSFET) operating in the weak-inversion region. The WuRx structure shown in Figure 4a uses an analog to digital converter (ADC) after a programmable gain amplifier (PGA) which occupies more area and increases power consumption. The WuRx shown in Figure 4b uses an analog band pass filter (BPF) at the output interface which requires more chip area. Figure 4c shows an envelope detector based WuRx structure with a front end amplifier and bulk acoustic wave (BAV) input network [17,18]. The WuRx in [19] also incorporates ADC at the output; however, in order to achieve better sensitivity and to reduce receiver noise, it incorporates a low noise amplifier (LNA) before an envelope detector and uses a double sampling technique. It o ffers better sensitivity at the cost of increased power consumption and larger chip area for WuRx. The passive WuRx structure [20] incorporates radio frequency to direct current (RF-DC) converter for harvesting energy from incident RF signals as shown in Figure 4d. For this purpose, an RF-DC converter [21,22] is employed to produce the envelope of the on–o ff keying (OOK) wake-up message signal, and at the same time, it e fficiently converts the RF carrier to a DC voltage in order to supply the comparator and the other WuRx circuits. Although this architecture is power e fficient, it exhibits low sensitivity. Furthermore, the deficiency of false and poor wake-up filtering is vulnerable.

**Figure 1.** The dedicated short range communication (DSRC) system overview with road side equipment (RSE) fitted at toll gate, battery operated on-board unit (OBU) fixed inside the vehicle, and a 5.8 GHz DSRC radio link as communication channel.

**Figure 2.** The DSRC OBU system level block diagram.

**Figure 3.** The road side equipment (RSE) and OBU pure asynchronous communication with the RF wake-up receiver (WuRx).

**(b)** 

**Figure 4.** *Cont*.

**Figure 4.** The previous wake-up receiver architecture: (**a**) RF envelope detector (RFED) based with analog to digital converter (ADC); (**b**) RFED based with band pass filter (BPF); (**c**) frequency conversion with LO; (**d**) passive circuit with RF-DC.

**(d)** 

The wake-up signal is categorized as a single wake-up tone of a bit sequence [23]. The bit sequence signal, also called identity-based wake-up, is widely used inWSN andWBAN for addressing a particular destination sensor node for unicasting. For broadcasting, single wake-up tone is adopted [23]. The DSRC wake-up signal is a 14 kHz OOK single tone signal of 15–17 cycles which is modulated with a 5.8 GHz carrier frequency [9].

The precise sensitivity control is essential for ETCS wake-up circuits [1]. Neither a very low nor very high sensitivity is intended. The available communication time will be insu fficient when WuRx sensitivity is lower than a minimum level. Similarly, if WuRx has very high sensitivity, it will turn on OBU and start communication even if vehicle is far away from a RSE and toll area. Moreover, very high sensitivity will result in communication failure and interrupts other OBU devices on the road. Therefore, WuRx sensitivity must be in a range, robust, insensitive to process, voltage, and temperature (PVT) variations [11].

The key characteristic of WuRx is to detect and ensure the presence of wake-up request in the received RF signal and decide whether to turn on the power hungry transceiver on OBU. In most previous studies, the WuRx circuits only identify the signal amplitude which is inadequate in ETC systems. If false and poor wake-up signals are not identified and filtered out in the WuRx circuit, these signals turn on power hungry main RF transceiver modules and the battery performance is degraded. In the past, numerous WuRx architectures have been investigated for improving the sensitivity and reducing the power consumption. However, false and poor wake-up problems have been left unaddressed. This paper presents a RFED based highly reliable WuRx. An intelligent digital controller (IDC) is proposed to ensure the WuRx reliability and accuracy by identifying and rejecting unwanted, false, and poor wake-up signals. It also replaces complex blocks such as ADC and BPF after amplifier and comparator [8–10,24] and reduces current consumption and area. Due to its digital nature, it is fully synthesizable, immune to noise and PVT variations [25], o ffers system flexibility, a wide dynamic range for wake-up and oscillator frequencies, and is adaptive to technology scaling.

The rest of the paper is organized as follows: Section 2 presents a proposed WuRx architecture overview. The detailed design of the proposed digital controller is described in Section 3. The tunable range communication (RC) oscillator is presented in Section 4. The RF front end and baseband analog processing is included in Section 5. Section 6 describes the experimental results. Lastly, the paper is concluded in Section 7.

#### **2. Proposed Wake-Up Receiver Architecture**

Figure 5 shows the proposed 5.8-GHz RF WuRx in which IDC is integrated to ensure its reliability and accuracy. An antenna receives the incoming RF signal and sends it to an o ff-chip pi-matching network. The matching network is an essential passive circuit to transfer the maximum RF signal power to the receiver circuit. The pi-matching network matches the antenna equivalent impedance with the input impedance of the proposed WuRx and ensures the maximum power transfer from the antenna to the WuRx circuit. Unlike [8,24], the chip internal matching network in addition to o ff-chip

pi-matching receives a RF wake-up signal, boosts voltage, and improves sensitivity and |*S*11|. The high gain RF envelope detector recovers the baseband wake-up signal and improves signal-to-noise ratio (SNR) without additional current consumption. The RFED is a critical circuit and it interfaces WuRx with the antenna, down-converts the amplitude of the modulated RF 5.8 GHz signal, and generates a 14 kHz baseband wake-up signal. The PGA provides flexibility to improve gain and amplify the baseband signal significantly. The main control unit (MCU) enables/disables and configures di fferent programmable parameters of RFED, baseband analog (BBA), comparator (COMP), and IDC. It can either be an on/off chip modem, externally controllable registers, or an external microcontroller. The comparator (COMP) generates digital output for IDC processing. An ultra-low power range communication (RC) oscillator (OSC) with a dynamic tuning range generates a configurable clock for the IDC block. The digital controller is proposed for ensuring WuRx reliability and accuracy by identifying and filtering non-wake-up signals. It is a fully synthesizable block, consumes very low power, and needs a very small chip area. The digital controller also replaces complex power consuming and large area interface blocks, such as ADC, BPF.

**Figure 5.** Proposed RF wake-up receiver architecture.

#### **3. Multi-Mode, Configurable Intelligent Digital Controller (IDC)**

In the DSRC WuRx design, other than high sensitivity and low power consumption, the false and poor wake-up signals identification is very crucial in order to extend OBU battery lifetime. This is achieved by filtering non-wake-up and noise signals and prohibiting turning on main power hungry RF transceiver. For this purpose, a novel, multi-mode, and configurable intelligent digital controller is proposed for ensuring WuRx reliability and accuracy. This controller is also a low power, small area digital replacement of complex, high power analog blocks such as ADC and a band pass filter. Di fferent parameters of wake-up, self-hibernation, digital hysteresis, wake-on, watch-dog timer, and self-test are fully configurable, which make the controller architecture very flexible and adaptive. The simplified architecture of a WuRx digital controller is illustrated in Figure 6 and the timing diagram is elaborated in Figure 7 for DSRC applications. The signal selection multiplexer (SSM) selects either a baseband wake-up signal, *WU\_SIG*, from the comparator output in normal operation or self-test signal *st\_sig*, generated from self-test pattern generator (STPG) during test mode. The signal positive edge generator (SPEG) detects rising transitions in the final selected signal *wusig* and generates a pulse signal *wu\_pe.* The finite state machine controller (FSMC) is the key building block of IDC which is designed as control unit and data path. It mainly senses, ensures, and generates the wake-up interrupt and filters unwanted signals. It controls other blocks such as the adaptive frequency measurement unit (AFMU), configurable watch-dog timer (CWDT), and wake-on generator (WOG). When enabled by FSMC (*fm\_en* = 1), the AFMU measures the frequency of the wake-up signal and determines by generating signal *fm\_det* if the input signal value is either within the configured range or not. It also ensures the valid successive number of configured (*WU\_N*) wake-up signal cycles. The CWDT, when enabled by signal *wdt\_en* from FSMC, starts a timer. The timer duration is configurable from the

*WDTN* parameter. It enhances IDC reliability and helps to avoid any halt situation during frequency measuring and signal ensuring states. If there is any abnormal situation, CWDT resets FSMC to its initial state when the configured timer expires. The WOG implements a pseudo-synchronous interrupt generation. When it is enabled, the wake-on interrupt WO\_INT is generated instead of the wake-up interrupt. The STPG enhances WuRx reliability by verifying IDC operation in self-test mode. When enabled (*st\_en* = 1), it is capable of generating a variety of valid and invalid signals with different frequencies and number of cycles. The output multiplexer (OM) outputs *WU\_INT* by selecting either internally generated interrupt signal *int\_r* or external manually control interrupt WU\_EXT. The control decoder (CDEC) decodes interrupt *int\_ctrl*, mode *mode\_ctrl*, and monitor *monitor\_ctrl* control signals from the external CTRL input.

**Figure 6.** RF WuRx intelligent digital controller (IDC) architecture.

**Figure 7.** RF wake-up and wake-on interrupt timing diagram.

#### *3.1. Self-Hibernation for Low Power Consumption*

A self-hibernation methodology with dynamic frequency and voltage scaling is introduced for reducing the IDC and oscillator power consumption during the non-wake-up interval. The average power consumption *PAV* in the CMOS circuit is the sum of dynamic *PDYN*, short circuit *PSHORT*, leakage *PLEAKAGE*, and static *PSTATIC* power consumptions [26] as explained in (1) as follows:

$$PAV = P\text{DYN} + P\_{\text{SHORT}} + P\_{\text{LEAKGE}} + P\_{\text{STATIC}}.\tag{1}$$

In CMOS circuits, *PDYN* is the dominant power consumption component. It is the linear function of operating frequency *f* and the quadratic function of the supply voltage *VDD* of the circuit as given in (2) as follows:

$$P\_{\rm DYN} = \mathbb{K}\mathbb{C}f V\_{\rm DD'}^2 \tag{2}$$

where *K* is switching activity factor, *C* is loading capacitance, and *VDD* is supply voltage [26].

From Equation (2) it becomes obvious that if the switching frequency reduces, the power consumption of the CMOS circuit is reduced significantly. Furthermore, if the supply voltage is minimized, the dynamic power is reduced. The OSC frequency is configurable from IDC. The IDC programs the OSC at a relatively higher frequency, *fWU*, and performs WuRx signal identification during the active interval. After the wake-up interval, it operates at a relatively very low frequency, *fSH*, during the sleep period after configuring the OSC for the slowest frequency. Since the communication between RSE and OBU is only for a very short duration and the OBU is in sleep mode for most of the time, the self-hibernation proves its significant impact for reducing WuRx power consumption and extending battery lifetime. The supply voltage is also reduced from 1.2 V to 0.9 V to save battery power.

#### *3.2. Built-In Self-Test for IDC Reliability*

For ensuring IDC reliability and accuracy, a built-in self-test technique is integrated. It verifies the IDC full operation and functional accuracy without the presence of an external RF wake-up signal. In the presented self-test scheme, a configurable self-test pattern generator module generates a variety of configurable wide range valid wake-up signals with a frequency described as follows in Equation (3):

$$f\_{ST} = \frac{N\_{ST}}{f\_{WU}}\tag{3}$$

where *fST* is test wake-up signal *st\_sig* frequency, which is programmable from the *NST* parameter. It is also capable of generating non-wake-up, false and poor wake-up, and noise signals during test mode and guarantees IDC functional accuracy and enhances overall WuRx reliability.

#### *3.3. Configurable Modes*

In the proposed IDC structure, two fully configurable modes are explored for WuRx. The wake-up mode (WUM) is for purely asynchronous wake-up signal detection from RSE with reduced latency. It processes the baseband recovered signal from the envelope detector after the comparator for identifying the wake-up signal. On the other hand, the wake-on mode (WOM) is an auxiliary pseudo-synchronous mode. When it is enabled, it turns on the main receiver for a very small configurable time interval, listens to any possible request from RSE, and keeps o ff for a relatively long duration. The mode control signal wake-up/-on (WUO) chooses the current selected mode. When WUO is low, a wake-up mode is enabled, which is the default mode. For enabling WOM, the WUO is configured as high.

#### 3.3.1. Wake-Up Mode

The FSMC is key building block of IDC, and its flow chart is elaborated in Figure 8. The wake-up mode with self-hibernation, digital hysteresis, and wake-up interrupt (WU-I) is the default flow in the wake-up period for ensuring WuRx reliability and accuracy. On power up, FSMC is in a wake-up self-hibernation (WUSH) state. The proposed self-hibernation technique reduces the power consumption of IDC and OSC significantly in the non-wake-up interval by configuring OSC to its lowest self-hibernation frequency, *fSH*. The dynamic power of a circuit is directly proportional to its operating frequency, as shown in (2). If the frequency reduces, the power consumption also reduces. When IDC detects high assertion on the *wusig* signal during self-hibernation, it configures OSC to its normal wake-up frequency, *fWU*, and waits for OSC settling in the WUSH state. The *fWU* is a much higher frequency than *fSH* for achieving higher wake-up signal measuring accuracy. The controller starts sensing a wake-up signal in the wake-up signal sense (WUSS) state. The SPEG detects *wusig* every rising edge and generates a *wu\_pe* pulse signal which is sensed in the WUSS state. The controller enables CWDT by asserting a high *wdt\_en* signal. The CWDT provides a self-recovery mechanism for FSMC and it is enabled to avoid uncertain situations and improve IDC reliability. If *WU\_SIG* is a noise pulse or glitch, it is identified and filtered out at this stage and FSMC moves back to WUSH for self-hibernation. After the sensing stage, the controller clears CWDT by asserting a high *wdt\_clr* signal for one clock cycle and moves to next state. The IDC verifies the *WU\_SIG* signal in the wake-up signal assurance (WUSA) state. The AFMU evaluates *WU\_SIG* each cycle and confirms if its frequency *fSIG* is in a configured range. The integrated configurable digital hysteresis technique accomplishes this task and accommodates wake-up frequency variations to improve reliability. The *WU\_SIG* is a valid signal if its frequency fulfills the following condition described in (4) as follows:

$$f\_{\text{MOD}\,\,MIN} \ge f\_{\text{SIG}} \le f\_{\text{MOD}\,\,\text{MAX}\,\,\nu} \tag{4}$$

where *fMOD.MIN* and *fMOD.MAX* are the lower and upper limits of the valid WuRx signal modulation frequencies. These limits are configurable by parameters *NNFX* and *NXFN*, respectively, and are described as follows in (5):

$$f\_{\text{MOD.MIN}} = \frac{f\_{\text{WU}}}{N\_{\text{XFM}}},\tag{5a}$$

$$f\_{\text{MODMAX}} = \frac{f\_{\text{WI}}}{\text{NNF}}.\tag{5b}$$

The configurable successive number of wake-up signal cycles, *WUN*, in the allowed frequency bandwidth are ensured in the WUSA state. If the *WU\_SIG* WuRx signal frequency is not in the allowed range as described in (4) or the signal cycles are less than *WUN*, then it means the signal is not a valid wake-up signal and a main transceiver must remain off to save power. The false and poor wake-up signals are identified and filtered out in the WUSA state by AFMU and CWDT successfully. If a non-wake-up signal is identified in this state, the controller moves back to a self-hibernation state. After sensing and assurance, the wake-up interrupt *WU\_INT* is initiated for configurable *THOLD* duration in the wake-up interrupt generation (WUIG) state. The interrupt hold duration is defined as follows in (6):

$$T\_{HOLD} = \frac{N\_{HOLD}}{f \text{\textquotedblleft}},\tag{6}$$

where *NHOLD* is the configurable parameter for defining wake-up interrupt hold duration. After the interrupt generation, FSMC remains silent for the *TSILENT* interval in the wake-up silent (WUS) state and moves back to the WUSH state. The WUS state prohibits the WuRx to detect the current wake-up signal again if *WUN* and *THOLD* parameters are configured to smaller values. The silent interval is programmable from parameter *NSILENT* according to (7) as follows:

$$T\_{SILENT} = \frac{N\_{SILENT}}{f\_{WUI}}.\tag{7}$$

If wake-up monitoring (WU-M) is enabled by signal *monitor\_ctrl,* then the FSMC moves to the wake-up interrupt enable (WUIE) state after confirming *WUN* wake-up signal cycles in the WUSA state. It asserts *WU\_INT* high and moves to the wake-up monitoring (WUSM) state. The controller continuously evaluates *WU\_SIG* for the presence of a valid wake-up signal and it additionally provides *WU\_INT* for the entire duration of the wake-up signal instead of *THOLD*. It gives more space to MCU to detect interrupt and trigger an acknowledge signal to RSE at the end of the wake-up signal. The proposed WUM guarantees to pass only a valid wake-up signal and it definitely identifies and filters out all non-wake-up signals. It ensures the accuracy and reliability of WuRx. The IDC turns on a main heavy powered transceiver at OBU only with a valid wake-up request from RSE.

**Figure 8.** WuRx intelligent digital controller (IDC) finite state machine controller (FSMC) flow diagram.

#### 3.3.2. Wake-On Mode

The pseudo-synchronous wake-on mode (WOM) enhances overall reliability of transceiver in case of an issue in the main WuRx path. When WOM is enabled, the IDC configures OSC to desire frequency *fWO* based on configured parameters in the wake-on oscillator configuration (WOOC) state, as shown in Figure 8. The wake-on interrupt *TWOI* and wake-on sleep *TWOS* intervals are computed according to (8) and (9), respectively, as follows:

$$T\_{\rm WOI} = \frac{N\_{\rm WOI}}{f\_{\rm WO}} \, ^\circ \tag{8}$$

$$T\_{\rm WOS} = \frac{N\_{\rm WOS}}{f\_{\rm WO}}.\tag{9}$$

After frequency configuration and OSC settling, the controller moves to a wake-on interrupt (WOI) state. In this state, *WO\_INT* is asserted high for the *TWOI* duration and MCU turns on the main receiver for intercepting any communication request from RSE. After the *TWOI* interval, FSMC jumps to a wake-on sleep (WOS) state. The *WO\_INT* is asserted low and MCU turns off the main receiver for the programmed *TWOS* duration. After a sleep interval, the controller moves back to the WOI state and periodically generates configurable wake-on interrupt *WO\_INT* for receiver.

#### **4. Ultra-Low Power Configurable RC Oscillator**

In the proposed WuRx, an ultra-low power configurable RC oscillator is integrated, which is the clock source for IDC. The RC oscillator structure is adopted rather than the crystal oscillator due to its low cost, less power consumption, fast start-up interval, and easy on-chip integration [27]. The fabricated oscillator has a wide controllable tuning range, *fCLK.MIN*~*fCLK.MAX*, and IDC configures it for di fferent frequencies in wake-up, self-hibernation, and wake-on mode by controlling its capacitance values. For ultra-low power applications, the circuits are preferred to be operated in a weak inversion region, also known as the sub-threshold region [28,29]. Therefore, the oscillator is designed to operate in a sub-threshold region. Figure 9 shows the ultra-low power RC oscillator [27]. The configurability for various frequencies is achieved by altering resistance *R* and capacitance *C* values from IDC. This oscillator is composed of current reference, start-up, capacitor charge/discharge sensing circuits, and a frequency generation part. The current source or sink circuit is preferable to function in a weak inversion region for low power operation. The MOS transistor is operating in a sub-threshold region when the drain current *ID* flows and the gate to source voltage *VGS* is less than the threshold voltage *VTH*. The di ffusion current between source and drain mainly contributes to this current. The start-up circuit prohibits self-biased circuits to work at a zero biasing point. To enhance current sink or source output resistance, the current mirrors in a cascade structure are used. This generated current is mirrored by the current mirror and fed to capacitor, hysteresis controller *M*1, and current-starved invertors for clock generation. The drain current *I* charges the capacitor *C*, and when *VC* becomes equal to hysteresis controlling transistor *M1 VTH* value, the *M*1 turns on. For clock frequency generator circuit, the voltage *VC* across capacitor *C* linearly increases with the increase in current *I* when constant current flows into the capacitor, as described in (10) as follows:

$$
\Delta V\_{\mathbb{C}} = \frac{I \Delta t}{\mathbb{C}}.\tag{10}
$$

**Figure 9.** Ultra-low power configurable range communication (RC) oscillator.

The transistor *M*1 logical *VTH* also controls capacitor voltage. Hence, the capacitor *C* charging and discharging duration is controlled by current *I* and transistor *M*1, and a triangular voltage waveform is generated for the capacitor. From (10), single charging or discharging cycle time Δ*t* is given in (11):

$$
\Delta t = \frac{C \Delta V}{I}.\tag{11}
$$

The current mirror builds a constant current source as a current generator part. The voltage *VR* is always stabilized by the feedback path. Hence, according to Ohm's law, the resistance *R* decides the amount of current. Thus, from (11), the generated clock period *TCLK* is described in (12) as follows:

$$T\_{\mathbb{C}\mathbb{L}K} = 2\text{RC}\frac{\Delta V\_{\mathbb{C}}}{V\_{\mathbb{R}}}.\tag{12}$$

The RC oscillator output frequency *fCLK* is given in (13) as follows:

$$f\_{\rm CLK} = \frac{1}{T\_{\rm CLK}} = \frac{1}{2RC} \cdot \frac{V\_R}{\Delta V\_C} \,. \tag{13}$$

The capacitance *C* is designed as unit weighted capacitor bank, and IDC configures this capacitor back at di fferent values for generating frequencies *fWU*, *fSH*, and *fWO* for the wake-up mode, self-hibernation, and wake-on mode, respectively.

#### **5. RF Front End and Baseband Processing**

The RF front end in the proposed WuRx is composed of a high sensitivity RF envelope detector with an embedded internal matching network. The RFED-based approach is most common for designing a WuRx circuit for its low current consumption. With this scheme, the requirement of a LO generation for frequency down-conversion and RF amplification is also eliminated at the cost of reduced sensitivity. The internal matching improves sensitivity of the circuit. The RFED is the key building block in the WuRx circuit for interfacing with an antenna through a matching network and generating a baseband output signal by down-converting the input amplitude-modulated RF signal. Figure 10 illustrates the proposed RF envelope detector circuit with internal matching network [18,30]. The circuit is mainly composed of nonlinear transistor element *M*1, input signal DC blocking capacitor *Cac*, self-biasing feedback resistor *Rf*, impedance matching network with gate inductor *Lg*, and excess capacitor *Cex*. The impedance matching network provides passive voltage amplification. With large self-biasing resistance, when RF input signal is not present, the *M*1 gate to source voltage *Vgs* is closed to transistor threshold voltage *VTH* with a very negligible biasing current. In this way, the limited sensitivity issue due to *VTH* loss is compensated. The *Rf* is designed with a pseudo-resistor for large resistance with minimized parasitic capacitance and a small area. It perfectly isolates output voltage *V*0 from RF input signal *VRF* and prevents envelope detector loading. When *VRF* is applied, the drain current *I*1 exponentially increases while the biasing current supplied from *M*2 is almost constant.

**Figure 10.** RF envelope detector with internal matching and self-biasing feedback resistor.

The capacitor *CO* discharges and this discharge current decreases *VO* until *I*1 and *I*2 become almost equal. This generates a 180◦ phase shift between *VRF* and *VO*. The convergence gain *GC*, defined as the ratio of output baseband signal voltage amplitude to the RF input signal voltage amplitude, is evaluated as follows in (14):

$$G\_{\mathbb{C}} = \frac{1}{4} \frac{Q^2 I\_1}{\left(nLI\_T\right)^2} r\_{0\prime} \tag{14}$$

where *Q* is quality factor of the matching network, *n* is sub-threshold slope factor, *UT* is thermal voltage, and *r*0 is intrinsic output impedance.

The baseband signal *VBB* produced by the RF envelope detector is subsequently processed for enhancing amplitude by a programmable gain baseband amplifier and a comparator before it is fed to IDC for digital processing for generating an interrupt signal. Figure 11 shows the PGA circuit that is a baseband amplification stage. It has high input impedance and its gain is configurable from external MCU. It provides flexibility for improving gain and amplifies the baseband signal *VBB* significantly.

**Figure 11.** Programmable gain amplifier.

The hysteresis comparator, shown in Figure 12, is the final stage of baseband processing to generate a digital signal for IDC processing. It is composed of a positive feedback circuit with an amplifier, AMP. A two stage amplifier with output inverter [31] is used as a low power CMOS amplifier. With feedback resistor *R*2, hysteresis upper and lower threshold values are configured for eliminating multiple transitions caused by noise. The three stage amplifier is composed of a differential amplifier, common source amplifier, and an output inverter. The analog differential input signals *IN*− and *IN*+ are applied at differential pair *M*1 and *M*2. The differential pair transistor width is increased to reduce input offset voltage and increase gain. To minimize the propagation delay and reduce common source transistor *M*7 gate parasitic capacitance, the *M*7 is designed with a small size. The final inverter stage also enhances gain and improves the comparator slew rate. The final digital wake-up comparator output signal *WU\_SIG* is fed to IDC for digital processing. The RF front end and analog baseband processing processes all signals and it does not filter or remove any non-wake-up signal. The IDC differentiates between actual wake-up signals and unwanted signals.

**Figure 12.** Hysteresis comparator with positive feedback and amplifier.

#### **6. Experimental Results**

The presented WuRx is integrated in a DSRC transceiver for ETCS applications. It is fabricated with a 130 nm CMOS process. Figure 13 shows the microphotograph of WuRx and magnified IDC layout. The WuRx occupied chip area is 532 × 910 μm<sup>2</sup> of which IDC takes only 94 × 82 μm2. The WuRx is measured extensively to ensure its reliability and accuracy. The experimental lab environment is captured in Figure 14a and the measurement board with the fabricated DSRC transceiver chip is depicted in Figure 14b. The board is powered up from the Agilent® DC Power Supply with 5 V and the on-chip low dropout regulator (LDO) generates 0.9 V for the WuRx circuit, which is measured at the output pin with a digital multi-meter (DMM). The lower supply voltage is used to minimize the power consumption and all blocks, and correct operation is verified at a supply voltage of 0.9 V. The OOK baseband wake-up signal is generated from the Tektronix® AFG3101 Function Generator and modulated at 5.8 GHz with the Agilent® E4438C Signal Generator. This modulated RF signal is fed at a *RF\_IN* SMA input connector on the board and after passing through external pi-matching network, package pin, and die PAD, it enters the WuRx circuit. The comparator output *WU\_SIG* and wake-up interrupt *WK\_INT* are plotted on a Tektronix® DSA71254C Digital Serial Analyzer. Different parameters and configurations are programmed through SPI and the graphical user interface (GUI) running on computer.

**Figure 13.** WuRx chip microphotograph and magnified IDC layout.

**Figure 14.** WuRx measurement: (**a**) experimental lab setup; (**b**) measurement board with chip.

The IDC performance is summarized in Table 1. The proposed digital controller is fully synthesizable. With an area of 0.007 mm<sup>2</sup> and a 34.62 nW power consumption, it not only ensures WuRx reliability and accuracy but also replaces complex and power hungry analog blocks such as BPF and ADC. The configurability, operating modes, digital hysteresis, and self-hibernation features prove its sublimity. The power consumption with and without self-hibernation for IDC and OSC and its

effect on overall WuRx power performance is summarized in Table 2. Since the DSRC communication between RSE and OBU lasts for a very short interval and the OBU is in sleep mode most of the time, self-hibernation by voltage and frequency scaling has a significant positive impact on battery performance. The performance comparison of the proposed WuRx with the existing designs is listed in Table 3. The wake-up circuits in [8,24] integrate the complex BPF and [9] use the frequency detector (FD) circuit as its interface output stage without ensuring reliability and filtering of non-wake-up signals. The proposed WuRx architecture incorporates a fully synthesizable intelligent controller, which is not only area and power efficient but it also ensures unwanted signals filtering, guarantees WuRx reliability, and improves battery performance. The measurement results report an almost identical sensitivity of −46 dBm and a power consumption of only 2.48 μW.


**Table 1.** IDC performance summary.

Without and with self-hibernation.

**Table 2.** Power consumption summary with and without self-hibernation.



**Table 3.** WuRx performance comparison.

1Configurable for any specific range. \* Without self-hibernation.

The WuRx accuracy and reliability is verified by applying various RF-modulated valid and invalid signals with different amplitudes and frequencies at the *RF\_IN* input. When the input signal is valid, meaning its amplitude is greater than the sensitivity and its frequency is in a configured hysteresis range, the WuRx gives out confirmed wake-up interrupt signal. In the measurement results in Figure 15a, initially random, invalid OOK sequence, modulated at 5.8 GHz, with a sensitivity of −46 dBm is applied at the *RF\_IN* input. The baseband signal is successfully recovered by RFED and the digital *WU\_SIG* from COMP is fed to IDC. As it is clear from the results, the IDC identifies this invalid sequence and does not generate a confirmation signal. Later, the valid wake-up signal is ensured and

verified by IDC. If IDC is not used at the comparator output, then WuRx reliability degrades as the main power hungry receiver is turned on, even with a non-wake-up signal. The consecutive burst of valid wake-up signals, as shown in Figure 15b, with exactly 14 clock cycles at 14 kHz is applied for proving proposed WuRx robustness, accuracy, and reliability. For each time, *WU\_INT* is generated for approximately 1 ms after confirming five clock cycles (*WUN* = 5) and IDC returns to its ideal state for the next wake-up signal sensing.

**Figure 15.** WuRx measurement result: (**a**) initially, invalid random sequence and then valid wake-up signal; (**b**) wake-up valid signal burst for robustness testing.

Figure 16 shows different WUM measurement results for various scenarios. In this measurement, *WUN* is set to 5 and digital hysteresis, watch-dog timer, and *THOLD* are configured to 11~18 kHz, 142.8 μs, and 1 ms, respectively. The OSC is configured for wake-up and self-hibernation frequencies of 140 kHz and 14 kHz, respectively. Figure 16a,b show WUM with WU-I and WU-M configurations, respectively, in which the *WU\_SIG* frequency is 14 kHz. The *WU\_INT* is generated after sensing and confirming five successive *WU\_SIG* clock cycles. In normal WUM, IDC and OSC current consumption from a 0.9 V supply is 38.47 nA and 214 nA, which reduces to 9.7 nA and 107 nA in self-hibernation, respectively. The self-test is measured in Figure 16c in which the *st\_sig* signal of 14 kHz is generated by STPG.

Figure 17 summarizes WuRx measurement results with false, poor, invalid signals. Figure 17a,b shows results when the *WU\_SIG* frequency is out of the configured hysteresis range (11 kHz~18 kHz in this case) and identifies false wake-up signals. Poor and false wake-up and noise signals are also perfectly identified and *WU\_INT* is not generated. The signal with a valid frequency but insufficient number of cycles (less than *WUN* = 5) is identified and filtered accurately by IDC, as shown in Figure 17c. Similarly, noise pulses and glitches in the RF signal are converted to a baseband digital signal and sensed and removed by IDC without generating interrupt and prohibits turning on the power hungry main receiver. If IDC is not integrated, then all these invalid signals are identified as wake-up signals, and as a consequence, power on transceiver falsely and degrading battery performance.

The WOM measurement result is depicted in Figure 18 in which *TWOI* and *TWOS* intervals are set for 65 ms and 0.65 s by configuring *NWOI* = 91 and *NWOS* = 91,000 according to (8) and (9), respectively.

The measured tuning range of OSC is captured in Figure 19. The OSC capacitor *C* is implemented as binary weighted capacitor bank which is controlled from an 8-bit *OSC\_CTRL* signal from IDC. The measured *fCLK.MIN* and *fCLK.MAX* frequencies are 12.16 kHz and 362.37 kHz when *OSC\_CTRL* values

are all high and all low, respectively, with a total frequency range Δ*fCLK* of 350.21 kHz. The spectrum also shows the WUM frequency which is configured as approximately 140 kHz. In self-hibernation mode, the OSC frequency *fSH* is configured to about 14 kHz. The WOM clock frequency depends on the configured parameters for *TWOI* and *TWOS* intervals. At *fWU* of 140 kHz, it draws 214 nA current from 0.9 V supply which is reduced to almost half in self-hibernation mode.

**Figure 16.** WuRx measurement results for different IDC wake-up modes with valid signals: (**a**) wake-up interrupt (WU-I); (**b**) wake-up monitoring (WU-M); (**c**) self-test with WU-I mode.

**Figure 17.** WuRx measurement results for invalid signals and IDC identification and filtering: (**a**) invalid wake-up signal with modulation frequency of 9 KHz, which is less than the minimum hysteresis configured limit of 11 kHz; (**b**) invalid wake-up signal with modulation frequency of 20 KHz, which is greater than the maximum hysteresis configured limit of 18 kHz; (**c**) poor wake-up signal with valid modulation frequency but less number of cycles than the configured value of 5; (**d**) invalid signal of noise pulse.

**Figure 18.** Wake-on mode measurement result: (**a**) Wake-on sleep of 0.65 s duration when *NWOS* is configured with value of 91,000; (**b**) wake-on interrupt of 65 ms when NWOI is configured as 91.

**Figure 19.** Oscillator (OSC) frequency range and measurement result.

Figure 20 shows the measured reflection co-efficient, |*S*11|, for the proposed WuRx. The measured value of |*S*11| at 5.8 GHz is about −25.622 dB, which shows the excellent matching. Moreover, |*S*11| values at 5.75 GHz and 5.85 GHz are −17.138 dB and −12.876 dB, respectively.

Figure 21 summarizes the detailed IDC post place and route (P&R) simulation results using the NC-Verilog® tool. The wake-up interrupt mode simulation result is shown in Figure 21a in which *WU\_SIG* with different frequencies is applied. It is clear from the simulation results that when the wake-up signal is either less or greater than the configured hysteresis range (11 kHz~18 kHz), it is identified and filtered out without generating interrupt at *WU\_INT*. The self-test simulation with one of the configurations is shown in Figure 21b. The STPG generates a variety of valid and invalid signals for ensuring the functional accuracy of IDC. Instead of a baseband digital *WU\_SIG* signal, the test wake-up signal *st\_sig* is generated internally by STPG. The IDC accurately generates interrupt *WU\_INT* after identifying and verifying the signal, as shown in Figure 21b. The self-test enhances the reliability of IDC itself. The WOM simulation is depicted in Figure 21c in which *TWOI* and *TWOS* intervals are set for 20.8 ms and 0.65 s by configuring *NWOI* = 2912 and *NWOS* = 91,000 according to (8) and (9), respectively.

**Figure 20.** RF external on board impedance matching measurement result.


**(a)** 

**(b)** 


**Figure 21.** The IDC post place and route (P&R) simulation result: (**a**) WU/WU-I with different wake-up frequencies; (**b**) self-test with WU\_I; (**c**) wake-on mode with interrupt and sleep durations of 20.8 ms and 0.65 s.
