**3. Results**

The CDC operation principle is analysed for the first time in Section 3.1, while its implementation in the commercial 180 nm CMOS technology is presented in Section 3.2, followed by detailed electrical simulation in Section 3.3.

#### *3.1. Principle of Operation*

The CDC operation consists of the discharge of the capacitance *CS* between two voltage levels, *VH* and *VL*, with *VH* being the precharge value and *VL* the value assumed at the end of the conversion (see Figure 2). For the sake of a clearer explanation, let us assume that *CS* has one of its terminals connected to the ground. The conversion operation starts by the falling edge of the precharge signal. The discharging of *CS* supplies the attached ring oscillator (RO), simply implemented by inverter gates, which starts oscillating at a frequency determined by its supply voltage (*VC*). The output of the RO is the frequency modulated two-level signal *p*(*t*), whose instantaneous oscillation frequency encodes the amplitude *VC*. The integral of this quantity is the phase *ϕ*, which is updated at every cycle as shown in Figure 2b. The oscillation frequency decreases by decreasing *VC* since the overdrive voltages of the logical gates are decreasing, thus slowing the charge of the next gate in the ring.

**Figure 2.** Simplified CDC operation based on a voltage level comparator: (**a**) block-level schematic diagram comprising an *RC*-circuit equivalent of the RO; (**b**) chronograms of the most important signals.

While the oscillation edge completes a loop, i.e., *ϕ* completes a full cycle, the RO absorbs a certain amount of charge from *CS*, which causes *VC* to decrease in time. An asynchronous counter keeps track of the number of loops. Finally, *VC* reaches the *VL* level, eventually detected by a voltage comparator set to the *VL* threshold, which, in turn, produces the end-of-conversion signal (eoc) used also to strobe the counter value (dout) into an output register.

Since each loop consumes a certain quantity of charge *q*[*i*] (at *i*-th loop), the following relationship must hold:

$$\sum\_{i=1}^{N} q[i] + q\_c = \mathbb{C}\_S (V\_H - V\_L)\_\prime \tag{1}$$

where *N* is the number of loops during the discharge, and *q* is the residual error due to the last incomplete loop.

The heuristic conclusion drawn in [17] is that *N* is proportional to *CS* apart from the quantization error *q*/(*VH* − *VL*). Nevertheless, Equation (1) does not give any support to this conclusion since the relation between *N* and *CS* is not explicit. Moreover, since the RO supply voltage-to-frequency characteristic is generally non-linear, the capacitanceto-digital conversion law is not evident. An explanation of the principle of conversion is given in [24]; however, some unverified assumptions were made to simplify the analysis, which, on the other hand, may lead to wrong interpretations about the linearity of the conversion characteristic.

In order to show the linear relationship between *CS* and *N*, let us consider the *RC* circuit represented in Figure 2a, where the parameters *R*RO and *C*P were introduced. The parameter *C*P represents any parasitic capacitance due to the RO and the precharge switch added to the discharge node, while *R*RO models the charge absorption rate at each voltage value *VC*. It is important to note that during the full RO cycle, charge is impulsively absorbed due to the sequential switching of the digital gates, causing *VC*(*t*) to resemble a staircase shape. Hence, an effective current *IC per* cycle can be defined, accounting for the amount of charge *q* in the interval of time defined by the *p* period. In our approach, *VC*(*t*) interpolates the actual staircase, allowing for a continuous-time description of the circuit behaviour as in Figure 2b. Hence, *R*RO is simply the ratio between the interpolated *VC* and *IC*. It is convenient to express *R*RO and *C*P as

$$R\_{\rm RO}(V\_{\rm C}) = R\_0 \, u\_{\rm RO}(V\_{\rm C}) \qquad \text{and} \qquad \mathbb{C}\_{\rm P}(V\_{\rm C}) = \mathbb{C}\_0 \, u\_{\rm P}(V\_{\rm C}), \tag{2}$$

being that *R*0 = *<sup>R</sup>*RO(*VH*), *C*0 = *<sup>C</sup>*P(*VH*) and the functions *<sup>u</sup>*RO(*VC*) and *<sup>u</sup>*P(*VC*) are positive and continuous in the (*VL*, *VH*) interval such that *<sup>u</sup>*RO(*VH*) = 1 and *<sup>u</sup>*P(*VH*) = 1. The charge absorption rate modelled by *R*RO is determined basically by two mechanisms: (i) charge is absorbed due to inter-stage charging within the RO, and (ii) charge is absorbed due to short-circuit currents in the digital gates of the RO at transition times.

The Kirchhoff's law of currents applied to the simple *RC* circuit of Figure 2 gives

$$\frac{d\left((\mathbb{C}\_S + \mathbb{C}\_P)V\_\mathbb{C}\right)}{dt} = -\frac{V\_\mathbb{C}}{R\_{\text{RO}}},\tag{3}$$

where the total charge *Q* = (*CS* + *<sup>C</sup>*P)*VC* is subjected to variations in time due to both *VC*(*t*) and *CS*(*t*), being that the latter is the dynamic component of the capacitive sensor (i.e., the capacitively transduced signal to be converted). This can be neglected when

$$\frac{1}{|\mathcal{C}\_S + \mathcal{C}\_P|} \left| \frac{d\mathcal{C}\_S}{dt} + \frac{d\mathcal{C}\_P}{dt} \right| \ll \left| \frac{1}{V\_C} \frac{dV\_C}{dt} \right|,\tag{4}$$

meaning that at any time point during the conversion, the variations of *CS* and *C*P relative to the total capacitance *CS* + *C*P are much smaller than the relative variation of *VC*. Such a condition is typically found in a large class of capacitive sensors, where the capacitively transduced signal varies slowly compared to the conversion time *T*conv. Under this hypothesis, (3) can be simplified in order to obtain

$$\left(1 + \frac{\mathbb{C}\_0}{\mathbb{C}\_S} \mu\_\mathcal{P}(V\_\mathbb{C})\right) \mu\_{\text{RO}}(V\_\mathbb{C}) \frac{dV\_\mathbb{C}}{V\_\mathbb{C}} = -\frac{dt}{\tau} \quad \text{and} \quad \tau = R\_0 \mathbb{C}\_S. \tag{5}$$

Note that in a linear *RC* circuit, i.e., where both *R*RO and *C*P are independent from *VC*, Equation (5) describes the known exponential relaxation of *VC*(*t*), determined by the time-constant *τ*. The analytical and/or numerical solution of Equation (5) is, in principle, viable once *<sup>u</sup>*RO(*VC*) and *<sup>u</sup>*P(*VC*) are known, either from an analytical insight on a particular RO topology, or directly from fitting simulation data.

The number of counts *N*, stored in dout, is determined by the accumulation of cycles during *T*conv, which is related to the accumulated phase *ϕ* as follows:

$$\varrho(T\_{\rm conv}) = 2\pi \int\_0^{T\_{\rm conv}} f\_{\rm osc}(t) \, dt \qquad \text{and} \qquad N = \lfloor \frac{\varrho(T\_{\rm conv})}{2\pi} \rfloor,\tag{6}$$

being that *fosc* is the instantaneous oscillation frequency of *p*(*t*). The operator *x* indicates the floor operation on the variable *x*. Since *fosc* is dependent on *VC*, we can elaborate Equation (6) as

$$N = \lfloor \int\_0^{T\_{\rm conv}} f\_{\rm osc}(t) \, dt \rfloor = \lfloor R\_0 \mathcal{C}\_S \int\_{V\_\mathcal{L}}^{V\_\mathcal{H}} \left( 1 + \frac{\mathcal{C}\_0}{\mathcal{C}\_S} u\_\mathcal{P}(V\_\mathcal{C}) \right) u\_{\rm RO}(V\_\mathcal{C}) f\_{\rm osc}(V\_\mathcal{C}) \frac{dV\_\mathcal{C}}{V\_\mathcal{C}} \rfloor, \tag{7}$$

where the differential *dt* and the time constant *τ* are substituted with their respective expressions given in Equation (5). For better readability, Equation (7) can be rewritten as

$$N = \lfloor k\_{\mathbb{G}} C\_{\mathbb{S}} + k\_{\mathbb{G}0} C\_0 \rfloor,\tag{8}$$

where

$$k\_{\rm G} = R\_0 \int\_{V\_{\rm L}}^{V\_H} \frac{u\_{\rm RO}(V\_{\rm C}) f\_{\rm osc}(V\_{\rm C})}{V\_{\rm C}} \, dV\_{\rm C}; \quad k\_{\rm G0} = R\_0 \int\_{V\_{\rm L}}^{V\_H} \frac{u\_{\rm P}(V\_{\rm C}) u\_{\rm RO}(V\_{\rm C}) f\_{\rm osc}(V\_{\rm C})}{V\_{\rm C}} \, dV\_{\rm C}. \tag{9}$$

The expressions in Equations (8) and (9) remarkably show that *N* is linearly dependent to the input *CS* through the conversion gain *kG* regardless of the oscillator implementation, as long as *fosc* > 0. An offset term, *kG*0*C*0, is also present due to any parasitic capacitance added to the precharge node.

The quantization error *Q* is

$$
\epsilon\_Q = \frac{\varrho(T\_{\rm conv})}{2\pi} - N = k\_G \mathcal{C}\_S + k\_{G0} \mathcal{C}\_0 - \left\lfloor k\_G \mathcal{C}\_S + k\_{G0} \mathcal{C}\_0 \right\rfloor. \tag{10}
$$

Clear design guidelines can be obtained from the expression of *kG* of Equation (9) under the following simplifying assumptions. First, let us assume the following relationship between *fosc* and *VC*, describing the linearised behaviour of the RO:

$$f\_{\text{osc}} = f\_0 + k\_{\text{osc}} V\_{\text{C}\prime} \tag{11}$$

where *f*0 is the frequency bias and *kosc*, given in [s−1V−1], is the voltage sensitivity coefficient. A second simplification regards the *<sup>u</sup>*RO(*VC*) function introduced in Equation (2), which is approximated to an effective constant value *u*-RO ≥ 1 across the whole interval (*VL*, *VH*):

$$
\mu\_{\rm RO}(V\_{\mathbb{C}}) = \mu\_{\rm RO^{\prime}}^{\star} \quad \text{for} \quad V\_{L} \le V\_{\mathbb{C}} \le V\_{H}. \tag{12}
$$

Under the assumptions (11)–(12), the integral of Equation (9) is simplified to

$$k\_{\rm G} = R\_0 u\_{\rm RO}^{\star} \cdot \left( f\_0 \log \frac{V\_H}{V\_L} + k\_{\rm osc} \cdot (V\_H - V\_L) \right). \tag{13}$$

The quantization error referred to as *CS*, i.e., *<sup>ε</sup>Q*/*kG*, is reduced by increasing *kG* (Equation (10)). Therefore, the simplified expression of *kG* suggests the following design guidelines:

1. *kG* is increased by increasing the *R*0*u*-RO term, which is related to both the *W*/*L* aspect ratio and the area *WL* of the digital ports and the number of delay stages of the inverter-based RO. The short-circuit current, which contributes to *IC*, is reduced by increasing *L*; however, the short-circuit time interval is minimized by reducing the total area. So for a given gate area *WL*, it is convenient to reduce the *W*/*L* ratio. Clearly, incrementing the number of delay stages increases the discharge rate in each cycle, thus reducing *R*0*u*-RO.


Points 1 and 2, in principle, may lead to divergent design indications as far as the *L* of the digital gates is concerned. For this reason, the optimal solution can be obtained by performing electrical simulations, where *L* is swept across a reasonable interval that includes *Lmin*.

Regarding the contribution of the comparator physical noise affecting the architecture shown in Figure 2, we can consider the comparator root-mean-square noise *Vn*,cmp. At the end of the conversion, *VC* will pass the *VL* threshold with a certain slope, so

$$N\_{\rm n,comp,motor} \simeq f\_{\rm osc}(V\_L) \frac{V\_{\rm n,cmp}}{d V\_{\rm C} / dt \vert\_{t=T\_{\rm conv}}} \simeq \text{tr} \, f\_{\rm osc}(V\_L) u\_{\rm RO}(V\_L) \frac{V\_{\rm n,cmp}}{V\_L},\tag{14}$$

The last part of the approximation is found elaborating Equation (5)—which also gives the definition of *τ*—and neglecting, for the sake of simplicity, the contribution of *C*P. Equation (14) describes the relationship between the comparator noise and the fluctuation on the conversion code, but most importantly, it establishes also a linear relationship between this fluctuation and the capacitance value through *τ* = *R*0*CS*. This is a very remarkable property of this converter type since the effects of one of the most important sources of physical noise scale proportionally with the quantity to be converted. This also suggests that no particular effort is to be put in the comparator design.

The architecture represented in Figure 2 is based on a continuous-time voltage-domain comparator whose noise effects are analysed in Equation (14). The next step in our analysis is the introduction of the time-domain comparator used in [17], which allows for a fullydigital implementation of the CDC—clearly advantageous since it nulls any static current consumption (except leakage current components).

In order to understand this step, let us consider the synchronized delay-chain RO shown in Figure 3b, derived from the simple RO of Figure 3a. Here, the time-encoded signals, *A*1 and *A*2, are originated by two separate delay chains. The following Xnor gate asserts the Boolean " *A*1 == *A*2" condition, i.e., both signals present the same logic level, so allowing the propagation of the oscillator travelling edge. In a scenario where the travelling edge of *A*2 lags the one of *A*1, this assertion permits their synchronization at the Nand gate before closing the feedback loop. Figure 3c shows the chronogram details of the oscillator signals *A*, *A*1, *A*2 and *B*.

In the actual CDC operation, *A*2 is generated by the reference delay chain fed at *VL*, while *A*1 is generated by the sensing delay chain, fed at *VC*. So, while *VC* > *VL*, the reference delay chain always lags behind the sensing delay chain. Ideally, both chains are synchronized for *VC* = *VL*, while the lagging condition is inverted as soon as *VC* < *VL*, marking the end-of-conversion condition.

**Figure 3.** Derivation of a RO with synchronized delay chains: (**a**) starting point representation of a generic RO; (**b**) synchronization principle by a Xnor gate; (**c**) synchronized delay-chain oscillator chronogram.

The time-delay comparator, proposed in [17] and depicted in Figure 4a, provides the same synchronizing function of the Xnor/Nand gates of Figure 3b, while also signalling the end of conversion. It is based on a Nand-type set–reset latch and simple combinational logic to produce the two output signals, *B* and finish. The operation of such circuit is described in Figure 4c considering the following conditions: (i) *A*1 leads *A*2, and (ii) *A*2 leads *A*1. In both conditions, *B* acts as a synchronization gate, while finish is an active-low signal that pulses only after the first occurrence of the *A*2-leads-*A*1 condition. It is important to observe at this point that, while the voltage-domain comparator of Figure 2a is placed outside the RO, the time-domain comparator will be part of the RO, thus contributing to the oscillator parameters, such as *f*0 and the conversion gain *kG* (see Equation (13)).

**Figure 4.** Time-delay comparator: (**a**) schematic diagram, (**b**) symbol view and (**c**) chronogram when operated inside the synchronized delay chains loop.

Figure 5 shows the effect of noise on the decision process of the comparator, both voltage-level based and time-delay based, when *VC* crosses the decision threshold *VL*. The figure shows how a lower value of *CS* makes the decision process less prone to error since for a constant amount of charge dissipated by the RO in a single cycle, the voltage step (the delay between the travelling edges of *A*1 and *A*2) is higher for smaller *CS* values. This observation is in accordance with Equation (14) and its related discussion on the contribution of comparator noise.

**Figure 5.** Comparison of comparator noise effects for two different values of *CS*: (**a**) classic voltagelevel based comparator as in Figure 2; (**b**) time-delay comparator of Figure 4.

Regarding the rest of noise sources in the circuit, it is well known that a standard voltage-fed RO presents a typical phase-noise spectrum characterized by the 1/ *f* 3 and 1/ *f* 2 behaviours, corresponding to the flicker and thermal noise sources, respectively [25–27]. In the synchronized-delay-chains case of Figure 3b, however, part of this noise is rejected due to the synchronization between the travelling edges of *A*1 and *A*2. Intuitively, every disturbance (i.e., phase lag or lead) produced after *B* and before *A*, affects both *A*1 and *A*2 in the same way, thus showing up as a common-mode noise, rejected by the differential-input nature of the time-delay comparator.

The residual differential-mode phase noise is generated once the RO path is split, corresponding to the separate delay-chain paths before the time-delay comparator. The effects of such noise on the final conversion count are influenced by the interval of time Δ*t* between the *A*1 and *A*2 edges. We observe that at the end of conversion, this temporal difference tends to zero; however, the time-domain comparators are less affected by metastability (less prone to error) if the sensitivity of Δ*t* with respect to *VC*, i.e., the quantity *d*(<sup>Δ</sup>*t*)/*dVC*, is high.

The complete IDCD-CDC is shown in Figure 6, which features also a noise reduction technique, also proposed in [17], based on correlated averaging on a three-comparators system.

**Figure 6.** Complete CDC schematic including time-delay comparator-noise averaging and the onepoint calibration network.

The comparator-noise averaging operates as follows: CMP1 and CMP2 are respectively fed with *A*1 and *A*2 and their inverted correspondents, while CMP3 is fed by *A*1 and a delayed version of *A*2 (*D*2). While CMP1's finish will detect the lagging condition on the rising edges, CMP2's finish will detect the same condition on the falling edges of *A*1 and *A*2. The travelling edges at comparator output are synchronized by a three-input Nand gate. The complete RO loop includes a *VL*-to-*VH* level shifter that guarantees the correct level transmission to both sensing and reference delay chains. The eoc signal pulses when the *A*1 travelling edge lags that of *D*2. Before this condition occurs, the finish outputs of CMP1 and CMP2 have pulsed a certain number of times depending on the amount of extra delay provided by the noise-averaging delay chain. These finish pulses of CMP1 and CMP2 are registered by dedicated counters, which provide dout1 and dout2, respectively. The final conversion code is given by

$$N = 2 \times \texttt{dout2} - (\texttt{dout1} + \texttt{dout2}).\tag{15}$$

The multiplicative factor of 2 before dout0 accounts for both the rising and falling edges. To give a better understanding of the noise averaging mechanism, let us consider in the first instance that all the delay chains of Figure 6 are identical and their individual delay on the travelling edge dominates over the rest of the elements in the RO, i.e., the time-delay comparators, the Nand gate and the level shifter.

In such a scenario and in absence of noise, if we artificially set *VC* = *VL*, CMP1 and CMP2 have 50% probability to pulse their finish signals, while CMP3's finish will not pulse. In order to force CMP3's finish to pulse, we need to further lower *VC* to a certain value *VC* = *V*-*L* < *VL*. At this point, the conversion ends, meaning that the effective voltage step explored by the sensing chain is *VH* − *V*-*L* , and thus, some excess count was made. Nevertheless, the finish signals of both CMP1 and CMP2 start to pulse as soon as *VC* is slightly below *VL*, thus dout1 = dout2, accounting for the excess of counts.

When the comparator noise is considered, the probability of CMP1 and CMP2 to make the wrong decision goes from 50% when *VC* = *VL* to much lower values, as soon *VC* < *VL*. By repeating the comparison process a certain number of times at different *VC* values below *VL*, the probability of error, and thus the noise effect, is reduced. In practice, starting from a certain value of *V*- *L* far from *VL*, the probability of decision error can be neglected; thus, the decision redundancy only adds up to power consumption. So, in terms of power vs. resolution trade-off, an optimum value *V*- *L* exists, which can be tuned by the sizing of the noise-averaging delay chain of Figure 6. It must be observed that the crossing of the zone between *VL* and *V*- *L* occurs at different slopes, depending of the value of *CS* to be converted and also depending on *d*(<sup>Δ</sup>*t*)/*dVC*, as previously discussed. As a consequence, the number of excess counts increases for higher values of *CS*, having a beneficial effect on the maximum attainable SNR.

The one-point calibration scheme is also shown in Figure 6, implemented through the *C*REF capacitance and a switch controlled by the signal cal. The CDC calibration is obtained on demand by operating a conversion on a known value of *C*REF, obtaining from Equations (6) and (10)

$$N\_{\rm REF} = k\_{\rm G} \mathcal{C}\_{\rm REF} + k\_{\rm G0} \mathcal{C}\_{\rm O} + \mathfrak{e}\_{\rm Q,REF}.\tag{16}$$

The parameters *kG*, *kG*0 and *C*0 may be strongly dependent on process corners and the operating temperature. While the former can be addressed by a one-time calibration at the beginning of the CDC operation, the latter can be addressed by occasionally performing a calibration conversion.

The calibrated value of the conversion, neglecting the physical noise, is obtained by the following formula:

$$\mathbf{C}\_{S}^{\text{calibrated}} = \mathbf{C}\_{\text{REF}} \frac{N}{N\_{\text{REF}}} = \mathbf{C}\_{S} \frac{1 + \frac{k\_{\text{G}0} \mathbf{C}\_{0}}{k\_{\text{G}} \mathbf{C}\_{S}} + \boldsymbol{\varepsilon}\_{Q}}{1 + \frac{k\_{\text{G}0} \mathbf{C}\_{0}}{k\_{\text{G}} \mathbf{C}\_{\text{REF}}} + \boldsymbol{\varepsilon}\_{Q, \text{REF}}}. \tag{17}$$

The rightmost side of Equation (17) reveals the residual error after calibration that can be minimized once *CS C*0 and *C*REF *C*0 for acceptable quantization errors *Q* and *Q*,REF. Clearly, this calibration method relies profoundly on the stability of the absolute value of *C*REF. Any process-related dispersion on the nominal value of *C*REF affects the conversion value, despite the calibration. From the system-level point of view, two alternative solutions can be adopted. On one side, *C*REF can be a very reliable external component, which, however, is affected by connection parasitics. On the other side, *C*REF can be integrated all together with the converter circuitry using a metal–oxide–metal (MOM) or a metal–insulator–metal (MIM), when available from the process, capacitor. Nevertheless, the solution concerning the monolithic integration will be affected by the process corners spread. This former hindrance can be overcome by dedicated *C*REF testing structures at the wafer level.

#### *3.2. 180 nm-CMOS Implementation*

Following the design indication explained in Section 3.1, a monolithic implementation of a IDCD-CDC is done in a standard 0.18 μm 1-poly 6-metal-level MIM CMOS technology. In this case study, we aim at optimizing the energy efficiency of the CDC while maintaining 10 effective number of bits (ENOB) of resolution and a total area ≤0.02 mm2. Regarding the operating conditions, we aim for a button-cell operated system; thus, the specification *VH* = 0.9 V applies for the rest of the discussion.

Referring to Figure 6, all inverters in the delay chain have *W* = 240 nm, *L* = 180 nm. All the delay chains (sensing, reference and noise-averaging) are implemented with 2 stages. With these values, *kG* results to be 246.468 × 10−<sup>12</sup> <sup>F</sup>−1, and the output code can be stored in a 16-bit output register. The digital gates of CMP1–CMP3, all identical, have all minimal *W* = 240 nm, and *L* = 180 nm.

The level shifter topology is adopted from [28]. Its schematic together with the sizes of transistor parameters are shown in Figure 7. Among other possible circuital solutions [29–32], that of Figure 7 provides the best energy efficiency when operating across subthreshold and super-threshold regions, defined by *VL* and *VH*. It is important to note that, in this design, the circuit propagation delay is of minor concern since it only affects the conversion time.

The *C*REF capacitance is implemented by a MIM capacitor of 10 pF, which is the largest component of the CDC. However, since it is implemented between the two highest topmetal layers, the area underneath is used for the rest of the digital circuitry, using the rest of the metal layers for signal routing.

**Figure 7.** Wilson current-mirror based level shifter and transistor optimized geometrical parameters values for the design case in Section 3.2.

The total energy per conversion, *Etot*, and the conversion time, *Tconv*, are evaluated as function of *VL* in order to find an acceptable trade-off between quantization error and energy consumption. Figure 8a shows that a shallow optimum is found for *VL* = 0.5 V. This is due to the fact that *Etot* accounts for currents supplied by the *VH* and *VL* sources, respectively *EH* and *EL*, during the precharge and the conversion phases:

$$E\_{\text{tot}} = E\_H^{\text{preccharge}} + E\_H^{\text{convversion}} + E\_L^{\text{convversion}},\tag{18}$$

where the precharge energy supplied by *VH* is

$$E\_H^{\text{preccharge}} = \mathcal{C}\_S V\_H (V\_H - V\_L) \tag{19}$$

and *E*conversion *H*is supplied to the level shifter.

Both Equations (18) and (19) neglect any leakage components, which add up to the total energy balance proportionally to *T*conv. Equation (19) depicts a monotonically decreasing function of *VL*. The terms *E*conversion *H* and *E*conversion *L* , related to the conversion phase, depend on *Tconv*, which increase by lowering *VL*, as shown in Figure 8b, where *VH* is fixed to 0.9 V. Intuitively, we may expect that both *E*conversion *H* and *E*conversion *L* should follow the same trend as *Tconv*. This is true for *E*conversion *H* , but *E*conversion *L* actually has the opposite behaviour as shown in Figure 8c. This is due to the dominant contribution of comparators activity happening at higher *VL* values: the higher the *VL*, the higher the *E*conversion *L* .

In our design, *VL* is set to 0.5 V. For such value and for *CS* = 250 pF, *Etot* = 1884 fJ, accounting for the following contributions: *E*precharge *H* = 90 fJ, *E*conversion *H* = 224 fJ (due to the operation of the level shifter) and *E*conversion *L* = 1570 fF. The latter is the major contribution since *VL* supplies also the time-domain comparators and the asynchronous counters.

The behaviour of *R*RO as a function of *VC*, introduced in Figure 2a, is shown in Figure 8d along with <sup>Δ</sup>*t*(*VC*). The *<sup>R</sup>*RO(*VC*) trend is to increase by increasing *VC*. This is due to the dominant short-circuit currents contributions (transition time shorten as *VC* increases) over the RO interstage-charging contribution. On the other hand, Δ*t*(*VC*) shows a quite noticeable non-linear behaviour. The relatively high value of *d*(Δ*t*)/*dVC* in the vicinity of *VL*, resulting to be 71.8 ns/V, favours the CDC immunity against the noise introduced by the split path of the sensing and reference delay chains, as discussed previously.

Finally, the layout of the implemented CDC is shown in Figure 9 showing a silicon area occupancy of 0.0192 mm<sup>2</sup> (excluding pads).

**Figure 8.** Key design parameters: (**a**) total energy per conversion *Etot* as function of *VL* for fixed *VH* = 0.9 V; (**b**) energy balance as from Equation (18) as function of *VL* for *CS* = 50 pF and fixed *VH* = 0.9 V; (**c**) conversion time *Tconv* as function of *VL* for fixed *VH* = 0.9 V; (**d**) *R*RO and Δ*t* as function of *VC*.

**Figure 9.** Layout of the CDC in a standard 0.18 μm 1-poly 6-metal-level-MIM CMOS technology. Bounding box size is 160 μm (width) × 120 μm (height).

#### *3.3. Prototype Performance*

The CDC DNL, calculated with respect to the end-points characteristic, when operated at *VL* = 0.5 V and *VH* = 0.9 V, is shown in Figure 10, and tested against process corners. In all cases, the maximum observed code deviation falls within the ±12 counts interval over an output register of 16 bits, corresponding to an equivalent capacitance LSB of 3.82 fF (*kG* = 246.468 × 10<sup>12</sup> <sup>F</sup>−1). The total energy per conversion scales linearly with *CS*, resulting to be 1.884 nJ at full-scale *CS*,FS = 250 pF. As far as process corner sensitivity is concerned, *Etot* presents small variations around its nominal value (worst case: +2.9% in the Fast-NMOS Slow-PMOS corner), while at the same time, *Tconv* shows quite large variations: 2.93 ms in the nominal case vs. 0.99 ms and 10.71 ms in the fast-NMOS fast-PMOS and slow-NMOS slow-PMOS, respectively.

The effectiveness of the one-point calibration against process corners is reported in Table 1, where the relative error *kG* , defined as

$$
\varepsilon\_{k\_G} = \frac{k\_G^{\text{nominal}} - k\_G}{k\_G^{\text{nominal}}} \tag{20}
$$

is evaluated, showing a ×30 error reduction when calibrated. The systematic offset of the CDC, as in Equation (6), is <255.6 fF. Hence, the CDC shows an input capacitance range from 255.6 fF to 250 pF with a small linearity error of 15.26 ppm.

**Table 1.** Conversion-gain relative error *kG* (see Equation (20)) againts process corners: before and after calibration. Offset code, for *CS* = 0, is also reported. Nominal offset code is 63.


For the sake of equal comparison, the figure of merit (FoM), as defined in [17], is evaluated:

$$\text{FoM} = \frac{E\_{\text{tot}}(\text{C}\_{\text{S,FS}})}{2^{(20\,\text{log}\_{10}(\text{Input range}/2\sqrt{2}/\text{Resolution}) - 1.76)/6.02}} = 99.61 \text{ f/convension-step.}} \\ \text{ (21)}$$

where the resolution is calculated only on the basis of nonlinearity effects, while noise is not taken into account.

Transient noise simulations are performed to determine the SNR, which results to be 63.9 dB (10.3 ENOB) at *CS*,FS. The noise-related FoM, FoMN, of this converter is calculated as

$$\text{FoM}\_{\text{N}} = \frac{E\_{\text{tot}}(\text{C}\_{\text{S,FS}})}{2^{(\text{SNR}\_{\text{max}} - 1.76)/6.02}} = 1.47 \text{ pJ/convension-step.} \tag{22}$$

Temperature sensitivity is also evaluated as shown in Figure 11, showing a ×20 improvement, from 1696.5 ppm/◦C without calibration to 81.9 ppm/◦C after calibration, across the −40 ◦C, +125 ◦C range.

**Figure 10.** CDC differential non-linearity (DNL) against process corners. The output register width is 16 bits.

**Figure 11.** CDC output temperature sensitivity before and after one-point calibration.
