**1. Introduction**

Capacitive sensing technologies underpin many sensory applications, including industrial, automotive, consumer [1] and life-science electronics [2]. At the same time, dedicated and power-optimized readout interfaces have been proposed to take full advantage of this technology. In this sense, capacitance-to-digital converters (CDCs) represent a class of integrated interfaces capable of delivering a digital output readout of the capacitive sensor. Many architectures of CDCs are demonstrated in the literature, exploiting the principles of phase/pulse modulation (PM) [3–7], ΔΣ modulation (ΔΣM) [8–10] and capacitive successive approximation register (CSAR) [11–15]. A detailed review of these techniques can be found in [16].

Recently, a simple and compact solution, which presents a significant number of innovations over other kinds of CDCs, was proposed in [17]. The most relevant innovations regard that (i) the CDC implementation is based on basic digital gates (inverters, Nands and Xors); (ii) an external clock signal is not required; and, (iii) as it will be clear in the remainder of this paper, the scaling of the capacitance full scale, i.e., the maximum capacitance value that can be converted, does not affect the internal state variables range in terms of voltage headroom and/or current intensity, as it usually occurs in many other CDC architectures. This fact allows for the extension of the CDC dynamic range (DR) relying only on the length extension of the digital output register. However, the inner working principles of the iterative delay-chain discharge (IDCD) architecture are poorly explained, leaving the designer with numerous unknowns hindering the adoption of this architecture despite its excellent performance in terms of power.

In this work, we address this issue by providing a deeper insight into this new architecture by giving a formal (rather than heuristic) explanation of the CDC operating principle.

Bruschi, P.; Dei, M. Design of a Capacitance-to-Digital Converter Based on Iterative Delay-Chain Discharge in 180 nm CMOS Technology. *Sensors* **2022**, *22*, 121. https://doi.org/10.3390/s22010121

Academic Editor: Youfan Hu

**Citation:** Cicalini, M.; Piotto, M.;

Received: 26 November 2021 Accepted: 23 December 2021 Published: 24 December 2021

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**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

This discloses the CDC's intrinsic limits, thus providing awareness of the fundamental trade-offs. Moreover, the analysis paves the way for different implementations of the same architecture that better adapts to specific cases within the voltage-headroom/signalbandwidth design space.

**Figure 1.** Concept of a wearable platform for volumetric sweat-rate sensing.

The target capacitive sensor considered in this work derives from the wearable platform for sweat-rate sensing sketched in Figure 1. This device is intended to be used for activity tracking in sport applications, and it consists of (i) a flexible printed-circuit board (FPCB) layer, typically a polyimide film; (ii) a decorated elastometer layer, typically polydimethylsiloxane (PDMS), and (iii) an application-specific integrated circuit (ASIC) [18–21]. The fluidic pathway is then formed by sealing the two layers together and providing an inlet and an outlet, facing, respectively, the skin and the air. In correspondence to the fluidic pathway, two buried electrodes, implemented by the FPCB Cu tracks, work as electrostatically coupling electrodes, providing the capacitive transduction mechanism for the volume occupied by the sweat within the channel. By taking successive capacitance measurements, the volumetric sweat flow can be reconstructed. The measurement readout control is provided by the ASIC, which is placed in close proximity to the sensor in order to avoid interference and excessive parasitic coupling. The ASIC may also provide a standard digital interface, e.g., a serial peripheral interface (SPI), for communication with an external wireless communication module. Preliminary estimation of the capacitance range of structures, such as those in Figure 1, suggests values between 10 and 250 pF, depending on the specific channel geometries and constitutive materials. Similar capacitance range can also be found in other capacitive sensors [22,23].

A 0–250 pF capacitive sensor interface, applying the design rules resulting from the theoretical analysis, is implemented in the UMC 180 nm complementary metal–oxide– semiconductor (CMOS) technology. The chosen capacitive conversion range is compatible with a number of micro-electro-mechanical systems (MEMS) capacitive sensors. Detailed electrical simulations show the following converter performance: systematic input offset of 255.6 fF, linearity error of 15.26 ppm, worst-case process-corner sensitivity on the conversion gain of 114 ppm, temperature sensitivity of 81.9 ppm/◦C, maximum signal-to-noise ratio (SNR) of 63.9 dB and maximum conversion energy of 1.884 nJ when operated at 0.9 V supply. In the discussion section of this work, these figures are compared to those of [17] in order to provide insight into the porting of this architecture across different CMOS technological nodes.

#### **2. Materials and Methods**

Electrical simulations were performed on a 3.3 GHz 14 core CPU x86-64 workstation, operated through CentOS 7, and Cadence IC6.1.7 (ADEXL, Spectre simulator and AMS simulator). The CMOS design kit from UMC 180 nm mixed mode/RF was made available from the Europractice IC Service to European academic and research institutions. Graphical data preparation and presentation were performed by means of Python 3.5.2 importing the following modules: Numpy 1.17.0 and Matplotlib 3.0.3.
