**5. Conclusions**

A low power 12-bit, 20 MS/s asynchronously controlled SAR ADC was fabricated with one poly six metal (1P6M) 65 nm CMOS technology to be used in WAVE protocol based intelligent transportation system. Several techniques have been proposed to optimize the architecture with respect to power consumption and performance. To alleviate the switching energy problem of the DAC part, the proposed switching method which employs CMCR switching technique is implemented in CDAC part. A mutated dynamic latch comparator with cascode is implemented to make certain a high speed operation with low power consumption and to overcome the kick back issue. Moreover, the presented modified asynchronous topology in control logic part optimizes the flexibility relating to the performance of logic part. The structure have an active area of 0.14 mm2. The presented SAR ADC was operated at a sampling rate of 20 MS/s, attaining a peak SNDR level of 65.44 dB with a peak ENOB of 10.58 bits at Nyquist frequency. While consuming only 472.2 μW of power with 1 V power supply, the proposed architecture achieved a FOM of 15.42 fJ/conv. step.

**Author Contributions:** Conceptualization, K.S. and D.V.; methodology, K.S.; software, K.S., D.V. and S.J.K.; validation, K.S., D.V. and Q.U.A.; formal analysis, K.S., D.V. and M.B.; investigation, K.S., D.V. and D.K.; resources, K.S.; data curation, K.S. and D.V.; writing—original draft preparation, K.S. and K.-Y.L.; writing—review and editing, K.S., D.K., Y.G.P. and K.-Y.L.; visualization, K.S., D.V., B.S.R. and K.-Y.L.; supervision, K.C.H., Y.Y. and K.-Y.L.; project administration, K.-Y.L. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research received no external funding.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** Not applicable.

**Acknowledgments:** This research was supported by the MOTIE (Ministry of Trade, Industry & Energy) (10080622) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device.

**Conflicts of Interest:** The authors declare no conflict of interest.
