*2.3. Oscillator*

An adjustable oscillator can easily change the operating frequency of the converter when the load condition changes. In the proposed converter, the integrated oscillator provides sixteen frequencies ranging from 0.1 to 200 MHz, which are selected by the main controller using 4-bit FC. For our voltage converter, the accuracy of the frequency is not critical to maintain the target output voltage, which is proven by the measurement results. Therefore, a simple low-power oscillator su ffices our needs.

Figure 3 illustrates the proposed oscillator, which is a ring oscillator consisting of nine current-starved inverters. The current-starved inverters are controlled by a biasing circuit using 4-bit digital control to tune the delay of each inverter. The digital current control has multiple current multiplication branches, one of which is selected based on the FC to provide appropriate current to the biasing circuit. A low-power Schmitt trigger is used at the output to reduce the power consumption of the subsequent bu ffers.

**Figure 3.** Ring oscillator with current starved inverters and biasing circuit.

#### *2.4. Non-Overlapping Signal Driver (NOSD)*

Conventional multiphase converters employ a shared delay controller to generate non-overlapping signals. Such architectures, however, require excessive number of long routing wires as shown in Figure 4a. In contrast, this paper proposes a distributed architecture that generates non-overlapping signals using edge delay circuits at each MOSFET switch, which is illustrated in Figure 4b. The proposed architecture can significantly reduce the number of long routing wires and their associated bu ffers, consequently reducing the power consumption. Each switch (NMOS and PMOS), in the capacitor banks of the proposed converter, includes a driver that generates non-overlapping control signals by delaying the turn-on transition of the switch, as shown in Figure 4c. The NMOS and PMOS drivers in the NOSDs, respectively, delay the rising and falling edges of the resulting non-overlapping signals. These drivers ensure that no short-circuit path occurs during switching, thus reducing the switching losses. From Figure 4c, it can be observed that the turn-on delay of a switch is approximately equal to the propagation delay of first bu ffer (*tp*1) in the drivers. This distributed topology reduces the number of wires connecting the controller with the switches.

**Figure 4.** (**a**) Conventional non-overlapping architecture; (**b**) proposed non-overlapping architecture with reduced buffers and wires; (**c**) proposed non-overlapping MOSFET drivers with edge-delaying.

Consider the propagation delays of the gates in drivers as: *tp*1 for the buffer, *tp*2 for OR/AND gates, and *tp*3 for the final multi-stage buffer. The rising- and falling-edge delays of PMOS driver can be represented as:

$$t\_{pp-r} = t\_{p2} + t\_{p3\prime} \tag{1}$$

$$t\_{pp-f} = t\_{p1} + t\_{p2} + t\_{p3}.\tag{2}$$

Similarly, the propagation delays for rising and falling edges through NMOS driver can be represented as:

$$t\_{pu-r} = t\_{p1} + t\_{p2} + t\_{p3\_\prime} \tag{3}$$

$$t\_{\text{pr}-f} = t\_{\text{p2}} + t\_{\text{p3\prime}} \tag{4}$$

By using the above equations, we can calculate the non-overlapping periods. Upon rising-edge, NMOS turns-on and PMOS turns-off, the non-overlapping period can be formulated as:

$$t\_{nol-r} = t\_{pu-r} - t\_{pp-r\_{\prime}} \tag{5}$$

$$t\_{ml-r} = t\_{p1} + t\_{p2} + t\_{p3} - \left(t\_{p2} + t\_{p3}\right),\tag{6}$$

$$t\_{nol-r} = t\_{p1\prime} \tag{7}$$

Upon falling-edge, PMOS turns-on and NMOS turns-off, the non-overlapping period can be formulated as:

$$t\_{nol-f} = t\_{pp-f} - t\_{pn-f\prime} \tag{8}$$

$$t\_{val-f} = t\_{p1} + t\_{p2} + t\_{p3} - \left(t\_{p2} + t\_{p3}\right) \tag{9}$$

$$t\_{mol-f} = t\_{p1}.\tag{10}$$

It is important that OR- and AND-gate have equal propagation delays to ensure symmetric non-overlapping periods for both the edges.

#### **3. Implementation of Test Chip**

To verify the proposed architecture, we have implemented a test chip consisting of four capacitor banks, a reconfigurable test controller, and clock oscillator using 130 nm 1.5 V CMOS process, as shown in Figure 5a. The individual outputs of the four capacitor banks have been brought out of chip

for measurement purposes, and they are combined on the PCB. In addition, to ensure accurate output voltage observations, four buffered outputs have been added. For test chip implementation, the oscillator does not include a digital current control circuit. Therefore, an external current Digital-to-Analog Converter (DAC) is used to drive the biasing circuit of the oscillator, as shown in Figure 5b. In addition, some components of the main controller (of Figure 2), such as OSI and VCR tables, have been moved to the off-chip CPU module to have flexibility in testing.

**Figure 5.** (**a**) Test chip implementation block diagram; (**b**) off-chip components for testing.

#### *3.1. Reconfigurable Test Controller Implementation*

A test controller is designed with a host interface that emulates the interface to power managemen<sup>t</sup> software. It operates the four capacitor banks at different phases (or in phase) and can be programmed through its host interface, as shown by the simplified block diagram in Figure 6. In addition to its main functions, we implemented various test and fallback modes in the controller for test purposes. The next entry of the OSI table provides the state information for each capacitor bank, which is stored in VCR state registers (state\_reg[0] and state\_reg[1]). The VCR state registers' values are used to generate control signals for each attached capacitor bank.

*\*op\_mode[1:0]: Enable Capacitor banks, 0- none, 1- sc0, 2- sc0+sc2, 3- all*

**Figure 6.** Reconfigurable test controller with interfaces, for a multiphase SC converter.

The multi-phase generator (MPG) block reads the state signals and operates the capacitor banks by supplying phase-delayed signals. The four operation modes of MPG are listed in Figure 6, which allows one, two or all four converters to operate concurrently. It is also possible to operate two or four capacitor banks in phase, by asserting *sphase* input, to compare the performance of single-phase and multi-phase operations.

The test controller has been synthesized using Synopsys design tools targeting 250 MHz. The final implemented layout of the controller has an active area of 590 μm × 15 μm. The aspect ratio of the test controller was chosen to minimize the routing overhead when connecting the controller to a stack of four capacitor banks.

#### *3.2. Capacitor Banks*

For the test chip, we implemented four identical series-parallel switched capacitor banks. A circuit block diagram of one bank is shown in Figure 7. Each bank has three flying capacitors which provide five buck voltage conversion ratios (1/4, 1/3, 1/2, 2/3, 3/4). For our target load current range, we chose 80 pF for each flying capacitor and 160 pF for the load decoupling capacitor in each capacitor bank.

**Figure 7.** Capacitor bank circuit diagram with three switched capacitor branches.

Figure 8 illustrates an example of non-overlapped switching operation. Figure 8a shows example MOSFET switches corresponding to transmission gates cA0 and cB0 of Figure 7. The NMOS and PMOS drivers are part of the NOSD of a capacitor bank shown in Figure 4c. Figure 8b shows the post-layout simulation result of the circuit in Figure 8a. It reveals that the NMOS and PMOS gates have a non-overlapped period when transitioning between φ1 and φ2, which ensures that no short-circuit path occurs while switching. For the test chip, the non-overlapped period introduced by the NOSD varies from 130 to 200 ps, depending on the potential on the source and drain terminals of the MOSFET being driven.

**Figure 8.** (**a**) Transmission gate switches controlled by Non-Overlapping Signal Drivers (NOSDs). For example, the blue transmission gate indicates cA0 and the red transmission gate indicates cB0 of Figure 7. (**b**) Post-layout simulation of the NOSDs, demonstrating non-overlapping control to mitigate short-circuit losses.

#### *3.3. Overall Test Chip Implementation*

Complete layout (including pads) of the overall test chip is shown in Figure 9a, where the converter occupies an area of 0.59 mm2. The voltage supplies are located on the top left, whereas analog/power outputs (vout and obsvout) are located on the bottom. Decoupling capacitors are added to the voltage supplies of MOSFET drivers, oscillator and reconfigurable test controller, as shown in Figure 9a. The test chip shown in Figure 9a occupies total area of 1.76 mm<sup>2</sup> (1.56 mm × 1.13 mm), including test circuits and pads. For this implementation, only metal–insulator–metal (MIM) capacitors are used for capacitor banks to minimize switching losses [12] caused by the bottom plate capacitance (Cbot.,mim = 0.0025 × C). To reduce the overall area, a metal–oxide–semiconductor (MOS)+MIM stack can be safely used as load capacitors, without sacrificing conversion efficiency. Using an MOS+MIM stack as a load capacitor, the area can be reduced by 21% (from 0.59 mm<sup>2</sup> to 0.461 mm2), compared to an MIM-only load capacitor. Moreover, our analysis also shows that replacing all capacitors by an MOS+MIM stack yields a 54% reduction in area (from 0.59 mm<sup>2</sup> to 0.266 mm2) at the expense of conversion efficiency.

**Figure 9.** (**a**) Die microphotograph of the implemented proposed controller with test controller and oscillator; (**b**) measurement setup showing test PCB and off-PCB current measurement devices.

## **4. Results**

The measurement setup to verify the implemented test-chip is shown in Figure 9b. For accurate current measurements at the input and output of the converter, two current sensors [13] and high-resolution Analog-to-Digital Converters (ADCs) are employed. To adjust the frequency of the on-chip oscillator, a 12-bit DAC is used. For the sake of testing, we have split the load and the power managemen<sup>t</sup> CPU of Figure 2 into separate external components. Two series variable resistors are acting as a load, one of which can be bypassed to toggle between heavy and light load conditions. A CPU module is used to run a power managemen<sup>t</sup> program and governs the on-chip controller, the external DAC, and the load. The CPU module also reads the current measurements using the external ADC and the voltage measurement using the internal ADC.

The first measurement result is the difference between single-phase and multi-phase operations, which is shown in Figure 10. It can be observed that the ripple voltage of the multi-phase case is significantly reduced compared with the single-phase. Moreover, the average output voltage of the multi-phase case has increased, resulting in improved efficiency.

**Figure 10.** Single-phase vs. multi-phase operation of the implemented converter.

To evaluate the performance of the implemented converter over a wide load range, a set of measurement are performed by reconfiguring the load and the oscillator frequency. The load is configured by adjusting the off-chip resistor, while the converter takes 1.4 V as input. The oscillator frequency is adjusted by the power managemen<sup>t</sup> CPU via the DAC. The results provided in Figure 11 demonstrate that the converter is able to maintain a high efficiency of above 80% for the targeted load range from 10 μA to 10 mA, by adjusting the switching frequency using the on-chip oscillator. Furthermore, the converter provides a conversion efficiency of 74% at 15 mA, while operating at 150 MHz. In the test chip, where the source and load are off-chip, the conversion efficiency drops above 7.5 mA due to a large voltage drop across the bonding and metal wires. However, for true on-chip implementation, this efficiency will be maintained above 7.5 mA as well. At high frequencies, the power losses (switching) increase while the power delivered slowly saturates due to conduction losses. This results in the degradation of the conversion efficiency at higher frequencies.

To verify the transition operation between heavy (active) and light (sleep) load, the CPU module momentarily changes the load and the frequency. Figure 12 shows the transition operation when the load switches between 68 μA and 10 mA by switching the frequencies between 600 kHz and 100 MHz, respectively. Usually in an active state, a higher voltage is needed to support fast computation in the load (CPUs or SoCs) than the sleep state [14,15]. Therefore, in the test for Figure 12, we configured the voltage conversion ratio to 1/2 for sleep and 3/4 for active period.

**Figure 11.** Measurement results demonstrating wide load range performance over various switching frequencies for a voltage conversion ratio of 3/4.

**Figure 12.** Measurement result for transitions between sleep and the active period of the load.

Figure 13 reflects the power consumption of the main blocks of the test chip, over the supported frequency range. It can be observed that the power consumption of the oscillator and the controller decreases with the decrease in frequency, allowing for higher conversion efficiencies at low currents. The power consumption of the SC converter does not include the power supplied to the test controller. Since the test controller is designed to provide many additional test features, its power consumption does not truly reflect an optimized main controller. Moreover, the on-chip analog buffers (used for output voltage observation) consume around 20 mW.

**Figure 13.** Test-chip power consumption at various operating frequencies.

## **5. Discussion**

The proposed SC converter's advantage—the ability to transition smoothly between light and heavy loads, while maintaining high conversion efficiency—makes the converter well suited to loads that frequently change operating states. We have proposed a figure of merit (FOM) to evaluate a converter for wide load range operation, using:

$$\text{FOM} = (\eta\_{\text{Max}} + \eta\_{l,\text{Max}} + \eta\_{l,\text{Min}}) \times \log\left(\frac{I\_{\text{Max}}}{I\_{\text{Min}}}\right) \tag{11}$$

Here, η*Max* is the peak conversion efficiency, while η*I*,*Max* and η*I*,*Min* are the conversion efficiencies at maximum and minimum load, respectively. Table 1 compares the design parameters and performance of our work with previously reported solutions. Table 1 shows that the proposed converter maintains higher efficiency compared to other works [6,10,16]. This is accomplished by the ability of the proposed converter to operate at a much wider switching frequency. Due to the limitation of existing feedback-based PFM, only limited fmax/fmin of 132 is used in [6], while the proposed converter allows for an extremely large fmax/fmin up to 1000. The capacitor banks used in this implementation offer five buck voltage conversion ratios, higher than the works in [5,6,9–11,16]. To further reduce the output ripple while having the wide load range, our architecture allows the number of phases to be increased to match [5,6]. The proposed FOM reveals the superior performance of 7.44, compared to existing works. Though the converter proposed in [9] reaches an FOM of 6.74, it uses off-chip flying capacitors and two discrete converters for sleep and active operation.


**Table 1.** Comparison of performance with state of the art.

aOff-chip Component. b Approximated values from graphs.

While this paper is focused on the proactive PFM, it is not limited only to proactive PFM with prior schedules. We can combine the proactive PFM with existing feedback-based PFM methods [6,11] to take advantage of both methods. Then, the feedback can allow finer adjustments in frequency, whereas the proactive PFM provides a wider frequency range, which is expected to provide further improvement.
