*Article* **Core-Shell Dual-Gate Nanowire Charge-Trap Memory for Synaptic Operations for Neuromorphic Applications**

**Md. Hasan Raza Ansari , Udaya Mohanan Kannan and Seongjae Cho \***

Graduate School of IT Convergence Engineering, Gachon University, Seongnam 13120, Korea; hasanrazaadnan@gmail.com (M.H.R.A.); kannan.um@gmail.com (U.M.K.) **\*** Correspondence: felixcho@gachon.ac.kr; Tel.: +82-31-750-8722

**Abstract:** This work showcases the physical insights of a core-shell dual-gate (CSDG) nanowire transistor as an artificial synaptic device with short/long-term potentiation and long-term depression (LTD) operation. Short-term potentiation (STP) is a temporary potentiation of a neural network, and it can be transformed into long-term potentiation (LTP) through repetitive stimulus. In this work, floating body effects and charge trapping are utilized to show the transition from STP to LTP while de-trapping the holes from the nitride layer shows the LTD operation. Furthermore, linearity and symmetry in conductance are achieved through optimal device design and biases. In a system-level simulation, with CSDG nanowire transistor a recognition accuracy of up to 92.28% is obtained in the Modified National Institute of Standards and Technology (MNIST) pattern recognition task. Complementary metal-oxide-semiconductor (CMOS) compatibility and high recognition accuracy makes the CSDG nanowire transistor a promising candidate for the implementation of neuromorphic hardware.

**Keywords:** short-term potentiation (STP); long-term potentiation (LTP); charge-trap synaptic transistor; band-to-band tunneling; pattern recognition; neural network; neuromorphic system
