**1. Introduction**

As the big data is coming, continuing rapid development of Internet business, communication network moves toward the direction of high speed and large capacity. To meet the data information transmission requirements of efficient, speedy, and integrated data, very large-scale integrated circuits (VLSI) were developed via continuing miniaturization of the transistor characteristic size according to Moore's law [1]. Si is always considered as the backbone material in the micro- and nano electronic industry owing to its natural abundance, high mobility, larger wafer size, low cost, and mature manufacturing technologies, etc. [2]. However, as the device characteristic size reaches to the sub-7 nm technology node, Si based integrated circuits are suffering from the physical and technological limitations in speed, power consumption, integration, and reliability, which further affect the device performance [3]. At present, two main technical roadmaps were expected to prolong the

**Citation:** Du, Y.; Xu, B.; Wang, G.; Miao, Y.; Li, B.; Kong, Z.; Dong, Y.; Wang, W.; Radamson, H.H. Review of Highly Mismatched III-V Heteroepitaxy Growth on (001) Silicon. *Nanomaterials* **2022**, *12*, 741. https://doi.org/10.3390/ nano12050741

Academic Editor: Cesare Malagù

Received: 22 December 2021 Accepted: 17 February 2022 Published: 22 February 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

Moore's law: (I) "non-silicon" high-mobility materials, such as SiGe, Ge, GeSn, GaAs, InAs, and InGaAs, were gradually extended into CMOS technology; (II) Si-based OEICs were proposed to integrate both photonic devices (such as the laser, optical modulator, optical waveguide, and photodetector) and electronic devices (transistors) on the sole Si wafer, which owns the advantages of faster transmission speed, larger transmission capacity, and low power consumption [4].

For high-mobility "non-silicon" materials, group III-V semiconductors can provide higher electron mobility (electron mobility of GaAs and InAs can reach up to 9000 cm2/(Vs) and 40,000 cm2/(Vs), respectively), and are ideal channel material for ultra-high speed and low-power devices, such as the high electron mobility transistor (HEMT) [5,6]. For example, to overcome the downscaling limit of conventional CMOS technology, monolithic integrations of various III-V devices, such as the sub−80 nm E–mode InGaAs/InAs HEMTs [7], InP-based HEMT [8], and AlGaN/GaN HEMT [9], have been proposed, enabling dense three-dimensional (3D) integration, low-power consumption, and high-speed applications [10]. On the other hand, for Si-based OEIC, the Si-based light source is the ultimate obstacle to achieve owing to the fact that Si is an indirect band-gap semiconductor material, and its emission efficiency is very low, which makes it unavailable as the active gain medium for Si-based high-efficient light sources. In contrast, most group III-V materials are definitely suitable for the optoelectronic devices in light-emitting/absorbing devices, including light-emitting diodes (LEDs), lasers, and detectors [11–14], owing to their direct bandgap properties, indicating their stronger photon emission and absorption efficiency in comparison than indirect semiconductors such as Si, Ge [15,16], and GeSn [17]. Thus, taking advantage of the excellent properties of III-V compounds, Si-based III-V CMOS devices and III-V photoelectric devices can further greatly improve the data transmission speed and amount, which effectively reduce integrated electricity and power consumption [18].

To realize the monolithic integration of III-V devices on the Si platform, it is critical to develop the heteroepitaxy technique for group III-V materials on Si [19]. Growth challenges for high-quality III-V heteroepitaxy on Si will cause APBs and TDDs/cracks [20,21]. APBs are caused by a polarity difference between III-V material and Si (surfaces for the III-V material and single Si are polar and non-polar), suggesting that it is prerequisite to prevent the formation of APBs. In case the APBs nucleated at the interface between III-V and Si, which can propagate through whole III-V epilayer, this leads to the devices' manufacturing on Si an impossibility [22]. Another important issue is the TDDs, an issue which is attributed to the mismatch of the lattice constant and thermal expansion coefficient between group III-V material and Si. As a result, both APBs and TDDs can lead to surface roughness, which act as the nonradiative recombination centers and leakage current to destroy the device performance [23]. Hence, the defects management strategy was proposed to decrease the TDDs and APBs for group III-V material, thus improving the device performance. Wafer bonding technologies, such as adhesive bonding [24,25], direct bonding [26], and fusion bonding [27,28], were adopted to form the advanced heterogeneous integration substrate platform. However, wafer bonding induces a high manufacturing cost and low integration density [29]. In addition, it is difficult to realize the graphics technology of alignment and passive devices in subsequent processing [30]. In this regard, growing high-quality III-V semiconductors on Si is the key pathway towards monolithic integration of III-V devices on Si-based OEICs.

The purpose of this review article is providing the types of defects and the mechanism of defects formation in silicon-based III-V heteroepitaxy and the detect solution. Particularly, we update recent advances in the epitaxial growth of large lattice-mismatched III-V materials on Si substrates, especially for GaAs and InP, which are both important materials for optic-device applications. This paper is arranged as follows: Section 2 introduces the fundamental challenges in III-V hetero-epitaxy on the (001) silicon wafer, and we also highlight their defect formation mechanism. Section 3 provides a brief review of growth strategies for the defect solution, including the miscut substrate, buffer layer, Strain super-lattice layers (SLSs), Aspect ratio trapping (ART), and epitaxial lateral overgrowth (ELO). Section 4 elaborates on recent approaches on growing high-quality III-V materials on Si. This includes global hetero-epitaxial thin film growth and selective-area hetero-epitaxy. Finally, we summarize the current status and discuss the potential future of III-V-on-Si heteroepitaxy. the lattice mismatch, thermal mismatch, and substrate polarity difference, are the main limitations. Figure 1 shows the bandgap (wavelength) and lattice constants (lattice misfit) for the most commonly used group III-V and group-IV materials [32]. Below each semi-

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the potential future of III-V-on-Si heteroepitaxy.

**2. Basic Challenges of III-V Hetero-Epitaxy on Si (001)**

buffer layer, Strain super-lattice layers (SLSs), Aspect ratio trapping (ART), and epitaxial lateral overgrowth (ELO). Section 4 elaborates on recent approaches on growing high-quality III-V materials on Si. This includes global hetero-epitaxial thin film growth and selective-area hetero-epitaxy. Finally, we summarize the current status and discuss

Heteroepitaxial growth represents a growth where materials with different lattice

constants are grown in a stacked order, which is usually named "metamorphic growth" [31]. The relaxed lattice constant of the epitaxial layer is generally different from that of the substrate. To grow high-quality III-V layers on Si, fundamental challenges, such as

### **2. Basic Challenges of III-V Hetero-Epitaxy on Si (001)** conductor material, there are also annotation numbers for their own electron and hole

Heteroepitaxial growth represents a growth where materials with different lattice constants are grown in a stacked order, which is usually named "metamorphic growth" [31]. The relaxed lattice constant of the epitaxial layer is generally different from that of the substrate. To grow high-quality III-V layers on Si, fundamental challenges, such as the lattice mismatch, thermal mismatch, and substrate polarity difference, are the main limitations. Figure 1 shows the bandgap (wavelength) and lattice constants (lattice misfit) for the most commonly used group III-V and group-IV materials [32]. Below each semiconductor material, there are also annotation numbers for their own electron and hole mobilities, from which we can see that III-V semiconductor materials own higher electron mobility than Si, which are more suitable for the high mobility CMOS device. Meanwhile, direct bandgap property of III-V semiconductors made it more conducive to optoelectronic devices compared to the indirect gap of IV materials. However, there is a huge challenge to grow the III-V layer on the Si substrate owing to the highly mismatched nature of III-V and Si. In III-V semiconductors, GaAs (4.1%) and InP (8.0%) have close lattice constants to IV relatively, especially the Ge, which are more likely to realize the heteroepitaxy on the Si substrate. In addition, Ge has the close lattice constant and thermal expansion coefficients to GaAs, which are often used as a buffer layer to grow III-V on Si. This huge mismatch can bring out many defects such as: APBs, TDDs, stacking faults. In this section, the definition of mismatch and the mechanism of defect caused by mismatch will be introduced. mobilities, from which we can see that III-V semiconductor materials own higher electron mobility than Si, which are more suitable for the high mobility CMOS device. Meanwhile, direct bandgap property of III-V semiconductors made it more conducive to optoelectronic devices compared to the indirect gap of IV materials. However, there is a huge challenge to grow the III-V layer on the Si substrate owing to the highly mismatched nature of III-V and Si. In III-V semiconductors, GaAs (4.1%) and InP (8.0%) have close lattice constants to IV relatively, especially the Ge, which are more likely to realize the heteroepitaxy on the Si substrate. In addition, Ge has the close lattice constant and thermal expansion coefficients to GaAs, which are often used as a buffer layer to grow III-V on Si. This huge mismatch can bring out many defects such as: APBs, TDDs, stacking faults. In this section, the definition of mismatch and the mechanism of defect caused by mismatch will be introduced.

**Figure 1.** Bandgap (wavelength), lattice constants (lattice misfit), and mobilities for the most commonly used group III-V and group-IV materials. Reprinted with permission from ref. [32]. **Figure 1.** Bandgap (wavelength), lattice constants (lattice misfit), and mobilities for the most commonly used group III-V and group-IV materials. Reprinted with permission from ref. [32]. Copyright 2014 Springer Nature.

Copyright 2014 Springer Nature. Electrical and optical properties of a semiconductor heavily depend on the crystal quality and, hence, defects in the crystal structure. There are several types of defects that can occur in semiconductor crystals, such as structural defects or compositional defects. Considering the spatial extension as a criterion, defects can be classified as 0 D point de-Electrical and optical properties of a semiconductor heavily depend on the crystal quality and, hence, defects in the crystal structure. There are several types of defects that can occur in semiconductor crystals, such as structural defects or compositional defects. Considering the spatial extension as a criterion, defects can be classified as 0 D point defects, such as vacancies, 1D line defects, such as misfit dislocations (MDs) or threading dislocations (TDs), 2D planar defects, such as APBs and stacking faults, 3D defects, such as voids. A detailed overview of defects is given by [33,34]. Figure 2 depicts three defect types relevant in this work. Figure 2a depicts a misfit dislocation forming at the interface to

fects, such as vacancies, 1D line defects, such as misfit dislocations (MDs) or threading

as voids. A detailed overview of defects is given by [33,34]. Figure 2 depicts three defect types relevant in this work. Figure 2a depicts a misfit dislocation forming at the interface to compensate for different lattice constants of the materials. Figure 2b shows the APBs' defect. Homopolar III-III or V-V bonds can form due to the atomic steps grown on the non-polar Si substrate, which lead to the formation of APB. Figure 2c is the stacking compensate for different lattice constants of the materials. Figure 2b shows the APBs' defect. Homopolar III-III or V-V bonds can form due to the atomic steps grown on the non-polar Si substrate, which lead to the formation of APB. Figure 2c is the stacking faults that can occur during the III-V growth. If the stacking sequence changes in every layer, a zinc-blende (ZB) ABC stacking can be switched to a Wurtzite (WZ) ABAB stacking [35,36], which can impact the optical band gap since some semiconductors exhibit different band gaps for different crystal structures [37] or even change the band gap from indirect to direct or vice versa [38,39]. The heteroepitaxial growth of mismatched III/V on Si introduces additional challenges; hence, the mechanisms of challenges and the defect will be discussed below. faults that can occur during the III-V growth. If the stacking sequence changes in every layer, a zinc-blende (ZB) ABC stacking can be switched to a Wurtzite (WZ) ABAB stacking [35,36], which can impact the optical band gap since some semiconductors exhibit different band gaps for different crystal structures [37] or even change the band gap from indirect to direct or vice versa [38,39]. The heteroepitaxial growth of mismatched III/V on Si introduces additional challenges; hence, the mechanisms of challenges and the defect will be discussed below.

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**Figure 2.** Schematic diagram of three defects (**a**) Misfit dislocation due to lattice mismatch, (**b**) APB at atomic steps of the substrate, (**c**) Stacking faults in the III-V material. **Figure 2.** Schematic diagram of three defects (**a**) Misfit dislocation due to lattice mismatch, (**b**) APB at atomic steps of the substrate, (**c**) Stacking faults in the III-V material.

### *2.1. Lattice Mismatch 2.1. Lattice Mismatch*

One important source of strain in heteroepitaxy is the difference in the lattice constant between different materials, referred to as lattice mismatch. This mismatch introduces strain in the epitaxial layer since it is forced to adapt to the lattice constant of the substrate when it is being deposited on. Eventually, after exceeding a critical thickness, the energy stored as strain will become so huge that the layer will relax. For example, at room temperature, the lattice constants of Si and GaAs were 0.543 nm and 0.565 nm, respectively, and the lattice mismatch was 4.1%. The strain in the heteroepitaxial layer resulting from mismatch is given by [4]: One important source of strain in heteroepitaxy is the difference in the lattice constant between different materials, referred to as lattice mismatch. This mismatch introduces strain in the epitaxial layer since it is forced to adapt to the lattice constant of the substrate when it is being deposited on. Eventually, after exceeding a critical thickness, the energy stored as strain will become so huge that the layer will relax. For example, at room temperature, the lattice constants of Si and GaAs were 0.543 nm and 0.565 nm, respectively, and the lattice mismatch was 4.1%. The strain in the heteroepitaxial layer resulting from mismatch is given by [4]:

$$\mathfrak{a}\_{m} = \frac{\mathfrak{a}\_{\mathfrak{s}} - \mathfrak{a}\_{\mathfrak{o}}}{\mathfrak{a}\_{\mathfrak{o}}} \tag{1}$$

mo (1) where *α<sup>m</sup>* is the mismatch strain in the epilayer; *α<sup>o</sup>* and *α<sup>s</sup>* are the substrate and overlayer lattice parameters, respectively.

⊥

where *α<sup>m</sup>* is the mismatch strain in the epilayer; *αo* and *α<sup>s</sup>* are the substrate and overlayer lattice parameters, respectively. If *α<sup>o</sup>* is greater than *αs*, it is a tensile strain; otherwise, it is compressive strain. In an epitaxial layer grown on a foreign substrate, the layer is subjected to biaxial strain in the If *α<sup>o</sup>* is greater than *α<sup>s</sup>* , it is a tensile strain; otherwise, it is compressive strain. In an epitaxial layer grown on a foreign substrate, the layer is subjected to biaxial strain in the plane of the substrate (normally the (001), if it is unrelieved, the biaxial strain will translate to a strain in the vertical direction according to:

$$
\varepsilon^{\perp} = \varepsilon^{\parallel} \frac{1}{R\_B} = \varepsilon^{\parallel} \frac{\mathbb{C}\_{11}}{2\mathbb{C}\_{12}} \tag{2}
$$

(2)

#### = ‖ = *2.2. Thermal Expansion Coefficient Mismatch*

 12 *2.2. Thermal Expansion Coefficient Mismatch* Most materials not only have specific lattice constants but also specific coefficients of thermal expansion (CTE). This is highly relevant in heteroepitaxy since epitaxy is normally carried out at a temperature of several hundreds of degrees, which means that Most materials not only have specific lattice constants but also specific coefficients of thermal expansion (CTE). This is highly relevant in heteroepitaxy since epitaxy is normally carried out at a temperature of several hundreds of degrees, which means that the lattices of two different materials will contract to different extents upon cool-down. Going from growth temperature to room temperature, there will be an amount strain introduced in the epitaxial layer according to [40]:

R B ‖

11 2C

C

$$
\varepsilon\_{\rm fll} = \int\_{T\_G}^{RT} a\_S - a\_0 dT \tag{3}
$$

where *α*<sup>s</sup> and *α*<sup>0</sup> are the thermal expansion coefficients of the substrate and the epitaxial overlayer, respectively, and *T<sup>G</sup>* the temperature at which growth takes place. Since the grown layer is normally more or less relaxed during growth, the introduced thermal strain may lead to formation of dislocations.

When III-V thin film is deposited on a thick substrate, the layer will undergo a formation of misfit dislocations and threading dislocations. After the growth is completed, during the process of lowering the temperature of the wafer, the difference in CTE between the two causes the shrinkage ratio of the two materials to be different, resulting in thermal strain. We assume that during the growth process, it is completely relaxed. After the wafer is cooled down to room temperature, larger CTE (III-V materials) causes greater contraction than the Si substrate, so tensile strain is generated in III-V epitaxy. Nevertheless, the strain caused by the thermal expansion mismatch can be solved through buffer thickness. However, the thermal cracks emerge easily if a thick buffer accumulates too much strain energy when temperature changes. For example, CTE of GaAs (6.6 <sup>×</sup> <sup>10</sup>−<sup>6</sup> <sup>K</sup>−<sup>1</sup> ) is larger than Si (2.3 <sup>×</sup> <sup>10</sup>−<sup>6</sup> <sup>K</sup>−<sup>1</sup> ); the thermal mismatches between Ge, GaAs, and Si are 103%, 105%. Thickness for III-V films on Si is typically below 10 µm [41]. Therefore, huge thermal strain is generated in the thick III-V layer when the temperature drops to room temperature, resulting in thermal cracks through the III-V epitaxial layer. Similar to other defects, the presence of thermal cracks introduces destructive effects on the quality of the III-V epilayer and performance of optoelectronic devices, such as light scattering centers, the electrical leakage path, and a limitation on the total thickness of the epilayer [19]

### *2.3. Anti-Phase Boundary*

Most materials have their own crystal structure and surface primarily. The V group (Si, Ge) has a diamond crystal structure, while III-arsenides and III-phosphides have a zincblende crystal structure which makes the different types of atomic stacking. For example, the diamond crystal structure has its ABAB . . . atomic stacking, but the zincblende crystal structure has its ABCABC . . . atomic stacking. When the III-V layer is grown on the Si substrate, the different types of atomic stacking make the APB defect formation, which arises from the polar on nonpolar nature of the III-V/Si heteroepitaxy and monatomic step of the (001) Si surface [42]. For instance, in the GaAs zincblende structure without defects, Ga atoms should be alternately connected with As atoms. Once the coordination of some atoms in the structure changes so that Ga atoms are no longer connected with As atoms, a two-dimensional structural defect will be formed at the interface where the changes occur, named APB. APBs arise as the existence of steps with odd atomic thickness on the surface of element semiconductor substrates (Si or Ge) and the uneven coverage of group III or V sources during silicon surface pretreatment [43].

In the process of substrate processing, it is impossible to obtain the (001) substrate with a perfect crystalline orientation. In this way, there are certain atomic steps on the actual substrate surface, which is a general monatomic layer height. The causes of APBs are shown in Ge substrate epitaxial GaAs. In the metal-organic chemical vapor phase epitaxy (MOCVD) system, arsenide (As) is pretreated with an arsenic atom (ideal) to grow GaAs on the Ge substrate (001) with the mono-atomic step surface. Due to the presence of the monatomic Ge step, the As atom and Ga atom are arranged alternately in the direction of (001), and GaAs interface with two orientations, and the As-As bond and Ga-Ga bond appear above the step, forming APBs. Figure 3a shows the single-layer steps (or odd layer height steps) to produce two domains in the III-V overlayer with opposite sub lattice allocation, whereas double-layer (or even-numbered) steps do not [44]. Although APBs do not involve partial dislocations, they can still interact with TDDs [45]. APBs are regarded as the non-radiative recombination centers for the optoelectronic devices, which will reduce the life of a few carriers in the device, and increase the scattering of most carriers, thus affecting the device performance. To characterize the influence of APBs on the optical properties, photoluminesce quenching and spectral broadening were usually adopted [46].

Besides, the APBs defect can be observed under SEM or AFM. As an example, irregular and curved boundaries were clearly observed for the SEM image of the as-grown GaAs/Si(100) sample (Figure 3b) [47]. APB is a plane defect, which can prevent the manufacture of Si-based III-V devices. Therefore, achieving APB-free III-V/Si heteroepitaxy is a fundament for following III-V devices' fabrication. Besides, the APBs defect can be observed under SEM or AFM. As an example, irregular and curved boundaries were clearly observed for the SEM image of the as-grown GaAs/Si(100) sample (Figure 3b) [47]. APB is a plane defect, which can prevent the manufacture of Si-based III-V devices. Therefore, achieving APB-free III-V/Si heteroepitaxy is a fundament for following III-V devices' fabrication.

involve partial dislocations, they can still interact with TDDs [45]. APBs are regarded as the non-radiative recombination centers for the optoelectronic devices, which will reduce the life of a few carriers in the device, and increase the scattering of most carriers, thus affecting the device performance. To characterize the influence of APBs on the optical properties, photoluminesce quenching and spectral broadening were usually adopted [46].

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**Figure 3.** (**a**) (Color online) Schematic showing nonpolar/polar interface between Ge and GaAs. Monoatomic steps on the Ge surface result in APBs, planes of As-As, or Ga–Ga bonds. The APD can either self-annihilate (left) or rise to the surface (right). Diatomic steps on the Ge surface (center) do not result in APD formation. Reprinted with permission from ref. [44]. Copyright 2016 American Vacuum Society. (**b**) SEM plan view images of GaAs/Ge/Si (100) sample with APBs. Reprinted with permission from ref. [47]. Copyright 2021 Springer Nature. **Figure 3.** (**a**) (Color online) Schematic showing nonpolar/polar interface between Ge and GaAs. Monoatomic steps on the Ge surface result in APBs, planes of As-As, or Ga–Ga bonds. The APD can either self-annihilate (left) or rise to the surface (right). Diatomic steps on the Ge surface (center) do not result in APD formation. Reprinted with permission from ref. [44]. Copyright 2016 American Vacuum Society. (**b**) SEM plan view images of GaAs/Ge/Si (100) sample with APBs. Reprinted with permission from ref. [47]. Copyright 2021 Springer Nature.

### *2.4. Threading Dislocation Density 2.4. Threading Dislocation Density*

Heteroepitaxy of III/V materials on Si substrates results in the huge strain energy, which is released in the thickness of epitaxy via the formation of MDs along the heterointerface and TDs toward the surface. Thick epitaxy can release the mismatch strain but generates a large number of line defect dislocations. In addition, because of the mismatch TEC of III-V and Si, thick III-V epitaxy also accumulates much strain energy upon temperature cool down, inducing thermal cracks that emerge easily. These thermal cracks case the defects and surface roughness in the epitaxial layer; usually the dislocation density near the interface is as high as 109–1011/cm<sup>2</sup> [48,49]. Heteroepitaxy of III/V materials on Si substrates results in the huge strain energy, which is released in the thickness of epitaxy via the formation of MDs along the heterointerface and TDs toward the surface. Thick epitaxy can release the mismatch strain but generates a large number of line defect dislocations. In addition, because of the mismatch TEC of III-V and Si, thick III-V epitaxy also accumulates much strain energy upon temperature cool down, inducing thermal cracks that emerge easily. These thermal cracks case the defects and surface roughness in the epitaxial layer; usually the dislocation density near the interface is as high as 109–1011/cm<sup>2</sup> [48,49].

Dislocations are line defects representing a break of symmetry along a line, called the dislocation line, which are defined by a line vector, a Burgers vector describing the distortion of the lattice along the line, and a glide plane on which the dislocation moves. Dislocations can generally be subdivided into edge dislocations and screw dislocations. The fundamental difference between these two dislocation types is that whereas the edge dislocation is perpendicular to the dislocation line vector, the screw dislocation has a Burger vector parallel to the line vector. According to the angle between Burgers and the dislocation line, 90° (edge), 0° (screw), and 60° units are the important dislocations, and the 60° unit is the main dislocation which occurs mostly at the edge of island growth during initial epitaxy. Hence, the defect formation and glide mechanism are discussed. For heteroepitaxy to begin, a two-dimensional film Tc (a few nanometers) was grown on the substrate, allowing plastic relaxation to start. Because of the lager lattice mismatch, TDs will originate from the interface and glide along the slip planes to the surface with the increase in the epitaxy. When many dislocations appear in the same area, dislocation lines are formed by upward extension of multiple obvious dislocations. The entanglement of dislocation lines changes the direction of the dislocation movement. When multiple dislocations are entangled into one, the total number of dislocation lines will decrease, thus reducing the penetrating dislocation generated by upward growth and ex- **(a) (b)** Dislocations are line defects representing a break of symmetry along a line, called the dislocation line, which are defined by a line vector, a Burgers vector describing the distortion of the lattice along the line, and a glide plane on which the dislocation moves. Dislocations can generally be subdivided into edge dislocations and screw dislocations. The fundamental difference between these two dislocation types is that whereas the edge dislocation is perpendicular to the dislocation line vector, the screw dislocation has a Burger vector parallel to the line vector. According to the angle between Burgers and the dislocation line, 90◦ (edge), 0◦ (screw), and 60◦ units are the important dislocations, and the 60◦ unit is the main dislocation which occurs mostly at the edge of island growth during initial epitaxy. Hence, the defect formation and glide mechanism are discussed. For heteroepitaxy to begin, a two-dimensional film Tc (a few nanometers) was grown on the substrate, allowing plastic relaxation to start. Because of the lager lattice mismatch, TDs will originate from the interface and glide along the slip planes to the surface with the increase in the epitaxy. When many dislocations appear in the same area, dislocation lines are formed by upward extension of multiple obvious dislocations. The entanglement of dislocation lines changes the direction of the dislocation movement. When multiple dislocations are entangled into one, the total number of dislocation lines will decrease, thus reducing the penetrating dislocation generated by upward growth and extension. However, the dislocation entanglement generates new dislocations in different directions, some of which annihilate with epitaxial growth and some penetrate to the surface, increasing the surface dislocation density. In addition, the surface dislocation mainly consists of proliferating dislocation and penetrating dislocation, forming a "dislocation half-loop". Figure 4 shows a sketch of MD formation by the glide of an existing TD from the substrate (I) and by

dislocation half-loop formation (II). This "dislocation half-loop" has a great contribution to the strain release [50]. half-loop" has a great contribution to the strain release [50].

tension. However, the dislocation entanglement generates new dislocations in different directions, some of which annihilate with epitaxial growth and some penetrate to the surface, increasing the surface dislocation density. In addition, the surface dislocation mainly consists of proliferating dislocation and penetrating dislocation, forming a "dislocation half-loop". Figure 4 shows a sketch of MD formation by the glide of an existing TD from the substrate (I) and by dislocation half-loop formation (II). This "dislocation

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Copyright 2018 IOP Publishing.

**Figure 4.** Schematic for the formation of misfit dislocation via threading dislocation glide: (**I**) TDs bend over and glide along the slip planes, (**a**,**b**) and half-loop formation; (**II**) half-loop nucleation at the surface and gliding down to the interface, (**c**,**d**). Reprinted with permission from ref. [50]. **Figure 4.** Schematic for the formation of misfit dislocation via threading dislocation glide: (**I**) TDs bend over and glide along the slip planes, (**a**,**b**) and half-loop formation; (**II**) half-loop nucleation at the surface and gliding down to the interface, (**c**,**d**). Reprinted with permission from ref. [50]. Copyright 2018 IOP Publishing.

TDs are one-dimensional crystal dislocations in semiconductor film, which has a serious impact on the properties of semiconductors. The TD is the scattering or absorption center of the carrier or light, which reduces the free path of the electron and greatly reduces the mobility of the carrier. For example, in optoelectronic devices, TDs are the center of non-radiative recombination because the intermediate bandgap energy level in the dislocation core is highly efficient at capturing minority carriers, resulting in a minority load in the material. These defects will form a non-radiative composite center, greatly reducing device lifetime and luminous efficiency. In the case of a semiconductor laser, only a large number of minority carrier reversals are realized in the active layer to obtain an effective gain, and a laser is generated, and it is seen that the reduction in minority carrier lifetime is disadvantageous [51]. In the laser structure, if the minority carrier lifetime is reduced due to dislocations, more injected minority carriers will form a TDs are one-dimensional crystal dislocations in semiconductor film, which has a serious impact on the properties of semiconductors. The TD is the scattering or absorption center of the carrier or light, which reduces the free path of the electron and greatly reduces the mobility of the carrier. For example, in optoelectronic devices, TDs are the center of nonradiative recombination because the intermediate bandgap energy level in the dislocation core is highly efficient at capturing minority carriers, resulting in a minority load in the material. These defects will form a non-radiative composite center, greatly reducing device lifetime and luminous efficiency. In the case of a semiconductor laser, only a large number of minority carrier reversals are realized in the active layer to obtain an effective gain, and a laser is generated, and it is seen that the reduction in minority carrier lifetime is disadvantageous [51]. In the laser structure, if the minority carrier lifetime is reduced due to dislocations, more injected minority carriers will form a non-radiative recombination before the number of population inversions are sufficient; then, the quality of the laser will fall. Early research work pointed out that for lasers, when the TDD is exceeded, the laser will not work properly due to the reduced lifetime of minority carriers [52]. Therefore, the necessary means to prevent the dislocation from extending upward and reducing TDD in the hetero-epitaxial layer is the main problem of laser fabrication on the basis of the current stage.

non-radiative recombination before the number of population inversions are sufficient; then, the quality of the laser will fall. Early research work pointed out that for lasers, when the TDD is exceeded, the laser will not work properly due to the reduced lifetime of minority carriers [52]. Therefore, the necessary means to prevent the dislocation from extending upward and reducing TDD in the hetero-epitaxial layer is the main problem of laser fabrication on the basis of the current stage. TDD is a quantitative parameter which describes the quality of the epitaxial layer. It can be measured by the three common approaches: (1) Etch-pit density (EPD) measure-TDD is a quantitative parameter which describes the quality of the epitaxial layer. It can be measured by the three common approaches: (1) Etch-pit density (EPD) measurement [53]; (2) X-ray diffraction (XRD) measurement [54]; (3) Transmission electron microscopy (TEM) [55]. In the EPD method, TDD is obtained by calculating the pits at the crystalline region by optical observation or atomic force microscopy (AFM), which is a very easy, quick, and cheap process, but it tends to underestimate the TDD. XRD provides a non-destructive measurement of TDD in the range from 10<sup>5</sup> to 10<sup>9</sup> cm−<sup>2</sup> . It is possible to calculate the TDD by measuring FWHM of rocking curve widths, because dislocations broaden the rocking curve. TEM measurement enables direct observation of TDs and quantitative analysis in the layer.

ment [53]; (2) X-ray diffraction (XRD) measurement [54]; (3) Transmission electron microscopy (TEM) [55]. In the EPD method, TDD is obtained by calculating the pits at the crystalline region by optical observation or atomic force microscopy (AFM), which is a

sible to calculate the TDD by measuring FWHM of rocking curve widths, because dislocations broaden the rocking curve. TEM measurement enables direct observation of TDs

to 10<sup>9</sup> cm−2. It is pos-

and quantitative analysis in the layer.

#### *2.5. Stacking Faults* Stacking faults (SFs) are planar defects (PDs) representing a disruption in the crys-*2.5. Stacking Faults*

*2.5. Stacking Faults*

Stacking faults (SFs) are planar defects (PDs) representing a disruption in the crystallographic stacking order. In crystals with the Face-Centered Cubic (FCC) type lattice, they normally occur on {111} planes since these have the lowest SF energy. SFs can occur either as an insertion or removal of a crystallographic plane. This may happen either during deposition or by the gliding of a plane from its natural position to another. Joseph et al. [44] investigated the SFs originating from defects or contamination on the surface prior to growth, especially at low Tsub, which caused pits on the surface along [110] direction, as shown in Figure 5. tallographic stacking order. In crystals with the Face-Centered Cubic (FCC) type lattice, they normally occur on {111} planes since these have the lowest SF energy. SFs can occur either as an insertion or removal of a crystallographic plane. This may happen either during deposition or by the gliding of a plane from its natural position to another. Joseph et al. [44] investigated the SFs originating from defects or contamination on the surface prior to growth, especially at low Tsub, which caused pits on the surface along [11 0] direction, as shown in Figure 5. Stacking faults (SFs) are planar defects (PDs) representing a disruption in the crystallographic stacking order. In crystals with the Face-Centered Cubic (FCC) type lattice, they normally occur on {111} planes since these have the lowest SF energy. SFs can occur either as an insertion or removal of a crystallographic plane. This may happen either during deposition or by the gliding of a plane from its natural position to another. Joseph et al. [44] investigated the SFs originating from defects or contamination on the surface prior to growth, especially at low Tsub, which caused pits on the surface along [11 — 0] direction, as shown in Figure 5.

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*Nanomaterials* **2022**, *12*, x FOR PEER REVIEW 8 of 48

**Figure 5.** (Color online) (**a**) Schematic down [110] direction showing a SFP that originates from defect or contamination on the Ge surface; (**b**) XTEM with g = 002; (**c**) AFM image for the surface pits. Reprinted with permission from ref. [44]. Copyright 2016 American Vacuum Society. **Figure 5.** (Color online) (**a**) Schematic down [110] direction showing a SFP that originates from defect or contamination on the Ge surface; (**b)** XTEM with g = 002; (**c**) AFM image for the surface pits. Reprinted with permission from ref. [44]. Copyright 2016 American Vacuum Society. defect or contamination on the Ge surface; (**b**) XTEM with g = 002; (**c**) AFM image for the surface pits. Reprinted with permission from ref. [44]. Copyright 2016 American Vacuum Society.

**Figure 5.** (Color online) (**a**) Schematic down [110] direction showing a SFP that originates from

### **3. Defect Solution for III-V Hetero-Epitaxy on (001) Silicon Wafer 3. Defect Solution for III-V Hetero-Epitaxy on (001) Silicon Wafer**

#### **3. Defect Solution for III-V Hetero-Epitaxy on (001) Silicon Wafer** *3.1. Surface Treatment for Si Substrate 3.1. Surface Treatment for Si Substrate*

*3.1. Surface Treatment for Si Substrate* The atomic-level Si substrate platform is a basis for the III-V semiconductor devices' manufacture. It is because rough or particle substrates can cause the stacking faults during the heteroepitaxy. To avoid stacking faults, a very clean surface for the Si substrate is very important. The ex-situ process [56] (including cycled HF dip and O<sup>2</sup> plasma treatments) The atomic-level Si substrate platform is a basis for the III-V semiconductor devices' manufacture. It is because rough or particle substrates can cause the stacking faults during the heteroepitaxy. To avoid stacking faults, a very clean surface for the Si substrate is very important. The ex-situ process [56] (including cycled HF dip and O<sup>2</sup> plasma treatments) was developed, and film thickness variation (around 0.3 nm) is well reproduced (Figure 6). The atomic-level Si substrate platform is a basis for the III-V semiconductor devices' manufacture. It is because rough or particle substrates can cause the stacking faults during the heteroepitaxy. To avoid stacking faults, a very clean surface for the Si substrate is very important. The ex-situ process [56] (including cycled HF dip and O<sup>2</sup> plasma treatments) was developed, and film thickness variation (around 0.3 nm) is well reproduced (Figure 6).

**Figure 6.** Thickness variation before and after HF 1% bath taken from a single Si substrate. Reprinted with permission from ref. [56]. Copyright 2015 ELSEVIER BV. **Figure 6.** Thickness variation before and after HF 1% bath taken from a single Si substrate. Reprinted with permission from ref. [56]. Copyright 2015 Elsevier BV.

**Figure 6.** Thickness variation before and after HF 1% bath taken from a single Si substrate. Re-
