*Article* **Investigate on the Mechanism of HfO2/Si0.7Ge0.3 Interface Passivation Based on Low-Temperature Ozone Oxidation and Si-Cap Methods**

**Qide Yao 1,2 , Xueli Ma 2,\*, Hanxiang Wang 1,2, Yanrong Wang 1,\*, Guilei Wang <sup>2</sup> , Jing Zhang <sup>1</sup> , Wenkai Liu <sup>1</sup> , Xiaolei Wang <sup>2</sup> , Jiang Yan <sup>1</sup> , Yongliang Li 2,\* and Wenwu Wang <sup>2</sup>**


**Abstract:** The interface passivation of the HfO2/Si0.7Ge0.3 stack is systematically investigated based on low-temperature ozone oxidation and Si-cap methods. Compared with the Al2O3/Si0.7Ge0.3 stack, the dispersive feature and interface state density (Dit) of the HfO2/Si0.7Ge0.3 stack MOS (Metal-Oxide-Semiconductor) capacitor under ozone direct oxidation (pre-O sample) increases obviously. This is because the tiny amounts of GeOx in the formed interlayer (IL) oxide layer are more likely to diffuse into HfO<sup>2</sup> and cause the HfO2/Si0.7Ge0.3 interface to deteriorate. Moreover, a post-HfO<sup>2</sup> -deposition (post-O) ozone indirect oxidation is proposed for the HfO2/Si0.7Ge0.3 stack; it is found that compared with pre-O sample, the Dit of the post-O sample decreases by about 50% due to less GeO<sup>x</sup> available in the IL layer. This is because the amount of oxygen atoms reaching the interface of HfO2/Si0.7Ge0.3 decreases and the thickness of IL in the post-O sample also decreases. To further reduce the Dit of the HfO2/Si0.7Ge0.3 interface, a Si-cap passivation with the optimal thickness of 1 nm is developed and an excellent HfO2/Si0.7Ge0.3 interface with Dit of 1.53 <sup>×</sup> <sup>10</sup><sup>11</sup> eV−<sup>1</sup> cm−<sup>2</sup> @ E−E<sup>v</sup> = 0.36 eV is attained. After detailed analysis of the chemical structure of the HfO2/IL/Si-cap/Si0.7Ge0.3 using X-ray photoelectron spectroscopy (XPS), it is confirmed that the excellent HfO2/Si0.7Ge0.3 interface is realized by preventing the formation of Hf-silicate/Hf-germanate and Si oxide originating from the reaction between HfO<sup>2</sup> and Si0.7Ge0.3 substrate.

**Keywords:** HfO2/Si0.7Ge0.3 gate stack; ozone oxidation; Si-cap; interface state density; passivation

### **1. Introduction**

High-mobility channel materials and novel device architectures, such as FinFETs (Fin Field-Effect Transistor) and nanowire FETs, are proposed to address the demand for scaling CMOS (Complementary Metal-Oxide-Semiconductor) technology [1,2]. In contrast to other potential materials, such as germanium (Ge) or III–V materials, silicon germanium (SiGe) is considered the most promising channel material for PMOS due to its tunability of band gaps and high hole mobility [3]. However, one of the main challenges in integrating SiGe into the novel devices is obtaining a high-quality interlayer (IL) between high-k gate oxide and SiGe substrate.

To control the interface quality, many methods have been extensively explored, such as plasma (N<sup>2</sup> or NH3) nitridation passivation [4,5], sulfur passivation [6], thermal oxidation [7,8], low-temperature ozone passivation [9–12] and Si-cap passivation [13]. Among them, low-temperature ozone passivation with low thermal budge and Si-cap passivation with excellent properties of interface are considered the most promising passivation methods. For example, the interface state density (Dit) of 2.2 <sup>×</sup> <sup>10</sup><sup>12</sup> eV−<sup>1</sup> cm−<sup>2</sup>

**Citation:** Yao, Q.; Ma, X.; Wang, H.; Wang, Y.; Wang, G.; Zhang, J.; Liu, W.; Wang, X.; Yan, J.; Li, Y.; et al. Investigate on the Mechanism of HfO2/Si0.7Ge0.3 Interface Passivation Based on Low-Temperature Ozone Oxidation and Si-Cap Methods. *Nanomaterials* **2021**, *11*, 955. https:// doi.org/10.3390/nano11040955

Academic Editor: Alexander Kromka

Received: 23 February 2021 Accepted: 7 April 2021 Published: 9 April 2021

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

is attained by using a low-temperature ozone oxidation to passivate the interface of Al2O3/Si0.7Ge0.3[11],and the Dit of 2 <sup>×</sup> <sup>10</sup><sup>11</sup> eV−<sup>1</sup> cm−<sup>2</sup> for the interface of HfO2/Si0.8/Ge0.2 is realized by using a Si-cap passivation method [14]. However, the technique and mechanism of interface passivation of the HfO2/SiGe via low-temperature ozone oxidation or Si-cap method still needs further investigation.

In this paper, we fabricated HfO2/IL/Si0.7Ge0.3 gate stacks MOS capacitors by utilizing low-temperature ozone oxidation and Si cap passivation methods. We carefully compared their electrical properties, and the chemical structure of HfO2/IL/SiGe gate stacks. It is found that the post-HfO2-depositon (post-O) ozone indirect oxidation is a better choice than a step-by-step procedure (pre-O) method in terms of Dit reduction. More importantly, the optimal Si cap method can realize a lower Dit of 1.53 <sup>×</sup> <sup>10</sup><sup>11</sup> eV−<sup>1</sup> cm−<sup>2</sup> @ E−E<sup>v</sup> = 0.36 eV by preventing the formation of Hf-silicate/Hf-germanate and Si oxide originating from the reaction between HfO<sup>2</sup> and Si0.7Ge0.3 substrate.

### **2. Materials and Methods**

After standard HF-last cleaning, the 30 nm Si0.7Ge0.3 layer was epitaxially grown in a reduced pressure chemical vapor deposition system (ASM E2000 plus, Amsterdam, The Netherlands) on an 8-inch Si substrate. The low-temperature ozone passivation or Si-cap passivation was employed to passivate the interface of HfO2/Si0.7Ge0.3. For lowtemperature ozone passivation samples, the ozone oxidation can occur on the Si0.7Ge0.3 surface directly (step-by-step procedure (pre-O)) or post HfO<sup>2</sup> deposition (post-O). The ozone oxidation was carried out in 10% O3/O<sup>2</sup> mixture ambience with the pressure of 3.1 Torr in an atomic-layer-deposition (ALD) chamber (Beneq TFS 200 system, Espoo, Finland). The temperature of the ozone oxidation was 300 ◦C. For Si-cap passivation, a Si-cap layer was in situ formed on the epitaxial Si0.7Ge0.3 layer in the same chamber. After the passivation treatment, the W/TiN or W/TiN/HfO<sup>2</sup> gate stack was deposited as the gate stack of MOS capacitors. Finally, W/TiN/HfO2/IL/Si0.7Ge0.3 MOS capacitors were annealed in the forming gas (10% H2, 90% N2) at 350 ◦C for 30 min.

The chemical structures of the HfO2/IL/Si0.7Ge0.3 stacks were studied by X-ray photoelectron spectroscopy (XPS), which was carried out in a Thermo Scientific ESCALAB 250xi (Waltham, MA, USA) system with a photon energy of 1486.7 eV (Al Kα source). The photoelectron emission take-off angle was 90◦ relative to the sample surface and the pass energy was 15 eV. Moreover, TEM (Transmission Electron Microscope) and EDX (Energy Dispersive X-Ray Spectroscopy) Mapping analysis were performed by using FEI Talos F200X (Hillsboro, MI, USA) to verify the gate stack lattice structure and element content. Multi-frequency capacitance-voltage (C-V) along with conductance-voltage (G-V) measurements were measured using a Keysight 4990 A (Santa Rosa, CA, USA), and leakage-voltage (I-V) was measured using an Agilent B-1500 semiconductor analyzer.

### **3. Results and Discussion**

### *3.1. Low-Temperature Ozone Oxidation Passivation of HfO2/Si0.7Ge0.3 Interface*

In our previous work, the low-temperature ozone oxidation passivation method has been studied in detail based on Al2O3/Si0.7Ge0.3 gate stacks. It was found that oxidation time played an important role to obtain a high-quality interlayer (IL) and should be at least 5 minutes. Otherwise, the unoxidized Ge atoms would be trapped in the IL, causing the IL as well as the relevant electrical properties to deteriorate. Moreover, increasing oxidation time would result in an increase in the ratio of Si4+ to Si3+ of the oxide interlayer, which can help decrease the Dit [15]. Thus, we chose 30 min as the oxidation time, which has proven to be an optimal experimental condition, to passivate the HfO2/Si0.7Ge0.3 interface in this work.

Figure 1a,b depicts the multi-frequency (1 kHz to 1 MHz) C-V characteristics of W/TiN/Al2O3/IL/Si0.7Ge0.3 (Al2O<sup>3</sup> sample) and W/TiN/HfO2/IL/Si0.7Ge0.3 (HfO2-pre-O sample) MOS capacitors treated with 30 min ozone direct oxidation, respectively. The flat band voltages (Vfb) are also shown in the figures. The frequency dispersion features

of the C−V curves observed at gate biases smaller than the Vfb, are caused by trapping and de-trapping of holes at traps with energies between approximately mid-gap and the Si0.7Ge0.3 valence band edge, corresponding to the depletion of the Si0.7Ge0.3 substrate. Comparing Figure 1b with Figure 1a, it is observed that the dispersion feature increases considerably. The energy distributions of the interface state density (Dit) were extracted using the conductance method [16], and given in their respective inset in Figure 1. We can see that both of the Dit of the two samples decreases along with SiGe band gap energy and the maximum Dit values appear near the valence band edge (Ev). However, the maximum value increases from 3.96 <sup>×</sup> <sup>10</sup><sup>12</sup> eV−<sup>1</sup> cm−<sup>2</sup> for the Al2O<sup>3</sup> sample to 2.67 <sup>×</sup> <sup>10</sup><sup>13</sup> eV−<sup>1</sup> cm−<sup>2</sup> for the HfO2-pre-O sample. According to our previous work [17], it is known that for 300 ◦C/30 min ozone oxidation, about 54% of the Ge atoms of the outermost atomic layer of Si0.7Ge0.3 can be oxidized in the initial stage of oxidation. No more Ge atoms would take part in the oxidation process as the oxidation time increases. The GeO<sup>x</sup> and SiO<sup>x</sup> thickness of the formed oxide layer are estimated to be 0.15 nm and 0.72 nm, respectively. Compared with Al2O3, GeO<sup>x</sup> is more likely to diffuse into HfO<sup>2</sup> and cause the HfO2/SiGe interface to deteriorate [18]. Therefore, the increased Dit of the HfO2-pre-O sample can be attributed to tiny amounts of GeO<sup>x</sup> in the formed oxide layer. C−V curves observed at gate biases smaller than the Vfb, are caused by trapping and de‐ trapping of holes at traps with energies between approximately mid‐gap and the Si0.7Ge0.3 valence band edge, corresponding to the depletion of the Si0.7Ge0.3 substrate. Comparing Figure 1b with Figure 1a, it is observed that the dispersion feature increases considerably. The energy distributions of the interface state density (Dit) were extracted using the con‐ ductance method [16], and given in their respective inset in Figure 1. We can see that both of the Dit of the two samples decreases along with SiGe band gap energy and the maxi‐ mum Dit values appear near the valence band edge (Ev). However, the maximum value increases from 3.96 × 1012 eV−1cm−<sup>2</sup> for the Al2O3 sample to 2.67 × 1013 eV−1cm−<sup>2</sup> for the HfO2‐ pre‐O sample. According to our previous work [17], it is known that for 300 °C/30 min ozone oxidation, about 54% of the Ge atoms of the outermost atomic layer of Si0.7Ge0.3 can be oxidized in the initial stage of oxidation. No more Ge atoms would take part in the oxidation process as the oxidation time increases. The GeOx and SiOx thickness of the formed oxide layer are estimated to be 0.15 nm and 0.72 nm, respectively. Compared with Al2O3, GeOx is more likely to diffuse into HfO2 and cause the HfO2/SiGe interface to dete‐ riorate [18]. Therefore, the increased Dit of the HfO2‐pre‐O sample can be attributed to tiny amounts of GeOx in the formed oxide layer.

Figure 1a,b depicts the multi‐frequency (1 kHz to 1 MHz) C‐V characteristics of W/TiN/Al2O3/IL/Si0.7Ge0.3 (Al2O3 sample) and W/TiN/HfO2/IL/Si0.7Ge0.3 (HfO2‐pre‐O sam‐ ple) MOS capacitors treated with 30 min ozone direct oxidation, respectively. The flat band voltages (Vfb) are also shown in the figures. The frequency dispersion features of the

*Nanomaterials* **2021**, *11*, x FOR PEER REVIEW 3 of 9

**Figure 1.** Multi‐frequency C‐V characteristics of (**a**) Al2O3 sample (**b**) HfO2‐pre‐O sample with 30 min oxidation time (di‐ rect). The insets are their respective energy distributions of Dit. **Figure 1.** Multi-frequency C-V characteristics of (**a**) Al2O<sup>3</sup> sample (**b**) HfO<sup>2</sup> -pre-O sample with 30 min oxidation time (direct). The insets are their respective energy distributions of Dit.

Figure 2 depicts the multi‐frequency (1 kHz to 1 MHz) C‐V characteristics of W/TiN/HfO2/IL/Si0.7Ge0.3 (HfO2‐post‐O sample) MOS capacitor treated with 30 min ozone indirect oxidation, in which the ozone oxidation was carried out after the deposition of HfO2. The corresponding energy distributions of Dit is also given in the inset. Compared with Figure 1b, an obvious improvement in the frequency dispersion feature is observed, and the Dit value decreases by about 50%. We infer that the improvement may arise from the following two factors. First, due to the barrier effect of the HfO2 layer on the diffusion of the oxidizer, the amount of oxygen atoms reaching the interface becomes fewer. Be‐ cause silicon oxidation is more favorable than germanium oxidation in view of thermo‐ dynamic considerations [19], germanium atoms are hardly oxidized in this case. There‐ fore, almost no GeOx would diffuse into HfO2 layer. In addition, the IL thickness of the HfO2‐post‐O sample is smaller than that of the HfO2‐pre‐O sample, which means the amounts of the Ge atoms accumulating at the IL/SiGe interface decrease accordingly. The experimental results prove that the post‐O method is a promising technology to realize an HfO2/IL/SiGe gate stack with small Dit. Figure 2 depicts the multi-frequency (1 kHz to 1 MHz) C-V characteristics of W/TiN/ HfO2/IL/Si0.7Ge0.3 (HfO2-post-O sample) MOS capacitor treated with 30 min ozone indirect oxidation, in which the ozone oxidation was carried out after the deposition of HfO2. The corresponding energy distributions of Dit is also given in the inset. Compared with Figure 1b, an obvious improvement in the frequency dispersion feature is observed, and the Dit value decreases by about 50%. We infer that the improvement may arise from the following two factors. First, due to the barrier effect of the HfO<sup>2</sup> layer on the diffusion of the oxidizer, the amount of oxygen atoms reaching the interface becomes fewer. Because silicon oxidation is more favorable than germanium oxidation in view of thermodynamic considerations [19], germanium atoms are hardly oxidized in this case. Therefore, almost no GeO<sup>x</sup> would diffuse into HfO<sup>2</sup> layer. In addition, the IL thickness of the HfO2-post-O sample is smaller than that of the HfO2-pre-O sample, which means the amounts of the Ge atoms accumulating at the IL/SiGe interface decrease accordingly. The experimental results prove that the post-O method is a promising technology to realize an HfO2/IL/SiGe gate stack with small Dit.

**Figure 2.** Multi‐frequency C‐V characteristics of HfO2‐post‐O sample with 30 min oxidation time (indirect). The corresponding energy distributions of Dit is given in the inset. **Figure 2.** Multi-frequency C-V characteristics of HfO<sup>2</sup> -post-O sample with 30 min oxidation time (indirect). The corresponding energy distributions of Dit is given in the inset. (indirect). The corresponding energy distributions of Dit is given in the inset.

The Al2O3 sample, HfO2‐pre‐O sample and HfO2‐post‐O sample were compared on capacitance equivalent oxide thickness (CET) at −1.5 V bias voltage in accumulation. The CETs of each are 2.28 nm, 1.5 nm and 1.37 nm respectively. Comparing the Al2O3 sample with the HfO2, the CET of the Al2O3 sample is bigger. The HfO2‐post‐O sample decreased the CET, compared to the HfO2‐pre‐O sample. This is supposed to be related to the diffu‐ sion of GeOx. In general, the diffusion of GeOx is less in Al2O3 and HfO2‐post‐O. Using the post‐O method can limit the diffusion of GeOx in HfO2. The diffusion of GeOx affects not only the CET but also the leakage current. The Al2O<sup>3</sup> sample, HfO2-pre-O sample and HfO2-post-O sample were compared on capacitance equivalent oxide thickness (CET) at −1.5 V bias voltage in accumulation. The CETs of each are 2.28 nm, 1.5 nm and 1.37 nm respectively. Comparing the Al2O<sup>3</sup> sample with the HfO2, the CET of the Al2O<sup>3</sup> sample is bigger. The HfO2-post-O sample decreased the CET, compared to the HfO2-pre-O sample. This is supposed to be related to the diffusion of GeOx. In general, the diffusion of GeO<sup>x</sup> is less in Al2O<sup>3</sup> and HfO2-post-O. Using the post-O method can limit the diffusion of GeO<sup>x</sup> in HfO2. The diffusion of GeO<sup>x</sup> affects not only the CET but also the leakage current. The Al2O3 sample, HfO2‐pre‐O sample and HfO2‐post‐O sample were compared on capacitance equivalent oxide thickness (CET) at −1.5 V bias voltage in accumulation. The CETs of each are 2.28 nm, 1.5 nm and 1.37 nm respectively. Comparing the Al2O3 sample with the HfO2, the CET of the Al2O3 sample is bigger. The HfO2‐post‐O sample decreased the CET, compared to the HfO2‐pre‐O sample. This is supposed to be related to the diffu‐ sion of GeOx. In general, the diffusion of GeOx is less in Al2O3 and HfO2‐post‐O. Using the post‐O method can limit the diffusion of GeOx in HfO2. The diffusion of GeOx affects not only the CET but also the leakage current. Figure 3 shows the gate Leakage of the Al2O3 sample, HfO2‐pre‐O sample and HfO2‐

Figure 3 shows the gate Leakage of the Al2O3 sample, HfO2‐pre‐O sample and HfO2‐ post‐O sample. Because GeOx is not easily diffused in Al2O3, the leakage current is mini‐ mal for the Al2O3 sample. Comparing with the HfO2‐pre‐O sample, the leakage current HfO2‐post‐O sample can be reduced by an order of magnitude. Figure3shows the gate Leakage of the Al2O<sup>3</sup> sample, HfO2-pre-O sample and HfO2-post-O sample. Because GeO<sup>x</sup> is not easily diffused in Al2O3, the leakage current is minimal for the Al2O<sup>3</sup> sample. Comparing with the HfO2-pre-O sample, the leakage current HfO2 post-O sample can be reduced by an order of magnitude. post‐O sample. Because GeOx is not easily diffused in Al2O3, the leakage current is mini‐ mal for the Al2O3 sample. Comparing with the HfO2‐pre‐O sample, the leakage current HfO2‐post‐O sample can be reduced by an order of magnitude.

**Figure 3.** Gate leakage of Al2O3 sample, HfO2‐pre‐O sample and HfO2‐post‐O sample. **Figure 3. Figure 3.**Gate leakage of Al Gate leakage of Al2O2O33sample, HfO sample, HfO22‐pre‐O sample and HfO2‐post‐O sample. -pre-O sample and HfO<sup>2</sup> -post-O sample.

### *3.2. Si-Cap Passivation of HfO2/Si0.7Ge0.3 Interface*

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To further reduce the Dit of the HfO2/Si0.7Ge0.3 interface, Si-cap passivation is in situ performed on the Si0.7Ge0.3 layer with different thicknesses. It is found that if the Si cap thickness is larger than or equal to 2 nm, there is a step observed in its C-V curve because a second channel is formed in the Si cap layer. This can be avoided by further thinning of the Si cap layer to 1 nm. Moreover, multi-frequency C-V curves (1 kHz to 1 MHz) of the W/TiN/HfO2/IL/Si-cap/Si0.7Ge0.3 MOS capacitor with 1 nm Si-cap are measured and shown in Figure 3. It is worthy to note that the frequency dispersive feature is obviously improved compared with the above ozone passivation. However, the CET of the Si-cap sample from Figure 4 may be inaccurate due to the large gate leakage in the accumulation region. In addition, it can be seen that the carriers are mainly confined in the Si0.7Ge0.3 layer under this optimal Si-cap thickness due to its large valance band offset. For quantitative analysis, the Dit of 1.53 <sup>×</sup> <sup>10</sup><sup>11</sup> eV−<sup>1</sup> cm−<sup>2</sup> @ E−E<sup>v</sup> = 0.36 eV is attained by using the conductance method. Meanwhile, HRTEM, Si and Ge element EDX mapping of the W/TiN/HfO2/IL/Si-cap/Si0.7Ge0.3 MOS capacitor with 1nm Si-cap is also implemented and shown in Figure 5. It is found that there is a ~0.6 nm Si capping on the Si0.7Ge0.3 with a smooth and high-quality interfacial layer. The reduction of Si cap thickness of 0.4 nm is due to the oxidation of Si cap layer in the process of MOS capacitor fabrication. Therefore, 1-nm Si-cap in situ epitaxial grown is chosen as the optimal Si-cap thickness. *3.2. Si‐Cap Passivation of HfO2/Si0.7Ge0.3 Interface* To further reduce the Dit of the HfO2/Si0.7Ge0.3 interface, Si‐cap passivation is in situ performed on the Si0.7Ge0.3 layer with different thicknesses. It is found that if the Si cap thickness is larger than or equal to 2 nm, there is a step observed in its C‐V curve because a second channel is formed in the Si cap layer. This can be avoided by further thinning of the Si cap layer to 1 nm. Moreover, multi‐frequency C‐V curves (1 kHz to 1 MHz) of the W/TiN/HfO2/IL/Si‐cap/Si0.7Ge0.3 MOS capacitor with 1 nm Si‐cap are measured and shown in Figure 3. It is worthy to note that the frequency dispersive feature is obviously im‐ proved compared with the above ozone passivation. However, the CET of the Si‐cap sam‐ ple from Figure 4 may be inaccurate due to the large gate leakage in the accumulation region. In addition, it can be seen that the carriers are mainly confined in the Si0.7Ge0.3 layer under this optimal Si‐cap thickness due to its large valance band offset. For quantitative analysis, the Dit of 1.53 × 1011 eV−1cm−<sup>2</sup> @ E−Ev = 0.36 eV is attained by using the conductance method. Meanwhile, HRTEM, Si and Ge element EDX mapping of the W/TiN/HfO2/IL/Si‐cap/Si0.7Ge0.3 MOS capacitor with 1nm Si‐cap is also implemented and shown in Figure 5. It is found that there is a ~0.6 nm Si capping on the Si0.7Ge0.3 with a smooth and high‐ quality interfacial layer. The reduction of Si cap thickness of 0.4 nm is due to the oxidation of Si cap layer in the process of MOS capacitor fabrication. Therefore, 1‐nm Si‐cap in situ epitaxial grown is chosen as the optimal Si‐cap thickness. *3.2. Si‐Cap Passivation of HfO2/Si0.7Ge0.3 Interface* To further reduce the Dit of the HfO2/Si0.7Ge0.3 interface, Si‐cap passivation is in situ performed on the Si0.7Ge0.3 layer with different thicknesses. It is found that if the Si cap thickness is larger than or equal to 2 nm, there is a step observed in its C‐V curve because a second channel is formed in the Si cap layer. This can be avoided by further thinning of the Si cap layer to 1 nm. Moreover, multi‐frequency C‐V curves (1 kHz to 1 MHz) of the W/TiN/HfO2/IL/Si‐cap/Si0.7Ge0.3 MOS capacitor with 1 nm Si‐cap are measured and shown in Figure 3. It is worthy to note that the frequency dispersive feature is obviously im‐ proved compared with the above ozone passivation. However, the CET of the Si‐cap sam‐ ple from Figure 4 may be inaccurate due to the large gate leakage in the accumulation region. In addition, it can be seen that the carriers are mainly confined in the Si0.7Ge0.3 layer under this optimal Si‐cap thickness due to its large valance band offset. For quantitative analysis, the Dit of 1.53 × 1011 eV−1cm−<sup>2</sup> @ E−Ev = 0.36 eV is attained by using the conductance method. Meanwhile, HRTEM, Si and Ge element EDX mapping of the W/TiN/HfO2/IL/Si‐ cap/Si0.7Ge0.3 MOS capacitor with 1nm Si‐cap is also implemented and shown in Figure 5. It is found that there is a ~0.6 nm Si capping on the Si0.7Ge0.3 with a smooth and high‐ quality interfacial layer. The reduction of Si cap thickness of 0.4 nm is due to the oxidation of Si cap layer in the process of MOS capacitor fabrication. Therefore, 1‐nm Si‐cap in situ epitaxial grown is chosen as the optimal Si‐cap thickness.

**Figure 4.** Multi‐frequency C‐V characteristic of W/TiN/HfO2/IL/Si‐cap/Si0.7Ge0.3 MOS capacitor with 1 nm Si‐cap. **Figure 4.** Multi-frequency C-V characteristic of W/TiN/HfO2/IL/Si-cap/Si0.7Ge0.3 MOS capacitor with 1 nm Si-cap. **Figure 4.** Multi‐frequency C‐V characteristic of W/TiN/HfO2/IL/Si‐cap/Si0.7Ge0.3 MOS capacitor with 1 nm Si‐cap.

**Figure 5.** (**a**) HRTEM, (**b**) Ge, and (**c**) Si element EDX mapping of the W/TiN/HfO2/IL/Si‐cap/Si0.7Ge0.3MOS capacitor with 1 nm Si‐cap. **Figure 5.** (**a**) HRTEM, (**b**) Ge, and (**c**) Si element EDX mapping of the W/TiN/HfO2/IL/Si‐cap/Si0.7Ge0.3MOS capacitor with 1 nm Si‐cap. **Figure 5.** (**a**) HRTEM, (**b**) Ge, and (**c**) Si element EDX mapping of the W/TiN/HfO2/IL/Si-cap/Si0.7Ge0.3 MOS capacitor with 1 nm Si-cap.

For the purpose of investigating the chemical structure of the HfO2/IL/Si-cap/Si0.7Ge0.3 gate stack (Si-cap sample), X-ray photoelectron spectroscopy (XPS) technology is implemented. The chemical structure of the HfO2/Si0.7Ge0.3 gate stack (SiGe sample), in which HfO<sup>2</sup> is deposited on Si0.7Ge0.3 directly, is also analyzed as a control sample. Gaussian-Lorentzian line shapes are used for deconvolution of all the spectra after standard Shirley background subtraction [20]. Figure 6a,b shows the Hf 4f core-level spectra of the Si-cap sample and SiGe sample, respectively. The spectra are both fitted with two component peaks. For the Si-cap sample (shown in Figure 6a), the Hf 4f spectrum consists of a main component at 16.8 eV related to the Hf-O bands in HfO2, and a second component shifted by ~0.9 eV to higher binding energy, which is from the Hf-O-Si and/or Hf-O-Ge bonds. Because the electro-negativities of the Hf second neighbors (i.e., Si and Ge) are similar, it is difficult to distinguish the two contributions of Hf-O-Si and Hf-O-Ge bonds by XPS. It is worth noting that for the SiGe sample (shown in Figure 6b), the areal intensity of Hf-O-Si/Hf-O-Ge is much more than that of Hf-O. This suggests that a large portion of HfO<sup>2</sup> would react with SiGe to form Hf-silicate/Hf-germanate during the HfO<sup>2</sup> ALD deposition process. In addition, no feature of lower banding energy (14.3 eV–14.8 eV) is detected, indicating that no metallic Hf-Si and/or Hf-Ge are formed in the two samples. For the purpose of investigating the chemical structure of the HfO2/IL/Si‐cap/Si0.7Ge0.3 gate stack (Si‐cap sample), X‐ray photoelectron spectroscopy (XPS) technology is imple‐ mented. The chemical structure of the HfO2/Si0.7Ge0.3 gate stack (SiGe sample), in which HfO2 is deposited on Si0.7Ge0.3 directly, is also analyzed as a control sample. Gaussian‐ Lorentzian line shapes are used for deconvolution of all the spectra after standard Shirley background subtraction [20]. Figure 6a,b shows the Hf 4f core‐level spectra of the Si‐cap sample and SiGe sample, respectively. The spectra are both fitted with two component peaks. For the Si‐cap sample (shown in Figure 6a), the Hf 4f spectrum consists of a main component at 16.8 eV related to the Hf‐O bands in HfO2, and a second component shifted by ~0.9 eV to higher binding energy, which is from the Hf‐O‐Si and/or Hf‐O‐Ge bonds. Because the electro‐negativities of the Hf second neighbors (i.e., Si and Ge) are similar, it is difficult to distinguish the two contributions of Hf‐O‐Si and Hf‐O‐Ge bonds by XPS. It is worth noting that for the SiGe sample (shown in Figure 6b), the areal intensity of Hf‐O‐ Si/Hf‐O‐Ge is much more than that of Hf‐O. This suggests that a large portion of HfO2 would react with SiGe to form Hf‐silicate/Hf‐germanate during the HfO2 ALD deposition process. In addition, no feature of lower banding energy (14.3 eV–14.8 eV) is detected, indicating that no metallic Hf‐Si and/or Hf‐Ge are formed in the two samples.

**Figure 6.** The fitted Hf 4f core‐level spectra of (**a**) Si‐cap sample and (**b**) SiGe sample. The blue and red dot lines denote the Hf 4f photoelectron from Hf‐O‐Si and/or Hf‐O‐Ge bonds and Hf‐O bonds in HfO2, respectively. **Figure 6.** The fitted Hf 4f core-level spectra of (**a**) Si-cap sample and (**b**) SiGe sample. The blue and red dot lines denote the Hf 4f photoelectron from Hf-O-Si and/or Hf-O-Ge bonds and Hf-O bonds in HfO<sup>2</sup> , respectively.

Figure 7a,b shows the Si 2p core‐level spectra of the Si‐cap sample and the SiGe sam‐ ple, respectively. The spectra are decomposed into four component peaks i.e., Si 2p pho‐ toelectron from SiGe (~99.7 eV), SiOx (~101.2 eV), HfSiO (~102.8 eV), and SiO2 (~103.9 eV). For the Si‐cap sample (shown in Figure 7a), the high‐binding energy shoulder (101 eV~105 eV) contains few amounts of Si oxide (SiOx and SiO2) and Hf‐silicate (HfSiO). When com‐ pared with the Si‐cap sample, an obvious increase in the areal intensity of the high‐bind‐ ing energy shoulder (101 eV~105 eV) can be observed for the SiGe sample, and there is no peak corresponding SiOx. Figure 8a,b shows the O 1s core‐level spectra of the SiGe sample and Si‐cap sample, respectively. The spectra are fitted by the O 1s of SiOx (~532.8 eV), HfSiO (~532.08 eV) and HfO2 (~531 eV). We can see that the O 1s photoelectron mainly originates from HfO2 for the Si‐cap sample, while that of the SiGe sample is mainly from SiOx and HfSiO. This is consistent with the previous discussions about Hf 4f and Si 2p spectra. All of these results indicate that the interfacial region of the HfO2/SiGe (SiGe sam‐ ple) is a composite of large amounts of HfSiO (and/or HfGeO) and Si oxide (SiO2). In other words, Si‐cap can prevent the formation of Hf‐silicate/Hf‐germanate and Si oxide origi‐ nating from the reaction between HfO2 and SiGe substrate, and obtain an excellent HfO2/SiGe interface. Figure 7a,b shows the Si 2p core-level spectra of the Si-cap sample and the SiGe sample, respectively. The spectra are decomposed into four component peaks i.e., Si 2p photoelectron from SiGe (~99.7 eV), SiO<sup>x</sup> (~101.2 eV), HfSiO (~102.8 eV), and SiO<sup>2</sup> (~103.9 eV). For the Si-cap sample (shown in Figure 7a), the high-binding energy shoulder (101 eV~105 eV) contains few amounts of Si oxide (SiO<sup>x</sup> and SiO2) and Hf-silicate (HfSiO). When compared with the Si-cap sample, an obvious increase in the areal intensity of the high-binding energy shoulder (101 eV~105 eV) can be observed for the SiGe sample, and there is no peak corresponding SiOx. Figure 8a,b shows the O 1s core-level spectra of the SiGe sample and Si-cap sample, respectively. The spectra are fitted by the O 1s of SiO<sup>x</sup> (~532.8 eV), HfSiO (~532.08 eV) and HfO<sup>2</sup> (~531 eV). We can see that the O 1s photoelectron mainly originates from HfO<sup>2</sup> for the Si-cap sample, while that of the SiGe sample is mainly from SiO<sup>x</sup> and HfSiO. This is consistent with the previous discussions about Hf 4f and Si 2p spectra. All of these results indicate that the interfacial region of the HfO2/SiGe (SiGe sample) is a composite of large amounts of HfSiO (and/or HfGeO) and Si oxide (SiO2). In other words, Si-cap can prevent the formation of Hf-silicate/Hf-germanate and Si oxide originating from the reaction between HfO<sup>2</sup> and SiGe substrate, and obtain an excellent HfO2/SiGe interface.

*Nanomaterials* **2021**, *11*, x FOR PEER REVIEW 7 of 9

**Figure 7.** The fitted Si 2p core‐level spectra of (**a**) Si‐cap sample (**b**) SiGe sample. The red, blue, magenta, and green dot lines denote the Si 2p of SiGe, SiOx, HfSiO, and SiO2, respectively. **Figure 7.** The fitted Si 2p core-level spectra of (**a**) Si-cap sample (**b**) SiGe sample. The red, blue, magenta, and green dot lines denote the Si 2p of SiGe, SiOx, HfSiO, and SiO<sup>2</sup> , respectively. **Figure 7.** The fitted Si 2p core‐level spectra of (**a**) Si‐cap sample (**b**) SiGe sample. The red, blue, magenta, and green dot lines denote the Si 2p of SiGe, SiOx, HfSiO, and SiO2, respectively.

denote the O1s photoelectron from HfO2, HfSiO, and SiOx, respectively. **Figure 8.** The fitted O 1s core‐level spectra of (**a**) Si‐cap sample (**b**) SiGe sample. The red, blue, and magenta dot lines denote the O1s photoelectron from HfO2, HfSiO, and SiOx, respectively. **Figure 8.** The fitted O 1s core-level spectra of (**a**) Si-cap sample (**b**) SiGe sample. The red, blue, and magenta dot lines denote the O1s photoelectron from HfO<sup>2</sup> , HfSiO, and SiOx, respectively.

### **4. Conclusions** In summary, the interface passivation of the HfO2/Si0.7Ge0.3 stack is systematically in‐ **4. Conclusions 4. Conclusions**

vestigated based on low‐temperature ozone oxidation and Si‐cap methods. Compared with pre‐O method, the Dit of the post‐O sample decreases by about 50% due to less GeOx available in the IL layer. However, the Dit of the HfO2/IL/Si0.7Ge0.3 gate stack still has room to be further optimized. Finally, an excellent HfO2/Si0.7Ge0.3 interface with a Dit of 1.53 × 1011 eV−1cm−<sup>2</sup> @ E−Ev = 0.36 eV is attained under the optimal Si cap method by preventing the formation of Hf‐silicate/Hf‐germanate and Si oxide from the reaction HfO2 and Si0.7Ge0.3 substrate. In summary, the interface passivation of the HfO2/Si0.7Ge0.3 stack is systematically in‐ vestigated based on low‐temperature ozone oxidation and Si‐cap methods. Compared with pre‐O method, the Dit of the post‐O sample decreases by about 50% due to less GeOx available in the IL layer. However, the Dit of the HfO2/IL/Si0.7Ge0.3 gate stack still has room to be further optimized. Finally, an excellent HfO2/Si0.7Ge0.3 interface with a Dit of 1.53 × 1011 eV−1cm−<sup>2</sup> @ E−Ev = 0.36 eV is attained under the optimal Si cap method by preventing the formation of Hf‐silicate/Hf‐germanate and Si oxide from the reaction HfO2 and Si0.7Ge0.3 substrate. In summary, the interface passivation of the HfO2/Si0.7Ge0.3 stack is systematically investigated based on low-temperature ozone oxidation and Si-cap methods. Compared with pre-O method, the Dit of the post-O sample decreases by about 50% due to less GeO<sup>x</sup> available in the IL layer. However, the Dit of the HfO2/IL/Si0.7Ge0.3 gate stack still has room to be further optimized. Finally, an excellent HfO2/Si0.7Ge0.3 interface with a Dit of 1.53 <sup>×</sup> <sup>10</sup><sup>11</sup> eV−<sup>1</sup> cm−<sup>2</sup> @ E−E<sup>v</sup> = 0.36 eV is attained under the optimal Si cap method by preventing the formation of Hf-silicate/Hf-germanate and Si oxide from the reaction HfO<sup>2</sup> and Si0.7Ge0.3 substrate.

Y.W., G.W., J.Z., W.L., X.W., J.Y., Y.L. and W.W.; investigation, Q.Y., X.M., Y.W. and Y.L., data cu‐ ration, Q.Y., X.M., H.W., Y.W. and Y.L.; writing original draft preparation, Q.Y., X.M., Y.W. and Y.L.; writing review and editing, X.M., Y.W., Y.L. and J.Z.; supervision, J.Y., Y.L. and W.W.; project administration, Y.L. and W.W.; funding acquisition, W.W. All authors have read and agreed to the published version of the manuscript. **Funding:** This research was funded in part by the Science and Technology Program of Beijing Mu‐ **Author Contributions:** Conceptualization, X.M., Y.W. and Y.L.; methodology, Q.Y., X.M., H.W., Y.W., G.W., J.Z., W.L., X.W., J.Y., Y.L. and W.W.; investigation, Q.Y., X.M., Y.W. and Y.L., data cu‐ ration, Q.Y., X.M., H.W., Y.W. and Y.L.; writing original draft preparation, Q.Y., X.M., Y.W. and Y.L.; writing review and editing, X.M., Y.W., Y.L. and J.Z.; supervision, J.Y., Y.L. and W.W.; project administration, Y.L. and W.W.; funding acquisition, W.W. All authors have read and agreed to the published version of the manuscript. **Author Contributions:** Conceptualization, X.M., Y.W. and Y.L.; methodology, Q.Y., X.M., H.W., Y.W., G.W., J.Z., W.L., X.W., J.Y., Y.L. and W.W.; investigation, Q.Y., X.M., Y.W. and Y.L., data curation, Q.Y., X.M., H.W., Y.W. and Y.L.; writing original draft preparation, Q.Y., X.M., Y.W. and Y.L.; writing review and editing, X.M., Y.W., Y.L. and J.Z.; supervision, J.Y., Y.L. and W.W.; project administration, Y.L. and W.W.; funding acquisition, W.W. All authors have read and agreed to the published version of the manuscript.

nicipal Science and Technology Commission (Grant no. Z201100004220001), in part by the CAS Pi‐ oneer Hundred Talents Program, in part by Beijing Municipal Natural Science Foundation (Grant

**Funding:** This research was funded in part by the Science and Technology Program of Beijing Mu‐ nicipal Science and Technology Commission (Grant no. Z201100004220001), in part by the CAS Pi‐ oneer Hundred Talents Program, in part by Beijing Municipal Natural Science Foundation (Grant

**Author Contributions:** Conceptualization, X.M., Y.W. and Y.L.; methodology, Q.Y., X.M., H.W.,

**Funding:** This research was funded in part by the Science and Technology Program of Beijing Municipal Science and Technology Commission (Grant no. Z201100004220001), in part by the CAS Pioneer Hundred Talents Program, in part by Beijing Municipal Natural Science Foundation (Grant no. 4202078), in part by National Natural Science Foundation of China (Grant no. 62074160) and in part by Scientific Research Startup Foundation of North China University of Technology.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** Not applicable.

**Acknowledgments:** We thank the Integrated Circuit Advanced Process Center (ICAC) at the Institute of Microelectronics of the Chinese Academy of Sciences for the devices fabricated on their advanced 200 mm CMOS platform.

**Conflicts of Interest:** The authors declare no conflict of interest.

### **References**


**Jian-Huan Wang 1,2, Ting Wang 1,3 and Jian-Jun Zhang 1,3,\***


**Abstract:** Controllable growth of wafer-scale in-plane nanowires (NWs) is a prerequisite for achieving addressable and scalable NW-based quantum devices. Here, by introducing molecular beam epitaxy on patterned Si structures, we demonstrate the wafer-scale epitaxial growth of site-controlled in-plane Si, SiGe, and Ge/Si core/shell NW arrays on Si (001) substrate. The epitaxially grown Si, SiGe, and Ge/Si core/shell NW are highly homogeneous with well-defined facets. Suspended Si NWs with four {111} facets and a side width of about 25 nm are observed. Characterizations including high resolution transmission electron microscopy (HRTEM) confirm the high quality of these epitaxial NWs.

**Keywords:** in-plane nanowire; site-controlled; epitaxial growth; silicon; germanium; nanowire-based quantum devices

### **1. Introduction**

Si and Ge nanowires (NWs) have potential applications for high-performance transistors [1,2] and for disruptively quantum computation technology [3–6]. The controllable growth of NW arrays in wafer-scale remains the major challenge for large scale integration. The top-down method by patterning and etching can precisely fabricate NWs in wafer-scale but also induce additional defects during the nanofabrications. For instance, IMEC has previously reported the vertically stacked horizontal Si NWs with selective etching of Si/SiGe multilayer fin structures [1]. Moreover, by selectively etching Si, stacked SiGe NWs were obtained to improve the channel mobility [7]. However, the top-down fabrication introduces atomic surface roughness and damages, which deteriorate the carrier mobility of the NWs [8].

Alternatively, the self-assembled growth of NWs via a vapor-liquid-solid (VLS) mechanism can form high quality NWs with a sharp interface [9,10]. A mobility of 730 cm<sup>2</sup> (Vs)−<sup>1</sup> [11] and a ballistic conduction up to several hundred nanometers [12] were reported in such {111}-oriented Ge/Si core/shell NWs. Compared to the {111}-oriented NWs, {110}-oriented Ge/Si core/shell NWs have substantially enhanced hole mobility as high as 4200 cm<sup>2</sup> (Vs)−<sup>1</sup> at 4 K [13]. Although, the VLS-grown Si and Ge NWs have recently presented single crystalline with controllable orientation [14–18], the out-of-planar geometry has not been compatible with the well-established planar device processing technology. Ex-situ assembly methods such as contact printing and capillary assembly have been developed to align the NWs on a target substrate [19,20], however, for such VLS-grown NWs, the precise positioning at a large scale is a challenge. Another challenge of the VLS-grown NWs is the poor size-controllability (including both length and diameter), which is considered to reduce the collective properties of NWs.

Combining top-down nanofabrication and bottom-up self-assembly, we have recently demonstrated site-controlled growth of Ge hut wires on trench-patterned Si (001) substrate [21]. The Ge hut wires have a height of 3.8 nm with sharp {105} facets specifically

**Citation:** Wang, J.-H.; Wang, T.; Zhang, J.-J. Epitaxial Growth of Ordered In-Plane Si and Ge Nanowires on Si (001). *Nanomaterials* **2021**, *11*, 788. https://doi.org/ 10.3390/nano11030788

Academic Editor: Filippo Giubileo

Received: 27 February 2021 Accepted: 16 March 2021 Published: 19 March 2021

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

oriented along <100> directions with high scalability. They are grown under a relatively high growth temperature where Si and Ge intermixing leads to a reduced Ge composition in the wires. Therefore, it is desirable to obtain epitaxial Si and Ge NWs with controllable size, orientation, and composition. In this work, we epitaxially grow {110}-orientated in-plane Si, SiGe, and Ge NWs on pre-patterned Si NW arrays. The pre-patterned Si NWs with an inverted trapezoidal structure are obtained through nanofabrications. On such pre-patterned Si NWs, homogeneous Si NWs with controllable sizes are epitaxially grown by molecular beam epitaxy. Furthermore, we demonstrate the formation of the conformal SiGe NWs and Ge NWs with {113} facets on the diamond-shaped Si NWs with {111} facets and truncated Si NWs. By transmission electron microscopy (TEM) characterizations, we investigate the material properties of the NWs mentioned above, which exhibit a high quality. [21]. The Ge hut wires have a height of 3.8 nm with sharp {105} facets specifically oriented along <100> directions with high scalability. They are grown under a relatively high growth temperature where Si and Ge intermixing leads to a reduced Ge composition in the wires. Therefore, it is desirable to obtain epitaxial Si and Ge NWs with controllable size, orientation, and composition. In this work, we epitaxially grow {110}-orientated in-plane Si, SiGe, and Ge NWs on pre-patterned Si NW arrays. The pre-patterned Si NWs with an inverted trapezoidal structure are obtained through nanofabrications. On such pre-patterned Si NWs, homogeneous Si NWs with controllable sizes are epitaxially grown by molecular beam epitaxy. Furthermore, we demonstrate the formation of the conformal SiGe NWs and Ge NWs with {113} facets on the diamond-shaped Si NWs with {111} facets and truncated Si NWs. By transmission electron microscopy (TEM) characterizations, we investigate the material properties of the NWs mentioned above, which exhibit a high quality.

Combining top-down nanofabrication and bottom-up self-assembly, we have recently demonstrated site-controlled growth of Ge hut wires on trench-patterned Si (001) substrate

*Nanomaterials* **2021**, *11*, x FOR PEER REVIEW 2 of 9

### **2. Materials and Methods 2. Materials and Methods**

A CMOS-compatible top-down method was explored here to define the planar Si NW arrays on 200 mm Si (001) wafers. Figure 1 describes the fabrication process: a SiO<sup>2</sup> grating structure is firstly prepared along <110> direction on Si wafer by plasma enhanced vapor deposition, deep ultraviolet lithography, and reactive ion etching. Such SiO<sup>2</sup> grating structure is used as a hard mask for the subsequent wet etching of Si. The SiO<sup>2</sup> grating structure has periods that range from 360 to 440 nm with a constant duty cycle of nearly 1:1 and a depth of 150 nm. After dipping for 5 s in a buffered HF solution (7:1) to remove the native oxide on the exposed Si, a diluted tetramethylammonium hydroxide aqueous solution (TMAH 5%) is used to create the planar Si NWs at 75 ◦C. The SiO<sup>2</sup> hard mask is finally removed in diluted HF solution. A CMOS-compatible top-down method was explored here to define the planar Si NW arrays on 200 mm Si (001) wafers. Figure 1 describes the fabrication process: a SiO<sup>2</sup> grating structure is firstly prepared along <110> direction on Si wafer by plasma enhanced vapor deposition, deep ultraviolet lithography, and reactive ion etching. Such SiO<sup>2</sup> grating structure is used as a hard mask for the subsequent wet etching of Si. The SiO<sup>2</sup> grating structure has periods that range from 360 to 440 nm with a constant duty cycle of nearly 1:1 and a depth of 150 nm. After dipping for 5 s in a buffered HF solution (7:1) to remove the native oxide on the exposed Si, a diluted tetramethylammonium hydroxide aqueous solution (TMAH 5%) is used to create the planar Si NWs at 75 °C. The SiO2 hard mask is finally removed in diluted HF solution.

**Figure 1.** Schematic of process flow for the trapezoidal Si nanowire (NW) array. **Figure 1.** Schematic of process flow for the trapezoidal Si nanowire (NW) array.

By obtaining these pre-patterned Si NWs, we then studied the direct epitaxial growth of Si NWs, SiGe NWs, and Ge/Si core/shell NWs inside a SiGe molecular beam epitaxy system (Octoplus 500 EBV, MBE-Komponenten, Weil der Stadt, Germany). The patterned wafer was cleaved into 10 × 10 mm<sup>2</sup> small samples before dipping in a diluted HF solution for deoxidation and hydrogen passivation. To reduce the thermal instability of these tiny pre-patterned NWs, a low-temperature dehydrogenation was performed at 500 °C. The Si epitaxial NWs were obtained after homoepitaxial growth of Si at growth temperatures from 380 °C to 480 °C with a growth rate of 1 Å /s. By obtaining these pre-patterned Si NWs, we then studied the direct epitaxial growth of Si NWs, SiGe NWs, and Ge/Si core/shell NWs inside a SiGe molecular beam epitaxy system (Octoplus 500 EBV, MBE-Komponenten, Weil der Stadt, Germany). The patterned wafer was cleaved into 10 <sup>×</sup> 10 mm<sup>2</sup> small samples before dipping in a diluted HF solution for deoxidation and hydrogen passivation. To reduce the thermal instability of these tiny pre-patterned NWs, a low-temperature dehydrogenation was performed at 500 ◦C. TheSi epitaxial NWs were obtained after homoepitaxial growth of Si at growth temperatures from 380 ◦C to 480 ◦C with a growth rate of 1 Å/s.

The SiGe NWs and Ge NWs were grown on the Si epitaxial NW after deposition 20 nm Si layer at 450 °C and 380 °C, respectively. The SiGe NWs were obtained by depositing 10 nm Si0.5Ge0.5 and 10 nm Si at 350 °C, where the growth rate of Si and Ge was 0.5 Å /s. The Ge NWs were obtained by depositing 2 nm Ge at 300 °C with a growth rate of 0.3 Å /s. The Ge/Si core/shell NWs were further formed after the deposition of 3 nm Si capping layer at 300 °C. The SiGe NWs and Ge NWs were grown on the Si epitaxial NW after deposition 20 nmSi layer at 450 ◦C and 380 ◦C, respectively. The SiGe NWs were obtained by depositing 10 nm Si0.5Ge0.5 and 10 nm Si at 350 ◦C, where the growth rate of Si and Ge was 0.5 Å/s. The Ge NWs were obtained by depositing 2 nm Ge at 300 ◦C with a growth rate of 0.3 Å/s. The Ge/Si core/shell NWs were further formed after the deposition of 3 nm Si capping layer at 300 ◦C.

Focus ion-beam (FIB) system (NanoLab Helios 600i, FEI, Hillsboro, USA) equipped with high-resolution field-emission scanning electron microscope (SEM) was employed to elucidate the morphology of NWs and prepare the TEM lamellae. Before the FIB-milling, the NW sample was coated with 5 nm Ti and 50 nm Au for protection. TEM was Focus ion-beam (FIB) system (NanoLab Helios 600i, FEI, Hillsboro, USA) equipped with high-resolution field-emission scanning electron microscope (SEM) was employed to elucidate the morphology of NWs and prepare the TEM lamellae. Before the FIB-milling, the NW sample was coated with 5 nm Ti and 50 nm Au for protection. TEM was performed to verify the quality of these epitaxial NWs, using a JEOL 2100 plus, operating at 200 kV.

### **3. Results and Discussion 3. Results and Discussion**

at 200 kV.

#### *3.1. Planar Trapezoidal Si NW Arrays 3.1. Planar Trapezoidal Si NW Arrays*

*Nanomaterials* **2021**, *11*, x FOR PEER REVIEW 3 of 9

TMAH solution provides anisotropic wet etching for Si, with selectivity more than 1:10 between the Si {111} and Si {100} planes [22]. Therefore, {111}-faceted V-grooves were fabricated along the <110> direction, as shown in the SEM images (Figure 2a,b). In Figure 2a, on the tips of the Si V-grooves, we observed a Si hourglass figure with inverted {111} facets contributing to the SiO<sup>2</sup> hard mask. With optimized etching conditions, the formation of Si NWs with an inverted triangular or trapezoidal shape are achieved. Multiple widths of Si NWs ranging from 20 nm to 40 nm can be fabricated simultaneously on 200 mm Si (001) wafer by varying the pattern sizes. Figure 2a shows trapezoidal Si NWs with a minimum width of approximately 20 nm, while still preserving good uniformity, as confirmed by the surface SEM images, as shown in Figure 2b. The average width of the neck is approximately 3 nm, as shown in the inset of Figure 2a, expected to be facilely isolated by thermal oxidation [23,24]. The lengths of NW arrays are defined ranging from 2 µm up to 2 mm, suggesting a large aspect ratio (length: width) of nearly 10<sup>5</sup> . TMAH solution provides anisotropic wet etching for Si, with selectivity more than 1:10 between the Si {111} and Si {100} planes [22]. Therefore, {111}-faceted V-grooves were fabricated along the <110> direction, as shown in the SEM images (Figure 2a,b). In Figure 2a, on the tips of the Si V-grooves, we observed a Si hourglass figure with inverted {111} facets contributing to the SiO<sup>2</sup> hard mask. With optimized etching conditions, the formation of Si NWs with an inverted triangular or trapezoidal shape are achieved. Multiple widths of Si NWs ranging from 20 nm to 40 nm can be fabricated simultaneously on 200 mm Si (001) wafer by varying the pattern sizes. Figure 2a shows trapezoidal Si NWs with a minimum width of approximately 20 nm, while still preserving good uniformity, as confirmed by the surface SEM images, as shown in Figure 2b. The average width of the neck is approximately 3 nm, as shown in the inset of Figure 2a, expected to be facilely isolated by thermal oxidation [23,24]. The lengths of NW arrays are defined ranging from 2 μm up to 2 mm, suggesting a large aspect ratio (length: width) of nearly 10<sup>5</sup> .

performed to verify the quality of these epitaxial NWs, using a JEOL 2100 plus, operating

**Figure 2.** (**a**) Cross-sectional view and (**b**) top view SEM images of the Si NW array with an average wire width of 19 nm. Insets: zoom-in SEM images of the NWs. Scale bar of insets: 300 nm. **Figure 2.** (**a**) Cross-sectional view and (**b**) top view SEM images of the Si NW array with an average wire width of 19 nm. Insets: zoom-in SEM images of the NWs. Scale bar of insets: 300 nm.

#### *3.2. Homoepitaxy of Si NWs 3.2. Homoepitaxy of Si NWs*

Figure 3a presents a typical NW array by homoepitaxially grown Si on pre-patterned trapezoidal Si NWs. They are highly uniform. The width of these epitaxial Si NWs can be tuned from 30 nm to 50 nm by simply changing the growth conditions. Figure 3b shows the cross-sectional SEM image of epitaxial NWs obtained after the deposition of 20 nm Si layer on 30 nm wide pre-patterned Si NWs at 380 °C. Although only 20 nm Si were deposited at 380 °C, the epitaxial NW evolved rapidly toward the {111}-faceted morphology and a small Si (001) terrace with a width less than 10 nm on the top was left, driven by the reduction of surface energy. We observe a truncated {111}-faceted Si NW with a Si (001) terrace on the top (Figure 3b). By depositing 20 nm Si at 380 °C on a 40 nm wide pre-patterned NW array, a Si (001) terrace with enlarged width of approximately 17 nm was obtained (Figure 3c). If we increase the growth temperature to 450 °C, the Si (001) terrace will evolve into two symmetric Si (111) facets (Figure 4a), which leads to a 33 nm wide diamond-shaped NW. By keeping the growth temperature at 450 °C, when the Si layer is increased to 50 nm, the average width of diamond-shape Si NWs enlarges to approximately 48 nm (Figure 4b). The NWs are characterized by high-resolution TEMs (HRTEMs). Figure 4c provides a cross-sectional HRTEM image of a single Si NW obtained at the identical growth conditions to those in Figure 4b. The green dashed line in Figure 4c represents the interface between the epitaxial layer and the initial hourglass structure (pre-patterned trapezoidal Si NW). The inset of Figure 4c provides a Figure 3a presents a typical NW array by homoepitaxially grown Si on pre-patterned trapezoidal Si NWs. They are highly uniform. The width of these epitaxial Si NWs can be tuned from 30 nm to 50 nm by simply changing the growth conditions. Figure 3b shows the cross-sectional SEM image of epitaxial NWs obtained after the deposition of 20 nm Si layer on 30 nm wide pre-patterned Si NWs at 380 ◦C. Although only 20 nm Si were deposited at 380 ◦C, the epitaxial NW evolved rapidly toward the {111}-faceted morphology and a small Si (001) terrace with a width less than 10 nm on the top was left, driven by the reduction of surface energy. We observe a truncated {111}-faceted Si NW with a Si (001) terrace on the top (Figure 3b). By depositing 20 nm Si at 380 ◦C on a 40 nm wide pre-patterned NW array, a Si (001) terrace with enlarged width of approximately 17 nm was obtained (Figure 3c). If we increase the growth temperature to 450 ◦C, the Si (001) terrace will evolve into two symmetric Si (111) facets (Figure 4a), which leads to a 33 nm wide diamond-shaped NW. By keeping the growth temperature at 450 ◦C, when the Si layer is increased to 50 nm, the average width of diamond-shape Si NWs enlarges to approximately 48 nm (Figure 4b). The NWs are characterized by high-resolution TEMs (HRTEMs). Figure 4c provides a cross-sectional HRTEM image of a single Si NW obtained at the identical growth conditions to those in Figure 4b. The green dashed line in Figure 4c represents the interface between the epitaxial layer and the initial hourglass structure (pre-patterned trapezoidal Si NW). The inset of Figure 4c provides a zoom-in HRTEM image of the epitaxial interface labeled in Figure 4c, showing a perfect arrangement of Si atoms. Atoms deposited on the Si hourglass structure diffuse upwards to the shoulder areas to reduce the surface area, as illustrated by black arrows.

shoulder areas to reduce the surface area, as illustrated by black arrows.

zoom-in HRTEM image of the epitaxial interface labeled in Figure 4c, showing a perfect arrangement of Si atoms. Atoms deposited on the Si hourglass structure diffuse upwards to the

**Figure 3.** (**a**) Tilted SEM image showing the NW array of epitaxial Si on pre-patterned trapezoidal Si NWs. SEM images of epitaxial Si NWs obtained after the deposition of 20 nm Si at 380 °C on 30 nm wide pre-patterned trapezoidal NWs (**b**) and on 40 nm wide pre-patterned NWs at 380 °C (**c**). Inset of (**b**) schematically shows the truncated {111}-faceted cross-section. **Figure 3.** (**a**) Tilted SEM image showing the NW array of epitaxial Si on pre-patterned trapezoidal Si NWs. SEM images of epitaxial Si NWs obtained after the deposition of 20 nm Si at 380 ◦C on 30 nm wide pre-patterned trapezoidal NWs (**b**) and on 40 nm wide pre-patterned NWs at 380 ◦C (**c**). Inset of (**b**) schematically shows the truncated {111}-faceted cross-section.

Although the pre-patterned trapezoidal NWs are thermally stable at the aforementioned low-temperature epitaxy, we note that a high-temperature dehydrogenation process at more than 600 ◦C will deform the pre-patterned Si NWs. The thermal instability becomes remarkable for Si NWs with smaller dimensions [25,26], as we find that the pre-patterned NWs with a size of about 20 nm in Figure 2a deform into discrete Si beads only after 500 ◦C dehydrogenation. Similar phenomena have been previously reported on an isolated Si NW as Plateau–Rayleigh instability (PRI) [27,28], while the critical temperature reported is much higher at 775 ◦C for a Si NW with 100 nm diameter. In our case, the root causes of thermal instability are not just dominated by PRI, also strongly influenced by the fragile narrow Si necks as well as the surface diffusion between NWs and patterned V-grooves.

**Figure 4.** Cross-sectional SEM images of epitaxial Si NWs obtained after the deposition of 20 nm (**a**) and 50 nm (**b**) of Si at 450 °C on 30 nm wide pre-patterned trapezoidal NWs. Inset of (**a**) schematically shows the fully {111}-faceted cross-section. (**c**) Cross-sectional transmission electron mi-The supporting Si neck of the hourglass structure can significantly affect the thermal instability of the NW growth with small dimensions. Here, we then study the possibility of creating suspended NWs. Figure 5a shows a typical 2 µm long suspended Si trapezoidal NW with a sub-20 nm average width. The supporting Si necks are removed by similar fabrication method mentioned above with over-etched conditions. Absence of the neck, such suspended structure can avoid the diffusion between the NW and the V-groove more effectively. After the growth of the 20 nm Si layer, although the gap between the NW and the pre-patterned V-groove appears to be unclear in the SEM picture (Figure 5b), TEM characterization in Figure 5c has verified that still retains the suspended configuration and forms {111}-faceted diamond-shaped NW with a side width of about 25 nm. Overall, the suspended Si NW exhibit enhanced thermal stability and homogeneity with four {111} facets at small dimensions, which can be considered as an ideal isolated one-dimensional NW system. But these suspended Si NWs are limited to a few micrometers in length, due to insufficient mechanical strength.

croscopy (TEM) image of an epitaxial NW in (**b**), projected toward <110> direction. The interface

taxial Si NWs obtained after the deposition of 20 nm Si at 380 °C on 30 nm wide pre-patterned trapezoidal NWs (**b**) and on 40

nm wide pre-patterned NWs at 380 °C (**c**). Inset of (**b**) schematically shows the truncated {111}-faceted cross-section.

zoom-in HRTEM image of the epitaxial interface labeled in Figure 4c, showing a perfect arrangement of Si atoms. Atoms deposited on the Si hourglass structure diffuse upwards to the

shoulder areas to reduce the surface area, as illustrated by black arrows.

**Figure 4.** Cross-sectional SEM images of epitaxial Si NWs obtained after the deposition of 20 nm (**a**) and 50 nm (**b**) of Si at 450 °C on 30 nm wide pre-patterned trapezoidal NWs. Inset of (**a**) schematically shows the fully {111}-faceted cross-section. (**c**) Cross-sectional transmission electron microscopy (TEM) image of an epitaxial NW in (**b**), projected toward <110> direction. The interface **Figure 4.** Cross-sectional SEM images of epitaxial Si NWs obtained after the deposition of 20 nm (**a**) and 50 nm (**b**) of Si at 450 ◦C on 30 nm wide pre-patterned trapezoidal NWs. Inset of (**a**) schematically shows the fully {111}-faceted cross-section. (**c**) Cross-sectional transmission electron microscopy (TEM) image of an epitaxial NW in (**b**), projected toward <110> direction. The interface of epitaxially formed Si NW and initial hourglass structure (pre-patterned Si NW) is sketched in green dashed line. The two shoulder areas marked in black are obtained by atomic diffusion during deposition. Inset of (**c**) shows a zoom-in high resolution transmission electron microscopy (HRTEM) confirming the perfect interface. method mentioned above with over-etched conditions. Absence of the neck, such suspended structure can avoid the diffusion between the NW and the V-groove more effectively. After the growth of the 20 nm Si layer, although the gap between the NW and the pre-patterned Vgroove appears to be unclear in the SEM picture (Figure 5b), TEM characterization in Figure 5c has verified that still retains the suspended configuration and forms {111}-faceted diamondshaped NW with a side width of about 25 nm. Overall, the suspended Si NW exhibit enhanced thermal stability and homogeneity with four {111} facets at small dimensions, which can be considered as an ideal isolated one-dimensional NW system. But these suspended Si NWs are limited to a few micrometers in length, due to insufficient mechanical strength.

**Figure 5.** Suspended Si NW before (**a**) and after epitaxy (**b**). They both have a straight structure without distortion. Scale bar: 400 nm. (**c**) Cross-sectional HRTEM showing the high-quality diamond with four {111} facets after epitaxy. The red arrow in the inset of (**a**) highlights the suspended structure. **Figure 5.** Suspended Si NW before (**a**) and after epitaxy (**b**). They both have a straight structure without distortion. Scale bar: 400 nm. (**c**) Cross-sectional HRTEM showing the high-quality diamond with four {111} facets after epitaxy. The red arrow in the inset of (**a**) highlights the suspended structure.

The size distributions of both the pre-patterned trapezoidal NW and epitaxial NWs were investigated. Figure 6a–c presents the SEM images of the pre-patterned NW and the epitaxial NWs obtained after the deposition of 20 and 50 nm-thick Si, respectively. After epitaxial growth, the rough surface of the pre-patterned NW has been significantly modified by form-The size distributions of both the pre-patterned trapezoidal NW and epitaxial NWs were investigated. Figure 6a–c presents the SEM images of the pre-patterned NW and the epitaxial NWs obtained after the deposition of 20 and 50 nm-thick Si, respectively. After epitaxial growth, the rough surface of the pre-patterned NW has been significantly modified by forming atomic {111} facets. As illustrated in Figure 6d, the average width

ing atomic {111} facets. As illustrated in Figure 6d, the average width of pre-patterned trapezoidal NWs is 29.8 nm with relative standard deviation of 6.4%. By depositing a 20 nm (50

and the relative standard deviation of the width distribution is reduced to 3.9% (2.9%).

of pre-patterned trapezoidal NWs is 29.8 nm with relative standard deviation of 6.4%. By depositing a 20 nm (50 nm)-thick Si layer, the epitaxially formed Si NWs exhibit average widths of 35.8 nm (46.0 nm), and the relative standard deviation of the width distribution is reduced to 3.9% (2.9%). *Nanomaterials* **2021**, *11*, x FOR PEER REVIEW 6 of 9 *Nanomaterials* **2021**, *11*, x FOR PEER REVIEW 6 of 9

**Figure 6.** (**a–c**) SEM images of a 30 nm wide pre-patterned trapezoidal NW, epitaxial NWs after the deposition of 20 nm Si and 50 nm Si, respectively. Scale bar: 200 nm. (**d**) Statistical histogram showing the width distribution of 30 nm wide pre-patterned NWs, epitaxial NWs after the deposition of 20 nm and 50 nm Si layer. The average width <W> and relative standard deviation σ of the NWs are quoted. **Figure 6.** (**a–c**) SEM images of a 30 nm wide pre-patterned trapezoidal NW, epitaxial NWs after the deposition of 20 nm Si and 50 nm Si, respectively. Scale bar: 200 nm. (**d**) Statistical histogram showing the width distribution of 30 nm wide pre-patterned NWs, epitaxial NWs after the deposition of 20 nm and 50 nm Si layer. The average width <W> and relative standard deviation σ of the NWs are quoted. **Figure 6.** (**a–c**) SEM images of a 30 nm wide pre-patterned trapezoidal NW, epitaxial NWs after the deposition of 20 nm Si and 50 nm Si, respectively. Scale bar: 200 nm. (**d**) Statistical histogram showing the width distribution of 30 nm wide pre-patterned NWs, epitaxial NWs after the deposition of 20 nm and 50 nm Si layer. The average width <W> and relative standard deviation σ of the NWs are quoted.

### *3.3. Epitaxy of SiGe NWs 3.3. Epitaxy of SiGe NWs 3.3. Epitaxy of SiGe NWs*

The epitaxial Si NWs provide platform for the subsequent growth of SiGe and Ge NWs. As mentioned, the SiGe NWs are obtained after the deposition of 10 nm Si0.5Ge0.5 and 10 nm Si layer at 350 °C on the {111}-faceted Si NW. We should note that all the thicknesses of the epitaxial layer mentioned in this work are referred to as-grown layer thickness on flat substrate. Here, the actual Si0.5Ge0.5 thickness that was deposited on the {111} facets should be 5.77 nm. The SEM images in cross-sectional view (Figure 7a,b) and top view (Figure 7c,d) indicate that these SiGe NWs are highly uniform. Attributed to the high Ge content in the SiGe layer, we can directly distinguish the SiGe layer in the magnified SEM image as shown in Figure 7b, where the SiGe layer has a brighter contrast. The epitaxial Si NWs provide platform for the subsequent growth of SiGe and Ge NWs. As mentioned, the SiGe NWs are obtained after the deposition of 10 nm Si0.5Ge0.5 and 10 nm Si layer at 350 ◦C on the {111}-faceted Si NW. We should note that all the thicknesses of the epitaxial layer mentioned in this work are referred to as-grown layer thickness on flat substrate. Here, the actual Si0.5Ge0.5 thickness that was deposited on the {111} facets should be 5.77 nm. The SEM images in cross-sectional view (Figure 7a,b) and top view (Figure 7c,d) indicate that these SiGe NWs are highly uniform. Attributed to the high Ge content in the SiGe layer, we can directly distinguish the SiGe layer in the magnified SEM image as shown in Figure 7b, where the SiGe layer has a brighter contrast. The epitaxial Si NWs provide platform for the subsequent growth of SiGe and Ge NWs. As mentioned, the SiGe NWs are obtained after the deposition of 10 nm Si0.5Ge0.5 and 10 nm Si layer at 350 °C on the {111}-faceted Si NW. We should note that all the thicknesses of the epitaxial layer mentioned in this work are referred to as-grown layer thickness on flat substrate. Here, the actual Si0.5Ge0.5 thickness that was deposited on the {111} facets should be 5.77 nm. The SEM images in cross-sectional view (Figure 7a,b) and top view (Figure 7c,d) indicate that these SiGe NWs are highly uniform. Attributed to the high Ge content in the SiGe layer, we can directly distinguish the SiGe layer in the magnified SEM image as shown in Figure 7b, where the SiGe layer has a brighter contrast.

images. The brighter contrast presenting in (**b**) results from the Si0.5Ge0.5 layer, where highlights in green in the schematic inset. The red arrow in (**d**) points to a strain-induced defect at the V-groove area. (**e**) Cross-sectional TEM image of SiGe at the V-groove area, showing that stacking faults (SFs) are generated from the interface and penetrate to the surface along the {111} gliding plane. (**f**) Cross-sectional HRTEM of a Si0.5Ge0.5 NW. Inset: FFT analysis of the SiGe/Si NW, showing a single set of spots indicating the SiGe is under fully strained condition. Due to 2.1% lattice mismatch between Si0.5Ge0.5 and Si, misfit dislocations will gener-**Figure 7.** (**a**) Cross-sectional and (**c**) top view SEM images of the Si0.5Ge0.5 NW array and (**b**,**d**) the corresponding zoom-in images. The brighter contrast presenting in (**b**) results from the Si0.5Ge0.5 layer, where highlights in green in the schematic inset. The red arrow in (**d**) points to a strain-induced defect at the V-groove area. (**e**) Cross-sectional TEM image of SiGe at the V-groove area, showing that stacking faults (SFs) are generated from the interface and penetrate to the surface along the {111} gliding plane. (**f**) Cross-sectional HRTEM of a Si0.5Ge0.5 NW. Inset: FFT analysis of the SiGe/Si NW, showing a single set of spots indicating the SiGe is under fully strained condition. **Figure 7.** (**a**) Cross-sectional and (**c**) top view SEM images of the Si0.5Ge0.5 NW array and (**b**,**d**) the corresponding zoom-in images. The brighter contrast presenting in (**b**) results from the Si0.5Ge0.5 layer, where highlights in green in the schematic inset. The red arrow in (**d**) points to a strain-induced defect at the V-groove area. (**e**) Cross-sectional TEM image of SiGe at the V-groove area, showing that stacking faults (SFs) are generated from the interface and penetrate to the surface along the {111} gliding plane. (**f**) Cross-sectional HRTEM of a Si0.5Ge0.5 NW. Inset: FFT analysis of the SiGe/Si NW, showing a single set of spots indicating the SiGe is under fully strained condition.

**Figure 7.** (**a**) Cross-sectional and (**c**) top view SEM images of the Si0.5Ge0.5 NW array and (**b**,**d**) the corresponding zoom-in

ate if the SiGe film reaches the critical thickness for pseudomorphic growth. From the

Due to 2.1% lattice mismatch between Si0.5Ge0.5 and Si, misfit dislocations will gener-

7e is a cross-sectional TEM image at the Si V-groove, showing that stacking faults (SFs) have generated from the interface and penetrated to the surface along the {111} gliding

generated at the Si V-groove, indicating the excessive deposition of the SiGe layer. Figure 7e is a cross-sectional TEM image at the Si V-groove, showing that stacking faults (SFs) have generated from the interface and penetrated to the surface along the {111} gliding

Due to 2.1% lattice mismatch between Si0.5Ge0.5 and Si, misfit dislocations will generate if the SiGe film reaches the critical thickness for pseudomorphic growth. From the magnified planar SEM image (Figure 7d), the red arrow indicates strain-induced defects generated at the Si V-groove, indicating the excessive deposition of the SiGe layer. Figure 7e is a cross-sectional TEM image at the Si V-groove, showing that stacking faults (SFs) have generated from the interface and penetrated to the surface along the {111} gliding plane. In addition, we also observed other types of defects including SFs in parallel to the side-wall, attributed to plastic relaxation [29]. *Nanomaterials* **2021**, *11*, x FOR PEER REVIEW 7 of 9 plane. In addition, we also observed other types of defects including SFs in parallel to the side-wall, attributed to plastic relaxation [29].

> The situation is different for the SiGe NW. Figure 7f is a HRTEM image of directly grown in-plane SiGe/Si NW, with absence of defects, indicating the high crystal quality and conformal growth of the SiGe NW. The inset in Figure 7f is the fast Fourier transform (FFT) pattern of the SiGe/Si NW, showing only a single set of diffraction spots without distinct splitting. The FFT pattern is in-line with the spatial measurement result, indicating the SiGe NW is fully strained on Si NW. The situation is different for the SiGe NW. Figure 7f is a HRTEM image of directly grown in-plane SiGe/Si NW, with absence of defects, indicating the high crystal quality and conformal growth of the SiGe NW. The inset in Figure 7f is the fast Fourier transform (FFT) pattern of the SiGe/Si NW, showing only a single set of diffraction spots without distinct splitting. The FFT pattern is in-line with the spatial measurement result, indicating the SiGe NW is fully strained on Si NW.

#### *3.4. Epitaxy of Ge/Si Core/Shell NWs 3.4. Epitaxy of Ge/Si Core/Shell NWs*

Despite a 4.2% lattice-mismatch between Ge and Si, we have further demonstrated Ge NW growth on the truncated {111}-faceted Si NW, where the average width of the Si (001) terrace is about 17 nm. As mentioned, the Ge NWs are obtained after the deposition of 2 nm Ge with a growth rate of 0.3 Å/s. In order to suppress the intermixing between Ge and Si, the growth is performed at a relatively low temperature of 300 ◦C [30]. Following a 3 nm Si capping layer deposited at 300 ◦C, Ge/Si core/shell NW is obtained, which can provide a high-performance one-dimensional hole gas system for exploring hole spin qubits [3,4,21]. Figure 8a,b shows cross-sectional and top view SEM images of the Ge/Si core/shell NW arrays, presenting a uniform morphology and smooth surface of NWs. To note, there are also numbers of strain-induced Ge islands formed on the Si V-grooves. Despite a 4.2% lattice-mismatch between Ge and Si, we have further demonstrated Ge NW growth on the truncated {111}-faceted Si NW, where the average width of the Si (001) terrace is about 17 nm. As mentioned, the Ge NWs are obtained after the deposition of 2 nm Ge with a growth rate of 0.3 Å /s. In order to suppress the intermixing between Ge and Si, the growth is performed at a relatively low temperature of 300 °C [30]. Following a 3 nm Si capping layer deposited at 300 °C, Ge/Si core/shell NW is obtained, which can provide a high-performance one-dimensional hole gas system for exploring hole spin qubits [3,4,21]. Figure 8a,b shows cross-sectional and top view SEM images of the Ge/Si core/shell NW arrays, presenting a uniform morphology and smooth surface of NWs. To note, there are also numbers of strain-induced Ge islands formed on the Si V-grooves.

**Figure 8.** (**a**) Cross-sectional and (**b**) top view SEM images of the Ge/Si core/shell NW arrays. (**c**) Cross-sectional HRTEM image of a Ge/Si core/shell NW. Inset: a zoom-in HRTEM shows the two {113} side facets and the flat (001) top surface. **Figure 8.** (**a**) Cross-sectional and (**b**) top view SEM images of the Ge/Si core/shell NW arrays. (**c**) Cross-sectional HRTEM image of a Ge/Si core/shell NW. Inset: a zoom-in HRTEM shows the two {113} side facets and the flat (001) top surface.

HRTEM micrograph in Figure 8c shows a typical cross-section of the Ge/Si core/shell NW. The Ge NW is grown on the <110>-oriented Si (001) terrace of the truncated {111} faceted Si NW. The zoom-in HRTEM image in the inset of Figure 8c presents a trapezoidal geometry of the Ge NW composed of two (113) side facets and a flat (001) top surface. The

these <110>-oriented Ge NWs exhibit a larger aspect ratio of more than 0.2, where the height and width of the Ge NW are about 4 nm and 18 nm, respectively. Comparing the height of the Ge NW on the Si (001) terrace h<sup>001</sup> ≈ 39.4 Å and the thickness of the Ge wetting

HRTEM micrograph in Figure 8c shows a typical cross-section of the Ge/Si core/shell NW. The Ge NW is grown on the <110>-oriented Si (001) terrace of the truncated {111} faceted Si NW. The zoom-in HRTEM image in the inset of Figure 8c presents a trapezoidal geometry of the Ge NW composed of two (113) side facets and a flat (001) top surface. The formation of Ge (113) facets is attributed to the low surface energy, which has been reported in previous works [31–33]. Compared with <100>-oriented Ge hut wires [21,34], these <110>-oriented Ge NWs exhibit a larger aspect ratio of more than 0.2, where the height and width of the Ge NW are about 4 nm and 18 nm, respectively. Comparing the height of the Ge NW on the Si (001) terrace h<sup>001</sup> ≈ 39.4 Å and the thickness of the Ge wetting layer on (111) side facets h<sup>111</sup> ≈ 6.3 Å, we conclude that there is a significant Ge diffusion from the (111) facet towards the (001) facet. In terms of thermodynamics, Si (001) features higher surface energy than Si (111) [35,36], thus such Ge diffusion toward (001) facet is energetically favored.

Considering the low growth temperature, the intermixing of Ge and Si is strongly suppressed, thus we can expect an almost pure Ge-core in such Ge/Si NWs. Furthermore, atomically sharp interfaces between the Ge-core and the Si-shell are observed in the inset of Figure 8c, which further confirms the negligible intermixing between Ge and Si.

### **4. Conclusions and Perspectives**

In summary, homogenous planar diamond-shaped Si NW arrays (30–50 nm in width) have been achieved on pre-patterned {111}-faceted Si arrays via direct epitaxial growth. Morphologies and dimensions of these NWs are controllable, while they can also be tuned under certain growth conditions. Suspended Si NWs exhibit diamond-shaped cross-section with four Si {111} facets. Furthermore, the SiGe NWs can be conformally grown on the {111}-faceted Si NWs. Additionally, {113}-faceted Ge NWs along [110] direction are also obtained after the deposition of 2 nm Ge on the truncated Si NWs. HRTEMs reveal the high quality of these epitaxial NWs.

The in-plane and site-controllable epitaxial NWs hold promise as the platform for the next generation of devices that require addressability and scalability. The Si and SiGe NWs have potential applications for high-perform transistors [7,23]. Moreover, the [110]-oriented Ge/Si core/shell NWs are expected to have a high mobility and a strong spin-orbit coupling [37,38] for the manipulation of hole spin qubits. Additionally, we believe this method is also applicable to obtain planar nanowires in other material systems with controllable size and orientation, such as III–V compound materials. However, the large V-groove poses a challenge for device fabrication, which needs to be addressed in future research work.

**Author Contributions:** Conceptualization, J.-J.Z.; methodology, J.-H.W. and J.-J.Z.; formal analysis, J.-H.W., T.W., and J.-J.Z.; investigation, J.-H.W., T.W., and J.-J.Z.; resources, J.-J.Z.; data curation, J.-H.W.; writing—original draft preparation, J.-H.W.; writing—review and editing, T.W. and J.-J.Z.; project administration, J.-J.Z.; funding acquisition, J.-J.Z. All authors have read and agreed to the published version of the manuscript.

**Funding:** This work was supported by the National Key R&D Program of China (Grant Nos. 2016YFA0301701), the NSFC (Grant Nos. 11574356, 11434010, and 11404252), the Strategic Priority Research Program of CAS (Grant No. XDB30000000).

**Data Availability Statement:** Data available on request.

**Conflicts of Interest:** The authors declare no conflict of interest.
