*Boolean Chaos Robust to Distinct Discrete Physical Implementation*

This subsection presents three different physical implementations of the Boolean chaos oscillators. The dynamics are affected by physical constraints and hardware differences. This may lead to time-delay variations where the boolean chaos displays. Therefore, the BCO-1 and BCO-2 are constructed with three different electronic devices (i) commercial-off-the-shelf logic gates (introduced previously), (ii) a GAL, and (iii) an FPGA. The experiments in Figure 3 demonstrate the robust generation of Boolean chaos. From the circuit conception, the implementations show the chaotic behavior source is the degradation effect [32]. In addition, there are no additional procedures to calculate the delay paths to achieve chaotic oscillations.

The implementation considers all cases of Tables 1 and 2, but for the sake of simplicity, the Table 3 displays only the examples where the largest Lyapunov exponent is higher. In particular, case 1 for both BCOs is of particular interest because they do not need extra time-delays for generating chaos. More specifically, we use the GAL22V10 for realizing both BCOs, as given in Figure 3b. The programming of the GAL was performed with VHDL language. Figure 4b,e,h give the experimental results for the cases 1, 3, and 7 of BCO-1; while Figure 5b,e shows the results for cases 1 and 5 of BCO-2. For FPGA implementation, the Spartan 6 was employed (Figure 3c). The experimental

results are shown in Figure 4c,f,i for cases 1, 3, 7 in Table 1, respectively. Figure 5c,f display the output signal for cases 1 and 5 in Table 2, respectively.

The measurements exhibit a 100 ns of time and a 2V of voltage grid per square. For all the three presented implementations, the output voltages (Figures 4 and 5) show the cumbersome temporal oscillations without evident periodicity. This continuous-time evolution can be identified as Boolean chaos. To verify the chaotic behavior, we compute the largest Lyapunov exponent for each implemented case of the corresponding technology, as shown in Figure 6. Table 3 also shows that the Lyapunov exponents for the three physical implementations have a similar value. This behavior suggests the Boolean chaos of proposed BCOs is robust to the distinct physical implementations changing the technology.

**Figure 6.** The divergence ln*d*(*s*) to determine the largest Lyapunov exponent of the attractor for cases in Table 3 from each discrete physical implementation (Logic gates, GAL, FPGA).



It is worth to noting that, although the intrinsic time-delays of the logic XOR and XNOR gates change among the physical realizations, Case-1 for both BCOs continues generating chaotic behavior. In agreement with Lemma 4, the fact that there is Boolean chaos, for various implementations without extra time-delays in the feedback links, demonstrates that the proposed BCOs are not overly sensitive to heterogeneous intrinsic time-delays.
