**5. An Application Specific Integrated Circuit for the Proposed Boolean Chaos Oscillators**

## *5.1. Chip Design*

This section describes the integrated circuit-based implementation of the prospected BCOs in this work. The Boolean chaos generators are described with Verilog, a Hardware Description Language (HDL), using the UMC 180 nm Generic Core Cell Library. The BCO-1 hardware description in Figure 7a uses one XNOR3S and two XOR3S cells from the Generic Core library. That verilogHDL code synthesizes the three logic gates, whereas the Encounter tool (from Cadence Design Systems) executes a generic routing algorithm. Similarly, the BCO-2 of Figure 7b uses one XOR3S and one XNOR3S for the description with the verilogHDL code. The integrated circuit was part of a multiprocess wafer run and is shown in Figure 8 (Left). The size of BCO-1 is 75 μm × 60 μm while the BCO-2 has physical dimensions of 32 μm × 26 μm. The area for biasing rails is considered in both scenarios. In any case, it is possible to reduce the size with routing optimization.

**Figure 7.** (**a**) Synthesis codes in VerilogHDL for (**a**) BCO-1, and (**b**) BCO-2, respectively.

**Figure 8.** Microphotography of the chip and the test-bench for the integrated circuit.

It is worth noting that the design process of the IC is straightforward, and it does not depend on critical design considerations. However, all the design processes were executed in a semiautomated way using the generic cells and routing tool from Cadence software and UMC 180 nm fabrication technology. Therefore, this demonstrates, once again, the flexibility and robustness of the proposed BCOs.

On the other hand, Figure 8 (Right) shows the test-bench for the integrated circuit. The chip-die is mounted on an FR4 printed circuit board. It is biased with a low-noise *VDD* = 1.8 V voltage source model B2962A while the oscilloscope DSOS104A captures the voltage time-series for further analysis.
