3.3.2. Conductivity-Voltage Measurements

Moreover, to quantify the interface defect distribution for all samples, the interface state density (*Dit*) has been extracted by the conductivity-voltage measurements with frequencies varying from 100 kHz to 1 MHz. *Dit* is related to the parallel interfacial trap capacitance (Cit) and parallel conductivity (G). At the same time, Cit can be related by the following equation. Cit = *qDit*, while the condition is that the position of the energy level does not change *Dit*. The basic principle of conductivity measurements is to analyze the losses due to the diversity of charge states at the trap level. Near the Fermi level, the synchronous conductivity occupancy is mobilized by the interfacial traps to produce a regular variation. The maximum loss occurs when the interface trap is resonantly shifted with the applied AC signal (*ωτ* = 1). The response time of the characteristic trap changes the frequency, *τ* = 2*π*/*ω*. The capture and emission rates from Shockley-Redhall theory modulate the response time [36]:

$$\tau = \frac{\exp\left[\Delta E / k\_B T\right]}{\sigma v\_{th} D\_{dos}} \tag{7}$$

where there is an energy difference Δ*E* between the trap level ET and the edge of the majority carrier band, *vth* is the majority carrier being thermally activated to obtain the average velocity, *Ddos* is the effective density of states of the majority carrier band, *kB* is the Boltzmann constant, and *T* is the temperature [37]. The curves between conductivity (G/ω) and gate voltage for all samples are shown in Figure 7a–c. The apparent shift of the conductivity peak proves the validity of the Fermi-level shift and confirms the existence of the Fermi-level deconvolution effect [38]. Assuming that the underlying surface oscillations can be neglected, the value of *Dit* is inferred using the normalized parallel conductivity peak (*GP*/*ω*)*max* [39].

$$D\_{it} \approx \frac{2.5}{Aq} \left(\frac{G\_p}{\omega}\right)\_{\text{max}}\tag{8}$$

where *A* is the device area. It is necessary to confirm the transformation law between the band bending potential of the energy location ET and the trap energy level distribution. Furthermore, the values of ET can be determined by the frequency of (*GP*/*ω*)*max*, where Equation (8) is used to calculate *Dit* and to correspond its value to Δ*E* [40].

$$
\Delta E = (\mathbf{E}\_{\rm C} - \mathbf{E}\_{\rm T}) = \frac{k\_B T}{q} \ln \left( \frac{\sigma v D\_{d\alpha}}{2 \pi f\_{\rm max}} \right) \tag{9}
$$

Figure 7d shows the variation of *Dit* for the three samples. With the increase of ΔE, the value of *Dit* shows an increasing trend. However, S3 possesses a lower density of interfacial states compared to S1 and S2, which indicates that the insertion of an Al2O3 passivation layer between the Sm2O3 gate dielectric and the InP substrate can suppress the formation of In and P suboxides and improve the quality of MOS capacitors.

We compared some of the data obtained from this work with some previously published work. As can be seen in Table 2, the Sm2O3 dielectric has a smaller leakage current density than TiO2 and HfO2, indicating that the Sm2O3 stacked gate dielectric has a larger conduction band shift, resulting in an increased barrier height and thus a reduced leakage current density. The Sm2O3 stacked gate dielectric has the smallest hysteresis value, indicating that the trapped charge in the gate dielectric is not very sensitive to the frequency response of the voltage, and will trap fewer electrons to keep the energy band from being bent, while the device maintains a consistent response to different test voltages in the antipattern region. In the interface state density, it is smaller than HfO2 as the gate dielectric directly deposited in InP, but it seems to be higher than TiO2 gate dielectric, considering the different testing methods, the interface state density of the current work is obtained directly by conductivity method with accuracy, the previous work is by C–V curve, there may be some differences.

**Figure 7.** Multi-frequency G–V characteristics of InP-based MOS capacitors of (**a**) S1, (**b**) S2, and (**c**) S3. (**d**) Energy distributions of Dit for S1, S2, and S3.


**Table 2.** Comparison of different InP MOS capacitor parameters.

3.3.3. *J*−*V* Analyses and Conduction Mechanisms at Room Temperature

Figure 8a shows the leakage current characteristics of all samples measured at room temperature. The leakage current density (*J*) values for S1, S2, and S3 at 1 V are 1.07 × <sup>10</sup><sup>−</sup>5, 8.42 × <sup>10</sup>−6, and 2.87 × <sup>10</sup>−<sup>6</sup> A/cm2, respectively. It can be seen that S1 has a higher leakage current density, which can be attributed to larger interface traps and the border traps that deteriorate the interface quality and degrade the device performance [44]. For the S3 sample, the minimum leakage current density has been observed, which is due to the higher Δ*E*<sup>c</sup> and the suppressed tunneling in the Sm2O3/Al2O3/InP gate stack [45].

To investigate the leakage current characteristics of various stacked gate dielectrics, we systematically studied three different current conduction mechanisms (CCMs) under substrate injection, as shown in Figure 8b–d. The extracted important electrical parameters are listed in Table 3.

**Figure 8.** (**a**) J–V characteristics measured at room temperature. (**b**) SE emission, (**c**) PF emission, and (**d**) FN tunneling plots for all the samples under substrate injection.

**Table 3.** Extracted MOS capacitors electrical parameters measured at room temperature.


Schottky emission (*SE*) is a typical type of thermal ionization emission in which charges gain energy to overcome barriers to migration into the dielectric. The standard *SE* can be described as [46]:

$$J\_{SE} = A^\* T^2 \exp\left[\frac{-q\left(q\_B - \sqrt{qE/4\pi\varepsilon\_0\varepsilon\_r}\right)}{k\_B T}\right] \tag{10}$$

$$A^\* = \frac{4\pi qk\_B^2 m\_{ox} \ast}{h^3} = 120 \frac{m\_{ox} \ast}{m\_0} \tag{11}$$

where *A*\* is the effective Richardson constant, the free electron mass and the effective mass of electrons in the gate dielectric correspond to mo and mox\*, E is the electric field, *qϕ<sup>B</sup>* is the Schottky barrier height, and ε<sup>o</sup> and ε<sup>r</sup> represent the vacuum dielectric constant and the optical dielectric constant, respectively [47]. It is observed in Figure 8b that at lower electric fields (0.36–0.81 MV/cm), there is a good linear relationship between ln(J/T2) and E1/2 for S1, S2, and S3. The slope of the SE diagram is denoted as q3/4πε0εr/kBT. The fitted ε<sup>r</sup> and the refractive index *n* (*n* = ε<sup>r</sup> 1/2) for S1, S2, and S3 are (4, 2), (4.96, 2.23), and (4.23, 2.06), respectively. All the fits are consistent with the previously reported values [48], revealing that CCM (current conduction mechanism) at room temperature is dominated by SE emission in the low electric field region.

The Poole–Frenkel (*PF*) emission can be ascribed to the thermally excited electrons obtaining sufficient energy to escape from traps into the conduction band of the dielectric at a higher electric field, which can be expressed by the following formula [49]:

$$J\_{PF} = AE \exp\left[\frac{-q\left(q\_t - \sqrt{qE/\pi \varepsilon\_0 \varepsilon\_{ox}}\right)}{k\_B T}\right] \tag{12}$$

where *A* represents a constant, the trap energy level of the conduction band corresponds to *ϕt*, and *εox* represents the dielectric constant. According to the previous theory, ln(*J*/*E*) should have a good proportionality with *E*1/2, as shown in Figure 8c. The εox extracted from the slope of the fitted line for all samples was calculated as 11.90, 13.01, and 13.41, which is in agreement with the reported reference [4]. It can be concluded that at higher electric fields (1.21–1.69 MV/cm), the PF emission dominates the CCM of all samples. Also, the value of the trap energy level (*ϕt*) can be extracted based on the intercept point of the fitted curve described as *lnB* <sup>−</sup> *<sup>q</sup>ϕ<sup>t</sup> kBT* . As shown in Figure 8c, the calculated values of *<sup>ϕ</sup><sup>t</sup>* are 0.53, 0.54, and 0.55 eV, corresponding to S1, S2, and S3. S3 has the largest *ϕ<sup>t</sup>* value in the three samples, indicating that the electrons obtain more energy to cross the trap, leading to present the smallest leakage current density in the S3 sample.

The high-field dependent conduction mechanism is represented by Fowler-Nordheim tunneling, which is manifested by the fact that the insulating layer can be penetrated by electrons, which enter the conduction band of the gate dielectric in a high electric field. The leakage current density is linked to other parameters of Fowler-Nordheim (*FN*) tunneling and is described by the following Equation [46]:

$$J\_{FN} = \frac{q^3 E^2}{16\pi^2 \hbar q\_{\text{ox}}} \exp\left[ -\frac{4\sqrt{2m\_T^\* q\_B^{3/2}}}{3\hbar q E} \right] \tag{13}$$

where *ϕox* is oxide barrier height; *m*<sup>∗</sup> *<sup>T</sup>* is the tunneling effective electron mass in the gate oxide film, and the other notations remain unchanged from the previous definitions. Figure 8d shows the curve of ln(*J*/*E*2) versus 1/*E*. The slope of the linear fit for the above samples shows an increase in current with increasing electric field, indicating that at high electric fields (1.47–1.85 MV/cm), all three samples are consistent with the *FN* tunneling conduction mechanism. Based on the previous analysis, it can be concluded that all samples are dominated by three main conduction mechanisms. In the lower electric fields, SE emission dominates, however, in the higher electric fields, PF emission dominates together with FN tunneling.

### 3.3.4. Low Temperature *J*–*V* Analyses and Conduction Mechanisms

To investigate the variation of CCMs in Sm2O3/Al2O3/InP MOS capacitor, low temperature (77–227 K) measurements were performed. The leakage current densities of Sm2O3/Al2O3/InP MOS capacitors measured at 1 V were extracted as 4.64 × <sup>10</sup>−9, 1.48 × <sup>10</sup><sup>−</sup>8, 1.13 × <sup>10</sup><sup>−</sup>7, and 1.02 × <sup>10</sup>−<sup>6</sup> A/cm2, corresponding to the temperature range of 77–227 K, respectively. By observing the leakage current densities at different temperatures, the Sm2O3/Al2O3/InP gate stack exhibits nearly three orders of magnitude lower leakage current density at 77 K than that measured at room temperature, indicating that the low temperature is favorable for the MOS capacitor to exhibit optimized *J*–*V* characteristics. Figure 9b–d show the variation of the CCM under substrate injection along with the temperature trend. The extracted important electrical parameters are listed in Table 4. Figure 9b shows the fitted lines for the vertical temperature range suitable for SE emission at lower electric fields (0.49–0.90 MV/cm). The extracted important electrical parameters are listed in Table 4. With increasing temperature, the values of *ε<sup>r</sup>* and n calculated from the slope and intercept are (20.39, 4.52), (18.53, 4.31), (10.40, 3.22), and (6.10, 2.47). It can be noted that at extremely low temperature of 77–177 K, these values are completely different from the theoretical values, indicating that SE emission is not the dominant conduction mechanism at lower temperatures. Figure 9c shows the curves in the temperature range 77–227 K compatible with PF emission at higher electric fields (0.64–1.44 MV/cm). Again, it can be noted that *ϕ<sup>t</sup>* and εox are not in the expected range of values, indicating that the PF emission is not compatible for all samples at intermediate electric fields of 0.64–1.44 MV/cm. FN tunneling is a potential conduction mechanism because of its dependence on the electric field at low temperatures. Figure 9d shows the fitted line of FN tunneling with a temperature range of 77–227 K at higher electric fields (1.11–1.67 MV/cm), and the established slope indicates that FN tunneling is dominant at low temperatures. In conclusion, the effects of SE emission and PF emission are attenuated due to low temperature, and FN tunneling is used to explain the Sm2O3/Al2O3/InP stacked gate dielectric structure showing low drain current density.

**Figure 9.** (**a**) J–V characteristics measured at low temperature. (**b**) SE emission, (**c**) PF emission, and (**d**) FN tunneling plots for all the samples under substrate injection.


**Table 4.** S3's MOS capacitors electrical parameters measured at low temperature.

Additionally, the integrated dielectric properties in MOS capacitors can be estimated from two important values, including the electron effective mass *m*∗ *ox* and the barrier height *<sup>q</sup>ϕ<sup>B</sup>* [50]. The intercept of the SE emission fitting curve described as ln 120 *<sup>m</sup>*<sup>∗</sup> 0*x m*<sup>0</sup> <sup>−</sup> *<sup>q</sup>ϕ<sup>B</sup> kBT* and the slope of the FN tunneling fitting curve expressed as −6.83 × <sup>10</sup><sup>7</sup> *<sup>m</sup>*<sup>∗</sup> *T m*<sup>0</sup> *ϕ*3 *<sup>B</sup>* can be calculated together with the above two values. By setting the equation *m*∗ <sup>0</sup>*<sup>x</sup>* = *m*<sup>∗</sup> *<sup>T</sup>*, the two key physical quantities *m*∗ <sup>0</sup>*<sup>x</sup>* and *qϕ<sup>B</sup>* of Sm2O3/Al2O3/InP MOS capacitor are obtained by applying mathematical analysis, which are calculated as 0.23 mo and 0.95 eV, respectively. Figure 10 shows the determination of the electron effective mass and barrier height for S3 sample. The smaller *m*∗ <sup>0</sup>*<sup>x</sup>* and the higher *qϕ<sup>B</sup>* are beneficial to obtain better electrical properties and optimized interface quality.

**Figure 10.** The determination of the electron effective mass and barrier height for S3 sample under substrate injection.
