**2. Materials and Methods**

In this work, we chose sulfur-doped n-type InP wafers as the substrate for fabricating MOS capacitors. Before depositing the Sm2O3 gate dielectric, the wafers were subjected to a standard degreasing process by sequential immersion in ethanol and acetone for 5 min each. After that, the wafers were immersed in 20% ammonium sulfide solution for 15 min to remove the native oxides. Then, the wafers are rinsed with deionized water and then blown dry with high purity nitrogen gas. The cleaned wafers are transferred to an ALD system (MNT-PD100Oz-L6S1G2, MNT Micro and Nanotech). On the ALD process, plasma O2 and trimethylaluminum (TMA) were selected as the oxidant and aluminum metal precursor, and a 2 nm Al2O3 passivation layer was deposited on the InP substrate. The Al2O3 passivation layers were deposited by using 30 pulse cycles of plasma O2 precursors [O2(2s)/Ar purge (25s)] and 15 pulse cycles of trimethylaluminum (TMA) and plasma O2 [TMA (0.03s)/O2 2s/Ar purge (25s)], respectively. During this process, the chamber pressure and the deposition temperature were maintained at 35 Pa and 200 ◦C. After ALD Al2O3 passivation, the wafers were transferred to a sputtering chamber to deposit Sm2O3 gate

dielectrics by sputtering samarium target with purity of 99.9%. When the chamber pressure was 0.8 Pa, Sm2O3 thin film was deposited under an Ar/O2 (50/10 sccm) atmosphere. To explore the electrical characteristics of Sm2O3/InP MOS capacitors with different stacking positions of Al2O3 passivation layers, a 200-μm-diameter Al electrode was deposited by thermal evaporation, while an aluminum electrode was grown on the back side to form an ohmic contact. Figure 1 demonstrates the schematics of InP-MOS capacitors based on different stacked gate dielectric structures. Sample S1 corresponds to Al2O3 (2 nm)/Sm2O3 (8 nm)/InP, sample S2 corresponds to Al2O3 (2 nm)/Sm2O3 (6 nm)/Al2O3 (2 nm)/InP, and sample S3 corresponds to Sm2O3 (8 nm)/Al2O3 (2 nm)/InP, respectively. By using the ESCALAB 250Xi system, XPS (X-ray photoelectron spectroscopy) measurements were performed at Al Ka (1486.7 eV) to investigate the interfacial chemical properties of the Sm2O3/InP gate stack and the chemical function of the Al2O3 passivation layer. Furthermore, the escape angle used in obtaining the XPS profiles is 50◦ and the corresponding probing depth is about 1–10 nm. Ultraviolet-visible spectroscopy (Shimadzu, UV-2550) was performed to obtain the samples' optical band gap. The physical thickness of the above samples was extracted by using spectroscopic ellipsometry measurements (SANCO Inc., Shanghai, China, SC630) with the help of the Cauchy-Urbach model. The Cascade Probe Station was connected to the semiconductor analysis equipment (Agilent B1500A) for capacitance-voltage (C-V), transconductance-voltage (G-V), and leakage current-voltage (I-V) measurements at room temperature. For low temperature (77–227 K) leakage current testing, the Lake Shore Cryotronics Vacuum Probing Station was used.

**Figure 1.** Schematics of InP-based MOS capacitors based on different stacked gate dielectrics.

### **3. Results and Discussion**
