**1. Introduction**

As the integration of IC continues to increase, CMOS feature sizes will also continue to decrease in order to reduce the cost of individual transistors, increase the switching speed of transistors, and reduce the power consumption of the circuit. As the feature size of CMOS devices continues to decrease, it will also cause the SiO2 gate dielectric and Si substrate used in conventional processes to decrease in size as well. When the size is smaller than a certain limit, the gate leakage current will grow exponentially, while the device will not operate properly due to the laws of quantum physics [1,2]. The use of high-k materials for the replacement of SiO2 gate dielectrics is an option that has been shown to be feasible [3]. Among these high k materials, samarium oxide (Sm2O3) is considered as the next potential gate dielectric due to its high dielectric constant (~15) [4], sufficiently large band gap (5.1 eV) [5], low hygroscopicity, and high chemical and thermal stability [6]. Coulomb scattering and phonon scattering at the interface between the high-k gate dielectric and the channel material lead to a significant reduction in channel mobility, which severely affects

**Citation:** Lu, J.; He, G.; Yan, J.; Dai, Z.; Zheng, G.; Jiang, S.; Qiao, L.; Gao, Q.; Fang, Z. Interface Optimization and Transport Modulation of Sm2O3/InP Metal Oxide Semiconductor Capacitors with Atomic Layer Deposition-Derived Laminated Interlayer. *Nanomaterials* **2021**, *11*, 3443. https://doi.org/ 10.3390/nano11123443

Academic Editor: Sergio Brutti

Received: 14 November 2021 Accepted: 16 December 2021 Published: 19 December 2021

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the further increase in the speed of CMOS logic devices. Selecting channel materials with high mobility is an effective way to solve this problem [7]. Compared with conventional Si-based material CMOS devices, III-V group semiconductors have advantages due to their large switching speed and small dynamic power consumption [8]. Among the group III-V semiconductors, InP has received more attention due to its higher carrier mobility and smaller band gap [9].

However, InP is prone to the formation of interfacial defects, which can limit the operating performance of the device [10]. Also, a surface with many chemical impurities can have a considerable impact on the performance of InP MOS capacitors [11]. High *D*it leads to the frequency dispersion of the Fermi energy level pegging and capacitance, which also prevents the formation of inverse or accumulation layers in CMOS devices [12].

Different InP surface passivation methods have been investigated for a long time, including low-temperature processes [13], ozone treatment [14], chemical etching [15], and sulfide solution passivation [16,17]. A great deal of work has also been devoted to atomic layer deposition (ALD) passivation layers to modulate the InP interface [18]. It has been demonstrated that ALD-derived Al2O3 films can effectively suppress the interfacial diffusion from the substrate to the high-k films. More importantly, the operating temperature can be kept low (~200 ◦C) when the Al2O3 film is on the passivated substrate surface. There are previous reports confirming that the insertion of Al2O3 between the high-k gate dielectric and GaAs can improve the thermal stability. However, even in the presence of an Al2O3 passivation layer to improve the interface, the diffusion of In and P elements into the gate dielectric still has an impact on the electrical characteristics of the device when fabricating InP MOS capacitors. R. V. Galatage et al. reported that the In-O and P-O states at the interface lead to a degradation of the electrical characteristics [19]. Their results also demonstrated the effectiveness of ALD-derived Al2O3 passivation layers between the gate dielectric and the InP substrate. Chee-Hong An et al. systematically analyzed that Al2O3 can inhibit dissociation and reactant diffusion in InP substrates [20]. However, the effect of the position of the Al2O3 passivation layer on the electrical properties and interfacial bonding state of InP MOS devices has not been reported systematically.

In this work, we deposited Sm2O3 films by magnetron sputtering and obtained Al2O3 passivation layers by ALD equipment to fabricate three different gate stacks on InP substrates, corresponding to Al2O3/Sm2O3/InP, Al22O3/Sm2O3/Al2O3/InP, and Sm2O3/Al2O3/InP, respectively. X-ray photoelectron spectroscopy (XPS) and electrical measurements were used to investigate the effect of Al2O3 passivation position on the chemical composition and electrical parameters of the interface. In addition, the leakage current conduction mechanisms (CCMs) of InP-based MOS capacitors with three different laminated gate electrical stacks measured at room temperature and low temperature (77–227 K) were systematically investigated.
