*3.1. Analysis of Shoot through Fault Protection*

In the proposed inverter, the complimentary operation of *S*<sup>2</sup> and *S*<sup>3</sup> at high switching frequency may result in the false turn-on of the switches [30]. Since Miller capacitance is present in all switches, the stored charge in it can cause the false turn ON of *S*3. If both switches are in the ON state at the same time, the positive DC link voltage may become shorted in a positive half cycle of operation. The same thing is true for negative voltage during the negative half cycle. MOSFETs, in contrast to bipolar devices such as IGBTs, cannot endure overcurrent. Although shoot-through fault can happen in any switching device, since UWBG devices such as Ga2O<sup>3</sup> switches are operating in this inverter at a very high frequency, they are more prone to this fault [31]. The issue is overcome by restricting

the rate of the rising fault current using the split inductors. Hence, the proposed inverter configuration offers zero dead-band between *S<sup>2</sup>* and *S3*.

To observe the impact, the shoot-through fault is allowed to happen on purpose when transitioning from the zero state *O*<sup>3</sup> to the state *P*. The fault current (*I<sup>f</sup>* ) is allowed to pass through *S<sup>2</sup>* and can be determined by:

$$I\_f(t) = \frac{0.5 \times V\_{DC}}{R\_{eq} + R\_1 + R\_2} \left(1 - e^{\frac{-t(R\_{eq} + R\_1 + R\_2)}{L\_{eq} + L\_1 + L\_2}}\right) \tag{6}$$

Here, *t* is the time interval when shooting through the fault is allowed to happen, the resistances of *L*<sup>1</sup> and *L*<sup>2</sup> are denoted by *R*<sup>1</sup> and *R*2, respectively, and, *Req* and *Leq* are the equivalent resistance and inductance of the printed circuit board (PCB) path. *Req* and *Leq* are required to calculate the maximum allowable time of shoot-through fault for a selected PCB.

The values of *Req* and *Leq* are calculated to be 0.245 Ω and 187 nH, respectively, from the information given for PCB in [32,33]. Thus, the maximum allowable time is 21.06 ns for the selected design which is, in fact, lower than the turn OFF time of the Ga2O<sup>3</sup> devices. In addition, the overcurrent limit for the design is 80 A. Therefore, before the switch *S*<sup>2</sup> is turned off (with *toff* = 94 ns), the switch *S*<sup>3</sup> will be turned on falsely and can cause device failure. This issue is resolved by allowing a shoot-through time which is almost twice the turn OFF time of the Ga2O<sup>3</sup> devices by using 1 uH split inductors. The numerical calculations can be realized by:

For conventional ANPC with split inductors,

$$I\_f(t) = \frac{600}{0.245\,\Omega} \left(1 - e^{\frac{-1004\,\text{ns}\,\times\,0.245\,\Omega}{2\,\text{lbf}\,\,\text{pH}}}\right) = 260.52\,\text{A}\tag{7}$$

For the proposed hybrid ANPC with split inductors,

$$I\_f(t) = \frac{600}{0.245\,\Omega} \left(1 - e^{\frac{-188\text{ ns}\times0.245\,\Omega}{2.187\,\mu\text{H}}}\right) = 51.04\text{ A}\tag{8}$$

A simulation is conducted to determine the shoot through fault current of the proposed inverter by taking into consideration all the parasitic elements of the presented inverter circuit. Accordingly, the shoot-through fault's current paths are illustrated for both the positive and negative half cycle in Figure 6a,b, respectively. The simulation results are shown in Figure 7, and it can be observed that they are almost similar to the calculated values. It can be observed that in the case of the proposed inverter, the fault current is within the limit. This validates the predominance of the UWBG device as well as the hybridization that has been utilized in this article. It is worth noting that the fault current can be reduced for the conventional ANPC by increasing the value of the split inductors. However, it will incur more inductor core losses into the system and will eventually reduce the inverter's efficiency, making it radically unsuitable for industrial applications.
