*2.2. Modelling of Hybrid ANPC Inverter*

The schematic diagram of the proposed topology is depicted in Figure 3. The four switches, namely, *S*1, *S*4, *S*5, and *S*6, are constructed by using Si-based IGBTs, which are rated as 1.2 kV. On the other hand, the *S*<sup>2</sup> and *S<sup>3</sup>* switches are made by Ga2O3-based MOSFETs of 800 V rating. The utilization of both Si and Ga2O<sup>3</sup> devices has ensured that the inductors can be split into *L*<sup>1</sup> and *L*<sup>2</sup> through these devices. In addition, it should be noted that the diodes *D*<sup>2</sup> and *D*<sup>3</sup> are both Ga2O3-based Schottky diodes [28]. As illustrated in Figure 3, the Ga2O3-based MOSFETs, i.e., *S*<sup>2</sup> and *S*<sup>3</sup> switches, are decoupled from *D<sup>2</sup>* and *D3*, and this leads to the division of the inductors. Some capacitors are series-connected in the DC-link to make up neutral point '*n*'. There is a common portion of the two inductors between point '*a*' and the terminal '*n*', and the output is taken from this portion. As it is listed in Table 1, this inverter has six possible states. The states denoted by *P* and *N* represent positive and negative states, respectively, and null states are referred to as *O*<sup>1</sup> to *O*4. *S*<sup>2</sup> and *S<sup>3</sup>* gallium trioxide (Ga2O3) switches are operated at a higher frequency, whereas Si IGBTs are operated in lower frequencies because it is required to maximize the output. To exploit this, only two null states, *O*<sup>3</sup> and *O*2, as shown in Table 3, are utilized. More specifically, in case of the positive half cycle, the states *P* as well as *O*<sup>3</sup> are used, and the states *N* and *O*<sup>2</sup> are utilized for the operation of the negative half cycle. The UWBG is operated at a higher frequency of 100 kHz while the other four Si-based switches are operated at a lower fundamental frequency of 50 Hz. The gate pulses for switches are created using the level-shifted pulse width modulation (LSPWM) [29], which are depicted in Figure 4. The *S*<sup>1</sup> and *S*<sup>6</sup> switches will remain ON, while switches *S*<sup>4</sup> and *S*<sup>5</sup> will be turned OFF in case of positive cycle operation. On the contrary, the *S*<sup>4</sup> and *S*<sup>5</sup> switches will be ON and start conducting, while the *S*<sup>1</sup> and *S*<sup>6</sup> switches will be turned off for the negative half cycle. *Micromachines* **2021**, *12*, x FOR PEER REVIEW 6 of 20

**Figure 3.** Schematic diagram of the hybrid ANPC inverter comprising UWBG switches. **Figure 3.** Schematic diagram of the hybrid ANPC inverter comprising UWBG switches.

**Figure 4.** Switching pulses of the Ga2O3 devices of the hybrid ANPC using LSPWM.

0 0.005 0.01

0.0025 0.0075 Time (ms)

Mode 2

in this paper as depicted in Figure 5.

Mode 1

*S*2

*VDC /2* 

*-VDC /2* 

*S*3

As illustrated in Figure 4, the LSPWM is employed for the output voltage generation. In addition, there are three voltage levels, namely, 0.5 *Vdc*, 0, and 0.5 *Vdc.* It can be observed from Figure 4 that the proposed inverter has four modes of operation. Mode 1 and mode 2 are for the first half cycle whereas mode 3 and mode 4 are for the negative half cycle. As both cycles have a symmetrical operation, only mode 1 and mode 2 are discussed

*S1 S2 S3 S4 S5 S6* 

*P* 1 1 0 0 0 1 *O*1 0 1 0 0 1 0 *O*2 0 1 0 1 1 0 *O*3 1 0 1 0 0 1 *O*4 0 0 1 0 0 1 *N* 0 0 1 1 1 0

Carrier Wave 2

Mode 4

Modulating Wave Carrier Wave 1

Mode 3

**Table 3.** Switching states for the proposed HANPC inverter.

**+**

*VDC /2* 

*S***5**

*S***6**

**-**

*VDC /2* 


**Table 3.** Switching states for the proposed HANPC inverter. **Figure 3.** Schematic diagram of the hybrid ANPC inverter comprising UWBG switches.

*n a*

*S***3**

*D***2**

*L***1**

*L***2**

*S***4**

*S***1**

*S***2**

*D***3**

*Micromachines* **2021**, *12*, x FOR PEER REVIEW 6 of 20

**Figure 4.** Switching pulses of the Ga2O3 devices of the hybrid ANPC using LSPWM. **Figure 4.** Switching pulses of the Ga2O<sup>3</sup> devices of the hybrid ANPC using LSPWM.

As illustrated in Figure 4, the LSPWM is employed for the output voltage generation. In addition, there are three voltage levels, namely, 0.5 *Vdc*, 0, and 0.5 *Vdc.* It can be observed from Figure 4 that the proposed inverter has four modes of operation. Mode 1 and mode 2 are for the first half cycle whereas mode 3 and mode 4 are for the negative half cycle. As both cycles have a symmetrical operation, only mode 1 and mode 2 are discussed in this paper as depicted in Figure 5. As illustrated in Figure 4, the LSPWM is employed for the output voltage generation. In addition, there are three voltage levels, namely, 0.5 *Vdc*, 0, and 0.5 *Vdc.* It can be observed from Figure 4 that the proposed inverter has four modes of operation. Mode 1 and mode 2 are for the first half cycle whereas mode 3 and mode 4 are for the negative half cycle. As both cycles have a symmetrical operation, only mode 1 and mode 2 are discussed in this paper as depicted in Figure 5.
