*3.2. Analysis of Core Losses*

The core losses of the proposed inverter are calculated in this section by considering the split inductors. The parameters which are considered for the proposed inverter's inductor design are listed in Table 5. The permissible losses in the copper winding are computed for the chosen core, with the required product area, which is the product of the window area (*Wa*) and the core area (*Ac*):

$$W\_{\rm d} \times A\_{\rm c} = \frac{LI\_{\rm max}I\_{\rm rms}}{K\_{\rm t}B\_{\rm max}j\_{\rm max}} \tag{9}$$

*S*1

*S*2 *S*3 *S*4 *S*5 *S*6

*If* (*t*) A

50 60

Gate Pulses

*a*

*L***1**

*L***2**

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**Figure 6.** Shoot through fault current paths of the hybrid ANPC inverter during (**a**) state *O3* to state *P* for positive half cycle, (**b**) state *O*2 to state *N* for the negative half cycle. **Figure 6.** Shoot through fault current paths of the hybrid ANPC inverter during (**a**) state *O<sup>3</sup>* to state *P* for positive half cycle, (**b**) state *O*<sup>2</sup> to state *N* for the negative half cycle. **Figure 6.** Shoot through fault current paths of the hybrid ANPC inverter during (**a**) state *O3* to state *P* for positive half cycle, (**b**) state *O*2 to state *N* for the negative half cycle.

shoot through fault, (**b**) hybrid ANPC, (**c**) conventional ANPC. **Figure 7.** Shoot through fault current analysis: (**a**) gate pulses of *S2* and *S3* overlapping and causing shoot through fault, (**b**) hybrid ANPC, (**c**) conventional ANPC. **Figure 7.** Shoot through fault current analysis: (**a**) gate pulses of *<sup>S</sup><sup>2</sup>* and *<sup>S</sup><sup>3</sup>* overlapping and causing shoot through fault, (**b**) hybrid ANPC, (**c**) conventional ANPC.

**Figure 7.** Shoot through fault current analysis: (**a**) gate pulses of *S2* and *S3* overlapping and causing


**Table 5.** Parameters for designing the split inductors.

Here, *L* is one of the split inductors, *Imax* is the maximum current flowing through the inductor, *Irms* is the rated RMS current, *K<sup>t</sup>* is the topological constant, *Bmax* is the maximum flux density, and *jmax* is the maximum current density of the inductor. Although for complete accuracy the optimum loss for copper should be measured, the maximum permissible copper loss is calculated in this section because of the minimal difference between the accurate and approximate values, as well as for simplicity. Thus, the maximum allowable copper loss is used to measure the efficiency. The product area value obtained from (9) is used to determine the thermal resistance *Rth* by utilizing the data from [33], assuming that the core temperature is increasing by 50 ◦C:

$$R\_{th} = 17.45(\mathcal{W}\_a \times A\_c)^{-0.509} + 0.416 \, ^\circ \text{C/W} \tag{10}$$

After the thermal resistance is calculated, this can lead to the measurement of maximum possible core loss (*PCu*) for a particular temperature rise ∆*T*, and it can be determined by the following equation:

$$P\_{\mathbb{C}u} = \frac{\Delta T}{R\_{th}}\tag{11}$$

The measurement of the copper winding loss can be performed for the split inductors by utilizing (9) to (11). Because of the minimal values of the product area, a large core size is selected for the practical design. The core losses for the selected material from Magnetics [34] are plotted using the values given in [33] in Figure 8 for the selected core volume. *Micromachines* **2021**, *12*, x FOR PEER REVIEW 12 of 20

**Figure 8.** Core loss induced by the inductors under different switching frequencies. **Figure 8.** Core loss induced by the inductors under different switching frequencies.

Although it is already clear that the use of split inductors in the hybrid ANPC module is a major source of loss in steady-state operation, the inherent nature of the hybrid ANPC

For switching loss measurement, double pulse testing (DPT) [30] is conducted. The DPT circuit used for the switching measurement is illustrated in Figure 9. The parasitic inductors in the PCB path are denoted by *Lp*1, *Lp*2, and *Lp*3; the series inductor in the DC link is denoted by *Ls*; and the output inductor is denoted by *Lo*. Similarly, the drain to source capacitance of Ga2O3 switches and the anode–cathode capacitance of the Ga2O3 Schottky diode are indicated as *Cds* and *Cac*, respectively. The output inductance is measured following [30] while *Lp*1, *Lp*2, and *Lp*3 are measured following [33]. All the calculated

switching losses. Therefore, to quantify the improvement, it is essential to know how

much loss is reduced after the addition of the UWBG switches.

**Figure 9.** DPT circuit of the hybrid ANPC inverter with parasitic elements.

*S***3**

*D***2**

*DS***<sup>2</sup>** *Cds Cac*

*Ls Lo*

Table 6 after putting these values in LT Spice, the simulation is conducted and switch-

*DS***<sup>3</sup>** *Cds*

*L***1**

*L***2**

*a*

*3.3. Analysis of Switching Losses* 

values are listed in Table 6.

*S***5**

*S***6**

*Ls*

*S***1**

*Lp***<sup>1</sup>** *Lp***<sup>2</sup>** *Lp***3**

*S***2**

*D***<sup>3</sup>** *Cac*

*Lp***<sup>1</sup>** *Lp***<sup>2</sup>** *Lp***3**

*S***4**

**+ -** *VDC /2 VDC /2 n*

*VDC*

ing transients are calculated.

### *3.3. Analysis of Switching Losses 3.3. Analysis of Switching Losses*

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Although it is already clear that the use of split inductors in the hybrid ANPC module is a major source of loss in steady-state operation, the inherent nature of the hybrid ANPC inverter is also responsible for the additional losses. The use of Ga2O<sup>3</sup> switches *S*<sup>2</sup> and *S*<sup>3</sup> is a viable solution for this topology because these UWBG switches help to reduce the switching losses. Therefore, to quantify the improvement, it is essential to know how much loss is reduced after the addition of the UWBG switches. Although it is already clear that the use of split inductors in the hybrid ANPC module is a major source of loss in steady-state operation, the inherent nature of the hybrid ANPC inverter is also responsible for the additional losses. The use of Ga2O3 switches *S*2 and *S*<sup>3</sup> is a viable solution for this topology because these UWBG switches help to reduce the switching losses. Therefore, to quantify the improvement, it is essential to know how much loss is reduced after the addition of the UWBG switches.

**Figure 8.** Core loss induced by the inductors under different switching frequencies.

For switching loss measurement, double pulse testing (DPT) [30] is conducted. The DPT circuit used for the switching measurement is illustrated in Figure 9. The parasitic inductors in the PCB path are denoted by *Lp*1, *Lp*2, and *Lp*3; the series inductor in the DC link is denoted by *L<sup>s</sup>* ; and the output inductor is denoted by *Lo*. Similarly, the drain to source capacitance of Ga2O<sup>3</sup> switches and the anode–cathode capacitance of the Ga2O<sup>3</sup> Schottky diode are indicated as *Cds* and *Cac*, respectively. The output inductance is measured following [30] while *Lp*1, *Lp*2, and *Lp*<sup>3</sup> are measured following [33]. All the calculated values are listed in Table 6. For switching loss measurement, double pulse testing (DPT) [30] is conducted. The DPT circuit used for the switching measurement is illustrated in Figure 9. The parasitic inductors in the PCB path are denoted by *Lp*1, *Lp*2, and *Lp*3; the series inductor in the DC link is denoted by *Ls*; and the output inductor is denoted by *Lo*. Similarly, the drain to source capacitance of Ga2O3 switches and the anode–cathode capacitance of the Ga2O3 Schottky diode are indicated as *Cds* and *Cac*, respectively. The output inductance is measured following [30] while *Lp*1, *Lp*2, and *Lp*3 are measured following [33]. All the calculated values are listed in Table 6.

**Figure 9.** DPT circuit of the hybrid ANPC inverter with parasitic elements. **Figure 9.** DPT circuit of the hybrid ANPC inverter with parasitic elements.

Table 6 after putting these values in LT Spice, the simulation is conducted and switch-**Table 6.** Parameters for DPT testing.


Table 6 after putting these values in LT Spice, the simulation is conducted and switching transients are calculated.

The DPT test is performed repeatedly for different load currents and switching voltages to emulate practical scenarios. The data obtained from DPT are used to measure the energies required for the turning ON and turning OFF of the switches by using simulation, and they are referred to as *Eon* and *Eoff*, respectively. Figure 10 illustrates the measured switching energies for both the conventional and the proposed inverter topologies. Though

the energy consumption in the ideal switch should be zero, the semiconductor switches are hardly ideal, and thus, from these curves, it can be observed how switching energies rise when the load current increases. In addition, it is evident from these curves that the use of Ga2O<sup>3</sup> switches has greatly contributed to reducing both the turn-on and turn-off switching energies. The simulated waveform shown in Figure 11 represents the minimization of switching losses with the utilization of Ga2O<sup>3</sup> switches. It can be observed from Figure 11a that when *S*<sup>2</sup> is turned on, the switching current has increased as soon as the gate pulse is applied. In other words, since conventional Si switches have a slow turn-on time, an overshoot current of 43 A is caused by *Cac* of *D*3. On the contrary, the Ga2O<sup>3</sup> switches have a very fast turn-on time, which is why the overshoot current in this case significantly declined as shown in Figure 11c. This phenomenon also implies that due to the decreased overshoot, a faster decrease in switching voltage across the switch *S*<sup>2</sup> in the case of the proposed inverter leads to decreased loss. In the case of turn-off, an almost similar event occurs in both case 1 and case 2, which are illustrated in Figure 11b,d, respectively. In this case, it can be observed that an overvoltage spike of almost 630 V is experienced by the conventional inverter compared to the 560 V spile of the hybrid. Though the energy consumption in the ideal switch should be zero, the semiconductor switches are hardly ideal, and thus, from these curves, it can be observed how switching energies rise when the load current increases. In addition, it is evident from these curves that the use of Ga2O3 switches has greatly contributed to reducing both the turn-on and turn-off switching energies. The simulated waveform shown in Figure 11 represents the minimization of switching losses with the utilization of Ga2O3 switches. It can be observed from Figure 11a that when *S*2 is turned on, the switching current has increased as soon as the gate pulse is applied. In other words, since conventional Si switches have a slow turnon time, an overshoot current of 43 A is caused by *Cac* of *D*3. On the contrary, the Ga2O3 switches have a very fast turn-on time, which is why the overshoot current in this case significantly declined as shown in Figure 11c. This phenomenon also implies that due to the decreased overshoot, a faster decrease in switching voltage across the switch *S*2 in the case of the proposed inverter leads to decreased loss. In the case of turn-off, an almost similar event occurs in both case 1 and case 2, which are illustrated in Figure 11b,d, respectively. In this case, it can be observed that an overvoltage spike of almost 630 V is experienced by the conventional inverter compared to the 560 V spile of the hybrid

**Equipment Nomenclature Value** 

Capacitors *Cds* 171 pF

The DPT test is performed repeatedly for different load currents and switching voltages to emulate practical scenarios. The data obtained from DPT are used to measure the energies required for the turning ON and turning OFF of the switches by using simulation, and they are referred to as *Eon* and *Eoff*, respectively. Figure 10 illustrates the measured switching energies for both the conventional and the proposed inverter topologies.

*Ls* 36.15 nH *Lp*1 11.6 nH *Lp*2 19.16 nH *Lp*3 11.6 nH *Lo* 1200 uH

*Cac* 80 pF

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**Table 6.** Parameters for DPT testing.

Inductors

**Figure 10.** Characteristics curves highlighting the energies required for switches to turn ON and turn OFF with respect to the switching current for conventional ANPC and hybrid ANPC inverters. **Figure 10.** Characteristics curves highlighting the energies required for switches to turn ON and turn OFF with respect to the switching current for conventional ANPC and hybrid ANPC inverters.

ANPC inverter. This has resulted in higher turn OFF losses incurred by the conventional inverter. Although the margin of differences between the conventional inverter and the hybrid ANPC for turn OFF losses is very close, the overall switching losses of hybrid ANPCs are significantly lower because the turn ON losses are more dominant.
