**4. Experimental Validation**

The experimental implementation was performed considering the parameters and conditions described in Section 3 and in Table 3. In Figure 15, the output currents in (a), the line-to-neutral voltages in (b), and the line-to-line voltages in (c) for the CSSVM strategy are presented. As can be observed, the waveforms are similar to those obtained for the simulation results. Namely, the output current for the three phases is sinusoidal plus the switching ripple, the voltage between each phase and the neutral connection has the typical five levels, and the voltages between lines are also the typical of a full-bridge three-phase system. Since these waveforms are close to the waveforms of the other two proposed SVPWM strategies, only the results for the CSSVM are included. In Figure 16, the results obtained for the common mode behavior for (a) CSSVM, (b) CASVM, and (c) DSVMMAX at the DC bus 1 and the common mode current are shown. Notice that, in all cases, the CMC has a value below 300 mA, which is established by the international norm DIN VDE 0126-1-1 as the maximum allowable limit. Note that the *CMV*<sup>1</sup> waveform contains a noise component, which is due to the oscilloscope internal calculations and the effect of parasitic components during the switching process. Moreover, the CMV regarding the second DC bus *CMV*<sup>2</sup> has also been obtained. The average value of this parameter is close to 266.66*V*, which is the value obtained by means of simulations; however, and considering that the waveform is similar to the signal presented for the *CMV*1, the last is not included in the paper.

In order to better compare the results obtained by the implementation of the proposed SVM algorithms regarding CMC, the measures are summarized in Table 5. As can be noted, the RMS value for the CMC for the three proposed cases is similar and complies with the international standard mentioned before. Moreover, the results regarding CMC were compared with the conventional full-bridge three-phase inverter (3PFB-VSI) under SVM, and it can be noted that the CMC has a larger magnitude regarding the proposed modulation topology and SVPWM algorithms.

**Figure 15.** Experimental output currents and voltages of the three-phase DCM-232 inverter under the SVM-CSSVM technique. (**a**) Output currents, (**b**) line-to-neutral voltages, and (**c**) line-to-line voltages.

**Figure 16.** Experimental common mode voltage (*CMV*<sup>1</sup> ) and common mode current (CMC) of the three-phase DCM-232 inverter under the (**a**) CSSVM, (**b**) CASVM, and (**c**) DSVMMAX techniques.

**Table 5.** CMC magnitudes of the DCM-232 under the proposed SVPWM strategies.

