**Comparison of the Total Ionizing Dose Sensitivity of a System in Package Point of Load Converter Using Both Componentand System-Level Test Approaches**

**Tomasz Rajkowski 1,2,\* , Frédéric Saigné 2 , Kimmo Niskanen <sup>2</sup> , Jérôme Boch <sup>2</sup> , Tadec Maraine <sup>2</sup> , Pierre Kohler <sup>1</sup> , Patrick Dubus <sup>1</sup> , Antoine Touboul <sup>2</sup> and Pierre-Xiao Wang <sup>1</sup>**

	- tadec.maraine@ies.univ-montp2.fr (T.M.); antoine.touboul@ies.univ-montp2.fr (A.T.)

**Abstract:** Testing at system level is evaluated by measuring the sensitivity of point-of-load (PoL) converter parameters, submitted to total ionizing dose (TID) irradiations, at both system and component levels. Testing at system level shows that the complete system can be fully functional at the TID level more than two times higher than the qualification level obtained using a standard-based component-level approach. Analysis of the failure processes shows that the TID tolerance during testing at system level is increased due to internal compensation in the system. Finally, advantages and shortcomings of the testing at system level are discussed.

**Keywords:** total ionizing dose; system-level testing; point-of-load converter; radiation hardness assurance; system qualification

### **1. Introduction**

The qualification of components that will be used for space missions requires test standards that allow the selection of components that will make up the on-board systems [1–3]. With the increasing use of commercial off-the-shelf (COTS) devices or the need to set up selection methodologies for new fields, such as nuclear decommissioning or NewSpace, the question of testing no longer at the component level but at the level of a system arises [4–12]. It is expected that testing at system level may lead to the reduction of the test effort when compared to testing at the component level of all the parts constituting the system—therefore, it may also reduce time-to-market for new products. System-level testing may also provide extended radiation data for some products, e.g., devices that were too difficult to characterize fully with component-level testing. However, currently there is no standard that would describe the qualification process of electronics through radiation testing at system level and this paper aims to evaluate some of the capabilities of this approach.

In this paper, TID system-level tests are discussed. They are typically easier and cheaper to perform than single event effect (SEE) system-level tests, due to relatively high accessibility of the standard test source, the Co<sup>60</sup> isotope that emits highly penetrating gamma rays, which can penetrate whole electronic boards and systems. The test setup is usually also simpler for TID testing because generally there is no need to monitor the performance of the system under test (SUT) during irradiation; characterization might be performed when irradiation is stopped and the SUT removed from the test area (remote testing), although sometimes it is chosen to perform in situ or even in-flux measurements with automated test equipment [6,7].

**Citation:** Rajkowski, T.; Saigné, F.; Niskanen, K.; Boch, J.; Maraine, T.; Kohler, P.; Dubus, P.; Touboul, A.; Wang, P.-X. Comparison of the Total Ionizing Dose Sensitivity of a System in Package Point of Load Converter Using Both Component- and System-Level Test Approaches. *Electronics* **2021**, *10*, 1235. https:// doi.org/10.3390/electronics10111235

Academic Editor: Elias Stathatos

Received: 15 April 2021 Accepted: 19 May 2021 Published: 22 May 2021

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**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

Fernández [6] presented a method of TID testing at system (equipment) level for the ITER experiment, where component test standards are followed where applicable (Test Method 1019 from MIL-STD-750E, Test Method 1019 from MIL-STD-883G and ESCC 22900), due to lack of a standard for system-level testing. Because the SUT has both CMOS and bipolar parts, low dose rate irradiation is used as the worst case for this scenario. Irradiation is followed by annealing. The target environment for the system is not very harsh and the predicted dose level to be achieved during operation in that environment is 100 rad. Therefore, it was possible to perform irradiation with a large margin (300 times) by testing the system up to 30 krad in a reasonable time of around 120 h. Such a large margin is favorable for the critical equipment, in the situation when the system-level test is used experimentally for the system qualification and, e.g., a lot-to-lot variability in the system is not known. The system was performing typical functions during irradiation ("test as you fly" approach) and its performance was continuously monitored: an in-flux functional test was performed every 30 min. Only minor functionality errors were observed at the end of the test, but due to the SUT complexity, it was not possible to track which exact component (or group of components) was responsible for this failure (particularly because high-level function health was monitored and not parameters (e.g., electrical parameters) of specific components) [6].

Rousselet [7] described board-level TID tests of the COTS single-board computer (SBC) equipped with an ARM Cortex A8 processor, memories (DDR3, Flash, EEPROM) and voltage regulators. In this test it was possible to observe degradation of specific components or subsystems and to identify the most sensitive components, as well as to define the failure mechanisms—board-level testing enabled better observability than equipment-level testing described in [6], thus providing more data for analysis. Testing of four SBC boards was presented in [7], with three biased boards and one unbiased board. Different functional and electrical parameters were measured (flash memory readout data rate, DDR3 memory input voltage, MicroProcessor Unit voltage, total current) and the measurement spread (between specific SBCs) was observed for these parameters. The test provides information on the dose level for which the SBC (or some of its functions) fail, but the maximum dose level for which it remains fully (or sufficiently) functional is not proposed (as a consequence, margins for such a value are not discussed). It is highlighted that system should be tested in the exact internal configuration in which it will be used in the target mission; differences between biased and unbiased boards were observed. On the other hand, testing in different environmental conditions is also proposed, i.e., in low and high temperatures to assess the worst-case condition for the system [7].

In order to further evaluate the capabilities of the testing at system level, in this paper we have performed TID experiments on a point-of-load (PoL) converter manufactured by 3D-Plus. This point-of-load converter has already been qualified using the ESA standard ECSS-22900 [13]. In addition, all the devices of the complete system have been tested individually following the standards. The PoL converter has also been qualified for a total dose of 50 krad(Si). In this work we have performed irradiations of the complete system to evaluate the total dose that could be reached before failure or being out of specifications and compared it with the 50 krad obtained using a qualification at component level. We have shown that the complete system is still functional after a Co<sup>60</sup> irradiation at 118 krad(Si). Some parameters have drifted but the system is largely within the specifications. In order to reach the failure of the device, X-ray irradiations have then been performed. A total dose above 400 krad(Si) was necessary to show failures of the tested systems. An analysis has been conducted to find the process at play leading to the degradation of the system. We have then shown that two blocks of the system compensate each other, leading to a lower sensitivity to TID. From this analysis, testing at system level is discussed.

#### **2. Experiment Description**

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#### *2.1. System under Test (SUT) 2.1. System under Test (SUT)*

The system under test is a PoL converter developed by 3D-Plus. It is a custom-built system based on COTS components, with 11 references of active components, (6 discrete and 5 integrated circuits) from different technologies (bipolar/CMOS). PoL is a space qualified product available as 3D system-in-package (SiP) module, characterized (based on component-level tests [14]) up to a TID level of 50 krad. In our work, the original 3D SiPs as well as 2D prototype boards were tested. The 2D board has size of 85 mm × 95 mm and is functionally and electrically equivalent to the 3D SiP. Components are on a single layer for the 2D board whereas components of the SiP are distributed on 3 layers, one above another, and encapsulated in a 26.5 mm × 25 mm × 10 mm metalized package. Another difference is that two CMOS ICs on the 2D board have different date codes than for the 3D SiP (but have the same reference and come from the same manufacturer). The PoL functional block diagram is presented in Figure 1. The photograph of the PoL 3D SiP and 2D boards is given in Figure 2. The system under test is a PoL converter developed by 3D-Plus. It is a custom-built system based on COTS components, with 11 references of active components, (6 discrete and 5 integrated circuits) from different technologies (bipolar/CMOS). PoL is a space qualified product available as 3D system-in-package (SiP) module, characterized (based on component-level tests [14]) up to a TID level of 50 krad. In our work, the original 3D SiPs as well as 2D prototype boards were tested. The 2D board has size of 85 mm × 95 mm and is functionally and electrically equivalent to the 3D SiP. Components are on a single layer for the 2D board whereas components of the SiP are distributed on 3 layers, one above another, and encapsulated in a 26.5 mm × 25 mm × 10 mm metalized package. Another difference is that two CMOS ICs on the 2D board have different date codes than for the 3D SiP (but have the same reference and come from the same manufacturer). The PoL functional block diagram is presented in Figure 1. The photograph of the PoL 3D SiP and 2D boards is given in Figure 2.

**Figure 1.** PoL functional block diagram. **Figure 1.** PoL functional block diagram.

#### *2.2. Test at Component Level*

TID tests on the 11 references of basic devices were characterized [14] during test campaigns performed in accordance with ESA Standard ESCC-22900.

Irradiation was performed using the Co<sup>60</sup> source GIF at the Université Catholic de Louvain (UCL) facility in Belgium. The dose rate was between 100 and 360 rad(Si)/h. The bias conditions during exposure are the worst-case bias as per the PoL design justification document.

It was shown in [14] that all the irradiated devices are functional up to 50 krad. In a first step, parameter drifts under irradiation were evaluated regarding the tolerances given by the manufacturer datasheet. In a second step, if drift was higher than the initial tolerance, a specific analysis was performed to evaluate the acceptability of the variation in the PoL system. A summary of the total dose test results is given in Table 1.

**Figure 2.** PoL 3D SiP on the auxiliary board and attached to the motherboard (first plan) and two PoL 2D boards on their motherboards (second plan). **Figure 2.** PoL 3D SiP on the auxiliary board and attached to the motherboard (first plan) and two PoL 2D boards on their motherboards (second plan).

TID tests on the 11 references of basic devices were characterized [14] during test


*2.2. Test at Component Level*  **Table 1.** TID status for active devices used in PoL module (from [14]).

**Table 1.** TID status for active devices used in PoL module (from [14]). From the TID test campaign and results analysis according to the acceptable drifts for the PoL system, the PoL converter has been guaranteed for a total dose of 50 krad(Si).

**Results in Accordance with** 

#### **Type Results in Accordance with**  *2.3. Test at System Level*

**Manufacturer Datasheet PoL Design Requirement**  Diodes >50 Krad >50 Krad Transistors >50 Krad >50 Krad Voltage reference 15.4 Krad >50 Krad Logic gates 7 Krad >50 Krad 5 Krad >50 Krad Comparator >50 Krad >50 Krad All SUTs were supplied during irradiation (5 V); the output voltage of each PoL (VOUT on Figure 1) was set to 2.5 V and the load connected to VOUT was 8 Ω. After each irradiation step, each SUT was removed from the irradiator, reconnected to the power supply and characterized electrically: 29 parameters were measured for 2D boards and 33 for 3D SiP, and both DC and AC parameters were measured. In this paper, only the most relevant experimental results are presented.

#### Op-amplifiers 9.8 Krad >50 Krad 2.3.1. Irradiation with a Co<sup>60</sup> Source

 4.9 Krad >50 Krad In order to achieve a direct comparison with the tests performed at component level in [14], complete PoL systems were irradiated using a Co<sup>60</sup> source. One PoL 3D SiP (SUT022) and one PoL 2D (SUT012) board were irradiated using the Co<sup>60</sup> source of the PRESERVE platform at the University of Montpellier. Irradiation was performed up to 125Krad(Si) and the dose rate was 15 rad/h.

#### 2.3.2. Irradiation with an X-ray Source

One PoL 3D SiP (SUT020) and two PoL 2D boards (SUT010 and SUT011) were irradiated using the X-RAD 320 irradiator of the PRESERVE platform at the University of Montpellier, with potential of the X-ray tube as high as 320 kV/12.5 mA. The dose rate used was 50 krad/h for all 3 SUTs tested.

#### **3. Experimental Results and Analysis**

### *3.1. Test at System Level Using a Co<sup>60</sup> Source*

At 118 krad(Si) both SUTs were fully functional. Among the 29 parameters measured, few of them drifted and the variation remained very small and largely inside the specifications. In Table 2, the parameters presenting the largest variations at 118 Krad(Si) are reported with their percentage of variation compared to the prerad value: the ON supply current, the OFF supply current and the oscillator frequency.

**Table 2.** Percentage of variation compared to the prerad value of parameters at 118 Krad(Si) (Co<sup>60</sup> irradiation).


The OFF supply current was measured when all the integrated circuits were supplied but the oscillator was stopped, therefore the loop controlling the output power was stopped and VOUT = 0V. The ON supply current was measured when the PoL system supplied the output.

The important point is then that the PoL system, when evaluated at system level, was shown to reach 118 krad(Si), whereas testing at component level allowed its qualification only at 50 krad(Si).

It is also important to note that the dose rate used for the test at system level was at least 7 times lower than the one used for the test at component level. The 15 rad/h used is compliant with testing for systems sensitive to ELDRS [13]. This also shows that no significant ELDRS is at play in the global system functionality.

The higher total dose reached during the test at system level than that using the test at component level could imply that there is compensation, at circuit level, between some of the system's blocks (Figure 1).

#### *3.2. Test at System Level Using X-rays*

In order to evaluate the limit of the system and to obtain significant variations of parameters to attempt an analysis of the possible interactions between the different system blocks, irradiations were performed using X-rays at a 50 krad/h dose rate. The goal was not to compare X-rays and Co<sup>60</sup> irradiations, but to reach, in a reasonable time, a total ionizing dose high enough to observe the system's degradation.

The output voltage of the PoL (VOUT) is reported as a function of TID in Figure 3. For both 2D boards (SUT010 and SUT011) functional failures were observed, respectively, at 450 and 500 krad (at the end of the irradiation step, the system was disconnected and then connected to the test bench but did not power up). This means that the last doses for which the device was functional were, respectively, 400 and 475 krad for SUT 010 and SUT 011. It is important to note that for the 3D SiP device, no functional failure was observed (the

irradiation was stopped at 500 krad). This is assumed to be related to the SiP packaging that mitigates X-rays on the internal circuit. From Figure 3, we can observe a very small drift of VOUT. The maximum measured drift of VOUT (which is the crucial parameter for the user) was not different from the initial value by more than 0.4% (SUT020, 500 krad) and the drift observed for SUT010 and SUT011 just one irradiation step before they failed was less than 0.3%. In Figure 3, two behaviors might be observed: an increase of the measured values up to level of 50–100 krad and a decrease above 50–100 krad. However, the goal of presenting the curves in Figure 3 was to show that the observed change of the output voltage was insignificant during irradiation and could not be used to predict that the system would soon fail. In this context, the insignificant linear change of the VOUT observed for TID above 50 krad gives no advantage in predicting when the system may fail. served (the irradiation was stopped at 500 krad). This is assumed to be related to the SiP packaging that mitigates X-rays on the internal circuit. From Figure 3, we can observe a very small drift of VOUT. The maximum measured drift of VOUT (which is the crucial parameter for the user) was not different from the initial value by more than 0.4% (SUT020, 500 krad) and the drift observed for SUT010 and SUT011 just one irradiation step before they failed was less than 0.3%. In Figure 3, two behaviors might be observed: an increase of the measured values up to level of 50–100 krad and a decrease above 50– 100 krad. However, the goal of presenting the curves in Figure 3 was to show that the observed change of the output voltage was insignificant during irradiation and could not be used to predict that the system would soon fail. In this context, the insignificant linear change of the VOUT observed for TID above 50 krad gives no advantage in predicting when the system may fail.

*Electronics* **2021**, *10*, x FOR PEER REVIEW 6 of 13

ionizing dose high enough to observe the system's degradation.

of the system's blocks (Figure 1).

*3.2. Test at System Level Using X-rays* 

The higher total dose reached during the test at system level than that using the test at component level could imply that there is compensation, at circuit level, between some

In order to evaluate the limit of the system and to obtain significant variations of parameters to attempt an analysis of the possible interactions between the different system blocks, irradiations were performed using X-rays at a 50 krad/h dose rate. The goal was not to compare X-rays and Co60 irradiations, but to reach, in a reasonable time, a total

The output voltage of the PoL (VOUT) is reported as a function of TID in Figure 3. For both 2D boards (SUT010 and SUT011) functional failures were observed, respectively, at 450 and 500 krad (at the end of the irradiation step, the system was disconnected and

SUT 011. It is important to note that for the 3D SiP device, no functional failure was ob-

**Figure 3.** Output voltage (normalized) of SUTs as a function of the total ionizing dose (X-ray irradiation). SUT 010 and SUT 011 failed, respectively, at 450 and 500 krad (measurements performed at these two TID steps have shown that output voltage is ~0 V and that most of the internal subsystems are not working). The 3D SiP was still fully functional. **Figure 3.** Output voltage (normalized) of SUTs as a function of the total ionizing dose (X-ray irradiation). SUT 010 and SUT 011 failed, respectively, at 450 and 500 krad (measurements performed at these two TID steps have shown that output voltage is ~0 V and that most of the internal subsystems are not working). The 3D SiP was still fully functional.

In Table 3, the percentages of variation compared to the prerad values are given at 400 krad(Si) for the ON supply current, the OFF supply current and the oscillator frequency to be compared to values shown in Table 2. No other parameters have shown a significant increase.

**Table 3.** Percentages of variation compared to the prerad values of parameters at 400 krad(Si) (X-rays irradiation).


It is shown that the OFF supply current strongly increases for both 2D and 3D systems, by 100% and 59%, respectively. The ON supply current increase is important for the 2D board (12.5%).

In Figure 4, the normalized oscillator frequency value is represented as a function of TID for 2D boards and 3D SiP systems. For the 2D boards (SUT010 and SUT011), the oscillator frequency value increases by a factor of 1.18. A saturation of the degradation significant increase.

rays irradiation).

is observed after 150 krad. The saturation value is equal to 490 kHz. The 3D SiP system also shows an increase in the oscillator frequency value by a factor of 1.125. A saturation is observed after 250 krad. The saturation value is equal to 440 kHz. Notches observed in each curve (e.g., at 200 krad for SUT 010 curve) are due to annealing, when irradiation had to be stopped for longer period (e.g., whole night). cillator frequency value increases by a factor of 1.18. A saturation of the degradation is observed after 150 krad. The saturation value is equal to 490 kHz. The 3D SiP system also shows an increase in the oscillator frequency value by a factor of 1.125. A saturation is observed after 250 krad. The saturation value is equal to 440 kHz. Notches observed in each curve (e.g., at 200 krad for SUT 010 curve) are due to annealing, when irradiation had to be stopped for longer period (e.g., whole night).

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In Table 3, the percentages of variation compared to the prerad values are given at 400 krad(Si) for the ON supply current, the OFF supply current and the oscillator frequency to be compared to values shown in Table 2. No other parameters have shown a

**Table 3.** Percentages of variation compared to the prerad values of parameters at 400 krad(Si) (X-

ON supply current 1% 12.5% OFF supply current 59% 100% Oscillator frequency 12.5% 18%

 **Percentage of Variation Compared to the Prerad Value** 

 **3DSip Module 2D Module** 

It is shown that the OFF supply current strongly increases for both 2D and 3D systems, by 100% and 59%, respectively. The ON supply current increase is important for the

In Figure 4, the normalized oscillator frequency value is represented as a function of TID for 2D boards and 3D SiP systems. For the 2D boards (SUT010 and SUT011), the os-

**Figure 4.** Normalized oscillator frequency value as a function of TID for 2D boards and 3D SiP. (notches observed in each curve (e.g., at 200 krad for SUT 010 curve) are due to annealing, when irradiation had to be stopped for a longer period (e.g., whole night)). **Figure 4.** Normalized oscillator frequency value as a function of TID for 2D boards and 3D SiP. (notches observed in each curve (e.g., at 200 krad for SUT 010 curve) are due to annealing, when irradiation had to be stopped for a longer period (e.g., whole night)).

Considering the results for 2D boards, when the PoL system was designed, specifications were given for the irradiation tests at device level. The specification limit for the oscillator frequency was 450 kHz. Results presented in our work show that oscillator frequency is 8–9% higher than this limit as soon as the total dose reaches 150 krad but the PoL remains functional up to a total dose above 400 krad. Considering the results for 2D boards, when the PoL system was designed, specifications were given for the irradiation tests at device level. The specification limit for the oscillator frequency was 450 kHz. Results presented in our work show that oscillator frequency is 8–9% higher than this limit as soon as the total dose reaches 150 krad but the PoL remains functional up to a total dose above 400 krad.

During component-level qualification of PoL [14] the Schmitt trigger, being a core part of the oscillator, was irradiated up to 50 krad with the Co60 source. Acceptability of During component-level qualification of PoL [14] the Schmitt trigger, being a core part of the oscillator, was irradiated up to 50 krad with the Co<sup>60</sup> source. Acceptability of Schmitt trigger variations has been verified from results at component level using standards but also on the PoL system. The maximum frequency drift measured for the oscillator built with an irradiated component was from 419 to 427 kHz and the part was then accepted. If, during this component-level qualification, the degradation of frequency had been similar to the X-ray irradiation test shown in Figure 4, the part would have been rejected, but the system-level test (Figure 3) shows that, regardless of the degradation of the oscillator frequency, the system remains functional not only after 50 krad, but also up to 400 krad under X-rays and 118 krad under Co<sup>60</sup> irradiations.

#### *3.3. Tracking of the System Failure Source*

From all the measurements made, there is no obvious way to identify the process at play leading to the 2D board failures above 400 krad. Investigation of the failure source of 2D boards tested with X-rays was performed and the conducted analysis is presented hereafter.

Increased current consumption in ON mode (Table 3) suggested that switching time of the power MOSFET might be longer—this was confirmed by analyzing waveforms of the MOSFET driver signal recorded at each step of the irradiation (see Figure 5 for example waveforms recorded for SUT010).

hereafter.

Schmitt trigger variations has been verified from results at component level using standards but also on the PoL system. The maximum frequency drift measured for the oscillator built with an irradiated component was from 419 to 427 kHz and the part was then accepted. If, during this component-level qualification, the degradation of frequency had been similar to the X-ray irradiation test shown in Figure 4, the part would have been rejected, but the system-level test (Figure 3) shows that, regardless of the degradation of the oscillator frequency, the system remains functional not only after 50 krad, but also up

From all the measurements made, there is no obvious way to identify the process at play leading to the 2D board failures above 400 krad. Investigation of the failure source of 2D boards tested with X-rays was performed and the conducted analysis is presented

Increased current consumption in ON mode (Table 3) suggested that switching time

to 400 krad under X-rays and 118 krad under Co60 irradiations.

*3.3. Tracking of the System Failure Source* 

ple waveforms recorded for SUT010).

**Figure 5.** SUT010 MOSFET driver waveforms recorded at steps 0, 200 and 400 krad (X-ray irradiation). Black color marks switching time for each irradiation step. Switching time is approximately 3 times longer for 200 krad (than prerad) and more than 15 times longer for 400 krad (than prerad). **Figure 5.** SUT010 MOSFET driver waveforms recorded at steps 0, 200 and 400 krad (X-ray irradiation). Black color marks switching time for each irradiation step. Switching time is approximately 3 times longer for 200 krad (than prerad) and more than 15 times longer for 400 krad (than prerad).

These waveforms show degradation of the switching threshold and increase of switching time of the MOSFET. For a high enough degradation, the MOSFET does not open fully (ON resistance is high), therefore it does not provide enough current to the PoL output. Because this current is too low, the feedback loop drives the control voltage too high and the overcurrent protection (OCP, based on the voltage control loop signal) is triggered. This triggering of the OCP is observed during characterization of failed SUTs (SUT010 at 450 krad and SUT011 at 500 krad) (Figure 6). The OCP signal not only provides information about the overcurrent state, but is also the input to the auto-reset circuit of the PoL. During normal operation of the PoL, when there is no overcurrent state, this signal is at the level of ~0.05 V. We can see from Figure 6 that the value of the OCP signal is repeated in the cycle: (1) slow decrease from ~3 V to around 0.5 V—in the beginning the These waveforms show degradation of the switching threshold and increase of switching time of the MOSFET. For a high enough degradation, the MOSFET does not open fully (ON resistance is high), therefore it does not provide enough current to the PoL output. Because this current is too low, the feedback loop drives the control voltage too high and the overcurrent protection (OCP, based on the voltage control loop signal) is triggered. This triggering of the OCP is observed during characterization of failed SUTs (SUT010 at 450 krad and SUT011 at 500 krad) (Figure 6). The OCP signal not only provides information about the overcurrent state, but is also the input to the auto-reset circuit of the PoL. During normal operation of the PoL, when there is no overcurrent state, this signal is at the level of ~0.05 V. We can see from Figure 6 that the value of the OCP signal is repeated in the cycle: (1) slow decrease from ~3 V to around 0.5 V—in the beginning the OCP is in a high logic state, forcing the reset of the PoL; (2) at some point, the OCP stops resetting the PoL and the converter starts to operate; (3) the operation of the PoL leads again to the overcurrent state—the OCP signal from the level of ~0.5 V goes rapidly to the level of ~3 V. The PoL is again reset.

> The switching time variations as a function of the total ionizing dose are shown in Figure 7 for both 2D boards and 3D SiP systems. It is shown that both 2D boards show a significant increase of the switching time compared to the 3D SiP systems. Such a difference is assumed to be due to the SiP packaging that reduces the total ionizing dose received by the components under X-ray irradiation. It is also shown that both 2D boards have the same degradation of the switching time up to 250 krad, but for doses above 250 krad, the SUT 010 systems present a higher degradation of the switching time than the SUT020 system for a given dose.

> Considering the dose leading to the system failure (Figure 3), for SUT010 failure is observed after 400 krad and for SUT011 failure is observed after 475 krad. In both cases, failure is observed when a 1 µs value of the switching time is reached. We then have a direct correlation between the failure of the system and the switching time parameter that allows us to identify the process at play leading to the device failure.

level of ~3 V. The PoL is again reset.

level of ~3 V. The PoL is again reset.

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**Figure 6.** OCP signal as observed after the failure of the SUT010. 3 different phases/steps of operation of the PoL during failure are marked: (1) PoL is in the reset state and the OCP signal decreases; (2) OCP signal enters the range of logic low state and the PoL starts to operate; (3) OCP signal is triggered and the PoL is reset again. **Figure 6.** OCP signal as observed after the failure of the SUT010. 3 different phases/steps of operation of the PoL during failure are marked: (1) PoL is in the reset state and the OCP signal decreases; (2) OCP signal enters the range of logic low state and the PoL starts to operate; (3) OCP signal is triggered and the PoL is reset again. ence is assumed to be due to the SiP packaging that reduces the total ionizing dose received by the components under X-ray irradiation. It is also shown that both 2D boards have the same degradation of the switching time up to 250 krad, but for doses above 250 krad, the SUT 010 systems present a higher degradation of the switching time than the SUT020 system for a given dose.

OCP is in a high logic state, forcing the reset of the PoL; (2) at some point, the OCP stops resetting the PoL and the converter starts to operate; (3) the operation of the PoL leads again to the overcurrent state—the OCP signal from the level of ~0.5 V goes rapidly to the

OCP is in a high logic state, forcing the reset of the PoL; (2) at some point, the OCP stops resetting the PoL and the converter starts to operate; (3) the operation of the PoL leads again to the overcurrent state—the OCP signal from the level of ~0.5 V goes rapidly to the

**Figure 7.** Switching time as a function of the total ionizing dose for both 2D boards and 3D SiP systems.

Let us now consider the fact that the system survived to a total dose significantly higher than 50 krad, which was the qualified level after the test at component level. Although the system failure was finally tracked down to the failure of a single component, it is worth noting that several parameters of the system were changed because of the MOSFET degradation: current consumption, parameters of the voltage control loop (compensating MOSFET degradation to retain a good level of VOUT) and MOSFET driver fall time. Particularly, it might be observed that the duty cycle of the MOSFET driver is changed by the PoL feedback mechanism, in order to compensate for the degradation of the MOSFET (see Figure 8). The related effects are presented in the block diagram in Figure 9: (1) the reduced output voltage is detected by the voltage control block; (2) the correction signal

(X-ray irradiation).

**4. Discussion** 

ence.

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**Figure 7.** Switching time as a function of the total ionizing dose for both 2D boards and 3D SiP systems.

allows us to identify the process at play leading to the device failure.

Considering the dose leading to the system failure (Figure 3), for SUT010 failure is observed after 400 krad and for SUT011 failure is observed after 475 krad. In both cases, failure is observed when a 1 µs value of the switching time is reached. We then have a direct correlation between the failure of the system and the switching time parameter that

Let us now consider the fact that the system survived to a total dose significantly higher than 50 krad, which was the qualified level after the test at component level. Although the system failure was finally tracked down to the failure of a single component, it is worth noting that several parameters of the system were changed because of the MOSFET degradation: current consumption, parameters of the voltage control loop (compensating MOSFET degradation to retain a good level of VOUT) and MOSFET driver fall

the MOSFET (see Figure 8). The related effects are presented in the block diagram in Figure 9: (1) the reduced output voltage is detected by the voltage control block; (2) the cor-

is sent to the PWM generation block; (3) the duty cycle of the MOSFET driver signal is modified. rection signal is sent to the PWM generation block; (3) the duty cycle of the MOSFET driver signal is modified.

**Figure 8.** PoL 2D board MOSFET driver duty cycle change as a function of the total ionizing dose **Figure 8.** PoL 2D board MOSFET driver duty cycle change as a function of the total ionizing dose (X-ray irradiation).

**Figure 9.** Block diagram explaining compensation of the MOSFET degradation. 3 effects are marked on the diagram: (1) the reduced output voltage is detected by the voltage control block; (2) the correction signal is sent to the PWM generation block; (3) the duty cycle of the MOSFET driver signal is modified. **Figure 9.** Block diagram explaining compensation of the MOSFET degradation. 3 effects are marked on the diagram: (1) the reduced output voltage is detected by the voltage control block; (2) the correction signal is sent to the PWM generation block; (3) the duty cycle of the MOSFET driver signal is modified.

In other words, the MOSFET degradation is compensated by the voltage control loop, extending the TID tolerance of the system. In other words, the MOSFET degradation is compensated by the voltage control loop, extending the TID tolerance of the system.

Testing at system level allows us, for this specific system, to show that the system can reach a higher total ionizing dose before failure than a test at component level, but the

In our case, the system was shown to be more tolerant to TID, but if a failure had

It is also important to consider if the test performed at system level is conservative or not. In our case, the failure was shown to have been induced by the increase in the switching time leading to a decrease in the output current. This will then depend on the load at the output of the PoL. It is then expected that by decreasing the load (8 ohms during our test), the degradation will also increase, leading to a lower tolerance to TID. Our test was not performed in the worst-case conditions, but defining the worst-case conditions was difficult when the failure source at system level was not known before the test. Such a

origin of the failure in order to improve the system and make corrections to the design. It is then very important to have a high observability during the testing, which means there are many system parameters to monitor. In our case, such a strong observability was possible due to the fact that SUT was a "white box". Full design information, as well as the placement of specific test points, were known during test preparation and during SUT characterization, which may not always be the case for other systems (e.g., COTS systems). It was shown (Figure 7) that the two 2D boards have different kinetics for switching time degradation. SUT010 degrades more rapidly than SUT011. Such a difference is assumed to be induced by the part-to-part variations of the basic devices. Once again, in our case, this is not a problem as the system is shown to be tolerant for high total doses, but this will not be always the case. If we consider that the PoL system should be qualified for a 450 krad total dose, the difference between the two 2D boards generates an uncertainty as SUT010 will pass the test whereas SUT011 will not. A statistical approach would then be necessary in order to minimize the error induced by the component part-to-part differ-

testing at system level could also be more difficult to qualify a system.

#### **4. Discussion**

Testing at system level allows us, for this specific system, to show that the system can reach a higher total ionizing dose before failure than a test at component level, but the testing at system level could also be more difficult to qualify a system.

In our case, the system was shown to be more tolerant to TID, but if a failure had been observed during this test before 50 krad, the difficulty would have been to find the origin of the failure in order to improve the system and make corrections to the design. It is then very important to have a high observability during the testing, which means there are many system parameters to monitor. In our case, such a strong observability was possible due to the fact that SUT was a "white box". Full design information, as well as the placement of specific test points, were known during test preparation and during SUT characterization, which may not always be the case for other systems (e.g., COTS systems).

It was shown (Figure 7) that the two 2D boards have different kinetics for switching time degradation. SUT010 degrades more rapidly than SUT011. Such a difference is assumed to be induced by the part-to-part variations of the basic devices. Once again, in our case, this is not a problem as the system is shown to be tolerant for high total doses, but this will not be always the case. If we consider that the PoL system should be qualified for a 450 krad total dose, the difference between the two 2D boards generates an uncertainty as SUT010 will pass the test whereas SUT011 will not. A statistical approach would then be necessary in order to minimize the error induced by the component part-to-part difference.

It is also important to consider if the test performed at system level is conservative or not. In our case, the failure was shown to have been induced by the increase in the switching time leading to a decrease in the output current. This will then depend on the load at the output of the PoL. It is then expected that by decreasing the load (8 ohms during our test), the degradation will also increase, leading to a lower tolerance to TID. Our test was not performed in the worst-case conditions, but defining the worst-case conditions was difficult when the failure source at system level was not known before the test. Such a remark goes in the direction towards testing at system level "as your mission". The obtained results might be also interpreted in the way that for the given system configuration (i.e., output voltage, output load), there was a margin given by the design that could be used to increase tolerance to TID. For another configuration (particularly the worst-case configuration), there might be not as large a margin to be used.

#### **5. Conclusions**

One of the advantages of the testing at system-level approach is the possibility to obtain more realistic results because the influence of the component's degradation on the system health is already included in system-level test results. In order to evaluate such an approach, experiments were performed on a system-in-package point-of-load converter to evaluate its sensitivity to the TID. Two different approaches were used. The PoL converter was evaluated through tests at component level using standards and by a complete system-level approach.

The main results show that using standards leads to a qualification of the PoL at 50 krad(Si), whereas testing at system level shows that the PoL is fully functional at 118 krad(Si). Both approaches were performed using a classical Co<sup>60</sup> source.

The test at system level was stopped at 118 Krad(Si) for experimental duration reasons and the PoL was still fully functional. X-rays were then used to go further in a short time irradiation. The TID level observed was higher than 400 krad before system failures.

Analysis of the results has shown that the extension of the TID tolerance of the system is related to compensations between some electrical blocks in the complete system.

In the discussion, it was clearly shown that the results obtained for this particular system cannot be generalized to others. The results were shown to represent an ideal case when testing at system level and points that have to be considered in a more general case were raised. The first point is related to the observability when performing tests at system level; the second one deals with the part-to-part variations; and the last one relates to the difficulty in defining the worst-case conditions when irradiating at system level.

**Author Contributions:** Conceptualization, T.R., F.S. and P.-X.W.; methodology, T.R., F.S. and P.-X.W.; software, T.R.; validation, T.R., F.S. and P.-X.W.; formal analysis, T.R. and F.S.; investigation, T.R., F.S., P.D. and P.-X.W.; resources, T.R., F.S., K.N., J.B., T.M., P.K. and P.-X.W.; data curation, T.R.; writing original draft preparation, T.R. and F.S.; writing—review and editing, T.R., F.S., K.N., J.B., T.M., P.K., P.D., A.T., P.-X.W.; visualization, T.R.; supervision, F.S. and P.-X.W.; project administration, F.S. and P.-X.W.; funding acquisition, F.S. and P.-X.W. All authors have read and agreed to the published version of the manuscript.

**Funding:** X-rays and Co<sup>60</sup> tests were performed using the PRESERVE Platform, which was funded by the Occitanie Region and the EU via ERDF funds. This work received funding from the European Union's Horizon 2020 research and innovation program under the Marie Skłodowska-Curie grant agreement number 721624.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**

