*Article* **Electrical Modeling and Characterization of Graphene-Based On-Chip Spiral Inductors**

**Da-Wei Wang <sup>1</sup> , Meng-Jiao Yuan <sup>1</sup> , Jia-Yun Dai 2,\* and Wen-Sheng Zhao 1,\***


**Abstract:** This paper investigates the electrical performance of graphene-based on-chip spiral inductors by virtue of a physics-based equivalent circuit model. The skin and proximity effects, as well as the substrate loss effect, are considered and treated appropriately. The graphene resistance and inductance are combined into the circuit model. It is demonstrated that the electrical characteristics of the on-chip square spiral inductor can be improved by replacing copper with graphene. Moreover, graphene exhibits more effectiveness in improving the inductance in tapered inductors than uniform ones.

**Keywords:** graphene; on-chip spiral inductor; circuit model; kinetic inductance; quantum resistance

## **1. Introduction**

With the improvement of CMOS technologies, radio-frequency integrated circuits (RF ICs) have become possible and have drawn increasing attention in the past decades. To make RF ICs lightweight, multi-functional, and low-cost, on-chip spiral inductors with high inductance density and low power consumption have been widely utilized in the design of low-noise amplifiers, voltage-controlled oscillators, and filters [1].

In order to improve the inductor performance, it is intuitive to pursue high inductance density and quality factors. There are various factors affecting inductor characteristics, such as substrate resistivity and metal thickness. Increasing metal thickness can improve the quality factor by minimizing Ohmic losses but is counter-productive at high frequencies due to accentuated proximity effect loss [2]. The magnetic field from all turns of a spiral inductor accumulates in the middle area, thereby resulting in severe current crowding in the inner turns. As the current crowding can be mitigated with narrow and widely spaced inner turns, a tapered spiral inductor was proposed in [3] to improve the quality factor without consuming extra area.

To facilitate the miniaturization of RF ICs, the scaling down of on-chip spiral inductors is inevitable [4]. However, there exists an inherent limitation in the scalability of conical spiral inductors, as the inductance value is limited by the laws of electromagnetic induction [5]. This is, the magnetic flux is proportional to the surface area, and the magnetic inductance cannot be scaled to retain desired inductance density.

Carbon nanomaterials, including carbon nanotube (CNT) and graphene, have been proposed as promising alternative candidates for interconnected applications. They have been demonstrated to have unique physical properties such as a long mean free path (MFP), extremely high ampacity, and large thermal conductivity, and they exhibit superior performance and reliability to traditional metal wires [6–9]. More importantly, carbon nanomaterials possess large kinetic inductance, which makes them suitable for building inductors in future scaled RF ICs. It was proven that CNT-based on-chip spiral inductors can provide better quality factors than their Cu counterparts [10]. In comparison with CNT, graphene is more compatible with the traditional CMOS process [11], and there are

**Citation:** Wang, D.-W.; Yuan, M.-J.; Dai, J.-Y.; Zhao, W.-S. Electrical Modeling and Characterization of Graphene-Based On-Chip Spiral Inductors. *Micromachines* **2022**, *13*, 1829. https://doi.org/10.3390/ mi13111829

Academic Editor: Ha Duong Ngo

Received: 8 October 2022 Accepted: 23 October 2022 Published: 26 October 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

ways to control graphene chirality and doping levels [12]. Graphene-based on-chip spiral inductors were explored in-depth recently [5,13]. It was experimentally demonstrated that the graphene kinetic inductance is beneficial for improving the inductor performance. Although the graphene-based inductors were investigated numerically in [13], the anomalous skin effect could be neglected as it mainly affects the electrical characteristics beyond 100 GHz, and the modeling methodology could be therefore simplified. ways to control graphene chirality and doping levels [12]. Graphene-based on-chip spiral inductors were explored in-depth recently [5,13]. It was experimentally demonstrated that the graphene kinetic inductance is beneficial for improving the inductor performance. Although the graphene-based inductors were investigated numerically in [13], the anomalous skin effect could be neglected as it mainly affects the electrical characteristics beyond 100 GHz, and the modeling methodology could be therefore simplified.

can provide better quality factors than their Cu counterparts [10]. In comparison with CNT, graphene is more compatible with the traditional CMOS process [11], and there are

This paper aims to provide a simple circuit model for investigating graphene-based inductors. Firstly, the equivalent circuit model of an on-chip tapered spiral inductor is developed, with the proximity effect and substrate loss taken into account. The quantum contact resistance, scattering resistance, and kinetic inductance of graphene ribbon (GR) are combined into the model to explore the electrical characteristics. By virtue of the circuit model, the electrical performance of graphene-based inductors is investigated, with some guidance provided for future development. The rest of this paper is organized as follows. Section 2 presents the geometry of the on-chip tapered spiral inductor and its physics-based equivalent circuit model. The graphene kinetic inductance is discussed in Section 3, and it is combined into the model to explore the inductor characteristics. The performance analysis of graphene-based spiral inductors is carried out in Section 4. Some conclusions are finally drawn in Section 5. This paper aims to provide a simple circuit model for investigating graphene-based inductors. Firstly, the equivalent circuit model of an on-chip tapered spiral inductor is developed, with the proximity effect and substrate loss taken into account. The quantum contact resistance, scattering resistance, and kinetic inductance of graphene ribbon (GR) are combined into the model to explore the electrical characteristics. By virtue of the circuit model, the electrical performance of graphene-based inductors is investigated, with some guidance provided for future development. The rest of this paper is organized as follows. Section II presents the geometry of the on-chip tapered spiral inductor and its physicsbased equivalent circuit model. The graphene kinetic inductance is discussed in Section III, and it is combined into the model to explore the inductor characteristics. The performance analysis of graphene-based spiral inductors is carried out in Section IV. Some conclusions are finally drawn in Section V.

#### **2. Circuit Model of On-Chip Square Spiral Inductor 2. Circuit Model of On-Chip Square Spiral Inductor**

*Micromachines* **2022**, *13*, x FOR PEER REVIEW 2 of 12

On-chip spiral inductors can be divided into rectangular, square, circular, hexagon, and octagonal types according to their geometries. Due to their simple configuration, square spiral inductors are widely used in the design of RF ICs, as shown in Figure 1. In the figure, *D*out is the outer diameter, and *w*<sup>1</sup> and *s*<sup>1</sup> denote the width and spacing of the outermost turn, respectively. For the tapered spiral inductor, the difference in the width between adjacent turns is defined as *taper*, with the pitch kept constant. Accordingly, the *i*th turn has a width of *w<sup>i</sup>* = *w*<sup>1</sup> − (*i* − 1) · *taper*, and its spacing with an adjacent inner turn is *s<sup>i</sup>* = *s*<sup>1</sup> + (*i* − 1) · *taper*. On-chip spiral inductors can be divided into rectangular, square, circular, hexagon, and octagonal types according to their geometries. Due to their simple configuration, square spiral inductors are widely used in the design of RF ICs, as shown in Figure 1. In the figure, ୭୳୲ is the outer diameter, and ଵ and ଵ denote the width and spacing of the outermost turn, respectively. For the tapered spiral inductor, the difference in the width between adjacent turns is defined as , with the pitch kept constant. Accordingly, the th turn has a width of = ଵ − ሺ−1ሻ ⋅ , and its spacing with an adjacent inner turn is = ଵ + ሺ−1ሻ ⋅ .

**Figure 1.** Schematic of on-chip square spiral inductor. **Figure 1.** Schematic of on-chip square spiral inductor.

Figure 2 shows the π-equivalent circuit model of the on-chip tapered spiral inductor, which is composed of oxide capacitance ୭୶, substrate capacitance ୗ୧, and substrate resistance ୗ୧ [14]. To obtain the inductance value accurately, the widely applied Greenhouse formulas of a planar spiral inductor are adopted, and the total inductance of the spiral inductor is calculated by Figure 2 shows the π-equivalent circuit model of the on-chip tapered spiral inductor, which is composed of oxide capacitance *C*ox, substrate capacitance *C*Si, and substrate resistance *R*Si [14]. To obtain the inductance value accurately, the widely applied Greenhouse formulas of a planar spiral inductor are adopted, and the total inductance of the spiral inductor is calculated by

$$L\_{\rm dc} = L\_{\rm self} + \sum M\_{+} + \sum M\_{-} \tag{1}$$

ances between two lines. where *L*self is the self-inductance of a metal line, and *M*<sup>+</sup> and *M*<sup>−</sup> are mutual inductances between two lines.

**Figure 2.** Equivalent circuit model. **Figure 2.** Equivalent circuit model.

ୢୡ <sup>=</sup> <sup>1</sup>

2୫ୟ୶

The dc resistance of a spiral inductor is calculated by The dc resistance of a spiral inductor is calculated by

ୀଵ

 

ே

ୀଵ

$$R\_{\rm dc} = \frac{1}{\sigma\_m t\_m} \sum\_{i=1}^{N} \frac{l\_i}{w\_i} \tag{2}$$

the frequency-dependent effect should be treated appropriately. A ladder network marked by the dashed box in Figure 2 is added for modeling skin and proximity effects [15]. At low frequencies, the current is uniformly distributed inside the inductor, while the current accumulation occurs at the surface layer of the inductor at high frequencies. The high-frequency resistance ଵ is calculated by ଵ <sup>=</sup> <sup>1</sup> ே where *σ<sup>m</sup>* is the metal conductivity. To accurately evaluate the inductor characteristics, the frequency-dependent effect should be treated appropriately. A ladder network marked by the dashed box in Figure 2 is added for modeling skin and proximity effects [15]. At low frequencies, the current is uniformly distributed inside the inductor, while the current accumulation occurs at the surface layer of the inductor at high frequencies. The high-frequency resistance *R*<sup>1</sup> is calculated by

$$R\_1 = \frac{1}{2\sigma\_m t\_m \delta\_{\text{max}}} \sum\_{i=1}^{N} l\_i \tag{3}$$

(3)

refer to [15]. Further, 2-branch networks are employed to improve the model accuracy, with the proximity factor defined as [15] =ୢୡ ⋅ 2ୢୡ <sup>−</sup> <sup>1</sup> 2 ൫, + ,୭୲୦ୣ୰ୱ൯ ே ൩ ିଵ (4) where *δ*max denotes the skin depth at the maximum operating frequency *f*max, and it is given as *δ*max = 1/ p *πµσ<sup>m</sup> f*max. The calculations of other resistances and inductances can refer to [15]. Further, 2-branch networks are employed to improve the model accuracy, with the proximity factor defined as [15]

$$d = L\_{\rm dc} \cdot \left[ 2L\_{\rm dc} - \frac{1}{2I} \sum\_{i=1}^{N} w\_i l\_i (B\_{i,i} + B\_{i, \rm others}) \right]^{-1} \tag{4}$$

maximum proximity effect [16]. The oxide and silicon capacitance are calculated by ୭୶ <sup>=</sup> ୭୶ ୭୶ ே (5) where *I* is the excitation current, and *Bi*,*<sup>i</sup>* and *Bi*, others represent the magnetic fields due to the *i*th turn and the other turns except *i*th turn, respectively. The minimum and maximum values of *d* are 0.5 and 1, which correspond to the cases of no proximity effect and maximum proximity effect [16].

where ୭୶ is the permittivity of the oxide layer, and ୗ୧ and ୗ୧ are the permittivity and

ୀଵ ୗ୧ = 2ୗ୧ ே The oxide and silicon capacitance are calculated by

2ℎୗ୧ <sup>+</sup> <sup>ට</sup>

conductivity of the silicon substrate, respectively.

ୀଵ

$$\mathsf{C}\_{\mathrm{ox}} = \frac{\mathsf{c}\_{\mathrm{ox}}}{t\_{\mathrm{ox}}} \sum\_{i=1}^{N} w\_{i} l\_{i} \tag{5}$$

$$\mathbf{C}\_{\rm Si} = 2e\_{\rm Si} \sum\_{i=1}^{N} \frac{w\_{\rm i} l\_i}{2l\_{\rm Si} + \sqrt{\frac{w\_{\rm i} l\_i}{\pi}} - \sqrt{4l\_{\rm Si}^2 + \frac{w\_{\rm i} l\_i}{\pi}}} \tag{6}$$

$$R\_{\rm Si} = \varepsilon\_{\rm Si} / (\sigma\_{\rm Si} \mathbb{C}\_{\rm Si}) \tag{7}$$

where *ε*ox is the permittivity of the oxide layer, and *ε*Si and *σ*Si are the permittivity and conductivity of the silicon substrate, respectively. full-wave electromagnetic simulator, i.e., ANSYS HFSS (2021 version, Ansys, Inc., Canonsburg, PA, USA). In the simulation; the silicon conductivity is 10 S/m, and the geomet-

To evaluate the circuit model, a set of square spiral inductors are simulated using a fullwave electromagnetic simulator, i.e., ANSYS HFSS (2021 version, Ansys, Inc., Canonsburg, PA, USA). In the simulation; the silicon conductivity is 10 S/m, and the geometrical parameters are as follows: *D*out = 200 µm; *w*<sup>1</sup> = 13 µm; and *s*<sup>1</sup> = 7 µm. For the tapered spiral inductor, *taper* = 2 µm/turn. The effective inductance and quality factor are obtained from the simulated *Y*-parameters and plotted in Figure 3: rical parameters are as follows: ୭୳୲ = 200 μm; ଵ = 13 μm; and ଵ = 7 μm. For the tapered spiral inductor, = 2 μm turn ⁄ . The effective inductance and quality factor are obtained from the simulated *Y*-parameters and plotted in Figure 3: = Imሺଵଵሻ Reሺଵଵሻ (8) ୣ <sup>=</sup> <sup>1</sup> 2 Im ൬ <sup>1</sup> ଵଵ ൰ (9)

$$Q = \frac{\operatorname{Im}(Y\_{11})}{\operatorname{Re}(Y\_{11})} \tag{8}$$

$$L\_{\rm eff} = \frac{1}{2\pi f} \text{Im}\left(\frac{1}{Y\_{11}}\right) \tag{9}$$

**Figure 3.** Effective inductance and quality factor of on-chip (**a**) uniform and (**b**) tapered spiral inductors (lines: simulation; symbols: model). **Figure 3.** Effective inductance and quality factor of on-chip (**a**) uniform and (**b**) tapered spiral inductors (lines: simulation; symbols: model).

**3. Modeling of Graphene-Based Inductors**  According to Faraday's law of electromagnetic induction, the current change in the metal turns of a spiral inductor produces time-varying magnetic flux. As the magnetic flux is proportional to the inductor area, the decreased size degrades the inductance density, thereby limiting the scaling of RF ICs. Kinetic inductance, which originates in the It is evident that the results obtained by the circuit model agree well with the simulated results. The uniform spiral inductor possesses smaller dc resistance than the tapered one but has larger high-frequency resistance due to skin and proximity effects. The effective inductance of the spiral inductor can be increased by introducing tapering, and therefore, the quality factor can be improved.

#### kinetic energy required by mobile charge carriers in alternative electromotive force, is usually ignored in conventional metals due to their small relaxation time and large con-**3. Modeling of Graphene-Based Inductors**

ducting channel number [5]. However, the momentum relaxation time of graphene is on the order of picoseconds, and therefore, graphene possesses large kinetic inductance, which makes it suitable for building on-chip spiral inductors in future scaled RF ICs. *3.1. GR Impedance*  Figure 4a shows the structure of a multilayer GR interconnect with side contacts [12]. In the figure, and are the width and thickness, is the spacing between adjacent graphene layers, and the number of graphene layers is calculated as = 1 + Inter൫⁄൯, where "Inter(·)" denotes that only the integer part is considered [10]. The corresponding According to Faraday's law of electromagnetic induction, the current change in the metal turns of a spiral inductor produces time-varying magnetic flux. As the magnetic flux is proportional to the inductor area, the decreased size degrades the inductance density, thereby limiting the scaling of RF ICs. Kinetic inductance, which originates in the kinetic energy required by mobile charge carriers in alternative electromotive force, is usually ignored in conventional metals due to their small relaxation time and large conducting channel number [5]. However, the momentum relaxation time of graphene is on the order of picoseconds, and therefore, graphene possesses large kinetic inductance, which makes it suitable for building on-chip spiral inductors in future scaled RF ICs.

equivalent circuit model of a multilayer GR is depicted in Figure 4b. The number of con-

ducting channels per layer of graphene sheet is given as [7]

#### *3.1. GR Impedance*

ୡ୦ = ቆ1 + ாିாಷ

ୀ

Figure 4a shows the structure of a multilayer GR interconnect with side contacts [12]. In the figure, *w<sup>g</sup>* and *t<sup>g</sup>* are the width and thickness, *δ* is the spacing between adjacent graphene layers, and the number of graphene layers is calculated as *n* = 1 + Inter *tg*/*δ* , where "Inter(·)" denotes that only the integer part is considered [10]. The corresponding equivalent circuit model of a multilayer GR is depicted in Figure 4b. The number of conducting channels per layer of graphene sheet is given as [7] *Micromachines* **2022**, *13*, x FOR PEER REVIEW 5 of 12

$$N\_{\rm ch} = \sum\_{i=0}^{n\_{\rm C}} \left( 1 + e^{\frac{\frac{E\_i - E\_F}{k\_B T}}{k\_B T}} \right)^{-1} + \sum\_{i=0}^{n\_V} \left( 1 + e^{\frac{\frac{E\_i - E\_F}{k\_B T}}{k\_B T}} \right)^{-1} \tag{10}$$

where the first and second summations on the right-hand side of (10) represent the contributions of the conduction subbands and valence subbands, respectively, *k<sup>B</sup>* is the Boltzmann constant, *T* is the temperature, *E<sup>F</sup>* is the Fermi energy, and *E<sup>i</sup>* denotes the *i*th conduction (valence) subbands with the lowest (highest) energy. For GR with *w<sup>g</sup>* > 10 nm and *E<sup>F</sup>* > 0.1 eV, *N*ch has a linear relationship with *w<sup>g</sup>* and *EF*, i.e., *N*ch = *αwgEF*, where *α* = 1.2 eV−<sup>1</sup> · nm−<sup>1</sup> is the fitting coefficient [17]. where the first and second summations on the right-hand side of (10) represent the contributions of the conduction subbands and valence subbands, respectively, is the Boltzmann constant, is the temperature, ி is the Fermi energy, and denotes the th conduction (valence) subbands with the lowest (highest) energy. For GR with > 10 nm and ி > 0.1 eV, ୡ୦ has a linear relationship with and ி, i.e., ୡ୦ = ி, where = 1.2 eVିଵ ⋅ nmିଵ is the fitting coefficient [17].

**Figure 4.** (**a**) Schematic of multilayer GR interconnect and its (**b**) equivalent distributed circuit model. **Figure 4.** (**a**) Schematic of multilayer GR interconnect and its (**b**) equivalent distributed circuit model.

The kinetic inductance of a single-layer GR is given by [17] The kinetic inductance of a single-layer GR is given by [17]

 <sup>≈</sup> 8 nH μm <sup>⁄</sup> ୡ୦

9 12 15 18 21 24 27

Width (μm)

0.0

2.0x10<sup>3</sup>

4.0x10<sup>3</sup>

Kinetic inductance (nH/m)

6.0x10<sup>3</sup>

8.0x10<sup>3</sup>

$$L\_K \approx \frac{8 \text{ nH/} \mu \text{m}}{N\_{\text{ch}}} = \frac{8 \text{ nH/} \mu \text{m}}{\alpha w\_{\text{g}} E\_F} \tag{11}$$

 EF=0.2eV EF=0.4eV EF=0.6eV

9 12 15 18 21 24 27

Width (μm)

It is worth noting that graphene tends to graphite as the layer number increases [18]. However, decoupled graphene layers were experimentally demonstrated in [19], and it is expected that a multilayer GR with a certain thickness can be realized in the future. Therefore, the multilayer GR is regarded as a stack of single-layer GRs in this study, and its inductance is calculated as ≈ 8 nH μm ⁄ ⁄൫ி൯. Figure 5 shows the kinetic inductances of single- and multilayer GRs. It is evident that the GR inductance decreases with ி, and single-layer GR exhibits much larger kinetic inductance than multilayer GR. However, the single-layer GR is not suitable for building inductors due to its ultrahigh resistive loss. It is worth noting that graphene tends to graphite as the layer number increases [18]. However, decoupled graphene layers were experimentally demonstrated in [19], and it is expected that a multilayer GR with a certain thickness can be realized in the future. Therefore, the multilayer GR is regarded as a stack of single-layer GRs in this study, and its inductance is calculated as *<sup>L</sup><sup>K</sup>* <sup>≈</sup> <sup>8</sup> nH/µm/ *nαwgE<sup>F</sup>* . Figure 5 shows the kinetic inductances of single- and multilayer GRs. It is evident that the GR inductance decreases with *EF*, and single-layer GR exhibits much larger kinetic inductance than multilayer GR. However, the single-layer GR is not suitable for building inductors due to its ultrahigh resistive loss.

 EF=0.2eV EF=0.4eV EF=0.6eV

**Figure 5.** Kinetic inductances of (**a**) single-layer and (**b**) multilayer GRs.

0

3

6

Kinetic inductance (nH/m)

9

12

15

Side contact

ୡ୦ = ቆ1 + ாିாಷ

MLGRs

tg

 <sup>≈</sup> 8 nH μm <sup>⁄</sup> ୡ୦

n=1+Inter(tg/δ)

δ

model.

loss.

ୀ

ಳ் ቇ

+ ቆ1 + ாିாಷ

ୀ

where = 1.2 eVିଵ ⋅ nmିଵ is the fitting coefficient [17].

wg Lkdx LMdx

(**a**) (**b**)

<sup>=</sup> 8 nH μm <sup>⁄</sup> ி

The kinetic inductance of a single-layer GR is given by [17]

ିଵ ೇ

ಳ் ቇ

where the first and second summations on the right-hand side of (10) represent the contributions of the conduction subbands and valence subbands, respectively, is the Boltzmann constant, is the temperature, ி is the Fermi energy, and denotes the th conduction (valence) subbands with the lowest (highest) energy. For GR with > 10 nm and ி > 0.1 eV, ୡ୦ has a linear relationship with and ி, i.e., ୡ୦ = ி,

Rxdx

**Figure 4.** (**a**) Schematic of multilayer GR interconnect and its (**b**) equivalent distributed circuit

It is worth noting that graphene tends to graphite as the layer number increases [18]. However, decoupled graphene layers were experimentally demonstrated in [19], and it is expected that a multilayer GR with a certain thickness can be realized in the future. Therefore, the multilayer GR is regarded as a stack of single-layer GRs in this study, and its inductance is calculated as ≈ 8 nH μm ⁄ ⁄൫ி൯. Figure 5 shows the kinetic inductances of single- and multilayer GRs. It is evident that the GR inductance decreases with ி, and single-layer GR exhibits much larger kinetic inductance than multilayer GR. However, the single-layer GR is not suitable for building inductors due to its ultrahigh resistive

(10)

CQdx

CEdx

(11)

(12)

ିଵ

**Figure 5.** Kinetic inductances of (**a**) single-layer and (**b**) multilayer GRs. **Figure 5.** Kinetic inductances of (**a**) single-layer and (**b**) multilayer GRs. *Micromachines* **2022**, *13*, x FOR PEER REVIEW 6 of 12

As shown in Figure 6a, the kinetic inductance of multilayer GR is in inverse proportion to the layer number and thereby decreases with increasing thickness. For building an on-chip spiral inductor, the GR length is usually larger than the effective MFP *λ*eff, and therefore, the scattering resistance of GR can be approximated as [17] As shown in Figure 6a, the kinetic inductance of multilayer GR is in inverse proportion to the layer number and thereby decreases with increasing thickness. For building an on-chip spiral inductor, the GR length is usually larger than the effective MFP ୣ, and

$$R\_S \approx \frac{12.9 \text{ k}\Omega}{nN\_{\text{ch}}\lambda\_{\text{eff}}} = \frac{12.9 \text{ k}\Omega}{n\omega w\_{\text{g}}E\_F \lambda\_{\text{eff}}} \tag{12}$$

where *λ*eff is related to various scattering mechanisms, and it has a dominating effect in determining the signal transmission performance [7]. As shown in Figure 6b, the GR resistance decreases with the thickness and Fermi level. To improve the graphene conduction, it is necessary to increase the Fermi level and MFP by appropriate doping techniques [20]. It is worth noting that the fabricated GRs usually cannot come up to theoretical predictions due to manufacturing errors and defects. where ୣ is related to various scattering mechanisms, and it has a dominating effect in determining the signal transmission performance [7]. As shown in Figure 6b, the GR resistance decreases with the thickness and Fermi level. To improve the graphene conduction, it is necessary to increase the Fermi level and MFP by appropriate doping techniques [20]. It is worth noting that the fabricated GRs usually cannot come up to theoretical predictions due to manufacturing errors and defects.

**Figure 6.** (**a**) Kinetic inductances and (**b**) resistance of GR interconnect versus thickness for different Fermi levels. **Figure 6.** (**a**) Kinetic inductances and (**b**) resistance of GR interconnect versus thickness for different Fermi levels.

#### *3.2. Spiral Inductors 3.2. Spiral Inductors*

given by

Although an anomalous skin effect exists in GR due to the large ratio of in-plane to out-plane MFP, it mainly appears as the operating frequency exceeds several tens of gigahertz [13]. Therefore, the anomalous skin effect can be neglected, as it has little influence on the inductor characteristics in the frequency range of interests of this study. Considering the kinetic inductance, the dc inductance of the graphene-based spiral inductor is Although an anomalous skin effect exists in GR due to the large ratio of in-plane to out-plane MFP, it mainly appears as the operating frequency exceeds several tens of gigahertz [13]. Therefore, the anomalous skin effect can be neglected, as it has little influence on the inductor characteristics in the frequency range of interests of this study. Considering the kinetic inductance, the dc inductance of the graphene-based spiral inductor is given by

×

1

$$L\_{\rm dc} = L\_{\rm self} + \sum M\_{+} + \sum M\_{-} + L\_{\rm K,t} \tag{13}$$

The effective width ୣ, is equal to two times the skin depth [5]. The effective con-

Note that the width in both the numerator and denominator cancel out, and the effective conductivity would be irrelevant to the width. Therefore, the conductivity can be treated as a constant for a specific GR line in the modeling of graphene-based inductors. By utilizing the above equations and circuit model shown in Figure 2, the electrical characteristics of graphene-based on-chip spiral inductors can be investigated. The quantum contact resistances are incorporated into the ends of the model, but it has little influence on the inductor performance. The metallic vias in graphene-based inductors could be made of Co [12]. Note that the modeling methodology can also be applied to other spiral inductor structures, such as circular, hexagon, and octagonal types. To verify the model,

൱ × 8 nH μm ⁄ (14)

12.9 kΩ (15)

where ,௧ represents the total kinetic inductance, and it can be calculated by

ୣ <sup>=</sup> <sup>1</sup>

 ୣ,

ே

ୀଵ

ductivity of multilayer GR is given by

ௌ <sup>=</sup> ிୣ 

where *LK*,*<sup>t</sup>* represents the total kinetic inductance, and it can be calculated by

$$L\_{\rm K,t} = \left(\frac{1}{n\alpha E\_F} \sum\_{i=1}^{N} \frac{l\_i}{w\_{\rm eff,i}}\right) \times 8\text{nH/}\mu\text{m} \tag{14}$$

The effective width *w*eff, *<sup>i</sup>* is equal to two times the skin depth [5]. The effective conductivity of multilayer GR is given by

$$
\sigma\_{\rm eff} = \frac{1}{R\_{\rm S}wt} = \frac{m\omega E\_{\rm F} \lambda\_{\rm eff}}{t} \times \frac{1}{12.9 \text{ k}\Omega} \tag{15}
$$

Note that the width in both the numerator and denominator cancel out, and the effective conductivity would be irrelevant to the width. Therefore, the conductivity can be treated as a constant for a specific GR line in the modeling of graphene-based inductors. By utilizing the above equations and circuit model shown in Figure 2, the electrical characteristics of graphene-based on-chip spiral inductors can be investigated. The quantum contact resistances are incorporated into the ends of the model, but it has little influence on the inductor performance. The metallic vias in graphene-based inductors could be made of Co [12]. Note that the modeling methodology can also be applied to other spiral inductor structures, such as circular, hexagon, and octagonal types. To verify the model, the quality factor of the graphene-based spiral inductor is obtained and compared with the experimental results in [5]. The geometrical parameters are as follows: *Dout* = 200 µm, *w* = 25 µm, and *s* = 5 µm. It can be seen from Figure 7 that the modeling results basically agree with the experimental results, and the deviation may be attributed to incorrect geometrical parameters, which will be investigated in the next study. *Micromachines* **2022**, *13*, x FOR PEER REVIEW 7 of 12 the quality factor of the graphene-based spiral inductor is obtained and compared with the experimental results in [5]. The geometrical parameters are as follows: ௨௧ = 200 μm, = 25 μm, and = 5 μm. It can be seen from Figure 7 that the modeling results basically agree with the experimental results, and the deviation may be attributed to incorrect geometrical parameters, which will be investigated in the next study.

**Figure 7.** Quality factors of Cu- and graphene-based inductors. **Figure 7.** Quality factors of Cu- and graphene-based inductors.

#### **4. Results and Discussion 4. Results and Discussion**

0.0 0.4 0.8 1.2 1.6

Thickness (μm)

Line: Copper taper = 2μm/turn

0 10 20 % increase

0.6

0.8

1.0

1.2

Inductance (nH)

1.4

Symbol: Graphene

1.6

For graphene-based on-chip spiral inductors, the inductance mainly comes from the magnetic inductance and the kinetic inductance, which originates in the kinetic energy required by mobile electrons, and its value depends on the number of conduction channels. In order to characterize the influence of kinetic inductance, the inductances of copper and graphene-based on-chip spiral inductors made of copper and graphene are plotted in Figure 8. It is evident that graphene becomes superior to copper for building on-chip inductors with a decreasing geometric size (e.g., thickness and width), implying that graphene is more suitable for the applications of future scaled RF ICs. Moreover, as shown in Figure 8b, the advantage of a graphene-based inductor over its copper counterpart can be strengthened by increasing . This is mainly because the inner ring of a graphenebased tapered spiral inductor could provide larger kinetic inductance due to its smaller width than that of a uniform inductor. For graphene-based on-chip spiral inductors, the inductance mainly comes from the magnetic inductance and the kinetic inductance, which originates in the kinetic energy required by mobile electrons, and its value depends on the number of conduction channels. In order to characterize the influence of kinetic inductance, the inductances of copper and graphene-based on-chip spiral inductors made of copper and graphene are plotted in Figure 8. It is evident that graphene becomes superior to copper for building on-chip inductors with a decreasing geometric size (e.g., thickness and width), implying that graphene is more suitable for the applications of future scaled RF ICs. Moreover, as shown in Figure 8b, the advantage of a graphene-based inductor over its copper counterpart can be strengthened by increasing *taper*. This is mainly because the inner ring of a graphene-based tapered spiral inductor could provide larger kinetic inductance due to its smaller width than that of a uniform inductor.

0.0 0.4 0.8 1.2 1.6

0 10 20 % Increase

Thickness (μm)

w1=3μm, s1=2μm

0.0 0.4 0.8 1.2 1.6

Thickness (μm)

taper=2μm/turn

taper=0μm/turn

(**a**) (**b**)

0.8

**Figure 8.** Inductance versus thickness for copper and graphene-based on-chip spiral inductors with different (**a**) width, spacing, and (**b**) taper. The inset plots the percentage increase in inductance of

In general, graphene doping can increase the Fermi level and thereby decrease the resistive loss. Moreover, the coupling effect between adjacent graphene layers can be alleviated and finally cancelled by intercalation doping. Therefore, alternate dopants such as AsF5, Br2, FeCl3, and KI are continually being investigated [21,22]. Among these dopants, Br is easy to diffuse into graphene layers, and its doping process is relatively simple

1.0

1.2

Inductance (nH)

1.4 Line: Copper Symbol: Graphene

w1=3μm, s1=2μm

0.0 0.5 1.0 1.5

Thickness (μm)

w1=5μm, s1=5μm w1=4μm, s1=3μm

graphene inductor to copper inductor.

the quality factor of the graphene-based spiral inductor is obtained and compared with the experimental results in [5]. The geometrical parameters are as follows: ௨௧ = 200 μm, = 25 μm, and = 5 μm. It can be seen from Figure 7 that the modeling results basically agree with the experimental results, and the deviation may be attributed to incorrect geo-

For graphene-based on-chip spiral inductors, the inductance mainly comes from the magnetic inductance and the kinetic inductance, which originates in the kinetic energy required by mobile electrons, and its value depends on the number of conduction channels. In order to characterize the influence of kinetic inductance, the inductances of copper and graphene-based on-chip spiral inductors made of copper and graphene are plotted in Figure 8. It is evident that graphene becomes superior to copper for building on-chip inductors with a decreasing geometric size (e.g., thickness and width), implying that graphene is more suitable for the applications of future scaled RF ICs. Moreover, as shown in Figure 8b, the advantage of a graphene-based inductor over its copper counterpart can be strengthened by increasing . This is mainly because the inner ring of a graphenebased tapered spiral inductor could provide larger kinetic inductance due to its smaller

metrical parameters, which will be investigated in the next study.

Graphene

**Figure 7.** Quality factors of Cu- and graphene-based inductors.

 [5] Simulation

0 10 20 30 40 50 60

Copper

Frequency (GHz)

width than that of a uniform inductor.

**4. Results and Discussion** 

Quality factor

**Figure 8.** Inductance versus thickness for copper and graphene-based on-chip spiral inductors with different (**a**) width, spacing, and (**b**) taper. The inset plots the percentage increase in inductance of graphene inductor to copper inductor. **Figure 8.** Inductance versus thickness for copper and graphene-based on-chip spiral inductors with different (**a**) width, spacing, and (**b**) taper. The inset plots the percentage increase in inductance of graphene inductor to copper inductor.

In general, graphene doping can increase the Fermi level and thereby decrease the resistive loss. Moreover, the coupling effect between adjacent graphene layers can be alleviated and finally cancelled by intercalation doping. Therefore, alternate dopants such as AsF5, Br2, FeCl3, and KI are continually being investigated [21,22]. Among these dopants, Br is easy to diffuse into graphene layers, and its doping process is relatively simple In general, graphene doping can increase the Fermi level and thereby decrease the resistive loss. Moreover, the coupling effect between adjacent graphene layers can be alleviated and finally cancelled by intercalation doping. Therefore, alternate dopants such as AsF5, Br2, FeCl3, and KI are continually being investigated [21,22]. Among these dopants, Br is easy to diffuse into graphene layers, and its doping process is relatively simple and efficient. The average thickness increment of Br-doped multilayer graphene is about 6.7% of the original thickness [5], i.e., the average layer spacing between adjacent graphene layers is about 0.3628 nm. As doping is a process of charge transfer, the carrier density and conductivity vary with the doping time. As the doping time exceeds 70 min, the resistivity of Br2-doped graphene becomes lower than that of bulk copper, and the Fermi level reaches 0.5 eV [23]. Here, two cases of Br2-doped graphene are considered, i.e., the conductivities are set as 5 <sup>×</sup> <sup>10</sup><sup>7</sup> S/m and 10<sup>8</sup> S/m, respectively.

By virtue of the circuit model in Figure 2, the effective inductance and quality factor of on-chip tapered spiral inductors made of copper and Br2-doped graphene are plotted in Figure 9. It is evident that the effective inductance can be improved by replacing copper with graphene. For graphene with a conductivity of 5 <sup>×</sup> <sup>10</sup><sup>7</sup> S/m, the quality factor of a graphene-based spiral inductor is slightly lower than that of its copper counterpart. However, as the graphene conductivity exceeds 10<sup>8</sup> S/m, the quality factor can be significantly improved due to the reduction of metal resistive loss. Figure 10 shows the effective inductance and quality factor of an on-chip spiral inductor with different values of *taper*. It can be seen from Figure 10a that the effective inductance can be increased by increasing *taper*. However, as the inductor characteristics are affected by various factors, such as substrate loss, the quality factor of a tapered spiral inductor is slightly larger than that of a uniform one. Further, the frequency-dependent impedances and scattering parameters of copper and graphene-based on-chip uniform spiral inductors are plotted in Figure 11. It is evident that GR could provide smaller resistance and a slightly larger inductance than its copper counterpart, but their scattering parameters are comparable due to other influences, such as the substrate loss effect.

ences, such as the substrate loss effect.

ences, such as the substrate loss effect.

**Figure 9.** (**a**) Effective inductance and (**b**) quality factors of on-chip tapered spiral inductors made of copper and graphene. **Figure 9.** (**a**) Effective inductance and (**b**) quality factors of on-chip tapered spiral inductors made of copper and graphene. **Figure 9.** (**a**) Effective inductance and (**b**) quality factors of on-chip tapered spiral inductors made of copper and graphene.

and efficient. The average thickness increment of Br-doped multilayer graphene is about 6.7% of the original thickness [5], i.e., the average layer spacing between adjacent graphene layers is about 0.3628 nm. As doping is a process of charge transfer, the carrier density and conductivity vary with the doping time. As the doping time exceeds 70 min, the resistivity of Br2-doped graphene becomes lower than that of bulk copper, and the Fermi level reaches 0.5 eV [23]. Here, two cases of Br2-doped graphene are considered, i.e.,

and efficient. The average thickness increment of Br-doped multilayer graphene is about 6.7% of the original thickness [5], i.e., the average layer spacing between adjacent graphene layers is about 0.3628 nm. As doping is a process of charge transfer, the carrier density and conductivity vary with the doping time. As the doping time exceeds 70 min, the resistivity of Br2-doped graphene becomes lower than that of bulk copper, and the Fermi level reaches 0.5 eV [23]. Here, two cases of Br2-doped graphene are considered, i.e.,

By virtue of the circuit model in Figure 2, the effective inductance and quality factor of on-chip tapered spiral inductors made of copper and Br2-doped graphene are plotted in Figure 9. It is evident that the effective inductance can be improved by replacing copper with graphene. For graphene with a conductivity of 5 × 107 S/m, the quality factor of a graphene-based spiral inductor is slightly lower than that of its copper counterpart. However, as the graphene conductivity exceeds 108 S/m, the quality factor can be significantly improved due to the reduction of metal resistive loss. Figure 10 shows the effective inductance and quality factor of an on-chip spiral inductor with different values of . It can be seen from Figure 10a that the effective inductance can be increased by increasing . However, as the inductor characteristics are affected by various factors, such as substrate loss, the quality factor of a tapered spiral inductor is slightly larger than that of a uniform one. Further, the frequency-dependent impedances and scattering parameters of copper and graphene-based on-chip uniform spiral inductors are plotted in Figure 11. It is evident that GR could provide smaller resistance and a slightly larger inductance than its copper counterpart, but their scattering parameters are comparable due to other influ-

By virtue of the circuit model in Figure 2, the effective inductance and quality factor of on-chip tapered spiral inductors made of copper and Br2-doped graphene are plotted in Figure 9. It is evident that the effective inductance can be improved by replacing copper with graphene. For graphene with a conductivity of 5 × 107 S/m, the quality factor of a graphene-based spiral inductor is slightly lower than that of its copper counterpart. However, as the graphene conductivity exceeds 108 S/m, the quality factor can be significantly improved due to the reduction of metal resistive loss. Figure 10 shows the effective inductance and quality factor of an on-chip spiral inductor with different values of . It can be seen from Figure 10a that the effective inductance can be increased by increasing . However, as the inductor characteristics are affected by various factors, such as substrate loss, the quality factor of a tapered spiral inductor is slightly larger than that of a uniform one. Further, the frequency-dependent impedances and scattering parameters of copper and graphene-based on-chip uniform spiral inductors are plotted in Figure 11. It is evident that GR could provide smaller resistance and a slightly larger inductance than its copper counterpart, but their scattering parameters are comparable due to other influ-

the conductivities are set as 5 × 107 S/m and 108 S/m, respectively.

the conductivities are set as 5 × 107 S/m and 108 S/m, respectively.

*Micromachines* **2022**, *13*, x FOR PEER REVIEW 8 of 12

**Figure 10.** (**a**) Effective inductance and (**b**) quality factor of on-chip uniform and tapered spiral inductors. **Figure 10.** (**a**) Effective inductance and (**b**) quality factor of on-chip uniform and tapered spiral inductors.

**Figure 11.** (**a**) Impedances (the model in the dashed box of Figure 2 and (**b**) scattering parameters of on-chip uniform spiral inductors. **Figure 11.** (**a**) Impedances (the model in the dashed box of Figure 2 and (**b**) scattering parameters of on-chip uniform spiral inductors.

Further, the parametric study of graphene-based on-chip spiral tapered inductors was conducted. The influence of thickness on the inductor characteristics is shown in Figure 12a. With the increasing thickness, the effective inductance decreases, while the quality factor increases significantly due to the reduction of metal resistive loss. As shown in Further, the parametric study of graphene-based on-chip spiral tapered inductors was conducted. The influence of thickness on the inductor characteristics is shown in Figure 12a. With the increasing thickness, the effective inductance decreases, while the quality factor increases significantly due to the reduction of metal resistive loss. As shown in Figure 12b,

Figure 12b, the increase in turn number increases the effective inductance and decreases the quality factor. Similarly, as shown in Figure 12c, the increasing outermost diameter

[24]. The larger the outermost diameter, the higher the eddy current loss. Thus, due to the increase in both effective inductance and eddy current loss, the maximum quality factor is slightly changed with the outermost diameter. Moreover, the self-resonant frequency decreases dramatically with the increasing outermost diameter. Figure 12d shows the characteristics of graphene-based inductors with different widths and spacings. With a decreasing width, the magnetic inductance increases, and the resistive loss is reduced due to the suppressed proximity effect, thereby increasing the maximum quality factor. The influence of oxide layer thickness on the quality factor of a graphene-based on-chip spiral inductor is explored, as shown in Figure 13a. The thicker the oxide layer is, the greater the quality factor is. The self-resonant frequency increases with the increasing oxide layer thickness. Moreover, as shown in Figure 13b, the quality factor increases with the decreasing substrate conductivity due to the reduced substrate loss. By virtue of the circuit model, some guidance is given for the design and fabrication of graphene-based inductors, which is anticipated to be validated in a future experimental study. It is worth noting that although the simulation could give insight into the device's operation, real-world implementation is inevitable, as the simulation might be too idealistic. Moreover, much effort should be spent in all fields related to the fabrication of graphene-based inductors, including gra-

phene growth and doping.

the increase in turn number increases the effective inductance and decreases the quality factor. Similarly, as shown in Figure 12c, the increasing outermost diameter increases the effective inductance. However, the magnetic field penetrating the inductor coil generates current in the substrate, thereby leading to an increase in eddy current loss [24]. The larger the outermost diameter, the higher the eddy current loss. Thus, due to the increase in both effective inductance and eddy current loss, the maximum quality factor is slightly changed with the outermost diameter. Moreover, the self-resonant frequency decreases dramatically with the increasing outermost diameter. Figure 12d shows the characteristics of graphene-based inductors with different widths and spacings. With a decreasing width, the magnetic inductance increases, and the resistive loss is reduced due to the suppressed proximity effect, thereby increasing the maximum quality factor. The influence of oxide layer thickness on the quality factor of a graphene-based on-chip spiral inductor is explored, as shown in Figure 13a. The thicker the oxide layer is, the greater the quality factor is. The self-resonant frequency increases with the increasing oxide layer thickness. Moreover, as shown in Figure 13b, the quality factor increases with the decreasing substrate conductivity due to the reduced substrate loss. By virtue of the circuit model, some guidance is given for the design and fabrication of graphene-based inductors, which is anticipated to be validated in a future experimental study. It is worth noting that although the simulation could give insight into the device's operation, real-world implementation is inevitable, as the simulation might be too idealistic. Moreover, much effort should be spent in all fields related to the fabrication of graphene-based inductors, including graphene growth and doping. *Micromachines* **2022**, *13*, x FOR PEER REVIEW 10 of 12

**Figure 12.** Effective inductance and quality factor of graphene-based on-chip tapered spiral inductors with different (**a**) thicknesses, (**b**) turn numbers, (**c**) outermost diameter, (**d**) width and spacing. **Figure 12.** Effective inductance and quality factor of graphene-based on-chip tapered spiral inductors with different (**a**) thicknesses, (**b**) turn numbers, (**c**) outermost diameter, (**d**) width and spacing.

**Figure 13.** Quality factor of graphene-based on-chip tapered spiral inductors with different (**a**) oxide

In summary, the graphene-based on-chip square spiral inductors are investigated by virtue of the circuit model. Although graphene possesses large kinetic inductance, its advantage over copper becomes significant only when the inductor dimensions are smaller than a certain value. This is, the area of the nanoscale inductor can be reduced by replacing copper with GR. On the other hand, the conductivity can be increased by employing doping techniques, thereby improving the inductor quality factor. However, the simulation is realistic, and much effort should be devoted to the fabrication of high-quality GRs.

0 5 10 15 20

σsub=10 S/m σsub=5 S/m σsub=1 S/m

Frequency (GHz)

(**a**) (**b**)

layer thicknesses and (**b**) substrate conductivities.

0

10

20

Quality factor

30

 tox=10μm tox=8μm tox=6μm

0 5 10 15 20

Frequency (GHz)

0

5

10

Quality factor

15

20

2

0

5

10

Effective inductance (nH)

15

20

3

4

Effective inductance (nH)

5

(**c**) (**d**)

**Figure 13.** Quality factor of graphene-based on-chip tapered spiral inductors with different (**a**) oxide layer thicknesses and (**b**) substrate conductivities. **Figure 13.** Quality factor of graphene-based on-chip tapered spiral inductors with different (**a**) oxide layer thicknesses and (**b**) substrate conductivities.

In summary, the graphene-based on-chip square spiral inductors are investigated by virtue of the circuit model. Although graphene possesses large kinetic inductance, its advantage over copper becomes significant only when the inductor dimensions are smaller than a certain value. This is, the area of the nanoscale inductor can be reduced by replacing copper with GR. On the other hand, the conductivity can be increased by employing doping techniques, thereby improving the inductor quality factor. However, the simulation is realistic, and much effort should be devoted to the fabrication of high-quality GRs. In summary, the graphene-based on-chip square spiral inductors are investigated by virtue of the circuit model. Although graphene possesses large kinetic inductance, its advantage over copper becomes significant only when the inductor dimensions are smaller than a certain value. This is, the area of the nanoscale inductor can be reduced by replacing copper with GR. On the other hand, the conductivity can be increased by employing doping techniques, thereby improving the inductor quality factor. However, the simulation is realistic, and much effort should be devoted to the fabrication of high-quality GRs.

#### **5. Conclusions**

0 5 10 15

Frequency (GHz)

0 5 10 15

Frequency (GHz)

 tm=1 μm tm=2 μm tm=3 μm

0

0

5

10

Quality factor

15

20

 D=200μm D=275μm D=350μm

(**a**) (**b**)

0

2

3

4

Effective inductance (nH)

2

4

Effective inductance (nH)

0 5 10 15

Frequency (GHz)

 w1=15μm,s1=5μm w1=17μm,s1=3μm

5 w1=13μm,s1=7μ<sup>m</sup>

0 5 10 15

Frequency (GHz)

**Figure 12.** Effective inductance and quality factor of graphene-based on-chip tapered spiral inductors with different (**a**) thicknesses, (**b**) turn numbers, (**c**) outermost diameter, (**d**) width and spacing.

<sup>6</sup> 2 turns

 3 turns 4 turns

0

0

5

10

Quality factor

15

20

5

10

Quality factor

15

10

Quality factor

20

30

In this paper, the ultimate electrical performance of graphene-based spiral inductors was investigated theoretically. The equivalent circuit model of a traditional on-chip spiral inductor was developed and verified. The graphene kinetic inductance was combined into the model, and the electrical characteristics of on-chip spiral inductors made of copper and graphene were captured and compared. In the modeling procedure, it was found that the quantum contact resistance has little influence on the inductor performance. Graphene could be superior to its copper counterpart for building inductors when the geometry is very small, indicating that graphene is more suitable for future nanoscale RFICs. Moreover, a tapered spiral inductor could better play the advantage of graphene than a uniform one, as the inner ring has larger kinetic inductance. Although graphene possesses high kinetic inductance, the quality factor of the graphene-based inductor may be limited by its resistive loss, and therefore, the intercalation doping technique should be pursued. By virtue of the circuit model, the influences of geometrical parameters on the performance of graphene-based on-chip spiral inductors were finally explored, with several design guidelines provided.

**Author Contributions:** Conceptualization, W.-S.Z.; methodology, D.-W.W., writing—original draft preparation, M.-J.Y.; writing—review and editing, J.-Y.D. and W.-S.Z. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by the Natural Science Foundation of China (NSFC) under Grants 62222401 and 61874038 and by the Zhejiang Provincial Natural Science Foundation under Grants LXR22F040001 and LD22F040003.

**Data Availability Statement:** Not applicable.

**Conflicts of Interest:** The authors declare no conflict of interest.

## **References**

