**4. Experimental Results**

Figure 7 shows the complete assembly of a single-phase SAPF. VSI was developed using four IGBT switches with protection and control circuits from Mitsubishi Intelligent Power Modules (IPMs). A diode bridge rectifier with a series resistor and an inductor was also included. Load variation was achieved by connecting and disconnecting parallel loads. A current transformer (CT) detected the supply, load, and filter currents, whereas an LEM voltage transducer (LV25-P) detected the DC-link capacitor voltage and source voltage. The signal sensing and conditioning circuit are shown in Figure 8. A signal conditioning circuit feds the detected signals to the FPGA board's A/D converters. The single-phase SAPF was controlled in the digital platform based on Cyclone-IV EP4CE30F484 FPGA of the altera controller (Intel, Santa Clara, CA, USA), which is shown in Figure 9. *Energies* **2022**, *15*, 4531 10 of 17 loads. A current transformer (CT) detected the supply, load, and filter currents, whereas an LEM voltage transducer (LV25-P) detected the DC-link capacitor voltage and source voltage. The signal sensing and conditioning circuit are shown in Figure 8. A signal conditioning circuit feds the detected signals to the FPGA board's A/D converters. The singlephase SAPF was controlled in the digital platform based on Cyclone-IV EP4CE30F484 FPGA of the altera controller (Intel, Santa Clara, CA, USA), which is shown in Figure 9. *Energies* **2022**, *15*, 4531 10 of 17 loads. A current transformer (CT) detected the supply, load, and filter currents, whereas an LEM voltage transducer (LV25-P) detected the DC-link capacitor voltage and source voltage. The signal sensing and conditioning circuit are shown in Figure 8. A signal conditioning circuit feds the detected signals to the FPGA board's A/D converters. The singlephase SAPF was controlled in the digital platform based on Cyclone-IV EP4CE30F484 FPGA of the altera controller (Intel, Santa Clara, CA, USA), which is shown in Figure 9.

**Figure 7.** Complete assembly of single-phase SAPF. **Figure 7.** Complete assembly of single-phase SAPF. **Figure 7.** Complete assembly of single-phase SAPF.

**Figure 8.** Signal sensing and conditioning circuit. **Figure 8.** Signal sensing and conditioning circuit. **Figure 8.** Signal sensing and conditioning circuit.

The design is done using Quartus II 15.0 software. The digital platform consisted of an FPGA and EPCS16 PROM devices, USB blaster, 4-channel 12-bit SPI bipolar ADC, 4-channel 12-bit SPI bipolar DAC, LCD, and on-board isolated RS232. Flash memory EPCS16 was used to configure the FPGA by connecting personal computers through a USB blaster. The VHDL code for the control of SAPF was verified, analyzed, and synthesized in the Quartus II 15.0 software platform. The JAM file was downloaded to the PROM device, which was used to configure the controller and experimental setup. The voltage and current signals were sampled using the ADC controller. Then, the controller read the signal from the ADC and generated the firing pulses to the SAPF.

The design is done using Quartus II 15.0 software. The digital platform consisted of an FPGA and EPCS16 PROM devices, USB blaster, 4-channel 12-bit SPI bipolar ADC, 4-

The design is done using Quartus II 15.0 software. The digital platform consisted of an FPGA and EPCS16 PROM devices, USB blaster, 4-channel 12-bit SPI bipolar ADC, 4-

**Figure 9.** Cyclone-IV EP4CE30F484 FPGA controller.

**Figure 8.** Signal sensing and conditioning circuit.

*Energies* **2022**, *15*, 4531 11 of 17

**Figure 7.** Complete assembly of single-phase SAPF.

**Figure 9.** Cyclone-IV EP4CE30F484 FPGA controller. **Figure 9.** Cyclone-IV EP4CE30F484 FPGA controller. pacitor voltage was set at 200 V, while the root mean square and also the grid frequency

The design is done using Quartus II 15.0 software. The digital platform consisted of an FPGA and EPCS16 PROM devices, USB blaster, 4-channel 12-bit SPI bipolar ADC, 4- The SAPF system settings were unchanged from the simulated test. The DC-link capacitor voltage was set at 200 V, while the root mean square and also the grid frequency remained at 100 V and 50 Hz, respectively. The sampling time for the proposed control scheme was 10 µs, which was suitable for high-speed FPGA processing. The suggested control technique's steady-state and switch-on responses were evaluated to ensure its practicality. The waveforms are shown in Figure 10a,b is the source voltage and the source current. Where the source current is not compensated. The supply current THD was found to be 24.9% before SAPF is connected to the PCC. It clearly showed the high harmonics of the supplying current waveform. During compensation, the supply current became harmonic-free, and the supply THD reduced from 24.9 to 3.7%. All of these waveforms were obtained using an Agilent DSO-X 3014A digital oscilloscope. Figure 10c–f illustrates the switch-on response and steady-state performance of SAPF. The harmonic current in the NLL was compensated by the operation of SAPF, so that the source current was sine in nature. The measure source current, SAPF current, and DC-link voltage are presented in Figure 10d–f, where the harmonics generated by the NLL are almost eliminated by the SAPF. The measured source voltage, filter current, and source current during switch-off conditions are exposed in Figure 10g. Figure 10h shows the PLL output. The test results show the ability to track the reference current very well and achieved source current in sinusoidal waveform with a power factor value of one. In the test, the switching frequency was nearly 15 kHz when not including the weighting factor in the cost function. scheme was 10 μs, which was suitable for high-speed FPGA processing. The suggested control technique's steady-state and switch-on responses were evaluated to ensure its practicality. The waveforms are shown in Figure 10a,b is the source voltage and the source current. Where the source current is not compensated. The supply current THD was found to be 24.9% before SAPF is connected to the PCC. It clearly showed the high harmonics of the supplying current waveform. During compensation, the supply current became harmonic-free, and the supply THD reduced from 24.9 to 3.7%. All of these waveforms were obtained using an Agilent DSO-X 3014A digital oscilloscope. Figures 10c–f illustrates the switch-on response and steady-state performance of SAPF. The harmonic current in the NLL was compensated by the operation of SAPF, so that the source current was sine in nature. The measure source current, SAPF current, and DC-link voltage are presented in Figures 10d–f, where the harmonics generated by the NLL are almost eliminated by the SAPF. The measured source voltage, filter current, and source current during switch-off conditions are exposed in Figure 10g. Figure 10h shows the PLL output. The test results show the ability to track the reference current very well and achieved source current in sinusoidal waveform with a power factor value of one. In the test, the switching frequency was nearly 15 kHz when not including the weighting factor in the cost function.

remained at 100 V and 50 Hz, respectively. The sampling time for the proposed control

loads. A current transformer (CT) detected the supply, load, and filter currents, whereas an LEM voltage transducer (LV25-P) detected the DC-link capacitor voltage and source voltage. The signal sensing and conditioning circuit are shown in Figure 8. A signal conditioning circuit feds the detected signals to the FPGA board's A/D converters. The singlephase SAPF was controlled in the digital platform based on Cyclone-IV EP4CE30F484 FPGA of the altera controller (Intel, Santa Clara, CA, USA), which is shown in Figure 9.

(**b**)

**Figure 10.** *Cont*.

channel 12-bit SPI bipolar DAC, LCD, and on-board isolated RS232. Flash memory EPCS16 was used to configure the FPGA by connecting personal computers through a USB blaster. The VHDL code for the control of SAPF was verified, analyzed, and synthesized in the Quartus II 15.0 software platform. The JAM file was downloaded to the PROM device, which was used to configure the controller and experimental setup. The voltage and current signals were sampled using the ADC controller. Then, the controller read the

The SAPF system settings were unchanged from the simulated test. The DC-link capacitor voltage was set at 200 V, while the root mean square and also the grid frequency remained at 100 V and 50 Hz, respectively. The sampling time for the proposed control scheme was 10 μs, which was suitable for high-speed FPGA processing. The suggested control technique's steady-state and switch-on responses were evaluated to ensure its practicality. The waveforms are shown in Figure 10a,b is the source voltage and the source current. Where the source current is not compensated. The supply current THD was found to be 24.9% before SAPF is connected to the PCC. It clearly showed the high harmonics of the supplying current waveform. During compensation, the supply current became harmonic-free, and the supply THD reduced from 24.9 to 3.7%. All of these waveforms were obtained using an Agilent DSO-X 3014A digital oscilloscope. Figures 10c–f illustrates the switch-on response and steady-state performance of SAPF. The harmonic current in the NLL was compensated by the operation of SAPF, so that the source current was sine in nature. The measure source current, SAPF current, and DC-link voltage are presented in Figures 10d–f, where the harmonics generated by the NLL are almost eliminated by the SAPF. The measured source voltage, filter current, and source current during switch-off conditions are exposed in Figure 10g. Figure 10h shows the PLL output. The test results show the ability to track the reference current very well and achieved source current in sinusoidal waveform with a power factor value of one. In the test, the switching frequency

was nearly 15 kHz when not including the weighting factor in the cost function.

signal from the ADC and generated the firing pulses to the SAPF.

**Figure 10.** *Cont*.

(**e**)

(**c**)

(**d**

)

**Figure 10.** *Cont*.

(**h**)

(**i**)

(**f**)

(**f**)

*Energies* **2022**, *15*, 4531 13 of 17

(**g**)

**Figure 10.** Experimental results of proposed SAPF (**a**) source voltage and current, load current, filter current (before compensation). (**b**) Source current and voltage. (**c**) Source voltage, source current, and filter current (switch-on condition). (**d**) Filter current, source voltage, and current. (**e**) Source current, filter current, and DC-link voltage. (**f**) Source current, filter current, and DC-link voltage. (**g**) Source voltage and current, filter current (switch-off condition). (**h**) PLL output. (**i**) Gating signals.

As shown in Figure 11a–d, the weighting factor is changed from 0 to 0.1, according to the change in the source current THD from 3.7 to 4.8%, and the switching frequency of VSI for the proposed control method decreases from 15.2 to 13.4 kHz in comparison to the conventional MPCC. Table 3 provides a comparison of the THD of the source current and switching frequency for the four dissimilar weighting factor values. Additionally, the comparison between various current controllers in the simulation and hardware based on source current THD is summarized in Table 4. As compared with hysteresis, predictive PWM, and conventional MPCC control methods, the cost function-based MPCC algorithm provides a lower switching frequency with an optimal source current THD value.

nals.

**Figure 10.** Experimental results of proposed SAPF (**a**) source voltage and current, load current, filter current (before compensation). (**b**) Source current and voltage. (**c**) Source voltage, source current, and filter current (switch-on condition). (**d**) Filter current, source voltage, and current. (**e**) Source current, filter current, and DC-link voltage. (**f**) Source current, filter current, and DC-link voltage. (**g**) Source voltage and current, filter current (switch-off condition). (**h**) PLL output. (**i**) Gating sig-

As shown in Figure 11a–d, the weighting factor is changed from 0 to 0.1, according to the change in the source current THD from 3.7 to 4.8%, and the switching frequency of VSI for the proposed control method decreases from 15.2 to 13.4 kHz in comparison to the conventional MPCC. Table 3 provides a comparison of the THD of the source current and switching frequency for the four dissimilar weighting factor values. Additionally, the comparison between various current controllers in the simulation and hardware based on source current THD is summarized in Table 4. As compared with hysteresis, predictive PWM, and conventional MPCC control methods, the cost function-based MPCC algorithm provides a lower switching frequency with an optimal source current THD value.

**Figure 11.** *Cont*.

**Before Compensation**

**Before Compensation**

mental study.

**Source Current THD (%) (RL Load)** 

**Switching Frequency (Fsw) in kHz**

0, (**c**) source current λ = 0.05, (**d**) source current λ = 0.1.

**Hysteresis Controller** 

**Hysteresis Controller** 

single-phase SAPF, including THD and switching frequency.

**Simulation Results** 28.47 3.82 4.5 3.53 4.20 4.66 **Hardware Results** 24.9 3.76 4.21 3.7 4.6 4.8

**Simulation Results** 0 15.27 15 15.071 14.208 12.866 **Hardware Results** 0 15.13 15 15.200 14.600 13.400

(**d**)

**Predictive PWM Controller** 

**Predictive PWM Controller** 

• The NLL's current harmonics and reactive power were efficiently adjusted. • The supply current took on a sine wave and aligned with the supply voltage.

As presented above the following conclusions have been ended from the experi-

**Figure 11.** Experimental outcomes: (**a**) source current (before compensation), (**b**) source current λ =

**Table 4.** Summary of the simulation and practical test results for weighting factor-based MPCC of

**After Compensation** 

**(Weighting Factor-based MPCC) 0 0.05 0.1**

**After Compensation (Weighting Factor-based MPCC) 0 0.05 0.1**

(**c**)

**Figure 11.** Experimental outcomes: (**a**) source current (before compensation), (**b**) source current λ = 0, (**c**) source current λ = 0.05, (**d**) source current λ = 0.1. **Figure 11.** Experimental outcomes: (**a**) source current (before compensation), (**b**) source current λ = 0, (**c**) source current λ = 0.05, (**d**) source current λ = 0.1.

**Table 4.** Summary of the simulation and practical test results for weighting factor-based MPCC of single-phase SAPF, including THD and switching frequency. **Table 4.** Summary of the simulation and practical test results for weighting factor-based MPCC of single-phase SAPF, including THD and switching frequency.


As presented above the following conclusions have been ended from the experimental study. As presented above the following conclusions have been ended from the experimental study.


## **5. Conclusions**

In this manuscript, a cost function-based MPCC was presented for reducing the switching frequency. The outcomes illustrate that the proposed system archives an excellent

trade-off among the VSI switching frequency and harmonics performance. A comparison study indicates that the proposed technique achieves a reduced switching frequency of 13.4 kHz, and also decreases the THD of the supply current well below 5% within the IEEE 519-2014 limit. In addition, the simulation and experiment results show the effectiveness of the proposed method. The suggested approach is easy to calculate, and the simulation and experimental results show that it performs well in terms of dynamic features, operational efficiency, and output power quality. This approach is applicable to all types of converters for which power quality is a primary concern.

**Author Contributions:** Conceptualization, V.I.; Formal analysis, S.R.; Funding acquisition, B.A.; Investigation, K.R.; Methodology, K.R.; Project administration, V.I.; Resources, B.A.; Writing—review & editing, S.R. All authors have read and agreed to the published version of the manuscript.

**Funding:** This work was funded by under the Research Groups Funding program grant code (NU/RG/SERC/11/6).

**Acknowledgments:** The authors are thankful to the Deanship of Scientific Research at Najran University for funding this work under the Research Groups Funding program grant code (NU/RG/SERC/11/6).

**Conflicts of Interest:** The authors declare no conflict of interest.

## **References**

