*2.2. Diode Equations*

As follows from (2), relations I–V for diodes are required to evaluate ˆ **J** (*l*) and **r**ˆ (*l*). While diodes play a crucial role in the RF–DC converters, their inherent nonlinearity renders circuit analysis considerably more complex. As in the present study, a sub-GHz range is concerned, the choice of diode model becomes even more critical with regard to the PCE estimation reliability. This is due to a number of effects that may be neglected at low frequencies, while they start to manifest themselves at high frequencies dramatically affecting the overall efficiency of the power conversion.

In the proposed approach, the standard SPICE model was selected to describe the behavior of the Schottky diodes. The model has the following advantages: ease of implementation, high stability when used in conjunction with 2F-HB, as well as accurate modeling of breakdown current and junction capacitance. The parameters of the SPICE model used in the theoretical analysis of voltage doubler PCE are taken from the datasheet for the SMS7630 Schottky diode [68]. The main part of the diode equivalent circuit (DEC) is shown in Figure 4. Throughout the paper, the voltage across the junction of the *m*-th diode is denoted as *vm*.

**Figure 4.** Low frequency diode SPICE model.

As indicated in Figure 4, the current flowing through the diode is comprised of two components: the junction current and the current determined by the junction capacitance. The former depends non-linearly on the voltage across it, and in the framework of the SPICE model it can be calculated as:

$$i\_{\rm d,m} = i\_{\rm s} \left( \mathbf{e}^{v\_{\rm m}/(Nv\_{\rm t})} - 1 \right) - i\_{\rm bv} \mathbf{e}^{-\frac{v\_{\rm tr} + v\_{\rm br}}{N\_{\rm br} \cdot \rm tr}},\tag{4}$$

where *<sup>i</sup>*d,*m* denotes the junction current of the *m*-th diode, *i*s—the saturation current, *<sup>v</sup>*t—the thermal voltage of the diode junction, *N*—the ideality factor, *v*bv denotes the breakdown voltage, and *N*bv and *i*bv, are the ideality factor and the knee current of the breakdown current, respectively.

The contribution of the non-linear diode capacitance to the total diode current plays an important role in the behavior of diodes at high frequencies, therefore, it has to be considered as well. The total capacitance of the diode is given by:

$$\mathbf{C}\_{\mathbf{d},\mathfrak{m}} = \mathbf{C}\_{\mathfrak{t},\mathfrak{m}} + \mathbf{C}\_{\mathfrak{j},\mathfrak{m}} = t\_{\mathfrak{t}} \frac{d(i\_{\mathfrak{s}}(\mathbf{e}^{v\_{\mathfrak{m}}/(Nv\_{\mathfrak{t}})} - 1))}{d v\_{\mathfrak{m}}} + \mathbf{C}\_{\mathfrak{j},\mathfrak{m}} \tag{5}$$

where *C*t,*m* is the transit time capacitance of the *m*-th diode and *t*t is the transit time. Since for the Schottky diodes this quantity is typically negligibly small and therefore does not have a substantial effect on diode performance, it is assumed that *C*t,*m* = 0. The other component is the junction capacitance given by *<sup>C</sup>*j,*m* = *<sup>C</sup>*j0(<sup>1</sup> − *FC*) −(*<sup>M</sup>*+<sup>1</sup>) (*K* + *Mvm*/*<sup>v</sup>*j), if *vm* > *FC* · *v*j and *<sup>C</sup>*j,*m*(*vm*) = *<sup>C</sup>*j0(<sup>1</sup> − *vm*/*<sup>v</sup>*j) −*M*, otherwise, where *<sup>C</sup>*j0 is zero bias voltage capacitance, *M* is the grading coefficient, *v*j is the junction built-in voltage, *K* = 1 − *FC*(*M* + <sup>1</sup>), and *FC* represents the forward-bias depletion capacitance coefficient. Using (4) and (5), the expressions for the Jacobian matrix and residual vector entries can be derived in a straightforward manner, however, for the sake of brevity they are not presented here. Parameters of the SMS7630 Schottky diode are compiled in Table 2.


**Table 2.** SPICE model parameters of the SMS7630 Schottky diode [68].

#### *2.3. Evaluating Y Parameters for the Linear Sub-Network*

In addition to the diode I–V relation, Equation (3) also requires the knowledge of the behavior of the linear sub-network composed of all linear elements, including the PCB. As it was mentioned previously, within the proposed approach the PCB is treated as a separate circuit element—multi-port network. In the frequency domain, the behavior of the PCB can be fully described in terms of Y parameters. Similar to diodes, a proper model of the PCB is essential, since the impact of the PCB upon the converter plays a crucial role and therefore should not be neglected.

Conventional lumped element equivalent circuits (LEEC) are not suitable for the excitation and the working frequency at hand due to highly pronounced non-linear distortions. More specifically, the equivalent circuit must be usable for a frequency range encompassing at least 6–8 harmonics of the CW, which is quite challenging to meet owing to the frequency-dependent nature of different parasitic effects. As it is rather difficult to evaluate the values of the LEEC constituents, the authors decided to perform a full-wave analysis (FWA) of the PCB for the RF–DC circuit under study. The main advantage of the FWA is that it allows capturing of the effects that other methods cannot because of their approximate nature. Thus, the FWA is the most reliable method for characterizing non-linear high frequency circuits.

The discrete circuit components are modeled as lumped elements (LE), or equivalent circuits composed of LE. Since the PCB of the circuit under study has a complex layout and it may be complicated to construct an LEEC that would be valid over a relatively wide band, the Y parameters of the circuit are obtained using an FWA.

For this purpose, commercially available software Ansys HFSS is employed [69], which solves Maxwell's equations using the well-established finite element method [70]. Each discrete element is replaced with a lumped port. The PCB model of the voltage doubler circuit can be seen in Figure 5a. The model is enclosed by a fictitious absorbing surface that truncates the solution domain [52]. The dimensions of the PCB model itself and its conducting parts are the same as for the prototype circuit used for the experimental

validation. As the main objective is to eliminate all linear equations, the Y matrix for the PCB model can be partitioned as follows:

$$
\begin{pmatrix}
\dot{\mathbf{i}}\_{\rm L} \\
\dot{\mathbf{i}}\_{\rm N}
\end{pmatrix} = \begin{pmatrix}
\mathbf{Y}\_{\rm LL} & \mathbf{Y}\_{\rm LN} \\
\mathbf{Y}\_{\rm NL} & \mathbf{Y}\_{\rm NN}
\end{pmatrix} \begin{pmatrix}
\mathbf{v}\_{\rm L} \\
\mathbf{v}\_{\rm N}
\end{pmatrix} \tag{6}
$$

where vectors **v**L and **v**N contain voltages at linear and non-linear ports, respectively, whereas **i**L and **i**N contain the vectors of current at linear and non-linear ports, respectively.

**Figure 5.** HFSS model of the voltage doubler-based RF–DC converter PCB (**a**), an equivalent network for 4 diodes in a single package (**b**).

In order to make the model even more reliable, various parasitic effects associated with diodes should also be considered by introducing a number of lumped elements, each modeling the corresponding effect, such as bond wire inductance, lead inductance, package capacitance, etc. An extended diode equivalent circuit (EDEC) incorporating parasitic inductances and capacitances of four diodes within a single package is illustrated in Figure 5b. A port composed of the reference terminal (indicated by 0' in Figure 5b) and a non-referenced one is termed an internal port (IP), whereas a port obtained by eliminating the non-linear part of the DEC depicted in Figure 4 is termed an external port (EP). Similar to the Y matrix of PCB-EC, the Y matrix for the EDEC can be partitioned as follows:

$$
\begin{pmatrix} \mathbf{i}^{(\mathrm{i})} \\ \mathbf{i}^{(\mathrm{e})} \end{pmatrix} = \begin{pmatrix} \mathbf{Y}\_{\mathrm{r}}^{(\mathrm{ii})} & \mathbf{Y}\_{\mathrm{r}}^{(\mathrm{ie})} \\ \mathbf{Y}\_{\mathrm{r}}^{(\mathrm{ei})} & \mathbf{Y}\_{\mathrm{r}}^{(\mathrm{ce})} \end{pmatrix} \begin{pmatrix} \mathbf{v}^{(\mathrm{i})} \\ \mathbf{v}^{(\mathrm{e})} \end{pmatrix}, \tag{7}
$$

where vectors **v**(o) and **i**(o) contain voltages and currents at the EPs, respectively, while vectors **v**(i) and **i**(i) correspond to the IPs.

Finally, combining (6) and (7), as well as using the Norton equivalent circuit parameters for all elements other than diodes connected to PCB-EC, yields the relation:

$$\mathbf{i}\_{\rm d} = \mathbf{i}\_{\rm d,eq} + \mathbf{Y}\_{\rm d} \mathbf{v}\_{\rm d} \tag{8}$$

where **i**d is a vector of total diode currents, **<sup>v</sup>**d is the voltages across the non-linear part of the DEC, **<sup>Y</sup>**d is the admittance matrix for the linear subcircuit of the RF–DC converter, and **<sup>i</sup>**d,eq contains equivalent currents that represent the effect of the voltage source.

#### *2.4. Estimation of the PCE for a Voltage Doubler Circuit*

A voltage doubler circuit shown in Figure 2 was considered as an example. Following the methodology described in the previous subsection, the circuit can be regarded as a multiport network representing the effect of the PCB on the circuit behavior. The voltage doubler circuit can then be represented as the multi-port network with other circuit elements, or their equivalent circuits connected to its ports. Since only 2, not 4, diodes in a single package are used for the prototype circuit, only one of the two subcircuits shown in Figure 6 must be considered. The entire circuit of the voltage doubler is represented as a multi-port network corresponding to the PCB, to which lumped circuit elements are connected, including the generator, as illustrated in Figure 3. The Y matrix of the PCB is computed using Ansys HFSS as described in the previous subsections. The impedance of the generator is assumed to be 50 Ω. The values of the elements of the DEC are taken from the relevant datasheet.

**Figure 6.** The equivalent circuit of the voltage doubler with the PCB replaced by the equivalent mesh network.

The equivalent circuit of the entire linear part of the voltage doubler circuit is depicted in Figure 6. It should be noted that the diode symbol in the equivalent circuits represents the non-linear part of the low frequency DEC, while the effect of *R*S (see Figure 4) is incorporated in the equivalent circuit for the linear part of the original one. The current sources *<sup>i</sup>*eq,<sup>1</sup> and *<sup>i</sup>*eq,<sup>2</sup> are the equivalent current sources representing the contribution of the voltage source to the total currents at nodes 1 and 2. Thus, the behavior of the circuit can be described using two non-linear equations:

$$\begin{cases} \begin{array}{c} i\_{\sum 1} = i\_1 + v\_1(\chi\_{11} + \chi\_{12}) + v\_2 \chi\_{12} - i\_{\text{eq},1} = 0\\ i\_{\sum 2} = -i\_2 - v\_2(\chi\_{22} + \chi\_{12}) - v\_1 \chi\_{12} - i\_{\text{eq},2} = 0 \end{array} \tag{9}$$

To determine the phasors of *v*1 and *v*2, system (9) is solved using the NM. The NM is employed as it has proven itself as a rapidly converging method, provided the initial guess is close enough to the actual solution. If it is not the case, the continuation method [41] can be utilized to take advantage of the fact that the convergence of the NM is more stable for small amplitudes. The convergence is ensured by gradually increasing the input excitation amplitude, starting with the smallest one. Each time the NM fails, the values of the equivalent current sources are reduced. The phasors of both the initial guess and input currents are multiplied by a scaling factor *F*. The NM is then applied to the altered (scaled) input data. If the algorithm still fails to converge, the scaling is applied repeatedly until the convergence is achieved. In addition, upon each failure, the scaling factor is reduced, thus making the procedure more adaptive. In the case of successful convergence, the algorithm does the opposite—it increases the scaling coefficient until its value reaches the desired one (the one before the scaling). The last successfully calculated set of phasors is used as an initial guess for the next iteration of the continuation method.

The flowchart of the algorithm employed to find the PCE of the circuit under study is depicted in Figure 7, where the scaling coefficients are denoted by *Si*, and *i* = 0 corresponds to the smallest magnitude. At the very first iteration of the algorithm, the spectral coefficients of diode voltages are initialized using some a priori knowledge about them. The optimal value of NM damping factor (β) is found to be in the range from 0.9 to 1.1. Values of β beyond this range result in an increase in the number of iterations. The value

of the DC voltage is utilized as a convergence criterion—the execution of the algorithm is terminated once the DC voltage falls below the prescribed threshold.

**Figure 7.** The flowchart of the algorithm to compute diode voltages.

#### *2.5. Comparison of the Proposed Method with Other Methods*

In order to demonstrate the efficiency of 2F-HB, a comparative study of the most commonly used non-nonlinear circuit analysis methods was undertaken. The methods were applied to an idealized voltage doubler circuit shown in Figure 2. The circuit element values are *C*1 = 2.4 pF, *C*2 = 8.5 nF, *C*3 = 1 μF, *R*1 = 7.5 kΩ, and *L*1 = *L*2 = 17 μH. The diode SPICE model parameters used in the analysis are summarized in Table 2 that correspond to the SMS7630 Schottky diode. The effect of the PCB, as well as parasitic inductances and capacitances of diodes and other circuit elements, were not taken into account in this study due to the lack of the appropriate PCB model for the TA (LTSpice [71]). The voltage doubler PCE obtained using the TA, 2F-HB, MHB, and HB is shown in Figure 8. Since both the HB and MHB are implemented in the commercially available Keysight ADS software [72] that has proven itself as a reliable and powerful non-linear circuit simulator, we employ it to calculate the PCE in place of custom programs. In order to compute the PCE using the TA, the well-established circuit simulator LTSpice is employed. The time required to compute the output voltage at 100 values of the input power level taken uniformly in the range of −20-0 dBm using each method is summarized in Table 3. The circuit was excited by a multi-carrier with 8 subcarriers occupying a 4.5 MHz band centered at 865.5 MHz (the CSF is 0.5 MHz). The Y of the PCB is computed for the two frequency ranges separately: 0.1-100 MHz and 0.1-10 GHz and exported into two MATLAB script files. The entire frequency range is divided into two subranges is to improve the calculation accuracy at low frequencies. More specifically, when applied to a wide frequency range, the interpolative sweep may result in a poor accuracy at the lower end. Once the computations are done, the exported MATLAB files are used by the program written in C++ to evaluate the entries of both the Jacobian matrix and the right-hand side vector, as well as to solve the resulting non-linear equations with Newton's method. Additionally, it should be noted that although the HB method can yield accurate results while solving the problem under consideration, it requires considering a large number of harmonics, which in turn would call for a considerable amount of computational resources. However, in this study, the issue is mitigated by considering signals whose CF is an integer multiple of the CSF. Unfortunately, such an approach imposes serious restrictions on the shape of the input signals.

**Figure 8.** The PCE of the ideal voltage doubler obtained using four different methods as a function of the input power level.


**Table 3.** Comparison of different analysis methods.

As can be seen in Figure 8, the HB, 2F-HB, and TA show sufficiently high accuracy, while the accuracy of the PCE obtained using the MHB method is much lower. The low accuracy is conditioned by a small number of harmonics used to approximate voltages (currents) in the circuit. However, as can be seen in Table 3, even with the small number of harmonics (425 harmonics), the CPU time required by the MHB is larger than that of other methods. The fundamental frequencies for the MHB were set to be equal to those of the subcarriers, i.e., 8 frequencies.

It should be noted that in this particular case the conventional HB method solves the task faster than the MHB, since the fundamental frequency was chosen to be equal to the CSF, and CF can be expressed as an integer multiple of CSF. In a more general case, however, the MHB considerably outperforms its conventional counterpart.

Although the computational time of the TA scales linearly with the number of harmonics provided the bandwidth is kept fixed, the main drawback of the TA is the lack of simple and reliable PCB-EC. In order to expedite simulation time, the TA was accelerated through the shooting method (SM) with the maximum number of iterations set to 20 and time step of 0.05 ns. The first period of the input signal envelope was skipped to avoid transients due to energy storage elements other than the filtering capacitor. The SM has been implemented as a MATLAB script that modifies the circuit netlist, runs the LTSpice simulations in the batch mode, and processes the results of the intermediate simulations, as well as performs postprocessing.

The proposed method (2F-HB) demonstrates good accuracy, allowing performing of computations considerably faster than other harmonic balance methods and TA. The reason why the 2F-HB outperforms the MBH when applied to multi-tone signals is the spectral redundancy of the latter. More specifically, because subcarriers are evenly spaced, a grea<sup>t</sup> deal of non-linear conversion products may have the same frequency, which is not considered by the MBH. Therefore, to ensure the same accuracy, the MBH requires much larger matrices than 2F-HB, and that explains the huge difference in the computational time. However, the MBH is more general. In contrast, the 2F-HB can handle multi-tone signals with unevenly distributed tone frequencies.

#### **3. Comparison of Theoretical and Experimental Results**

This section discusses experimental verification of the validity of the proposed theoretical PCE evaluation method, especially in the case of employment of the multi-tone power-carrying signals. For this purpose, the voltage doubler circuit discussed in the previous section was chosen as a test object. The set of non-linear equations describing the circuit was derived in the preceding section. The PCE can be calculated by applying the approach presented in the previous section to the set of equations. From the calculated current spectrum of the second diode it is then possible to retrieve the output DC voltage in a straightforward way. To obtain a full picture of the performance of the voltage doubler circuit under different conditions, including different types of excitations, the calculations were carried out for different values of the inductance and capacitance of the matching circuit in order to find an optimal combination for achieving the highest PCE.

The power-carrying signals considered in the present study are a classical sine wave (SW). The three types of the considered multi-tone periodic envelope signals are listed below:


#### *3.1. Calculation of the PCE by Means of the Theoretical Model*

The doubler circuit was selected for being one of the most widespread RF–DC converter topologies. It has been used in a wide variety of applications and demonstrates sufficiently high efficiency [74]. The converter employs an SMS7630-005LF Schottky diode [68] that possesses a low forward voltage, small junction capacitance, and is capable of operating in the desired license free sub-GHz ISM band around 865.5 MHz.

The results of the theoretical analysis are displayed using a color plot shown in Figure 9. The plot is composed of colored squares, different colors correspond to different values of the PCE. Darker colors correspond to lower PCE values, while brighter colors are used for higher PCE values. The squares are arranged into a two-dimensional array. Each row corresponds to a particular value of the matching network capacitance, and each column corresponds to a specific value of the matching network inductance according to

the topology illustrated in Figure 2. Each array element is also a two-dimensional array, whose rows correspond to different values of the input power level in dBm. The columns of subarrays correspond to different waveforms of the input signals in the following order: SW, HPAPR with 4, 8, and 16 subcarriers, LPAPR with 4, 8, and 16 subcarriers, and RPAPR with 4, 8, and 16 subcarriers. The results obtained for signals with the number of subcarriers greater than 16 are omitted in this example, since for HPAPR signals the highest achieved PCE does not exceed 25% and thus they are of little practical interest in WPT. Additionally, the obtained results demonstrate that consideration of the LPAPR and RPAPR signals with the number of subcarriers greater than 16 is completely irrelevant, since for these types of signals the PCE does not exhibit any dependence on the number of subcarriers.

**Figure 9.** Color plot showing the PCE value of the voltage doubler for different values of the matching circuit parameters, waveforms, and average input power levels.

The power levels considered are −2 dBm, −8 dBm, and −14 dBm. The frequency of the carrier SW in all cases was 865.5 MHz. The reason why the results are given for the range of −14–2 dBm is due to a relatively low breakdown voltage of the diode employed in the experimental studies, namely, SMS7630. The breakdown voltage for this diode is just 2 V, resulting in considerable degradation of the PCE as the input power level exceeds approximately 0 dBm. Another reason is the nonlinearity of the generator that manifests itself at power levels close to −2 dBm when producing HPAPR signals with a large number of subcarriers, as they exhibit high peak voltages. The primary factor determining the lower limit of the input power level range being considered is the total noise level due to the generator, and both diodes. More specifically, the noise power measured by the oscilloscope when the generator power level was set to −30 dBm was in the vicinity of 4 μW that corresponds to about −23.9 dBm. This noise has not been considered during the theoretical modeling, which might result in huge discrepancies between the calculated data and the experimentally obtained data for input power levels below −14 dBm.

Figure 9 shows that the optimal value of the inductances is *L* = *L*1 = *L*2 = 17 nH, while the optimal value of *C*1 is 2.4 pF. The SW and LPAPR signals are the waveforms with the highest achieved PCE (approx. 70%). The PCE obtained for the HPAPR signals is lower than that of the SW and LPAPR signals. Furthermore, it deteriorates as the number of subcarriers increases, attaining the maximum and minimum values for 4 and 16 subcarriers, respectively. The PCE obtained for the RPAPR signal with different subcarriers is slightly lower than that of the SW and LPAPR signals.

#### *3.2. Experimental Validation of the Theoretical Model*

In order to validate the proposed theoretical approach, experimental verification is performed with a specially designed prototype (see Figure 10) of the voltage doubler with SMS7630-005LF Schottky diode [68] capable of effectively operating at the required frequency of 865.5 MHz. The circuit components of voltage doubler are mounted on the top layer of PCB made of FR-4 with a dielectric constant of 4.2 and the thickness of the substrate of 1.6 mm. The SMA type connector is used to feed the power-carrying signal via a coaxial cable with characteristic impedance of 50 Ω during the current experimental study, or via antennas during wireless power transfer or harvesting in the real employment scenario. The matching network component values are selected by enumeration, obtaining the input impedance of the matching network closest to 50 Ω resistive load at 865.5 MHz and 0 dBm. Table 4 shows the matching process, where the optimal values of *L*1, *L*2, and *C*1(matching network elements) are examined. The initial values are *L*1 = *L*2 = 20 nH, *C*1 = 2.4 pF. The values of other circuit elements are: *C*2 = 8.2 pF, *C*3 = 1 μF, and *R*1 = 7.5 kΩ.

**Figure 10.** The fabricated prototype of the voltage doubler circuit for 865.5 MHz carrier frequency.


**Table 4.** Determining nominal values of the matching network.

1 All instances of "j" mean the imaginary unit.

Measurements are made for different multi-tone signals with a different number of subcarriers and at different average input signal power levels. The SW is considered as the reference signal for comparison of the obtained PCE. The measurement setup is shown in Figure 11, it demonstrates the average input power level measurement (a) and converted power level measurement (b), and PCE estimation as the ratio of the average input and output powers.

**Figure 11.** Measurement setup for evaluating the RF–DC conversion efficiency: (**a**) setup used for measuring the average power level of the input signal using a digital oscilloscope with the embedded average power estimation function, (**b**) setup used for measuring the RF–DC converted power level.

#### *3.3. Evaluation of the Effect of the Matching Network Parameters on the PCE*

In order to evaluate how the values of the matching network elements, namely, *L* and *C*1, affect the performance of the voltage doubler circuit in terms of PCE, the following two different case study scenarios are considered:


In order to validate the theoretical model, the aforementioned dependences are obtained experimentally as well.

As can be observed in Figures 12 and 13, the results of the theoretical analysis are in good agreemen<sup>t</sup> with those achieved experimentally, which means that the proposed methodology allows predicting of the behavior of diode-based RF–DC converters with a reasonably small discrepancy between the measurements and simulations. It is particularly apparent in the case of HPAPR signal, i.e., the shapes of the curves corresponding to different number of subcarriers match the calculated ones well. In the case of the dependence of the PCE on *C*1 the largest discrepancy between the results is observed for small values of *C*1. Similar to *L* sweep, in this case, the largest difference is also observed at the input power level of −14 dBm. The highest PCE of 64.8% was achieved for the SW. As for the multi-tone signals, the LPAPR signals exhibit the highest PCE of 63.15%. Furthermore, the PCE of LPAPR signals varies only slightly with the number of carriers. In the case of the HPAPR signals, the highest PCE reaches 51.64% for the signal with 4-subcarriers.

**Figure 12.** The calculated (dashed line) and measured (solid line) PCE of the voltage doubler RF–DC converter as a function of *L* when *C*1 = 2.4 pF for different numbers of subcarriers: 4 (blue), 8 (red), and 16 (yellow) with the SW (purple) used as a reference.

The highest PCE of 60% that is very close to the one obtained in this work for a sine wave-driven single diode rectifier operating at 10 GHz was achieved in [75]. Though the working frequency is about an order of magnitude higher than the one considered in the present study, the input power level at which such a high efficiency has been attained is much higher. To compute the PCE the authors employed both the closed form expressions and LIBRE software employing the harmonic balance.

**Figure 13.** The calculated (dashed line) and measured (solid line) PCE of the voltage doubler RF–DC converter as a function of *C*1 when *L* = 17 nH for different numbers of subcarriers: 4 (blue), 8 (red), and 16 (yellow) with the SW (purple) used as a reference.

A comprehensive comparative analysis of the efficiencies attainable by means of various RF–DC converters, including diode converters and CMOS technology-based converters, is presented in [76,77]. From this analysis it follows that using a pure sine wave, i.e., a single tone signal, the maximum achievable PCE does not exceed 60% when input power levels below 1 mW (0 dBm) are considered. Nevertheless, the same analysis also demonstrates that it is possible to achieve a PCE of up to 90% for sufficiently high power levels (around 1 W). However, to obtain such an amount of received power for medium distances (few tens of meters), that are typical distances in IoT sensor networks, according to the well-known Friis transmission equation one needs to maintain a high transmitted power that, in turn, necessitates more expensive equipment. This makes the deployment and wireless charging process costly, while the goal of the present study is to develop an affordable medium power alternative with sufficiently high PCE not the highest possible.

Although the voltage doubler circuit studied in this work has a limited range of the input power level (<0 dBm) due to a relatively low breakdown voltage of the diodes, as well as exhibiting the highest PCE that is just about 65%, the proposed approach has no limitation with respect to the circuit topology, PCB layout, working frequency, and power levels of input signals as it relies on the full-wave analysis. Alternatively, the only limitation of the full-wave analysis is the CPU time that increases with the frequency, and the complexity of the layout.

#### *3.4. Simulation and Experimental Results for HPAPR Signals*

The results discussed in the previous subsection show that the notable difference of PCE for different carrier number is observed only in the case of the high PAPR level. Thus, they deserve more detailed consideration. The PCE for the circuit under study is obtained for a larger number of subcarriers to obtain a more in-depth insight into the circuit behavior driven by such signals. The considered signals are HPAPR signals with 4, 8, 16, 32, 64, 128, and 256 subcarriers. Both the calculated and experimental PCE are graphically represented with scatterplots. For the graphs shown in Figure 14, the horizontal axis represents values of the matching network inductance, while the vertical one—the input power level. Each

circle corresponds to a specific number of subcarriers. The size of circles increases with the number of subcarriers, i.e., the innermost circle corresponds to 4 subcarriers, while the outermost—to 256 subcarriers. The color of each circle represents different values of the PCE (both calculated and measured), where darker colors show the lower values of the PCE, while brighter ones—the higher values of the PCE. Regarding the graphs shown in Figure 15, the same format is used, but the horizontal axis represents different values of *C*1.

**Figure 14.** The calculated (**a**) and measured (**b**) PCE of the voltage doubler RF–DC converter as a function of both *L* and input signal power for *C*1 = 2.4 pF. PCE is represented by color. Size of the circle represents the number of subcarriers (4, 8, 16, 32, 64, 128, 256), the smallest is for 4 carriers and the largest—for 256 carriers.

**Figure 15.** The calculated (**a**) and measured (**b**) PCE of the voltage doubler RF–DC converter as a function of *C*1 values and input signal power for *L* = 17 nH. PCE is represented by color. Size of the circle represents the number of subcarriers (4, 8, 16, 32, 64, 128, 256), the smallest is for 4 carriers and the largest—for 256 carriers.

Again, Figures 14 and 15 show that the results of the measurements are consistent with the results obtained with the theoretical model, proving the validity of the proposed method. Both theoretical and experimental results show that in the case of input signal

formed, to have the maximum possible PAPR level among signals with the same number of subcarriers, the PCE diminishes progressively with the number of subcarriers. In most of the cases considered, the highest PCE is attained by the signals with 4 subcarriers. The PCE for signals with 8 subcarriers is typically 10% lower than that of the signal with 4 subcarriers. For some combinations of the matching network element values (*L* and *<sup>C</sup>*1), the opposite behavior is observed, i.e., a 4-subcarrier signal shows lower PCE than its 8-subcarrier counterpart. However, those combinations are not the optimal ones and the PCE of the sine wave in these cases is lower or comparable with that of the signals with 4 and 8 subcarriers. Another finding of this study concerns the sensitivity of the PCE to variations in the values of *L*, and *C*1. Despite being the most optimal waveform in terms of the PCE, it was found that SW exhibits the highest sensitivity to variations in the matching network element values.

In some cases, the difference between the calculated and experimentally obtained results is quite small, e.g., for HPAPR signals with a small number of tones (<16). Although even in this case the error is large at large deviation from the optimal values of *L* and *C* (matching circuit elements), it occurs due to the shift between the theoretical and measured curves. A possible source of such a shift is likely the difference between the actual values of the discrete inductor used in the experimental studies and the one used in the theoretical model calculated from the data provided in the relevant datasheets.

The PCE is unacceptably low as far as signals with the number of subcarriers greater than 16. For this reason, such signals cannot be used for powering isolated sensor network nodes. This finding agrees with the results of a recent study undertaken by another group of researchers who also examined a voltage doubler circuit, but operating at lower frequencies [78]. The researchers also found that the use of signals with a high peak-toaverage power ratio does not improve the PCE of RF–DC converters.

For numerical comparison of the theoretical and measured results from Figures 14 and 15, the estimation error is presented in Tables 5 and 6 corresponding to each figure. The error is taken as relative to the measured PCE. Since Figures 14 and 15 contain a substantial amount of data, tables show estimation errors for the input power of −2 dBm and in the range of 4–32 carriers. The tables show that the estimation error reaches as low as 0.37%, and the maximal estimation error is 32.65%. In Table 5 the estimation error notably increases when *L* is greater than 18 nH, which is visible in Figure 12 for the HPAPR. In Figure 12 the difference between the theoretical and measured curves increases with subcarrier number and *L* value. The source of such shift between the theoretical and measured curves is explained with the nominal mismatch of the two *L* elements (*L*1 and *<sup>L</sup>*2) and the SDR signal nonlinearity in the case of a large number of subcarriers.

**Table 5.** Relative error for theoretical and measured PCE results in % (*C* = 2.4 pF).


**Table 6.** Relative error for theoretical and measured PCE results in % (*L* = 17 nH).

