*3.1. Frequency Tripler*

As shown in Figure 1, the LO chain integrates a frequency tripler, a BPF, an LO driving power amplifier, and an HPF. The schematic of the frequency tripler and the succeeding frequency selective BPF is illustrated in Figure 2. The tripler core is composed of antiparallel diode pairs (APDP) [13,14], and the diode is implemented by connecting the drain and source of pHEMT transistors as the cathode with the gate as the anode. Due to the passive structure, sufficient input power is required for the tripler to generate odd-order harmonics while suppressing even-order spurs [15]. Two 4-finger 10 μm pHEMTs are employed as the APDP in this design in consideration of a trade-off between output power and bandwidth. The input matching network consists of a capacitor connected in parallel to ground and a microstrip line connected in series. The output matching network consists of two capacitors connected in series and an inductor connected in parallel to ground in a T-shaped configuration. In order to effectively improve the unwanted harmonics suppression of the tripler and reduce the frequency conversion loss, a transmission line TL as depicted in Figure 2 is adopted to reflect idle frequency signals to the APDP core. A seventh-order BPF was connected after the frequency multiplier to further improve the harmonic suppression characteristics of the LO chain.

The simulation results of each harmonic output power of the tripler plus the cascaded BPF when the input power is 16 dBm are shown in Figure 3. The simulated input and output return loss are better than −10 dB over 41–51 GHz, and the simulated output power of the third harmonic signal is around 0 dBm. Benefiting from the BPF, all unwanted harmonics can be suppressed significantly within the interested frequency bands. It can be deduced from Figure 3 that the fundamental signal and 2nd harmonic rejection are over 30 dB compared with the third harmonic signal, and the 4th and 5th harmonic suppressions are better than 35 dB.

**Figure 2.** Schematic of the frequency tripler and its cascaded frequency selective BPF.

**Figure 3.** Simulated output power of the tripler with BPF.
