**2. Mechanical Design**

In this work, we focus on developing a series switch using a CPW structure as shown in Figure 1. Under applied external bias voltage, the electrostatic force pulls the cantilever towards the bias pad. The voltage that provides sufficient force that can turn the switch to an ON state is the actuation voltage. Once the external bias voltage reduces, the cantilever starts to restore to its initial position and returns to the OFF state under zero bias. In Figure 2, the switch's ON/OFF states are presented.

**Figure 1.** (**a**) 3-D model of an electro-static actuated MEMS switch in a series configuration. The switch's OFF state isolation is provided an air gap between the actuator's tip and the CPW section's tip. When applying external DC bias, the electrostatic force between the bias pad and the actuator will pull the actuator down and provide an RF signal path. (**b**) A photomicrograph of a fabricated switch.

**(E) switch is "ON'' under actuation voltage**

**Figure 2.** The OFF and ON states of the RF MEMS switch under different DC bias conditions. The cantilever to bias pad gap *g* and dimple to CPW distance *g*<sup>1</sup> are both marked. (**a**) The Switch is under OFF state. (**b**) The Switch is under ON state.

The first step of this switch design is to choose the desired substrate. Among several widely used materials, high resistivity silicon and fused quartz are chosen. These two substrates have significant differences in physical features that lead to different approaches in their mechanical and electrical designs. Silicon, with its higher relative permittivity (*<sup>r</sup>* = 11.9) than fused quartz (*<sup>r</sup>* = 3.8), takes less physical length to build the same RF circuit on a silicon substrate, moreover, the transmission line features are also narrower. This can be an advantage to develop a more compact device but requires finer adjustment on the device RF optimization. On the other hand, depending on the type of fused quartz

been used, it could have a dielectric strength as high as 10 MV/cm [14] in comparison with 0.3 MV/cm for resistivity silicon substrates. Therefore, using equivalent circuit dimensions, fused quartz substrate can potentially support 30× higher DC bias voltage than the silicon substrate. Such an additional safe margin provides more design flexibility for designing electrostatic actuated MEMS devices. Meanwhile, high resistivity silicon's resistivity is at the order of 104 <sup>Ω</sup> ·cm [15]; in comparison, fused quartz has a higher resistivity at the order of 1014–1016 <sup>Ω</sup> ·cm [16]. A thin layer of silicon dioxide should be deposited on top of the silicon surface to improve DC isolation.

The actuator of the proposed RF MEMS switch can be modeled as a cantilever from a mechanical perspective. The cantilever's spring constant *k* can be calculated by the following equation [17]:

$$k = 2Ew(\frac{t}{l})^3 \frac{1 - (\frac{x}{l})}{3 - 4(\frac{t}{l})^3 + 4(\frac{t}{l})^4}. \tag{1}$$

Its pull-down voltage *Vpull* can be estimated by the following equation [1]:

$$V\_{pull} = \sqrt{\frac{8 \text{kg}^3}{27 \epsilon\_0 L\_1 w}}.\tag{2}$$

Here, *E* is Young's modulus of the cantilever material; *x* is the distance from the cantilever anchor to the center of the bias pad; *l*, *t*, and *w* are the cantilever's length, thickness, and width. As shown in Figures 1 and 2, *g* and *L*<sup>1</sup> are the actuation gap and the length of the actuation pad beneath the actuator.

A small dimple structure is attached beneath the cantilever tip. Its thickness *h* is 0.2 μm. This dimple reduces the contact surface at the switch's ON state to reduce the Van der Waals forces.

Previous research [17] included a similar sized dimple beneath the cantilever beam tip, and the experimental result suggests a restoring force of 0.07 mN is needed for reliable restoration. Assuming gold as the cantilever material, *l* in a range of 70–100 μm and *x* is roughly half of *l*, *w* and *t* can be calculated accordingly. In consideration of fabrication feasibility, *w* should be at least 2–3 times longer than *t*. With an actuation gap *g* of 1.2 μm, the initial values of *t* and *w* are selected as 2.3 μm and 7 μm, respectively. The resulting *Vpull* is estimated to be around 55 V.

To prevent dielectric breakdown during actuation, the electric field between the bias pad and nearby CPW should be kept well below the substrate dielectric strength. As presented in Figure 3, a crude estimate of the electric field strength can be obtained by assuming a uniform field distribution.

**Figure 3.** The strongest electric field is between the CPW and the adjacent DC bias pad.

In the fused quartz-based design, the strongest electric field extends along the minimum gap between the CPW and adjacent bias pad. Under a 55-V bias voltage, the electric

field is approximately 0.11 MV/cm along the 5 μm gap. This value is well below the substrate's dielectric strength and can be further reduced by increasing the gap between the bias pad and CPW. By comparison, in the silicon based design, the electric field extended through the silicon dioxide thickness as depicted in Figure 3. Considering silicon dioxide's dielectric strength of around 3–5 MV/cm, the silicon dioxide insulation layer should be around 100 nm to prevent dielectric breakdown. One common method to deposit a silicon dioxide layer is through plasma-enhanced chemical vapor deposition (PECVD). However, previous fabrication and subsequent tests suggest this PECVD oxide has a high risk of creating an un-covered silicon area known as pinholes inside the oxidation layer that result in potential shorts between the MEMS devices and silicon substrate [18,19]. In this work, a very uniform dry thermal silicon-dioxide layer was grown on the high resistivity silicon surface with a thickness of 100–110 nm.

## **3. Electrical Design**

In Figure 4, a cross-section view of a coplanar waveguide (CPW) structure is presented. The impedance of a CPW is largely determined by the signal line's width, *w*, and the signal to ground gap, *gc*. When scaling *w* and *gc* by the same ratio, CPW's impedance has little variation. At a minimum feature size *gc* = 4 μm, the corresponding *w* to realize a 50 Ω impedance on different substrates is simulated through Ansys HFSS and listed in Table 1. The result shows that a lower relative permittivity substrate require a large signal line width. On silicon, the required signal line width is 7 μm, while for a fused quartz, the signal line width increases to 35 μm.

**Figure 4.** The cross-section view of a CPW. In this work, both high resistivity silicon and fused quartz substrate have thickness h of 500 μm. The CPW is evaporated gold with a thickness t of 400 nm. The signal line width *w* and signal-ground gap *g* are impacted by the substrate's relative permittivity.


**Table 1.** The cross-section dimensions of a 50 Ω CPW on different substrates.

The dimensions of 50 Ω CPWs on the different substrates are compared through Ansys HFSS simulation. In the CPW design, the signal-ground gap *gc* is limited to 4 μm to keep the transmission line fabrication feasible. With the same *gc*, the differences in signal line width *w* are compared under different relative permittivity .

At the OFF state, the switch's actuator is coupled to the bias pad and the CPW signal line through parasitic capacitances as presented in Figure 5. Here *C*<sup>1</sup> is actuator-bias pad coupling capacitance; *C*<sup>2</sup> is pad-CPW coupling capacitance; *Ctip* is the coupling capacitance between actuator tip and CPW. The equivalent series capacitance of *C*<sup>1</sup> and *C*<sup>2</sup> is designed to be much smaller than *Ctip* so that the total parasitic capacitance *Ctotal* ≈ *Ctip*. At the OFF state, the switch's RF isolation is determined by the impedance of the total capacitance.

**Figure 5.** The parasitic capacitance of MEMS switch under OFF state and the switch's equivalent circuit model.

To reach a higher RF isolation, a smaller *Ctip* is desired. Assuming the switch actuator and CPW overlaps by 2 μm, the initial switch designs on silicon and fused quartz are each shown in Figures 6a and 7a. Using the parallel plate capacitance equation, the tip capacitance of the silicon and quartz designs are estimated to be 0.6 fF and 2 fF, respectively. From these initial capacitance values, their isolation performance is simulated through a simplified transmission line circuit model. The results are plotted in blue and black curves in Figure 8. In this work, limited by equipment availability, the highest measurement frequency is 750 GHz; so the simulation is plotted in the DC-750 GHz frequency range. For the purposes of switch design comparison, a 15 dB isolation level is drawn as a reference. The estimation suggests the silicon design will have 15 dB isolation at around 470 GHz; due to the wider cantilever causing larger capacitance, the isolation of the quartz design is reduced to 15 dB at about 140 GHz.

**Figure 6.** Three dimensional (3-D) model of high resistivity silicon-based MEMS switch. The initial design (**a**) has a larger parallel area at the actuator tip, which causes larger capacitance. To reduce such capacitance for higher isolation performance, its actuator tip is trimmed (**b**).

**Figure 7.** Three dimensional (3-D) model of fused quartz-based MEMS switch. In the initial design (**a**) the actuator has the same width as the CPW's signal line, which causes roughly 2 fF parasitic capacitance at the tip. To reduce such capacitance, the actuator's width was reduced and the tip is trimmed to further reduce the capacitance (**b**).

**Figure 8.** Estimated switch isolation performance dominated by actuator tip capacitance.

To improve the isolation performance, the overlapping area that forms *Ctip* must be trimmed to minimize the cantilever's parasitic capacitance. In the silicon switch, as shown in Figure 6b, the cantilever tip and the CPW's signal line tip are both tapered from 7 μm to 3.5 μm. With a smaller overlapping area, the capacitance is reduced to 0.3 fF. In the quartz switch, the cantilever width is reduced to 8 μm. To match the elevated CPW impedance to 50 Ω, the horizontal gap between signal and ground is adjusted to 15 μm; the CPW's signal line tip is also tapered to 3 μm. This adjustment is presented in Figure 7b. Through trimming the geometries of the cantilever and the CPW, the parasitic capacitance of the quartz switch is significantly reduced to roughly 0.5 fF. The estimated RF isolation of both silicon and fused quartz switches are plotted in green and red in Figure 8. The fused quartz switch's cut-off frequency with 15 dB isolation is expanded to 560 GHz, in comparison, the silicon switch's 15 dB isolation bandwidth is higher than 750 GHz.

At the ON state, the switch's RF performance can also be analyzed through a transmission line model. As presented in Figures 1 and 2, the actuator in the MEMS switch creates a discontinuity in physical geometry and impedance mismatch. The switch's actuator and its adjacent ground lines can be modeled as a CPW section, which is elevated from the substrate. As the CPW elevates further away from the silicon substrate surface, the effective relative permittivity *εeff* for the CPW decreases and the impedance increases. This relationship is presented in Figure 9a. In Table 2, the simulated CPW impedance with different elevation heights above the silicon substrate is provided.

**Figure 9.** (**a**) Impedance variation caused by CPW structure elevation. (**b**) impedance tuning is realized by adjusting the DC bias pad size.



Because the actuator beam is elevated to 1.2 μm above the substrate, the effective relative permittivity *εeff* reduces to around 4.8, the impedance rises to 70 Ω, and the return loss will be more than 10 dB at 700 GHz. Such RF performance change can be explained through a simplified transmission line model in Figure 10. For example, at 3 GHz, a 70 μm cantilever beam has an electrical length of merely 0.9◦ and the resulting impedance mismatch is negligible. In comparison, at 300 GHz, the electrical length significantly increases to 90◦, which naturally has a significant impact on the RF performance.

**Figure 10.** Simplified transmission line model of MEMS switch at the ON state.

The cantilever's impedance mismatch is most significant at the frequency when it reaches 90◦ electric length. Here *Zc* is the introduced resistance due to switch Ohmic contact, on a scale of around 1 Ω or less. The *Za* section is a quarter wavelength long and therefore, the input impedance at is given by:

$$Z\_{in} = Z\_a^2 / Z\_0$$

In this case, the equivalent impedance of *Zin* is 98 Ω.

In order to reduce this impedance mismatch, the DC bias pad size is engineered to reduce the actuator impedance *Za*. Since the coplanar waveguide's characteristic impedance is approximated as:

$$Z = \sqrt{\frac{L}{\mathcal{C}}} \tag{3}$$

by increasing the bias pad's size, the total parasitic capacitance at the actuator area is doubled, and the impedance is then successfully tuned to 48 Ω. This engineering tuning method is presented in Figure 9b.

A more comprehensive circuit model includes the anchor and the actuator's tip is provided in Figures 11 and 12 respectively. Figure 11 represents the ON state, in which the actuator is pulled down to make tip contact at the free end. *Zanc* represents the anchor section of the actuator; *Za* represents the elevated actuator after impedance tuning. *Zelev* represents the elevated CPW section assuming no fringing capacitance impact from the bias pad. The switch's transmission line model for the OFF state is shown in Figure 12. The gap beneath the actuator tip serves as an isolation capacitor and introduces impedance *Zc*1.

The simulation result of a silicon-based switch at the ON state is presented in Figure 13a. In this figure, both the transmission line model and HFSS finite element analysis are included and compared. The insertion loss is smaller than 1 dB across DC-750 GHz band, while the return loss is better than 15 dB. Compared with EM simulation, the transmission line model catches the major scale and trends of insertion loss and return loss.

**Figure 11.** A comprehensive transmission line circuit model for ON state MEMS switch.

**Figure 12.** A comprehensive transmission line circuit model for OFF state MEMS switch.

The silicon switch's OFF state simulation is given in Figure 13b. The result shows the expected OFF state isolation better than 15 dB. The transmission line model fits the EM simulation result well in the isolation plots (S21/S12). In the reflection plots (S11/S22), the transmission line model does not account for the radiated energy. As a result, its simulation result has a minor difference from HFSS analysis. Similar results are also seen in fused quartz based simulation in Figure 13c,d.

**Figure 13.** The THz MEMS switches were modeled as transmission line circuits and simulated using AWR Microwave Office (marked as T line). The circuit simulation results are compared with ANSYS HFSS finite element analysis. (**a**) Silicon based design at the ON state. (**b**) Silicon based design at the OFF state. (**c**) Quartz based design at the ON state. (**d**) Quartz based design at the OFF state.

#### **4. Switch Fabrication Challenge & Solution**

The silicon-based MEMS switch fabrication flow is simplified and presented in Figure 14. The fabrication process starts with circuit layer deposition using the lift-off technique. After that, two aluminum sacrificial layers are deposited and the dimple position is prepared with another lift-off. Dry etching and plating were used to form the anchor of switch. After the gold seed layer and photoresist patterning, the actuator beam was plated. After a series of wet etch steps, the switch is finally released by a critical point dryer (CPD). The quartz-based MEMS switch fabrication process is very similar.

**Figure 14.** A simplified silicon-based MEMS switch fabrication flow. The fabrication process starts with circuit layer deposition using a lift-off technique in (**a**,**b**). After that, two aluminum sacrificial layers are deposited and dimple position is prepared with another lift-off in (**c**). Etching and plating were used to form the switch's anchor in (**d**). After the gold seed layer and a photoresist patterning, the beam was plated in (**e**). After a series of wet etch steps, the switch is finally released by CPD in (**f**).

Typical MEMS fabrication uses photoresists such as SU-8 as a sacrificial layer, which has a coefficient of thermal expansion (CTE) as high as 50–102 ppm/K [20,21]. In comparison, Aluminum's CTE is 25.5 ppm/K, much closer to Gold's CTE of 13.9 ppm/K. In this research, using an Al sacrificial layer significantly reduced the CTE mismatch between the actuator beam and the sacrificial layer beneath it, which prevented the commonly observed beam bowing after device release [22].

The Al sacrificial layer can also be easily removed through halogen gas-based reactive ion etch (RIE) or alkali solution wet etch. However, using an Al sacrificial layer also brings challenges in fabrication because it can easily form Al-Au compounds which cannot be easily removed. This red Al-Au compound can be observed in Figure 15a. A chromium layer is added as a diffusion barrier layer between the Al sacrificial layer and Au circuit layer [23,24]. In Figure 14d–e, a chlorine RIE and wet etch combined procedure is used to remove the aluminum layer and the chromium barrier layer.

**Figure 15.** (**a**) The Al-Au compounds observed (**b**) Al-Au compounds are reduced with 50 nm chromium barrier layer applied between the gold and aluminum layer (**c**) 80 nm chromium barrier layer prevented Al-Au to produce.
