*3.2. Power Amplifier*

The schematic of the LO driving power amplifier and the HPF is shown in Figure 4. The power amplifier adopts a three-stage common-source structure to obtain sufficient power gain at 41–51 GHz while ensuring high power-added efficiency (PAE) [16]. The first two driver stages use a 4 × 25 μm pHEMT transistor to obtain sufficient gain, and the final power stage uses a larger 4 × 50 μm pHEMT transistor to obtain a sufficiently high output power. Source degeneration inductors are connected to the source of the pHEMT transistors to increase the stability of the power amplifier. The input matching network of the power amplifier is co-designed with the previous frequency selective BPF. The output matching network is co-simulated with the following HPF in full wave electromagnetic simulation. All transistors are biased with a shunt by-pass capacitor and a series resistor close to the gate, and the dc power (Vdd) is feeded through an LC network to the drain.

**Figure 4.** Schematic of the power amplifier with HPF.

For the power amplifier used in the LO chain, a key indicator is the out-of-band suppression. For the channel emulator, the requirements for the suppression of each harmonic in the LO chain are higher, because this out-of-band clutter will degrade the dynamic operating power range of the channel emulator. Therefore, the fifth-order HPF is employed after the power amplifier. As depicted in Figure 5, an additional 25 dBc forward fundamental signal rejection can be obtained with the HPF. The 2nd harmonic is suppressed by 10–25 dBc, while the 4th and 5th harmonics are amplified with low gain by tuning matching networks to make the out-of-band gain drop slope as steep as possible. The simulated input and output return loss of the power amplifier is better than −10 dB in the 41–51 GHz frequency band, and the small-signal gain is around 20 dB. Saturated output power varies from 17 dBm to 18.8 dBm including the insertion loss of the HPF. The circuit draws a total current of 102 mA at 3.3 V power supply with −0.4 V gate bias.

**Figure 5.** Simulated S-parameters of the LO driver power amplifier with or without HPF.
