*4.2. Circuit Simulations*

The proposed OTA was simulated within the Cadence Virtuoso environment assuming a supply voltage of 0.3 V and an output load capacitance of 50 pF.

Referring to the open-loop simulation test bench the differential gain (magnitude and phase) was evaluated as reported in Figure 6. As can be observed from the figure, the phase margin is about 52.40°, whereas the gain-bandwidth product is about 35.16 kHz. Figure 6 also shows the common mode gain in typical conditions.

**Figure 6.** Differential (solid) and common mode (dashed) gain of the proposed OTA.

Figure 7 confirms that the bias currents of all the three stages of the OTA are accurately set and are also very stable for an input signal amplitude going rail-to-rail in closed-loop unity-gain configuration.

**Figure 7.** Biasing currents of the three stages vs. input common mode level.

The amplifier was then tested in unity-gain configuration and its transfer characteristic is reported in Figure 8, highlighting the rail-to-rail capabilities of the OTA.

**Figure 8.** Unity-gain amplifier transcharacteristic.

Sinusoidal waves at different amplitudes and with a frequency of 200 Hz were used to excite the unity-gain amplifier and evaluate distortions. The OTA exhibits very good total harmonic distortion (THD), also with an input signal swing equal to the supply voltage (as depicted in Figure 9). As can be observed from Figure 9, when a 90% signal swing is considered, the THD is about 0.673%, whereas when a full-swing signal is used the THD is still good and equal to about 1.38%. Furthermore, to assess the slew-rate (SR) performance of the amplifier, a full range square wave was used, and results are shown in Figure 10. The amplifier shows positive and negative slew-rate (SR*<sup>p</sup>* and SR*n*) equal to 18.61 and 11.51 V/ms, respectively. Though not symmetrical, the worst-case slew-rate is not much worse than the best one, hence large-signal performance is good on both signal edges.

**Figure 9.** THD vs. amplitude of the input signal in unity-gain configuration.

**Figure 10.** Response to square input wave.

The input-referred noise spectrum of the proposed OTA is reported in Figure 11 and shows a value of about 1.60 <sup>μ</sup>V/√Hz at 1 kHz.

**Figure 11.** Input-referred noise of the proposed OTA.

*4.3. Robustness to Mismatch and PVT Variations*

The OTA was then extensively tested by means of parametric and Monte Carlo simulations to demonstrate its robustness to PVT and mismatch variations. Table 2 reports

the results of 200 Monte Carlo iterations. Power dissipation (P*D*) has a standard deviation lower than the 10% of the mean value. Large-signal performance (i.e., *SRp* and *SRm*) is close to the nominal value, whereas the attained mean value of the phase margin *m<sup>ϕ</sup>* is about 53°. The standard deviation of the offset is relatively large, confirming the suboptimal performance in terms of noise and offset of the proposed OTA. Its value is however similar to other ULV OTAs reported in the literature.

**Mean StdDev Min Max** P*<sup>D</sup>* (nW) 20.85 1.44 16.6 24.34 Idiss (nA) 69.50 4.80 55.33 81.13 Offset (mV) 3.84 15.46 −30 50 SR*p* (V/ms) 18.54 0.30 17.84 19.42 SR*m* (V/ms) 11.63 0.34 10.82 12.52 Gain (1 Hz) (dB) 51.48 1.22 49.59 56.49 CMRR (dB) 42.11 10.44 27.84 98.85 PSRR (dB) 56.13 2.12 48.05 56.39 Mphi (deg) 53.08 6.27 38.25 74.98 GBW (kHz) 32.72 8.42 11.54 49.33 THD (%) 0.74 0.57 0.51 2.61

**Table 2.** Performance under mismatch variations.

Figure 12 reports the histogram of the CMRR that clearly shows a log-normal distribution, probably due to the sub-threshold operating condition of the circuit. The architecture exhibits a CMRR up to 98dB for some iterations (as expected from theoretical results in Section 3.2), and remains relatively high under mismatch variations, with a mean value of about 42 dB.

**Figure 12.** Histogram of the common mode rejection ratio (CMRR) of the proposed OTA for 200 Monte Carlo mismatch iterations.

The power supply rejection ratio (PSRR) of the proposed OTA is also quite good despite the very low supply voltage. Figure 13 reports the histogram of the PSRR, that shows a mean value of about 56.13 dB with a limited variation under mismatch.

**Figure 13.** Histogram of the power supply rejection ratio (PSRR) of the proposed OTA for 200 Monte Carlo mismatch iterations.

The performance under PVT variations was investigated taking into account a ±10% supply voltage variation and a [0, 70] °C temperature range. In Table 3, the performance under temperature variations is summarized. Total power consumption, the gain-bandwidth product as well as noise and total harmonic distortion are adequately stable across the considered temperature range. However, it is evident from Table 3 that the differential gain and CMRR degrade at high temperatures; this is probably due to variations in the bias point of *stage*<sup>2</sup> and in particular in transistors *M*4*<sup>A</sup>* and *M*4*<sup>B</sup>* entering the triode region. A temperature-dependent current biasing approach would probably allow achievement of better results, but this has not been considered in this work. Furthermore it has to be noted that an ideal constant current source was considered: while such generator can be devised (e.g., see [49], or using a higher supply voltage for the current reference), this clearly remains a critical issue, dependent on the application environment of the OTA.

**Table 3.** Performance vs. temperature variations.


‡ Computed at 1 kHz.

Table 4 shows that the amplifier is stable under power supply variations, with power dissipation and slew-rate increasing significantly with the supply voltage, whereas CMRR improves at lower supply voltages due to the following design centering approach.


**Table 4.** Performance vs Voltage Variations.

‡ Computed at 1 kHz.

The OTA was then tested under different process corners and results are reported in Table 5. As is evident from Table 5, the proposed OTA shows good performance, even assuming the worst case process conditions.


‡ Computed at 1 kHz.
