**5. Simulated Results**

The bootstrapped bulk-driven voltage buffer in Figure 2b, the linearized transconductor in Figure 7, and the second-order *Gm*-*C* BPF in Figure 10 have been designed in 180 nm CMOS technology to operate with a single-supply of 0.6 V. The simulated results corresponding to the voltage buffer have already been provided in Section 2 in order to demonstrate its principle of operation and, hence, the metrics corresponding to the other two blocks are described here.

The sizes of the main transistors involved in the implementation of the linearized transconductor are reported in Table 2, whereas the value of capacitors *CG*<sup>1</sup> and *CG*<sup>2</sup> was set equal to 0.25 pF. The circuit was biased with a current *IB* = 100 nA and the value of the voltages *VBULK* and *VTUN* was nominally set equal to 400 mV. In addition, a load capacitor of 1 pF was connected to the output terminal. The transconductor was first characterized at low frequency, as the bootstrapped structure is not DC coupled. The effective transconductance, *Gm*,*eff* , was simulated and is represented in Figure 11 as a function of the input DM voltage when the value of the tuning variable *VTUN* is swept from 200 mV to 600 mV. As observed, the transconductance can be programmed in a range of approximately 5×, showing a linearized behavior, even though some dependence on the level of the input signal can also

be noticed, as predicted by (12). The open-loop frequency response of the transconductor is illustrated in Figure 12, where the magnitude and the phase of the voltage gain are represented. The low frequency corner due to the bootstrapping network is located at around 2.5 Hz, whereas the voltage gain in the low frequency band is 54.2 dB with a unity gain frequency is equal to 94.2 kHz and a phase margin of 85.6º. The low frequency corner achieved is compatible with the frequency range of interest in the intended application. If, for any reason, a lower cutoff frequency is required, a larger value for the gate capacitor *CG* or the pseudo-resistor MG in the bootstrapping network has to be implemented, as already indicated in Section 2. The stability of the transconductor is easily ensured with the value of the load capacitor selected, as the phase margin ranged between 83.5º and 87.6º when *VTUN* was swept in the range [200 mV, 600 mV]. The transient behavior to a square wave of the *Gm* cell connected in unity-gain non-inverting configuration allowed for confirming its stability.


**Table 2.** Aspect ratios (μm/μm) for the main transistors of the transconductor in Figure 7.

The robustness of the proposed transconductor has been checked by considering in the simulations mismatches as well as process, voltage, and temperature (PVT) variations. In particular, a 1000-run Monte Carlo analysis with process and mismatch variations in a 3-*σ* range has been carried out. Under these stringent mismatch conditions, the values of the open-loop voltage gain, unity-gain frequency, and phase margin were found to be 45.0 ± 12.0 dB, 131.9 ± 17.9 kHz, and 83.7 ± 25.2º. In addition, the closed-loop BW of the transconductor was 110.0 ± 24.1 kHz. In all of these results, the data are represented as the mean value plus/minus the standard deviation. Corner analyses were also run in order to determine the impact of PVT variations on the performance of the transconductor. For the active devices' typical mean (*tt*), fast-fast (*ff*), slow-slow (*ss*) fast-slow (*fs*), and slow-fast (*sf*) conditions were considered, whereas the values of the passive components were varied between the minimum and maximum ranges indicated by the foundry. Additionally, the supply voltage was varied ±10% and the temperature, with nominal value equal to 27 ºC, was moved in the range between −20 ºC and 80 ºC. Considering a total of 45 corners, the open-loop gain, unity-gain frequency, and phase margin varied in the ranges [41.8, 55.6] dB, [84.8, 101.1] kHz, and [84.8, 86.4]º, the closed-loop BW being constrained between 61.4 kHz and 125.4 kHz.

The overall performance of the transconductor is summarized in Table 3, where is it also compared to other similar solutions previously reported. The following figure-of-merit (FoM) has been used for a fair comparison of the transconductors:

$$FoM\_T = 100 \cdot \frac{BW \cdot \mathbb{C}\_L}{P} \tag{17}$$

where BW is the bandwidth of the transconductor connected in non-inverting unity-gain configuration, *CL* is the load capacitor, and *P* the power consumption. As observed in Table 3, the proposed low-voltage linearized transconductor is competitive in terms of the *FoMT*, whereas it presents a high open-loop gain at low frequency and provides the largest BW in the comparative.

**Figure 11.** Effective transconductance of the linearized transconductor vs. *vI*,*DM*.

**Table 3.** Simulated performance of the linearized transconductor and comparison with other similar solutions previously reported.


The BPF was implemented by using four transconductors exactly equal excluding the linearization active resistor. Indeed, blocks *Gm*<sup>1</sup> and *Gm*<sup>4</sup> have a nominal transconductance nominally equal to *Gm* and, thus, the sizes of devices MR1 and MR2 correspond to those indicated in Table 2, that is, 1/0.5 μm/μm. Nevertheless, as circuit sections *Gm*<sup>2</sup> and *Gm*<sup>3</sup> were sized with a transconductance equal to 4*Gm*, transistors MR1 and MR2 in these cases were provided with aspect ratios equal to 3.8/0.5 μm/μm. The biasing current for all the transconductors was set again equal to 100 nA, leading to a total DC power consumption of 2.74 μA. The capacitors in the BPF were implemented as metal–insulator– metal devices, with equal values *C*<sup>1</sup> = *C*<sup>2</sup> = 25 pF. With these transconductance and capacitor ratios, the quality factor of the BPF was nominally set equal to 4. The reason for selecting relatively high capacitor values is to separate the filter center frequency from the secondary poles of the transconductors, thus avoiding as much as possible any overdamping in the frequency response.

The magnitude response of the BPF over the frequency is depicted in Figure 13 for different values of the tuning variable *VTUN*. As observed, the filter center frequency ranges between 6.5 kHz and 37.5 kHz, which demonstrates that the tuning mechanism results are suitable to avoid the parameter variations due to the fabrication process with a very economical implementation. When *VTUN* = *VBULK* = 400 mV, the center frequency is equal to 19.1 kHz. The gain of the BPF at the center frequency, nominally set equal to 0 dB as already indicated in (16a), increases slightly as the value of *VTUN* is decreased, due to the slight overdamping caused by the approaching of *f*<sup>0</sup> to the position of the secondary poles in a system with a relatively high quality factor. The noise of the BPF has been integrated in the −3-dB band for the same tuning conditions previously indicated, obtaining a value of 190.5 μV*rms*. Furthermore, the −40-dB THD criterion has been used to determine the maximum input signal amplitude that can be processed with a given linearity, obtaining a maximum amplitude of 55 mV. At this point, it is interesting to mention that the large value of the time constant associated with capacitor *CG* and pseudo-resistor MG in the bootstrapping network leads to a transient response in the BPF output signal of around 1 s before the steady-state regime is achieved. Additionally, the compression curve of the BPF output signal and the third-order intermodulation distortion are represented in Figures 14 and 15, respectively. The IMD3 has been obtained by applying two input tones separated ±100 Hz with respect to the BPF center frequency. In addition, from Figure 14, the input-referred 1-dB compression point has been determined to be −19.13 dBm.

**Figure 13.** Magnitude response vs. frequency of the BPF for different values of *VTUN*.

**Figure 14.** Compression curve of the BPF.

**Figure 15.** IMD3 vs the input signal.

The impact of mismatches and PVT variations on the response of the proposed BPF has been estimated by means of Monte Carlo and corner analyses in the same conditions as described in the case of the linearized transconductor. Regarding Monte Carlo simulations, the center frequency demonstrated itself to be very stable, with a value of 19.4 ± 1.3 kHz, showing worst-case responses equal to 16.1 kHz and 20.7 kHz in the corners.

The performance of the proposed BPF is reported in Table 4, where it is compared to other similar solutions previously reported. In order to establish an objective comparison between the different BPF structures, the following FoM has been used [7]

$$FoM\_{BPF} = \frac{P \cdot V\_{DD}}{n \cdot f\_0 \cdot DR} \tag{18}$$

where *P* is the power consumption, *VDD* the supply voltage, *n* the filter order, *f*<sup>0</sup> the center frequency, and DR the dynamic range. It is worth pointing out that the DR has been calculated as the ratio of the input signal leading to a THD of −40 dB and the in-band input-referred integrated noise. As observed, the proposed approach features a reduced power consumption in a low supply voltage, which results in being very suitable for bioimpedance-based IoT applications. In addition, the FoM is competitive as compared to the other solutions, with an acceptable DR taking into account the stringent operating conditions at the used supply voltage.


**Table 4.** Simulated performance of the proposed *Gm*-*C* filter and comparison with similar BPF solutions.

<sup>∗</sup> Simulated, † @ −40 dB THD, ‡ @ 1-dB compression point.
