*3.1. Dynamic Comparators Using Standard Logic Circuitry*

A fully synthesizable dynamic voltage comparator was proposed by Weaver et al. in [19]. As depicted in Figure 7, the circuit relies on a two cross-coupled 3-input digital NAND gates and, when two NANDs are connected, assuming that the common-mode voltage of the input signal is high enough to cut off the input *PMOS* devices, an analoginput comparator is created. When the clock is low, the outputs are reset to the positive supply rail, *VDD*, and when the clock goes high, the outputs start to discharge through the *NMOS* devices. Since the discharging rate is proportional to the input, once one of the outputs achieves a value below than the threshold voltage, the cross-coupled connection forces the outputs to assume the supply rail values. A static SR latch is also used to hold the output decision and it is buffered by an inverter to reduce the memory effect.

**Figure 7.** GATE-based comparator proposed by Weaver et al. [19].

In spite of being suitable for an all-digital implementation, this circuit is sensitive to the input common-mode range. Consequently, the usage of this comparator is restricted to stochastic ADCs [20].

Replacing NAND gates with NOR gates, as shown in Figure 8, the comparator only operates correctly if the input common-mode voltage is close to the ground. Thus, merging the 3-input NAND with 3-input NOR solutions, a rail-to-rail dynamic voltage comparator was proposed in [20]. In this case, NAND gates operate correctly for the portion of the common-mode towards *VDD*, while NOR gates work properly for the portion towards the ground.

**Figure 8.** NOR-based comparator that was merged with the NAND-based circuit (shown in Figure 7), producing the proposed rail-to-rail dynamic voltage comparator by Aiello et al. described in [20].

Ojima et al. proposed an NAND-based 4-input clocked comparator to achieve a fully synthesizable SAR ADC [21]. As Figure 9 shows, the four 3-input NAND gates define the preamplifier and the first latch stage (the output of one pair of preamplifiers is fed back to the input of the other pair), while the following 2-input NAND gates form the second latch stage, enhancing the comparator gain and reducing the comparison time. In this scheme, the comparison is carried out on the basis of (*VIN* <sup>+</sup> + *VDAC* <sup>+</sup>) and (*VIN* <sup>−</sup> + *VDAC* <sup>−</sup>).

In the previous scheme, when the *Vin* was low and the *clk* was disabled, the reset path of the *NMOS* of the preamplifier was cut off. Consequently, a residue voltage remained at the drain node that could be amplified during the next comparison, generating an error output. To resolve that, it was proposed to replace the NAND gates with OR–AND inverter (OAI) cells [6]. Thus, an explicit reset is performed on the drain nodes, eliminating the residue voltages and thereby reducing the probability of a wrong output.

On the basis of the described 4-input solution [6], a 2-input comparator based on the same OAI cells was designed (Figure 10). In addition to the obvious reduction in complexity and power dissipation, because fewer transistors are used, this topology presents satisfactory characteristics (comparison time, noise, and output error probability) for simple ADC topologies such as SAR-ADCs and digital-ΔM, both with NS.

**Figure 10.** OAI-based comparator with 2 inputs.

Recently, different works have been proposed with the goal of achieving rail-to-rail dynamic voltage comparators with good energy efficiency [22,23].

#### *3.2. Inverter-Based OTA Topologies*

Amplifiers are also difficult to design and to port between technologies. Thus, standard-cell-based synthesizable solutions have been drawing attention in recent years. Inverter-based switched-capacitor (SC) circuits are one possibility that has been deeply studied due to the inherent simplicity and capability to operate with low *VDD*, in contrast with other operational transconductance amplifiers (OTAs).

A simple inverter allows for a push–pull operation, a large output swing (OS), and good energy efficiency. Furthermore, both devices contribute to global transconductance [24]. However, taking into consideration that the inverter does not have an explicit reference virtual ground, different cancellation techniques have been investigated to compensate the offset voltage, *Voff* , and reduce its impact [25].

The technique proposed by Nagaraj et al. in [26] is one of the most used approaches. Besides the offset impact reduction, it requires a lower gain specification, facilitating its design. In this scheme, depicted in Figure 11, while capacitors *CS* and *CF* perform the integration, the *CNAG* is used to compensate for the finite gain error and *Voff* [25–27].

**Figure 11.** Scheme of the SC integrator proposed by Nagaraj et al. [26].

There are some relevant specifications with which OTAs need to comply in order to render them good candidates for employment in ADCs, namely, the gain and its linearity over *Vout*, since it affects ADC linearity, low complexity, and good energy efficiency. These are fundamental requirements to be observed, especially for IoT and fully synthesizable applications.

Thus, the key performance parameters of three different OTA topologies were evaluated in [28]. The circuits, *OTA 1*, *OTA 2* and *OTA 3*, can be described as follows:


As summarized in Table 2, there are significant differences between these three OTA circuits. Since a cascade of inverters was used in *OTA 2* and *OTA 3*, a higher DC gain was achieved. However, this also increased the complexity. Furthermore, the RC network utilized in *OTA 2* as CMFB increased the current consumption. Regarding the linearity over *Vout*, significant differences were also noticed with *OTA 2* and *OTA 3* being the best options when the linearity of the OTA is extremely important in the system, such as in the case of ADCs.

**Figure 12.** *OTA 1*: a pseudodifferential inverter-based Nagaraj integrator with a fully passive SC CMFB circuit [24].

**Figure 13.** *OTA 2*: a pseudodifferential with a three-stage multipath inverter-based Nagaraj integrator [29].

**Figure 14.** *OTA 3*: a single path three-stage pseudodifferential Nagaraj integrator using a fully passive SC CMFB circuit [28].


**Table 2.** Dynamic performance for the three described inverter-based OTA topologies.

<sup>1</sup> Considering 2/3 of the full-scale output.
