*2.3. Stage*<sup>3</sup>

The topology of stage3 is shown in Figure 5. This stage combines the signal behavior of an inverter-based pseudo-differential pair (Arbel topology) with differential-to-singleended conversion through the body current mirror and robust biasing, and is composed by an n-input and a p-input stage similar to that of Figure 4, but without diode loading, connected together. The signal is applied to the gates of two PMOS and two NMOS devices, respectively *M*6*A*, *M*6*<sup>B</sup>* and *M*8*A*, *M*8*B*, and the body-diode connections in *M*6*<sup>A</sup>* and *M*7*<sup>B</sup>* implement body-driven current mirrors performing differential-to-single-ended conversion and common mode current cancellation. Transistors *M*5*A*, *M*5*<sup>B</sup>* and *M*7*<sup>A</sup>* and *M*7*<sup>B</sup>* act as current sources and are exploited to set the bias current in all the branches of the third stage through *VGP* and *VGN*, respectively; thus, each transistor has a well-defined bias point.

**Figure 5.** Stage3 used in the proposed OTA architecture.

### *2.4. Architectural Considerations*

It has to be noted that, referring to the proposed architecture, at the interfaces between stage1 and stage2 and between stage2 and stage3, we have a body-to-gate (B2G) connection. These B2G connections result in lower voltage gain with respect to the conventional drainto-gate connections, but the lower gain allows avoidance of high-impedance internal nodes, and therefore compensation capacitors. In fact, even if each B2G interface generates a pole (as shown in Appendix A), it is placed at a much higher frequency than the one given by the output stage, which provides the dominant pole.
