**3. Design Considerations**

The main features of the FD IA proposed are analysed and discussed in view of the fundamental performance, in order to facilitate the design procedure. In a FD implementation, the CM signal must be processed at least with the same accuracy and speed as the DM signal. Therefore, the CMFB network, in particular, and the CM feedback loop, in general, must be designed so that the open-loop gain (LG) and gain-bandwidth product (LGBW) of both components are similar [30]. This requirement can be analytically expressed as

$$LG\_{CM} \simeq LG\_{DM} \tag{7a}$$

$$LGBV\_{CM} \simeq LGBV\_{DM} \tag{7b}$$

Therefore, it is recommendable to provide similar paths to the DM and the CM signal in order to accomplish these requisites. In the case of the IA represented in Figures 3 and 4, the output branch of the core circuit (Figure 3) is common to both the DM and the CM section. Nevertheless, the differential input stage of each loop, and hence the corresponding effective transconductance, is different in every case. Indeed, for the DM signal, the input transconductance is given by (4), whereas for the CM component the transconductance is equal to the individual transconductances of transistors MCM1 to MCM4 in Figure 4. As the linearization carried out in *GmI* implies a reduction of the transconductance value, it is expected that effective input transconductance of the DM loop is lower as compared to the CM loop. This fact ensures that an appropriate treatment of the DM signal will result in an adequate processing of the CM signal.

Regarding the signal processing of the FD IA, only the DM component gives rise to an output current in the input and output *V*-to-*I* converters, being the CM signal rejected by the differential structure of these stages. However, a CM signal can also produce an output current, given that the presence of mismatches is unavoidable in a real implementation. In order to evaluate the impact of the join action of a CM signal and the mismatches on the output current produced, the residual transconductance of the input and the output transconductor in the IA, defined as <sup>Δ</sup>*Gm* <sup>≡</sup> *<sup>i</sup> vCM* , has been analytically calculated. With this purpose, each small signal parameter *gi* has been assumed to have values equal to *gi* + Δ*gi*/2 and *gi* − Δ*gi*/2 for a given pair of ideally matched transistors. In addition, the contributions to the residual transconductance, due to considering mismatches in every

pair of transistors, have been evaluated individually. The corresponding expressions were obtained by means of a hand analysis and the main terms were determined by simulations, resulting to be dominant the responses associated to mismatches in the transconductance (Δ*gm*) and output conductance (Δ*go*) of the input driver transistors, MDI and MDO. The corresponding expressions are:

$$\Delta G\_{m}|\_{\Delta \mathcal{G}\_{m,MD}} \approx \frac{2}{R} \cdot \frac{\Delta \mathcal{G}\_{m,MD} \mathcal{G}\_{o,MD}}{\mathcal{G}\_{m,MD}^2} \cdot \frac{1}{\left[1 + \frac{2}{R} \frac{1}{\mathcal{G}\_{m,MD}} \left(\frac{\mathcal{G}\_{o,MD} + \mathcal{G}\_{o,MD}}{\mathcal{G}\_{m,MD}}\right)\right]} \tag{8a}$$

$$
\Delta G\_{\rm m}|\_{\Delta \mathcal{G} \Rightarrow MD} \approx \frac{2}{R} \cdot \frac{\Delta \mathcal{G}\_{\rm o, MD}}{\mathcal{G}\_{\rm m, MF}} \cdot \frac{1}{\left[1 + \frac{2}{R} \frac{1}{\mathcal{G}\_{\rm m, MD}} \left(\frac{\mathcal{G}\_{\rm o, MD} + \mathcal{G}\_{\rm o, MD}}{\mathcal{G}\_{\rm m, MF}}\right)\right]} \tag{8b}
$$

where MD represents the driver transistors in *GmI* and *GmO*. The impact of the transconductance and output conductance mismatches of other transistors on Δ*Gm* is negligible and, hence, is not reported here for the sake of conciseness.

The use of the CM rejection ratio (CMRR) is a very widespread habit in order to compare the magnitude of the CM gain with respect to the DM gain. As the proposed IA has a single-stage structure, the voltage gain for DM and CM signals will be given by the product of the input transconductance and the output impedance. Assuming the same output impedance for both signal components, the CMRR of the IA can be expressed in terms of the ratio of the effective and the residual transconductance, given respectively by (4) and (8b), as:

$$\text{CMRR} \equiv \frac{G\_{mI}}{\Delta G\_{mI}} = \frac{1}{\left(\frac{\Delta\_{\text{S},nMII}\varrho\_{\text{s},MDI}}{\mathcal{S}\_{m,MDI}^2} + \frac{\Delta\varrho\_{\text{s},MDI}}{\mathcal{S}\_{m,MDI}}\right)} \cdot \frac{\left[1 + \frac{2}{\mathcal{K}\_I} \frac{1}{\mathcal{S}\_{m,MDI}} \left(\frac{\mathcal{G}\_{\text{s},MDI} + \mathcal{G}\_{\text{s},MDI}}{\mathcal{S}\_{m,MDI}}\right)\right]}{\left[1 + \left(1 + \frac{2}{\mathcal{K}\_I} \frac{1}{\mathcal{S}\_{m,MDI}}\right) \left(\frac{\mathcal{G}\_{\text{s},MDI} + \mathcal{G}\_{\text{s},MDI}}{\mathcal{S}\_{m,MDI}}\right)\right]}\tag{9}$$

The most-right term in (9) represents the ratio of the load regulation effects of resistor *R* for the CM and the DM signals, respectively. Thanks to the improved response of the SSF cell, the value of these terms is very close to unity, which allows the expression of the CMRR as a function of the different mismatches in the actual implementation of the circuit. At this point it is worth to mention that, as observed in Figure 2, the structure of the input section of both the PD IA and the FD IA is the same and, hence, both structures present a similar rejection to CM signals form the architecture point of view.

Another key parameter for an IA is the noise, as it indicates the minimum signal level that can be processed. In the case of an IA for bioimpedance spectroscopy, the signal bandwidth required is usually wide and, hence, thermal noise is dominant. The spectral density of the input referred thermal noise has been analytically determined, assuming that the main contributions are due to the input *V*-to-*I* converter, and can be expressed as:

$$\frac{\sigma\_{IN,th}^2}{\Delta f} = \left[1 + \left(1 + \frac{2}{R\_I} \frac{1}{g\_{m,MDI}}\right) \left(\frac{g\_{o,MDI} + g\_{o,MDI}}{g\_{m,MFI}}\right)\right]^2 \cdot 4kTR\_I \cdot \left[1 + \frac{4}{3}(g\_{m,MDI} + g\_{m,MSII})R\_I\right] \tag{10}$$

where *k* and *T* are Boltzmann's constant and the absolute temperature, respectively. The first term in (10) represents the conversion factor for referring the noise from the resistor to the input of the circuit, and is the inverse of the load regulation effect of resistor *RI* on the SSF cell (see Equation (4)), the second factor is the thermal noise of resistor *RI*, and the last term includes the main thermal noise contributions of the devices involved in the circuit implementation of the input *V*-to-*I* converter, *GmI*. It can be inferred from (10) that the noise of the IA can be decreased by reducing the value of the source degeneration resistor *RI*, which is possible until a certain limit thanks to the use of SSF sections.

The fact of linearizing the *V*-to-*I* converters in the IA by means of a resistor, requires a given level of biasing current to achieve a given input DM voltage range with a determined linearity. In each SSF cell in the input and output transconductors, the bias current 2*IB* is split into two branches corresponding to the input and feedback transistors. As the tail current of the driver devices is fixed to *IB* by the lower current sources, a current equal to *IB* is steered towards the feedback transistors. Consequently, the maximum input DM signal that can be processed by each *V*-to-*I* converter is that leading to a current equal to zero through one of the feedback transistors. This condition can be expressed for *GmI* as

$$
\upsilon\_{I,DM\_{max}} = \pm R\_I \cdot I\_B \tag{11}
$$

(**b**)

where the voltage gain of the SSF cells has been assumed to be equal to unity. Nevertheless, this is an extreme situation that leads to switching off one of the branches of the input transconductor. Instead, a specific criterion, such as considering a given total harmonic distortion (THD) level, is assumed in a practical case to determine the value of *vI*,*DMmax* in an objective way.
