*3.4. Noise Analysis*

The noise analysis has been carried out assuming that each transistor can be modelled with only one noise current generator, which includes both thermal and flicker noise. The power spectral density of the modelled current generator can be expressed as follows:

$$S\_{n\_i} = \overline{i\_{i\_w}^2} + \overline{i\_{i\_f}^2} \tag{27}$$

where:

$$\overline{i\_{n(p)\_w}} = 4kT n\_{n(p)} \gamma g\_{m\_i} = 2qI\_d \tag{28}$$

$$\overline{d\_{n(p)f}^2} = \frac{K\_{n(p)}}{f \mathbb{C}\_{ox}} \frac{\mathcal{G}^2}{WL} \tag{29}$$

Taking into account that the noise sources due to stage3 can be neglected due to the high gain of the preceding stages (considering also the contribution of the tree structure), the equivalent input noise mainly results from the first two stages and can be expressed as follows:

$$S\_{v\_{eq}} = \frac{S\_{n\_1} + S\_{n\_2}}{2 \, g\_{mb\_1}^2} + \frac{1}{4 \, g\_{m\_4}^2} \cdot \frac{\mathcal{S}\_{mb\_2}^2}{\mathcal{S}\_{mb\_1}^2} (S\_{n\_3} + S\_{n\_4}) \tag{30}$$

As it can be observed from Equation (30), the noise performance of the amplifier is worsened by body driving, which shows a transconductance gain (i.e., *gmb*) which is *n*-times lower than *gm*. Consequently, in order to reduce the equivalent input noise, larger transistors are required. The result in Equation (30) can be written in a less concise form as:

$$S\_{v\_{eq}} \approx \frac{1}{16} (4S\_{no1} + \frac{2S\_{no2}}{A\_V^2}) \tag{31}$$

where

$$S\_{no1} = \frac{2}{\mathcal{S}\_{mb\_1}^2} (S\_{n1} + S\_{n2}) \tag{32}$$

and

$$S\_{n\alpha2} = \frac{2}{g\_{m\_4}^2} (S\_{n\_3} + S\_{n\_4}) \tag{33}$$

are the input-referred noise spectra for the first and second stage (contribution of the single cell). Factor 16 in the denominator of (31) accounts for the 2(*N*−1) gain contribution of a N-level tree architecture, whereas the factors 4 and 2 in the numerator consider how many identical cells are present.

#### **4. Amplifier Design and Simulation Results**

The proposed OTA has been designed and simulated in a 130 nm CMOS process from STMicroelectronics. Small-signal and large-signal figures of merit (FoMs) were used to compare it against recently published OTAs with supply voltages lower than 0.5 V. Extensive parametric and Monte Carlo simulations were carried out in order to assess the robustness of the amplifier to PVT variations and mismatch referring to both open-loop and closed-loop simulation test benches.

### *4.1. Sizing*

The transistors in the stages implementing the architecture in Figure 1 were sized as reported in Table 1. The bias voltages *VGN* and *VGP* in Figures 2, 4 and 5, are generated by the biasing circuit shown in Figure 3. Moreover, the sizing of the NMOS transistors *M*9*<sup>A</sup>* and *M*9*<sup>B</sup>* and of the PMOS transistor (*M*10) of the biasing circuit are reported in Table 1. The voltages *VGN* and *VGP* propagate the bias current, *IB* = 4 nA, through body-mirroring or gate-mirroring.


