**Appendix A**

Verilog netlist of the proposed OTA is as follows: *'timescale 1 ns/1 ns*

*module OTA ( inout REF, inout Vim, inout Vip, inout Vout );*

*IV\_X20 I24 ( .Z(feed), .A(CM)); IV\_X20 I15 ( .Z(net8), .A(Vop1)); IV\_X20 I14 ( .Z(Vout), .A(net8)); IV\_X20 I13 ( .Z(net8), .A(net8)); IV\_X20 I12 ( .Z(Vout), .A(Vom1)); IV\_X20 I10 ( .Z(Vop1), .A(Vim)); IV\_X20 I9 ( .Z(Vop1), .A(feed)); IV\_X20 I8 ( .Z(Vom1), .A(feed)); IV\_X20 I7 ( .Z(feed), .A(feed)); IV\_X20 I2 ( .Z(CM), .A(CM)); IV\_X20 I0 ( .Z(Vom1), .A(Vip)); IV\_X80 I32 ( .Z(feed), .A(REF)); IV\_X80 I3 ( .Z(CM), .A(Vop1)); IV\_X80 I1 ( .Z(CM), .A(Vom1));*

*endmodule*
