*2.1. Delta Modulator (*Δ*M) ADC*

In a patent from 1946 submitted by Deloraine et al., delta modulation was referred to for the first time as a method to transmit analog data by means of a one-bit code [9].

As shown in Figure 1a, the basic ΔM transforms an analog input signal, *Vin*, into a synchronous digital output, *Dout*. It employs a 1-bit quantizer, a digital-to-analog (D/A) converter (DAC), and an integrator in the feedback path as an attempt to anticipate the input signal. Thus, this integrator acts as a predictor [10].

**Figure 1.** ΔM ADC: (**a**) block diagram and (**b**) illustrative magnitude of STF, NTF and *Smax*.

Noise can negatively impact ΔM performance in two different ways: through granular noise or slope overload. While the former results from the quantization of a continuous signal (the signal is forced to assume a discrete value), the latter is dominant when the step size of the integrator is too small, resulting in the incorrect tracking of the input signal [10,11].

Despite the good robustness to transmission errors, simple filtering requirements, and low associated complexity, the nonidealities associated with the integrator in the

feedback path can limit linearity, noise performance, and system accuracy. Furthermore, the amplitude of *Vin* and ADC performance are inversely proportional to the input signal frequency, *Fin*. Therefore, as Figure 1b illustrates, while the signal transfer function (STF) and the noise transfer function (NTF) are constant, the maximal signal, *Smax*, decreases with the frequency [5].

Both noise and nonidealities can be problematic and severely restrict the maximal dynamic performance of the converter [4].

#### *2.2. SAR-ADC with Noise Shaping (NS)*

SAR-ADCs are currently one of the most popular topologies to realize A/D conversion due to their energy efficiency, low die area, and low circuit complexity [12]. However, higher resolutions are difficult to achieve without sacrificing energy efficiency.

In conventional topologies, the circuit relies essentially on a 1-bit comparator, an *N*-bit DAC, and a sample-and-hold (S/H) block. A binary-search algorithm is used to reduce the analog residue to less than one least significant bit (LSB) [13].

Like in other architectures, the most critical building block is the DAC because its nonidealities, the associated noise, and its settling time dominated by the reference settling directly affect the ADC performance. This aspect is even more crucial for high-resolution converters.

In the last decade, the introduction of oversampling and NS in the conventional SAR-ADC allowed for better higher dynamic performance beyond 14 bits of resolution (i.e., 12.5 bits of effective number of bits (ENOB)) [3]. The main idea is to use the analog residue that still remains after the SAR operation, the residue voltage (*Vres*), and integrate it to perform a NS, spreading the noise through a higher BW than the band of interest. The block diagram of a SAR-ADC employing NS is shown in Figure 2a, in which the ADC can simply be a single comparator. In Figure 2b, the STF, NTF, and *Smax* magnitudes as a function of frequency are illustrated, with the NTF slope characteristic from systems employing NS being notable.

**Figure 2.** SAR-ADC employing NS: (**a**) block diagram and (**b**) illustrative magnitude of STF, NTF and *Smax*.

Given the absence of amplifiers in the pure topology (besides the comparator), in these hybrid structures, the same strategy has been pursued, maintaining the circuit simplicity, and relaxing the specifications of the comparator and DAC [14]. Thus, different works have been proposed using passive NS structures [15–17].
