**3. Circuit Analysis**

In this section, the small-signal and large-signal performances of the proposed architecture are analyzed from an analytical point of view, and design equations for the

main performance parameters, such as gain, frequency response, slew-rate and noise, are presented to provide insight into circuit behavior.

## *3.1. Differential Gain*

Referring to the small-signal equivalent circuits of stage1, stage2 and stage3, the differential mode gain of the different stages was computed. Using the standard notation for small-signal parameters of MOS devices, the differential gain of the first stage can be expressed as:

$$A\_{vd\_1} = \frac{g\_{mb\_1}}{g\_{mb\_2}} \frac{1 + s\frac{\tau\_1}{2}}{(1 + s\tau\_1)(1 + s\tau\_2)}\tag{1}$$

where:

$$\begin{aligned} \tau\_1 &\approx \frac{2\mathbb{C}\_{\mathcal{S}^{s\_1}} + \mathbb{C}\_{\mathcal{S}^{d\_1}}(1 + \frac{\mathcal{S}^{m\_1}}{\mathcal{S}^{m\_2}}) + \mathbb{C}\_{\mathcal{S}^{d\_2}}}{\mathbb{C}\_{\mathcal{S}^{s\_4}} + \mathbb{C}\_{\mathcal{S}^{d\_4}}(1 + \frac{\mathcal{S}^{m\_4}}{\mathcal{S}^{m\_3}}) + \mathbb{C}\_{\mathcal{S}^{d\_2}} + \mathbb{C}\_{\mathcal{S}^{d\_1}} + \mathbb{C}\_{\mathcal{S}^{d\_2}}}} \tag{2} \\ \tau\_2 &\approx \frac{\mathbb{C}\_{\mathcal{S}^{s\_4}} + \mathbb{C}\_{\mathcal{S}^{d\_4}}(1 + \frac{\mathcal{S}^{m\_4}}{\mathcal{S}^{m\_3}}) + \mathbb{C}\_{\mathcal{S}^{d\_1}} + \mathbb{C}\_{\mathcal{S}^{d\_2}} + \mathbb{C}\_{\mathcal{S}^{d\_3}}}}{\mathcal{S}^{m\_2}} \end{aligned} \tag{2}$$

According to usual approximations, the pole-zero doublet in Equation (1) can be neglected.

Thereafter, the differential gain of stage2 can be derived to be:

$$A\_{vd\_2} = \frac{g\_{m\_4}}{g\_{mb\_3}} \frac{1 + s\frac{\tau\_3}{2}}{(1 + s\tau\_3)(1 + s\tau\_4)}\tag{3}$$

where:

$$\begin{aligned} \mathsf{T\_3} \approx \frac{2\mathsf{C\_{bs\_4}} + \mathsf{C\_{yd\_3}} + \mathsf{C\_{gd\_4}}}{\mathcal{S\_{mb\_4}}}\\ \mathsf{T\_4} \approx \frac{\mathsf{C\_{s^\*b}} + \mathsf{C\_{s^\*b}} + \mathsf{C\_{gd\_3}} + \mathsf{C\_{gd\_4}} + \mathsf{C\_{bs\_3}} + \frac{\mathcal{S}m\_8}{\mathcal{S}\_{out}}\mathsf{C\_{gd\_8}} + \frac{\mathcal{S}m\_6}{\mathcal{S}\_{out}}\mathsf{C\_{gd\_6}}}{\mathcal{S}\_{mb\_3}} \end{aligned} \tag{4}$$

Moreover, in this case, the pole-zero doublet in Equation (3) can be neglected.

Finally, the stage3 differential gain can be computed by neglecting the pole-zero doublets given by body–diode connections of *M*6*A*,*<sup>B</sup>* and *M*7*A*,*<sup>B</sup>* ; hence, it can be expressed as:

$$A\_{vd3} = \frac{\mathcal{g}\_{m\_8} + \mathcal{g}\_{m\_6}}{\mathcal{g}\_{out}} \frac{1}{1 + s\frac{\mathcal{C}\_L}{\mathcal{g}\_{out}}} \tag{5}$$

where it is denoted with:

$$\mathbf{g}\_{\rm out} = \mathbf{2}(\mathbf{g}\_{ds\boldsymbol{\aleph}} + \mathbf{g}\_{ds\boldsymbol{\aleph}}) \tag{6}$$

considering that *M*<sup>5</sup> = *M*<sup>8</sup> and *M*<sup>6</sup> = *M*7.

The overall gain of the amplifier can then be expressed as:

$$A\_{\rm vd\_{tot}}(s) = 4 \prod\_{i=1}^{3} A\_{\rm vd\_i}(s) \tag{7}$$

and rewritten as:

$$A\_{\rm rdl\_{tot}}(s) = 4 \cdot \frac{\mathcal{g}\_{m\_8} + \mathcal{g}\_{m\_6}}{\mathcal{g}\_{out}} \cdot \frac{\mathcal{g}\_{mb\_1}}{\mathcal{g}\_{mb\_2}} \cdot \frac{\mathcal{g}\_{m\_4}}{\mathcal{g}\_{mb\_3}} \cdot \frac{1}{\left(1 + s\frac{\mathcal{C}\_L}{\mathcal{g}\_{out}}\right)} \cdot \frac{1}{\left(1 + s\tau\_2\right)\left(1 + s\tau\_4\right)}\tag{8}$$

It is evident from Equation (8) that the output capacitance sets the dominant pole since the poles of stage1 and stage2 are at higher frequencies due to the body–diode connected loads and the smaller load capacitances.

Starting from the above results, the gain-bandwidth product (GBW) of the proposed OTA can be computed as:

$$\text{GBW} = \frac{\mathcal{g}a}{2\pi \cdot \mathcal{C}\_L} \tag{9}$$

where:

$$\mathcal{g}\_a = (\mathcal{g}\_{m\_8} + \mathcal{g}\_{m\_6}) \cdot \frac{\mathcal{g}\_{m\flat\_1}}{\mathcal{g}\_{m\flat\_2}} \cdot \frac{\mathcal{g}\_{m\_4}}{\mathcal{g}\_{m\flat\_3}} \tag{10}$$

The phase margin of the whole OTA can then be expressed as:

$$\varphi\_{\mathcal{W}} = \frac{\pi}{2} - \arctan\left(\frac{\mathcal{S}\_{\mathcal{R}}}{\mathcal{C}\_{L}} \cdot \tau\_{2}\right) - \arctan\left(\frac{\mathcal{G}\_{\mathcal{R}}}{\mathcal{C}\_{L}} \cdot \tau\_{4}\right) \tag{11}$$

According to Equation (11), the proposed OTA requires a minimum value of *CL* for stability. However, Equation (11) shows also that the desired phase margin can be set by properly designing MOS devices' size for a given load capacitor; a higher *CL* results in a smaller GBW and a larger phase margin.

#### *3.2. Common Mode Gain*

The common mode gain of stage1 was found to be:

$$A\_{\mathfrak{m}\_1} = -\frac{g\_{mb\_1}(\mathcal{g}\_{ds\_1} + \mathcal{g}\_{ds\_2})}{\mathcal{g}\_{mb\_2}\mathcal{g}\_{m\_1}} \frac{1 + s\tau\_{z\_1}}{(1 + s\tau\_{p\_{1,1}})(1 + s\tau\_{p\_{2,1}})} \tag{12}$$

where:

$$
\pi\_{z\_1} = \tau\_1 \frac{\mathcal{G}\_{m\_1}}{\mathcal{g}\_{ds\_1} + \mathcal{g}\_{ds\_2}} \quad \tau\_{p\_{1,1}} = \tau\_1 \quad \tau\_{p\_{2,1}} = \tau\_2 \tag{13}
$$

therefore, the CMRR of stage1 can be expressed as:

$$\text{CMRR}\_1 = \frac{\mathcal{g}\_{m\_1}}{\mathcal{g}\_{ds\_1} + \mathcal{g}\_{ds\_2}} \tag{14}$$

The common mode gain of stage2 is:

$$A\_{\rm rc2} = -\frac{g\_{m4}}{g\_{mb\_4}} \frac{g\_{ds3} + g\_{ds4}}{g\_{mb\_3}} \frac{1 + s\tau\_{z2}}{(1 + s\tau\_{p12})(1 + s\tau\_{p22})} \tag{15}$$

where:

$$
\pi\_{z\_2} = \pi\_3 \frac{g\_{mb\_4}}{g\_{ds\_3} + g\_{ds\_4}} \quad \pi\_{p\_{1,2}} = \pi\_3 \quad \pi\_{p\_{2,2}} = \pi\_4 \tag{16}
$$

whereas its CMRR amounts to:

$$\text{CMRR}\_2 = \frac{\mathcal{S}\_{mb\_4}}{\mathcal{S}\_{ds\_4} + \mathcal{g}\_{ds\_3}} \tag{17}$$

Stage3 shows a common mode gain of:

$$A\_{\rm rC\_3} = \frac{\mathcal{g}\_{m\_8} + \mathcal{g}\_{m\_6}}{2\mathcal{g}\_{mb\_6}} \frac{1 + s\,\tau\_{z\_3}}{(1 + s\,\tau\_{p1,3})(1 + s\,\tau\_{p2,3})} \tag{18}$$

where:

$$\tau\_{z\_3} = \frac{2\mathbb{C}\_{bs\_6} + \mathbb{C}\_{gd\_8} + \mathbb{C}\_{gd\_6}}{g\_{mb\_6}} \quad \tau\_{p\_{1,3}} = 2\frac{2\mathbb{C}\_{bs\_6} + \mathbb{C}\_{gd\_8} + \mathbb{C}\_{gd\_6}}{g\_{ds\_8} + g\_{ds\_6}} \quad \tau\_{p\_{2,3}} = \frac{\mathbb{C}\_L}{g\_{ds\_8} + g\_{ds\_6}} \tag{19}$$

and its CMRR results:

$$\text{CMRR}\mathfrak{g} = \frac{\mathcal{S}\_{\text{sub}}}{\mathcal{S}\_{d\mathfrak{s}\_{\text{8}}} + \mathcal{g}\_{d\mathfrak{s}\_{\text{6}}}} \tag{20}$$

Due to the body current mirror, the CMRR of these stages is reduced with respect to stage1. Combining the above results, the common mode gain of the proposed tree-like architecture can be derived as:

$$A\_{\text{nc\_{TOT}}} = \prod\_{i=1}^{3} A\_{\text{vc}\_i} \tag{21}$$

Finally, the CMRR of the overall OTA can be expressed as:

$$\text{CMRR}\_{tot} = 4 \prod\_{i=1}^{3} \text{CMRR}\_{i} \tag{22}$$

therefore, the total CMRR is about:

$$\text{CMRR}\_{tot} = 4 \cdot \frac{\mathcal{g}\_{m\_1}}{\mathcal{g}\_{ds\_1} + \mathcal{g}\_{ds\_2}} \cdot \frac{\mathcal{g}\_{mb\_4}}{\mathcal{g}\_{ds\_4} + \mathcal{g}\_{ds\_3}} \cdot \frac{\mathcal{g}\_{mb\_6}}{\mathcal{g}\_{ds\_8} + \mathcal{g}\_{ds\_6}} \tag{23}$$

By looking at Equation (22), it is evident that the CMRR in typical conditions is high, due both to the cascade of several stages and to the scaling factor of the tree architecture, and that it can be enhanced by further iterating the tree-like structure of the proposed OTA architecture. However, in ULV conditions, PVT variations and mismatch may impact on the stability of the operating point, especially in the presence of a B2G interface, and significantly degrade the CMRR*i*-th of the OTA. As a consequence, the CMRR of this architecture is more sensitive to PVT variations and mismatch than other architectures which adopt higher supply voltages and/or a more stable operating point. Anyway, to cope with this problem, design centering techniques are exploited in this work in order to increase the overall CMRR in a given range of PVT and mismatch conditions achieving a reasonable robustness. The above reported frequency analysis shows that the common mode gain presents some zeros that could appear before the unity-gain frequency (depending on the *CL*/*Cgs* ratio), thus reducing the CMRR at high frequency. A large load capacitance is usually required to achieve stability, therefore the resulting CMRR reduction is often limited.
