**1. Introduction**

It is known that CMOS technology scaling, together with supply voltage reduction, is principally aimed at improving the performance of digital circuits and that, in this framework, the design of analog and mixed-signal blocks becomes increasingly demanding. It is indeed very difficult to obtain high linearity and high precision under near- and subthreshold supply.

For this reason, operational transconductance amplifiers (OTAs) remain indispensable blocks for the implementation of high-accuracy closed-loop analog circuits, and several techniques have been proposed for the implementation of (ultra) low-voltage solutions. These include subthreshold-operated MOS transistors [1,2], bulk (body) driven [3,4], floating gate and quasi-floating gate MOS transistors [5,6], threshold lowering [7,8], level shifting [9], complementary pairs with body-driven gain boosting, and non-tailed pairs [10]. Additional approaches have also been proposed to replace OTAs, though not for general purpose usage, including dynamic amplifiers [11], ring amplifiers [12], and zero-crossing based circuits [13]. In addition, one interesting trend is the use of inverter-based topologies [14–28]. (A good review of the principal techniques for low-voltage OTAs can be found in the last reference.) At the basis of this approach is the single inverter (CMOS NOT gate), which is topologically simple, as it requires only two transistors between the supply rails, it provides a quite good voltage gain (though multi-stage topologies are usually required for 40 dB or more), and it exhibits class-AB and full swing operation. Therefore, it is rather effective under low supply voltages. However, the main drawback of the inverter-based solutions is related to the difficult control of the quiescent current feature that is especially required in low-power applications with a restricted current budget.

**Citation:** Ballo, A.; Pennisi, S.; Scotti, G. 0.5 V CMOS Inverter-Based Transconductance Amplifier with Quiescent Current Control. *J. Low Power Electron. Appl.* **2021**, *11*, 37. https://doi.org/10.3390/ jlpea11040037

Academic Editor: Orazio Aiello

Received: 26 August 2021 Accepted: 27 September 2021 Published: 28 September 2021

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**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

In this paper, a body-biasing technique, originally developed in [29] and utilized in [30], is applied to set the quiescent current of the generic inverter stage. Starting from this generic stage, a gate-driven, two-stage, inverter-based transconductance amplifier, suitable for switched-capacitor applications, is designed. Simulations results are also provided taking into account process and temperature variations. The proposed amplifier is designed in a 28-nm bulk process and is powered by a 0.5 V supply voltage. Typical quiescent current is 488 nA and, with a 1-pF//1.5-MΩ load, it provides 51-dB DC gain with a unity gain frequency of 1 MHz and phase margin of 70 degrees. Settling time at 1% is 6.6 <sup>μ</sup>s and white noise is 125 nV/√*Hz*.

### **2. The Proposed Solution**

Figure 1 shows the circuit schematic of the proposed amplifier. It consists of a first noninverting stage, made up of transistors M1-M6, and a second inverting stage, made up of transistors M7-M8. As it is seen, the second stage is a straight CMOS NOT gate while the first one is based also onto the NOT topology, but rearranged to invert the gain trough two complementary p-channel and n-channel current mirrors M3, M5 and M4, M6. In quiescent conditions, the input terminal is set to VDD/2 and thanks to the overall negative feedback (not shown) also the output and intermediate node, *out1*, are all biased at VDD/2.

**Figure 1.** Simplified schematic of the proposed solution.

As far as the quiescent current control of the two stages is concerned, it is implemented through the bulk terminals via voltage VBP, for p-channel transistors, and VBN, for the n-channel ones. These voltages are generated by exploiting a technique proposed in [29] and utilized also in [10,30]. The basic working principle can be inferred with the aid of Figure 2, showing the simplified schematic of the amplifier's biasing section.

MR1 and MR2 are two reference transistors both with their |VGS| equal to VDD/2. Their quiescent drain current is equal to *IBIAS* thanks to the local feedback loop operated by the auxiliary amplifiers A1 and A2, which generate the required bulk voltages, VBP and VBN, under the following summarized constraints:


**Figure 2.** Simplified schematic of the biasing section generating VBN and VBP for the main amplifier in Figure 1.

Of course, aspect ratios of MR1 and MR2 must be set so that the required bulk voltages are within VDD and ground. Moreover, the auxiliary amplifiers A1 and A2 should provide a maximum (rail-to-rail) output voltage range, whereas input common mode range is not a concern as input voltage is kept constant to VDD/2. Therefore, simple two-stage OTAs biased in subthreshold can be profitably used. An example of implementation of this type of amplifier is found in [10], albeit operating with MOSFETs in saturation.

Consider now transistor M1 of the main amplifier in Figure 1 and remember that in quiescent conditions *Vin* is equal to VDD/2. As a consequence, MR1 and M1 have respectively the same source, gate, and bulk voltage and hence the drain current of M1 is related to that of MR1 in a mirror-like condition

$$I\_{D1} = \frac{(W/L)\_1}{(W/L)\_{R1}} I\_{BIAS} \tag{1}$$

where equality is accurately verified because the source-drain voltage of M1 is also equal to VDD/2, thanks to the diode-connected transistor M4 in Figure 1 which absorbs *ID*<sup>1</sup> and is designed so that

$$\frac{\left(W/L\right)\_2}{\left(W/L\right)\_{R2}} = \frac{\left(W/L\right)\_1}{\left(W/L\right)\_{R1}}\tag{2}$$

and consequently *VGS*<sup>4</sup> = VDD/2.

Similar considerations hold for all the transistors in the main amplifier, in practice, all p-channel and n-channel devices have their current linked to IBIAS via the current-mirrorlike relations

$$I\_{Di\\_P} = \frac{(\mathcal{W}/L)\_{i\\_P}}{(\mathcal{W}/L)\_{R1}} I\_{BIAS} \tag{3a}$$

$$I\_{Dj\\_N} = \frac{(W/L)\_{j\\_N}}{(W/L)\_{R2}} I\_{BIAS} \tag{3b}$$

where (*W/L*)*i\_P* (i = 1,3,5,7) and (*W/L*)*j\_N* (j = 2,4,6,8) are respectively the aspect ratios of the generic p-channel and n-channel MOSFET in the main amplifier.

As a concluding remark, closed loop stability is ensured thanks to the conventional frequency compensation network made up of the Miller capacitor, CC, and nulling resistor, RC, around the last inverting stage.
