*2.2. Stage*<sup>2</sup>

The topology of stage2 is shown in Figure 4. This stage converts the input differential signal to single-ended providing some gain, a well defined bias point and contributing to the overall CMRR. The input signal is applied to the gates of *M*4*<sup>A</sup>* and *M*4*B*, and the bias current is set through the gates of *M*3*<sup>A</sup>* and *M*3*<sup>B</sup>* connected to the bias voltage *VGP* generated by the circuit in Figure 3. The current cancellation given by the body-to-body (B2B) current mirror (Appendix B) *M*4*A*, *M*4*<sup>B</sup>* allows to attain good common mode rejection ratio as will be better shown in the next sections. Since the output is body-loaded, also this stage doesn't show any high-impedance internal node and thus does not require any internal compensation.

**Figure 4.** Stage2 used in the proposed OTA architecture.
