**3. Validation Results**

The proposed solution was designed in a 28-nm triple-well CMOS technology provided by STMicroelectronics and simulated at the schematic level. Threshold voltages of the n- and p-channel devices were 445 mV and −462 mV, respectively. Single power supply was set to 0.5 V, IBIAS was 60 nA, and transistor dimensions, together with other component values, were set as summarized in Table 1. All p-channel (n-channel) MOSFETS are equal to the reference device 990/90 (210/90) nm/nm, except for the last stage transistors that have four times greater aspect ratios. This is important to increase the output current drive capability and the output transconductance to reduce the required value of the nulling resistor (to avoid introducing a positive zero), whose value is in the range of 1/gm2. Observe that the DC gain of the auxiliary amplifiers, A1 and A2, is around 40 dB. As a consequence of the transistor's dimension, the nominal quiescent current in each branch of the first stage is 60 nA, while it is 240 nA in the last stage, resulting in a total nominal quiescent current of 420 nA. The small-signal parameters of the amplifier stages are summarized in Table 2. Load capacitor CL was 1 pF in parallel to a load resistor of 1.5 MΩ, and the compensation capacitor and the nulling resistor were set to 1.5 pF and 50 kΩ, respectively.


**Table 1.** Design parameters used in simulations.

**Table 2.** Small signal parameters of the amplifier.


The robustness of the quiescent conditions were validated at first. The nominal bulk voltages, VBP and VBN, generated by a circuit in Figure 2 were 256.4 mV and 231.9 mV, respectively. The simulated quiescent current in the main amplifier in Figure 1 was 488 nA, on average, with a standard deviation of 93.7 nA, after running 1000 Monte Carlo iterations. The difference with respect to the expected value of 420 nA is due to the low DC gains of the auxiliary amplifiers, which cause a closed-loop gain error.

Figure 3 shows the Bode plots (magnitude and phase) of the amplifier open-loop gain at the standard temperature (27 ◦C) and nominal component models with a 1-pF and 1.5-MΩ parallel load. DC gain is 51 dB, unity gain frequency (UGF) is 1 MHz and phase margin (PM) is 70 degrees. Note that the load resistance is almost equal to ro2 in Table 2, hence causing a 6-dB reduction in the maximum achievable gain.

**Figure 3.** Bode plots (magnitude and phase versus frequency) of the amplifier open-loop gain with 1-pF and 15-MΩ parallel load.

Figure 4 shows the time transient response of the amplifier with the closed-loop gain set to −2. These plots are achieved with two feedback resistors, as in an inverting closedloop amplifier topology, one of 1 MΩ (connected between the input and output) and the other of 0.5 MΩ (connected between the signal source and the input). The almost rail-to-rail output behavior is apparent. Positive/negative settling time at 1% of the final value is symmetrical and equal to 6.6 μs.

**Figure 4.** Time response to a 240-mVp-p input step (closed-loop gain is set to −2).

Power Supply Rejection Ratio was also evaluated from both supply rails. Magnitude versus frequency of PSRR is shown in Figure 5. PSRR<sup>+</sup> was 56 dB at DC, while PSRR– was 58 dB. Equivalent input noise is also simulated and depicted in Figure 6. The white component is 125 nV/√*Hz* and is dominated by the voltage noise of transistors M1–M6 forming the input stage.

**Figure 5.** Magnitude versus frequency of the Power Supply Rejection Ratio (PSRR) from positive (PSRR+) and negative (PSRR–) supply rail. Open loop gain is also shown.

**Figure 6.** Equivalent input noise voltage spectral density.

The effect of mismatches was also simulated through 1000 Monte Carlo iterations. Table 3 summarizes the results. The largest variation is experienced by the unity gain frequency and settling times (more than 30%).


**Table 3.** Statistical analysis of main performance parameters due to mismatches (1000 Monte Carlo iterations).

<sup>1</sup> with 100-mVp-p input and in inverting unity gain configuration.

Temperature and process variations were also evaluated via corner simulations under three different temperatures (−20 ◦C, +27 ◦C and +85 ◦C). Results are summarized in Table 4. It is seen that the quiescent current is sensitive to temperature and to FF and SS corners. In particular, the total amplifier nominal current (which was approximately 488 nA) decreases to 249 nA at −20 ◦C, SS corner, and increases to 2.4 μA at +80 ◦C, FF corner. DC gain, PM and PSRR exhibit only quite negligible changes, whereas UGF and settling time are affected by these standby current variations. This problem is mainly related to the large threshold voltage excursion induced by temperature variation that cannot be counteracted by the restricted range of the bulk control voltages limited to VDD.

**Table 4.** Corner simulations (Typical, Fast-Fast, Fast-Slow, Slow-Fast, and Slow-Slow) under three different operating temperatures.

