*4.4. Simulation Results of the Stacked Receiver Front-End*

The wideband stacked receiver front-end using a clock strategy was designed and simulated in a 22 nm CMOS technology. The receiver consumes 2.4 mA from a 1.2 V supply voltage.

The wideband input matching (S11) of the LNTA is shown in Figure 11, showing an S11 of less than −10 dB over a wide frequency range by switching the capacitor bank at the input balun. The capacitor bank uses 16 binary weighted codes. The rest of the simulations in this work are verified using code 8.

**Figure 10.** NFDSB of the stacked receiver with the 1/ *f* NC circuit enabled and disabled.

**Figure 11.** The stacked receiver input matching (S11) performance versus RF.

The receiver-performance, integrated NFDSB from 100 kHz to 50 MHz, conversion gain and input-referred third-order intercept point (IIP3) versus *fLO*, which is equivalent to an RF input signal of 4 × *fLO*, from 2.2 GHz to 3.2 GHz, is shown in Figure 12 . It shows that the NFDSB varies in terms of frequency from almost 4.5 dB to 6.3 dB. On the other hand, the conversion gain varies from almost 34.5 dB to 36 dB as *fLO* is increased. A constant feedback resistor is used in the TIA. To perform IIP3 simulation, a two-tone signal at 4 × *fLO* + 10 MHz and 4 × *fLO* + 11 MHz is applied at the input of the LNTA. This generates two third-order intermodulation products at 9 MHz and 12 MHz, along with two fundamental products at 10 MHz and 11 MHz. The IIP3 performance varies over *fLO* from −21 dBm to −17.5 dBm.

The harmonic rejection can be affected by transistor and layout mismatch. The effect of the transistor process and mismatch variation is verified using Monte-Carlo simulation over 100 runs, and the results are shown in Figure 13. The HR1, HR2, ... HRn (n = 7) are the 1st, 2nd, ... nth harmonics rejected relative to the 4th harmonic, which is the wanted signal in this work. The harmonic rejection in the stacked receiver front-end architecture is much less than the cascaded receiver architecture. The minimum rejection is achieved in HR5 with a 61 dB rejection using a 3× sigma calculation.

**Figure 12.** The stacked receiver NFDSB, conversion gain, and IIP3 performances versus *fLO*.

**Figure 13.** *HRn* performance of the stacked receiver over 100 runs.

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### **5. Discussion**

Table 2 provides a performance summary and comparison of the cascaded and stacked receiver front-end using the clock strategy proposed in this work and compare them to the state-of-the-art. The cascaded receiver front-end with the clock strategy achieves a higher RF bandwidth, IIP3, and lower NF compared to the staked receiver front-end proposed in this work, while consuming almost four times current but operating at a slightly lower supply voltage of 1 V. The cascaded receiver architecture also achieved a higher RF bandwidth than work in [3,9,16] while consuming much lower power. Overall, both circuits presented in this work are suitable for wide modulation bandwidth application. The NF, IIP3, and bandwidth performance compare well with the state-of-the-art considering the power

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consumption of the presented receivers. The harmonic recombination technique verified by both receiver architectures validates the viability of the technique for different receiver architectures. The minimum harmonic rejection ratio of the cascaded, stacked receiver, refs [3,4,12,16] are approximately 134, 61, 35, 51, 80, and 52 dB, respectively. The stacked receiver architecture is better suited to very low power wireless applications with relaxed performance requirements such as Bluetooth Low Energy, while the cascaded receiver architecture can be used for a wide range of higher performance applications.


**Table 2.** Performance summary and comparison.

\* In-band IIP3 out-of-band IIP3; <sup>⊕</sup> measurement results; and simulation results.

#### **6. Conclusions**

Wideband cascaded and stacked receiver front-ends employing a clock strategy to down-convert an RF signal at 4× the *fLO* frequency were designed in a 22-nm CMOS process for SDR applications. The simulation results are presented showing the benefits of both architectures. The cascaded receiver front-end achieved higher bandwidth, lower NF, and better linearity performance than the stacked receiver front-end at the cost of higher power consumption. In the cascaded receiver front-end, low NF was achieved thanks to the feed-forward noise cancelling technique of the LNTA. The LNTA used by the cascaded receiver front-end operates over a frequency range from 0.4 GHz to 13 GHz. In the stacked receiver front-end, the low power consumption was achieved by sharing the current between the TIA and the LNTA using a single supply. The noise performance was also improved by using an AI and 1/ *f* noise-cancellation technique.

Thanks to the current mode harmonic recombination, both receivers do not require additional circuits for harmonic recombination, reducing the power consumption. Dynamic power consumption is ultimately reduced thanks to the clock strategy technique that downconverts an RF signal at 4 × *fLO*, reducing the clock frequency requirements. In the stacked receiver architecture, the CCC technique boosts gm by two times without consuming additional power. The LNTA and balun can be tuned over an input frequency range from 2 GHz to 6 GHz.

The wideband operation and performance metrics of the proposed front-ends make them very suitable for SDR receivers that require a wideband frequency response and good harmonic rejection performance.

**Author Contributions:** Conceptualization, A.A. and F.N.; methodology, A.A.; software, A.A.; validation, A.A.; formal analysis, A.A.; investigation, A.A.; resources, A.A.; data curation, A.A.; writing original draft preparation, A.A.; writing—review and editing, A.A. and F.N.; visualization, A.A.; supervision, A.A. and F.N.; project administration, A.A.; and funding acquisition, F.N. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research received funding from the Natural Sciences and Engineering Research Council of Canada.

**Institutional Review Board Statement:** Not applicable

**Informed Consent Statement:** Not applicable

**Data Availability Statement:** Not applicable

**Acknowledgments:** The author would like to thank CMC Microsystems for providing access to the EDA tools.

**Conflicts of Interest:** The authors declare no conflict of interest.
