**1. Introduction**

Battery-operated or energy harvested systems such as biomedical implantable devices or sensor nodes for Internet of Things (IoT) applications require the development of low voltage, low power CMOS Systems on Chip (SoCs) in which analog interface circuits are integrated together with the digital processing and communication cores [1].

In the conventional design flow of mixed-signal integrated circuits, the design and implementation of the analog building blocks is usually carried out manually by the analog designer who iterate several times each step of the design flow in order to optimize performance, power and area figures of merit.

Nowadays, due to the continuous scaling of MOS feature size in the nanometer regime, the analog designer has to cope with new challenges in the simulation and implementation steps of the design flow. In fact, the performance of nanometer MOS transistors from an analog designer perspective is worsening with technology scaling, and accurate simulation models are becoming more and more difficult to develop. These challenges often result in analog building blocks which require some form of calibration or programmability after production in order to achieve the required performance [2,3].

If we focus on the design flow of digital circuits, we see that the synthesis and place and route steps are carried out automatically by using CAD tools for the physical synthesis. The netlist of digital circuits is built by the synthesis tool and is made up only of digital gates taken from a standard cell library, which is usually provided by the IC manufacturer.

From a time to market perspective, since the standard cells commonly adopted for the digital design flow exhibits a DRC clean layout, their usage for the implementation of analog building blocks can drastically reduce the layout effort of the analog part and thus the overall time to market of mixed signal SoCs for IoT applications. In addition,

**Citation:** Palumbo, G.; Scotti, G. A Novel Standard-Cell-Based Implementation of the Digital OTA Suitable for Automatic Place and Route. *J. Low Power Electron. Appl.* **2021**, *11*, 42. https://doi.org/ 10.3390/jlpea11040042

Academic Editor: Orazio Aiello

Received: 12 October 2021 Accepted: 26 October 2021 Published: 28 October 2021

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for these reasons, recently, several architectures of mixed signal integrated circuits, suited for battery-operated or energy harvested systems that are mostly or completely based on digital standard cells, have been introduced in the technical literature [4–8].

The netlists of analog blocks, which are built using only digital standard cells, can be described using structural VHDL or Verilog languages and are suitable to be integrated in an automatic synthesis and place and route flow for digital circuits. This approach strongly reduces the design effort and brings the advantages of digital circuits, such as design and technology portability, low-voltage operation and effective area shrinkage at more advanced technology generations.

Since the standard cell libraries adopted in semi-custom digital flows allow the usage of a wide set of logic gates with different size ratios (and therefore driving capability), the analog designer can have significant design freedom for different application environments. In addition, the use of digital standard cells can heavily relax the design complexity of analog components, such as amplifiers and voltage comparators requiring ultra-low supply voltage, thus avoiding complex circuit topologies typically developed for ultra-low voltage conditions.

In this paper, we focus on the digital-in-concept approach for the design of analog differential circuits originally presented in [9] and recently exploited in [10–12], but only standard cell libraries are used. Indeed, the pioneering work in [9], which presents the first fully digital alternative to the conventional differential pair to implement low voltage analog amplifiers and comparators, still requires some passive components (resistors or floating-gate resistors). Meanwhile, the evolution of circuits in [9] presented in [10–12], despite not requiring any passive component, exploit the C-Muller element as a fundamental building block, which typically cannot be found among the digital standard cells.

The digital OTA implementation proposed in this paper does not make use of resistors, floating gate resistors nor C-Muller elements and is made up of only digital gates usually available in the standard cell libraries. Being fully standard cell-based, the proposed digital OTA implementation can be integrated in a semi-custom design flow of a mixed signal SoC, and its layout can be automatically generated as is usually done for digital blocks.

In the following, Section 2 describes the proposed standard cell implementation of the digital OTA, Section 3 reports the results of the simulations, whereas the comparison against the state of the art is discussed in Section 4. Finally, some conclusions are drawn in Section 5.
