*5.1. CMOS Inverter*

The CMOS inverter in Figure 10 is a versatile and simple circuit employed in various ULV digital circuits [6,8] and analog building blocks, such as amplifiers and oscillators [10,24].

**Figure 10.** The classic CMOS inverter.

Well-designed CMOS inverters usually present a perfect balance between the N and P networks, which means that in the voltage transfer curve, the mid-point voltage corresponds to *VOUT* = *VIN* = *VDD*/2. The CMOS inverter herein was designed to be balanced for the supply voltage *VDD* = 100 mV, room temperature and typical process parameters.

For this particular design, we chose transistors with threshold voltages lower than those of the standard transistor, which favors them in the design of ULV circuits. They are called medium-*VT* transistors, and their minimum channel length is 300 nm in this 0.18 μm technology. The PMOS and NMOS transistors were designed with channel lengths of *LP* = *LN* = 300 nm and widths of *WP* = *WN* = 600 nm. The values in Table 3 correspond to the extracted parameters of these medium-*VT* transistors for the simulation through the 4PM in Verilog-A.


**Table 3.** Corner-extracted parameters for medium-*VT* NMOS/PMOS transistors with *<sup>W</sup> <sup>L</sup>* <sup>=</sup> 600 nm 300 nm .

The design was validated through a DC analysis in Cadence by using each model (4PM and BSIM 4.5) separately. The results of the DC simulations for five different supply voltages *VDD*s at room temperature and typical conditions are depicted in Figure 11, which includes the voltage transfer characteristic (VTC), small-signal gain and short-circuit current (*ISC*). From Figure 11, it can be verified that the ACM model with only four parameters is sufficient to properly describe the electronic behavior of the classic CMOS inverter in the ULV domain.

**Figure 11.** CMOS inverter results of (**a**) voltage-transfer characteristic (VTC), (**b**) small-signal gain and (**c**) short-circuit current.

Figure 12 presents the VTC curves for the CMOS inverter across the corners of process variation for both BSIM and the 4PM at supply voltages of 100 mV and 300 mV and a temperature of 300 K. Even with variations of up to 15% and 30% in the threshold voltage and specific current, respectively, the 4PM clearly adapts to the corners and follows BSIM since the four parameters were extracted for each corner.

**Figure 12.** Voltage-transfer characteristics of the CMOS inverter using BSIM and the 4PM across the corners of process variation. (**a**) *VDD* = 100 mV. (**b**) *VDD* = 300 mV.

### *5.2. Ring Oscillator*

In Figure 13, the ring oscillator comprises *N* CMOS inverters in a loop and the load capacitance *CL* in between stages, which includes external capacitors that load each node, along with the transistors' intrinsic and extrinsic capacitances presented in Section 2.2. The load capacitance is crucial to set the frequency of oscillation and is critical for the successful start-up of the oscillator.

**Figure 13.** Ring oscillator.

According to [24], in order to facilitate the start-up of the ring oscillator in the ultralow-voltage domain, the minimum gain required to establish a condition of oscillation can be reduced by increasing the number of stages in the ring oscillator. We chose the number of stages *N* = 11, which corresponds to a minimum voltage gain of 1.04 V/V for the start-up of oscillations.

Figure 14 presents the voltage signal at one of the stages of the ring oscillator for the supply voltage *VDD* of 100 mV. Table 4 summarizes the frequencies obtained through the use of either ACM or BSIM for various *VDD* values without the inclusion of any external capacitor.

**Figure 14.** Voltage signal in the time domain at one of the stages of the oscillator. Results for BSIM and 4PM simulations at 100 mV of supply voltage.


**Table 4.** Oscillation frequency at various *VDD*s obtained through time-domain simulations of the 11-stage ring oscillator without external *CL*.

As expected, due to a lack of extrinsic capacitances associated with fringing and diode junctions [15] in the implemented dynamic model, the frequency of oscillation using the 4PM was higher than BSIM's overall. Table 4 shows that the oscillation frequency obtained through the 4PM diverged from the frequency obtained through BSIM at *VDD* = 300 mV and 400 mV for more than 200%, which suggests that the implemented dynamic model lacks sufficient information to provide frequency results closer to BSIM's in these voltages.

To further evaluate the difference in the oscillation frequency, we added the external capacitor *CL* = 1 *pF* between stages. Figure 15 presents the oscillation frequency at supply voltages from 60 mV to 400 mV.

**Figure 15.** Oscillation frequency vs. the supply voltage *VDD*.

From Figure 15 and Table 5, it can be seen that the inclusion of high-value external capacitors attenuated the effect of the capacitances inherent to the ring oscillator on the frequency response and, consequently, improved the ACM's accuracy in relation to BSIM for voltages from 200 mV to 400 mV. However, it deteriorated the results for voltages below 100 mV. Overall, the 4PM delivers a time/frequency domain result that closely matches BSIM's.

**Table 5.** Oscillation frequency at various *VDD*s obtained through time-domain simulations of the 11-stage ring oscillator with external *CL* = 1 *pF*.


These results suggest the capacitances in BSIM have a strong dependence on the supply voltage, a dependence which was not incorporated in the implemented extrinsic dynamic model, hence the observed difference in the oscillation frequency at various supply voltages.

In addition, the computational efficiency was verified by comparing the CPU transient simulation time required to simulate the oscillator with the external *CL* = 1 *pF* at the supply voltage *VDD* = 300 mV, which provides signals with similar frequencies for BSIM and ACM (*fACM*/ *fBSIM* = 1.04). The total CPU time required to run the transient analysis with BSIM was 76.25 s, while the same simulation required a total CPU time of 55.64 s using the 4PM in Verilog-A, representing 73% of the time BSIM used, which is very significant when it comes to several long simulation runs.
