**2. The Four-Parameter Model (4PM)**

The advanced compact MOSFET (ACM) model describes static and small-signal lowfrequency characteristics of MOS transistors in all regions of operation [13]. ACM employs three main transistor parameters: the specific current *IS*, the threshold voltage *VT*<sup>0</sup> and the slope factor *n*, which are usually sufficient to design a broad amount of circuits.

Nevertheless, the four-parameter model herein also employs drain-induced barrier lowering (DIBL), a secondary effect [13]. In spite of being a very pronounced effect for short-channel transistors, the DIBL cannot be ignored for long-channel transistors in weak inversions. For long-channel transistors in strong inversions (out of the scope of this work), DIBL is overshadowed by channel-length modulation.

In the long-channel ACM model [13], the drain current *ID* in Figure 1 is split into the forward term *IF* and the reverse term *IR*, both of them dependent on the voltage *VGB*. The component *IF* also depends on *VSB*, while *IR* depends on *VDB*. This source-drain symmetry is given by using (1).

$$I\_D = I\_F - I\_R = I\_S \ (i\_f - i\_r\ )\tag{1}$$

The specific current *IS*, depicted in (2), is influenced by the device's geometry and technological parameters, such as the carrier mobility *μ*, *Cox*, the slope factor *n* and temperature through the thermal voltage *φt*.

$$I\_S = \mu \mathcal{C}\_{ox} n \frac{\phi\_t^2}{2} \frac{W}{L} \tag{2}$$

The relationship between the voltages at the device terminals and the normalized inversion charge density at the source (drain) *qIS*(*D*) is established by using the normalized form of the unified charge-control model (UCCM) in (3).

$$\frac{V\_P - V\_{S(D)B}}{\Phi t} = q\_{IS(D)} - 1 + \ln q\_{IS(D)}\tag{3}$$

The pinch-off voltage *VP* can be approximated by using (4), where *VT*<sup>0</sup> is the equilibrium threshold voltage that corresponds to the gate voltage for which *VP* = 0 and for which *σ* is the magnitude of the DIBL coefficient. In the four-parameter model, the DIBL effect must comply with the MOSFET symmetry.

$$V\_P = \frac{V\_{GB} - V\_{T0} + \sigma V\_{DB} + \sigma V\_{SB}}{n} \tag{4}$$

Equation (5) gives the definition of the normalized inversion charge, which is the inversion charge (*QI*) normalized to the pinch-off charge (−*nCoxφt*).

$$q\_{IS(D)} = \frac{Q\_I}{-n\mathbb{C}\_{ox}\phi\_t} \tag{5}$$

$$
\eta\_{IS(D)} = \sqrt{1 + i\_{f(r)}} - 1 \tag{6}
$$

The voltage-to-inversion level relationship is established by applying (6) to (3), which results in (7a,b), also known as the unified current-control model (UICM). For design purposes, *if* < 1 characterizes an operation in a weak inversion (WI), while for *if* > 100, it is assumed there is an operation in a strong inversion (SI). For inversion levels between 1 and 100, it is said that the transistors operate in moderate inversion (MI).

$$I\_{F(R)} = I\_S F \left[ \frac{V\_P - V\_{S(D)}}{\Phi\_t} \right] \tag{7a}$$

$$F^{-1} = \sqrt{1 + i\_{f(r)}} - 2 + \ln\left(\sqrt{1 + i\_{f(r)}} - 1\right) \tag{7b}$$

**Figure 1.** Symbol of an n-channel MOSFET transistor and its four terminals: gate (G), source (S), drain (D) and bulk (B). Source-drain symmetry illustrated by using currents.
