**5. Experimental Results**

The performance of the Type I canonic oscillator of Figure 5a has been verified by both LTSpice simulations and experimental results. In particular, the approximated expression for *ω*<sup>0</sup> in (49) has been checked for different values of *τ* and *τ<sup>x</sup>* = *τz*, and errors lower than 1% have been found.

Then, we have used the commercially available AD844 to configure a VCII− as shown in Figure 9. A single VCII is realizable using two AD844 ICs, whose Spice model can be found in [45]. The situation is quite different in the case of an integrated design, where a single VCII block can be exploited to design the oscillator, as shown in the previous sections.

The circuit was supplied with a dual ±5 V voltage, achieving a total power consumption of 14 mA.

Firstly, simulation of the topology in Figure 5a has been carried out to evaluate performance in terms of robustness to parasitics, and to estimate the achievable THD. In particular, the circuit has been designed with *C*<sup>3</sup> = 2*C*<sup>5</sup> = 2 nF and *R*<sup>5</sup> = 2*R*1= 15 kΩ, and an oscillation frequency *f* <sup>0</sup> = 10.6 kHz was expected.

However, AD844 parasitics can slightly change the oscillation frequency and/or cause failing of oscillation condition: in this case, starting from the nominal design, the resistance *R*<sup>1</sup> can be changed (to 7.3 kΩ in the present case, see the schematic in Figure 10) to allow fulfillment of oscillation condition in (41): the obtained oscillation frequency is *f* <sup>0</sup> = 10.8 kHz, as shown in Figure 11.

A model for the VCII composed of AD844 components, shown in Figure 9, has been extracted from Spice simulations according to the equations presented in Section 4. At terminal *X*, we have found *Cx* = 5.5 pF in parallel with a resistor *Rx* =3MΩ. Purely resistive input impedances have been extracted at node *Y* (*Ry* = 50 Ω) and *Z* (*Rz* = 15 Ω). Finally, a dominant pole has been found for both the transfer function *α*(*s*) at *f* = 49 MHz (corresponding to *τ<sup>x</sup>* = 3.25 ns), and for *β*(*s*) at *f* = 764 MHz (*τ<sup>z</sup>* = 208 ps).

**Figure 9.** Realization of a VCII− using the AD844.

**Figure 10.** VCII oscillator based on the AD844.

The element values used for the different design case studies, the simulated THD and the oscillation frequency evaluated with both the LTSpice AD844 non-linear model and with the VCII linear model, including parasitics, are summarized in Table 2. The linear model is accurate enough to be used for circuit design, and excellent simulated performance has been achieved in terms of THD with the proposed VCII topology.

**Figure 11.** Simulated output spectrum of the oscillator shown in Figure 10.

**Table 2.** Simulation results at different frequencies.


Finally, experimental verification of performance has been carried out, exploiting the test bench shown in Figure 12: for data acquisition, the Digilent Analog Discovery 2™ board was used [46]. The design of Figure 5a was implemented as the reference topology for the oscillator. Measurements were carried out in the range (10–106) Hz and are reported in Table 3. In agreement with simulation results, the oscillator shows a very low THD value even at 1 MHz (considering 10 harmonics). The average relative frequency error between measured and ideal values is −5.2% and is comparable with tolerances of the passive components.

**Figure 12.** Test bench for the experimental verification of the VCII oscillator based on the AD844.


**Table 3.** Measured results.

An example of the output signal, both in the time and frequency domains, is reported in Figure 13a,b for a frequency of 1 MHz.

**Figure 13.** Output waveform of the canonic VCII-based oscillator of Figure 5a. (**a**) Time domain, (**b**) frequency domain for an output frequency of 1 MHz.

Figure 14 shows the THD and frequency error trends vs. frequency.

**Figure 14.** THD and frequency error vs. frequency.
