*2.2. Analytical and Simulated Results*

In this subsection, analytical expressions and simulation results of the conventional and proposed buffer are provided. The simulations have been obtained using a standard 180 nm CMOS technology with the following aspect ratios for the common transistors *WMD*/*LMD* = 20 μm/1 μm, *WMF*/*LMF* = 1 μm/1 μm, *IB* = 100 nA, set by a simple current mirror with *WMS*/*LMS* = 4 μm/1 μm. For the bootstrapped implementation, *CG* = 0.25 pF and transistor MG (*WMG*/*LMG* = 240 nm/340 nm) is connected as a pseudoresistor, implemented by a thick oxide device to obtain a larger value of resistance when it is compared to standard transistors. As a consequence, a lower operating cutoff frequency can be achieved. The supply voltage was set equal to 0.6 V; both cells were loaded with an output capacitor of 50 fF, and *VBIAS* was fixed to 0.1 V.

*Gain, area, and power consumption:* Figure 3 shows a comparison of the AC smallsignal response of the conventional and the bootstrapped buffers. The technique operates properly for frequencies higher than 3 Hz, obtaining a gain of 0.21 V/V (−13.4 dB) and 0.92 V/V (−0.7 dB) for the conventional and the proposed cell, respectively. For obtaining operation at lower frequencies, capacitor *CG* should be made larger or the configuration of the pseudo-resistor could be modified to increase its value. In the case of the high cutoff frequency, the value for the proposed cell is lower as compared to the conventional solution, since the output resistance of the proposed cell has been increased. The small overdamping observed in the magnitude response of the proposed circuit at frequencies slightly higher than 1 MHz can be easily cancelled by connecting a very small capacitor at the drain terminal of the driver transistors MD in Figure 2b. In any case, it does not affect the stability of the feedback loop implicit in the buffer. The power consumption is the same in both designs, 60 nW (not including the bias circuits), whereas in terms of silicon area, the proposed cell is twice as large as the conventional technique due to the presence of capacitor *CG*. However, larger capacities (in the order of tenths of pF) will be used in the final application, thus making this increase in area not very significant. In addition, it is worth mentioning that, in the used technology, metal–insulator–metal capacitors can be placed on top of the active devices, which allows for reducing the total area occupation of the voltage buffer.

Figure 4 shows the voltage gain of the conventional and the bootstrapped buffers as a function of the input differential-mode (DM) voltage in a range from −200 mV to 200 mV with respect to a common-mode (CM) voltage of 300 mV. Note that the gain of the proposed cell is more than four times higher than that of the conventional cell in the voltage range between −150 mV and 150 mV, and it is much closer to unity. In addition, the proposed cell has a more constant response than the conventional cell, leading to a more linear behavior, as it will be demonstrated next.

**Figure 3.** Frequency response comparison of the conventional and bootstrapped buffers.

**Figure 4.** Gain versus input DM voltage of the two voltage buffers.

*THD analysis:* Considering that the PMOS transistors in Figure 2 operate saturated in the weak inversion region, and neglecting the channel length modulation effect, their drain current can be defined as [22]

$$i\_D = I\_T \left(\frac{W}{L}\right) \exp\left(\frac{V\_{SG} + V\_{th}}{nV\_T}\right) \left[1 - \exp\left(\frac{V\_{SD}}{V\_T}\right)\right] \tag{1}$$

where *IT*, *Vth*, *n*, and *VT* are the technology current, the threshold voltage, the subthreshold slope, and the thermal potential, respectively. In a bulk-driven transistor, the signal is implicit in the threshold voltage, which can be expressed as

$$V\_{t\text{th}} = V\_{t\text{th0}} - \gamma\_P \left(\sqrt{2\phi + V\_{BS}} - \sqrt{2\phi}\right) \tag{2}$$

where *Vth*<sup>0</sup> is the threshold voltage when *VBS* = 0 and *φ* and *γ<sup>P</sup>* are fabrication process constants. It is worth pointing out that, for a PMOS transistor, the values of *Vth*, *Vth*0, and *γ<sup>P</sup>* are negative. Using these expressions, it is possible to find a closed-form relationship between *vOUT* and *vIN* for the circuits in Figure 2. Indeed, the large-signal input/output voltage expression for the conventional bulk-driven FVF cell is the solution of a quadratic function that can be written as follows:

$$v\_{OUT} = \frac{-(2A + \gamma\_P^2) \pm \sqrt{\gamma\_P^4 + \gamma\_P^2(4A + 8\phi) + 4\gamma\_P^2 v\_{IN}}}{2} \tag{3}$$

with *A* = −*VBIAS* + *Vth*<sup>0</sup> + *γ<sup>P</sup>* 2*<sup>φ</sup>* <sup>−</sup> *nVT* ln *IT IS*(*W*/*L*) . An evident nonlinear behavior can be observed in the input/output transfer characteristic of the conventional voltage follower. On the other hand, the *vOUT* − *vIN* transfer characteristic of the proposed buffer is inherently linear and given by:

$$
v\_{\rm OUT} = 2\phi - \frac{A^2}{\gamma\_P^2} + v\_{IN} \tag{4}$$

As inferred from (4), the linearity of the proposed cell is improved since the AC signal at the source terminal of transistor MD is copied to its gate, allowing the input/output voltage relationship to become linear. As a consequence, the THD performance is better for the proposed bootstrapped buffer as compared to the conventional structure.

Figure 5 shows the simulated THD comparison for a sinusoidal input signal of 1 kHz with an amplitude swept from 10 mV to 250 mV. The dominant distortion contribution in both cases is due to the second-order harmonic. Note that the proposed cell has a THD lower than 1% (−40 dB) for input signals up to 180 mV, with a corresponding output voltage of 166 mV, whereas, for the conventional cell, an input signal of only 50 mV, corresponding to an output voltage of 10 mV, is allowed to achieve the same distortion level. This represents an increase of almost 5 and 20 times of the maximum input and output signal levels, respectively, that can be processed.

**Figure 5.** THD comparison.

*Noise response:* A straightforward analysis of the noise equivalent circuit of the conventional buffer reveals that the power spectral density of the input-referred noise is:

$$\frac{\overline{\eta\_{iC}^{2}}}{\Delta f} = \frac{\overline{i\_{n,MF}^{2}}}{\Delta f} \frac{1}{\mathcal{g}\_{m,MF}^{2} \mathcal{g}\_{mb,MD}^{2} (r\_{o,MD} \parallel r\_{o,MS})^{2}} + \frac{\overline{i\_{n,MD}^{2}}}{\Delta f} \frac{1}{\mathcal{g}\_{mb,MD}^{2}} + \frac{\overline{i\_{nb,MF}^{2}}}{\Delta f} \frac{(\mathcal{g}\_{m,MD} + \mathcal{g}\_{mb,MD})^{2}}{\mathcal{g}\_{m,MF}^{2} \mathcal{g}\_{mb,MD}^{2}} \tag{5}$$

where the subscripts of the noise current sources are related to the names of the transistors in Figure 2. On the other hand, for the bootstrapped version of the voltage buffer, we have:

$$\frac{\overline{\eta\_{\rm iB}^{2}}}{\Delta f} = \frac{\overline{\eta\_{\rm n,MF}^{2}}}{\Delta f} \frac{1}{\mathcal{g}\_{\rm m,MF}^{2} \mathcal{g}\_{\rm mb,MD}^{2} (r\_{o,MD} \parallel r\_{o,MS})^{2}} + \frac{\overline{\eta\_{\rm n,MD}^{2}}}{\Delta f} \frac{1}{\mathcal{g}\_{\rm mb,MD}^{2}} + \frac{\overline{\eta\_{\rm mb,MF}^{2}}}{\Delta f} \frac{1}{\mathcal{g}\_{\rm m,MF}^{2}} \tag{6}$$

As it can be seen in (5) and (6), the first two noise contributions are equal because the ratio of *Rout* to gain and *RS*,*MD* to gain are the same in both circuits. The difference relies on the last term, related to the ratio of *RD*,*MD* to gain, which is different in both implementations. Subtracting both equations and defining *gmb*,*MD* = *ηgm*,*MD* and *gmb*,*MD* = *λgm*,*MF*, the extra noise for the conventional buffer is:

$$\frac{\overline{n\_{i\gets}^2}}{\Delta f} - \frac{\overline{n\_{iB}^2}}{\Delta f} = \frac{\overline{i\_{nb,MF}^2}}{\Delta f} \cdot \frac{\frac{2\lambda^2}{\eta} + \frac{\lambda^2}{\eta^2}}{\overline{g\_{mb,MD}^2}} \tag{7}$$

In Figure 6, it is evidenced by simulations that the noise corresponding to the bootstrapped buffer is lower than in the case of the conventional solution, according also to the prediction in (7).

**Figure 6.** Noise comparison. The input power spectral density is represented in dB on the *y*-axis to illustrate more clearly the tendencies.
