**1. Introduction**

The continuous evolution of electronic systems and the ever increasing symbiotic relationship between humans and electronic devices characterize the era of Internet of Things (IoT) [1,2]. Smart and portable devices, such as laptops, smartphones, smartwatches, fit-trackers and so on, are used more and more often for checking emails, banking management, counter services and the like. Indeed, most of these electronic apparatuses have changed the way we work, study or play.

This IoT revolution has also driven the development of body area networks [3], which exploit implantable and wearable devices, and are widely used in healthcare monitoring and in the study of neurodegenerative diseases such as Parkinson's, Alzheimer's and so on [4–7].

The growing popularity of these electronic devices is also due to their increasing capability to work with low power consumption and low supply voltage in order to maximize battery life or employ energy harvesting techniques.

The stringent requirements in terms of ultra-low-power (ULP) and ultra-low-voltage (ULV) operation set by the above applications have brought about a revolution also in

**Citation:** Centurelli, F.; Della Sala, R.; Monsurrò, P.; Scotti, G.; Trifiletti, A. A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers. *J. Low Power Electron. Appl.* **2022**, *12*, 12. https://doi.org/ 10.3390/jlpea12010012

Academic Editor: Orazio Aiello

Received: 20 January 2022 Accepted: 11 February 2022 Published: 17 February 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

59

the approach to the design of analog integrated circuits (ICs). In fact, the latter have to be reinvented to enhance the autonomy of smart devices and find a balance between performance, area footprint and power consumption at supply voltages of a few hundreds of millivolts. As such, analog interfaces are among the most challenging building blocks for IoT applications [1,8–11].

The Operational Transconductance Amplifier (OTA) stands out, among the analog building blocks, for its design complexity, especially if ULP and ULV operation are key requirements. In the last few years, there has been a growing trend in the design of ULP OTAs and a plenty of solutions have been proposed in the literature [12–14]. Most of the low voltage OTAs reported in the last decade operate with supply voltages ranging from 0.5 V to about 1 V, and are based on the conventional cascode, folded cascode, multistage or gain-boosting approaches, which have been successfully exploited in the past to implement high-performance amplifiers for several application scenarios [15–19]. A novel OTA architecture based on current gain stages to improve bandwidth and slew rate has been recently proposed in [20]. The OTA reported in [20] operates with a supply voltage of 1 V and exhibits state of the art small-signal and large-signal figures of merit. Unfortunately, most of these conventional amplifier topologies are not suited for applications requiring supply voltages lower than 0.5 V, and inverter-based [21–26] and pseudo-differential [27,28] architectures are preferred. However, an aggressive supply voltage scaling severely limits the swing of the control voltage, thus strongly limiting the effectiveness of body bias approaches to set the bias or the common mode current. Therefore, gate-driven amplifiers operating at supply voltages lower than 0.5 V are not able to guarantee either rail-to-rail input common mode range (ICMR) or well-defined bias currents.

The bulk-driven technique [29–31] allows rail-to-rail ICMR in ULV amplifiers at the cost of reduced gain and a resistive input impedance component. Bulk-driven amplifiers are surely one of the best alternatives to attain rail-to-rail input–output swing when a well-defined bias or common mode current is required to increase the robustness against process, supply voltage, and temperature (PVT) variations [32–42]. Indeed, the signal-free gate terminals can be used to accurately set the bias current of the different OTA stages. The bulk-driven technique combined with inverter-based topologies has also been exploited in recent papers to design ULV amplifiers [33,36,39].

A completely novel approach based on fully digital operation to the design of analog differential circuits has been introduced in [43]. Several papers dealing with the fully digital implementation of OTAs for IoT applications have been recently published [44–46]. The digital OTAs in [44,45] are based on the C-Muller element and do not require any passive component. Such digital OTAs are able to operate at supply voltages lower than 0.3 V and are very interesting from the viewpoint of the area footprint and power consumption. However, the operation of this kind of circuits can be sensitive to PVT variations and mismatch and may require suitable calibration strategies to achieve high production yield [47].

Indeed, even if bulk-driven OTAs exhibit some drawbacks with respect to gate-driven ones (higher noise, larger area and lower bandwidth) and to digital OTAs (larger area and power consumption), they can be designed to be robust against PVT and mismatch variations and still represent the best solution to attain rail-to-rail ICMR at supply voltages of the order of 0.3 V.

In this work, we present a novel OTA architecture based on a tree-like structure. This can be viewed as the ULV implementation of the OTA reported in [20], previously proposed by the authors to enhance the bandwidth efficiency. The current gains obtained by means of conventional current mirrors in [20] are not feasible in ULV conditions and have to be implemented by means of other solutions such as the one presented in [48]. In the ULV architeture proposed in this paper, the current gains are implemented by using a different approach which is based on the body-to-gate (B2G) interfaces as will be detailed in the following. The proposed architecture exploits a body-driven input stage to guarantee a railto-rail input common mode range and body-diode loading to avoid Miller compensation, thanks to the absence of high-impedance internal nodes. The bias currents and the static

output voltages of all the stages implementing the proposed architecture are accurately set through the gate terminals of biasing transistors in order to guarantee a good robustness against PVT variations. However, this biasing strategy results in pseudo-differential stages and therefore has a negative impact on CMRR performance. The proposed tree-like structure improves the CMRR of the OTA with respect to conventional pseudo-differential amplifiers and allows achievement of a reasonable CMRR even in ULV conditions. A 0.3 V supply voltage ULP OTA based on this architecture was designed in a 130 nm CMOS process, and simulation results show state of the art small-signal and large-signal figures of merit (FoMs).

The paper is organized as follows: Section 2 introduces the proposed OTA architecture. Circuit analysis is reported in Section 3. Section 4 deals with design and simulation results and conclusions are drawn in Section 5.

#### **2. Proposed Topology**

The block scheme of the proposed OTA architecture is depicted in Figure 1. This architecture of ULV OTA was derived from the OTA introduced by the authors in [20] and is a three stage, tree-like OTA, made up of the cascade of differential-to-single-ended converter stages, to maximize CMRR. Three different topologies are exploited in the three stages of the OTA to optimize the tradeoff between performance and efficiency. Each one of these stages was extensively investigated and their behavior is discussed in the next subsections. It has to be remarked that the proposed ULV OTA makes extensive use of the body terminals of MOS devices and thus it can be implemented only in CMOS technologies (such as triple-well-bulk or FDSOI), where both NMOS and PMOS transistors have available body connections. However, this is not a strong limitation, since most modern processes have available body connections for both PMOS and NMOS transistors.

**Figure 1.** Proposed tree-like architecture of the OTA.
