*3.3. Comparator*

The comparator in Figure 7 shows an OTA topology using dual cross-coupled load pairs and a cascode arrangement to boost the overall gain. The front differential stage, which makes use of the cross-coupled load pairs, *M*3–*M*<sup>6</sup> and *M*13–*M*16, is used to produce gain enhancement as well as to reduce the delay in the comparator, the outputs of which are followed by the current mirror high-gain stage consisting of *M*7–*M*<sup>12</sup> and *M*15–*M*20. Finally, the CMOS inverter, formed by *M*<sup>23</sup> and *M*24, aims to sharpen the output square waveform and provide the driving capability of the comparator.

**Figure 7.** Proposed comparator.

Considering the cross-coupled pairs *M*3–*M*6, the aspect ratio of *M*<sup>3</sup> is larger than that of *M*5. In small-signal analysis, the output impedance is obtained as

$$R\_{O1} = \frac{r\_{O3} + r\_{O5}}{(g\_{m3} - g\_{m5})(r\_{O3} + r\_{O5}) + 1} \approx \frac{1}{g\_{m3} - g\_{m5}}\tag{14}$$

where *gmi* is the respective transistor's transconductance and *rOi* is the respective transistor's output resistance, with *i* = 3 or 5. From (14), *RO*<sup>1</sup> is increased from 1/*gm*<sup>3</sup> to 1/(*gm*3–*gm*5) to increase the voltage gain because of the positive feedback allowing *M*<sup>5</sup> to behave as a negative resistance. When there is a voltage change on the drain of *M*3, the positive feedback introduced by *M*<sup>5</sup> can accelerate this change, causing faster output response to reduce the delay in the comparator.

The four cascode transistors *M*17–*M*<sup>20</sup> are used to reduce the effect of supply variation Δ*VDD* on the delay in the comparator. For *M*<sup>7</sup> and *M*<sup>17</sup> in small-signal analysis, the change in *VDS*<sup>7</sup> caused by Δ*VDD* can be approximated as [27]

$$
\Delta V\_{DS7} \approx \frac{\Delta V\_{DD}}{\mathcal{g}\_{m17} r\_{O17}} \tag{15}
$$

As interpreted from (15), it indicates that the change in *VDS* on *M*7–*M*<sup>10</sup> can be ignored when *VDD* varies. This means the current change in each branch caused by channel length modulation and DIBL can be minimized with cascode transistors. Moreover, the bias current for the comparator is directly copied from *IREF*, with the cascode current mirror in different ratios. This avoids the need for an extra bias branch, which would cause an increase in supply current consumption.

In fact, when the constant bias current is applied to the comparator, the delay in the comparator is reduced with an increasing temperature. From (3) and (6), the *VGS* of the MOS transistor working under weak inversion is expressed as

$$V\_{GS} = \eta V\_T \ln\left[\frac{I\_{sub}}{\mu \mathcal{C}\_{OX}(\eta - 1) V\_T^2 \frac{\mathcal{W}}{L}}\right] + V\_{TH0} - \kappa T \tag{16}$$

It can be observed that the *VGS* exhibits CTAT behavior. *M*<sup>3</sup> is in the diode connection, meaning that *VDS*<sup>3</sup> is equal to *VGS*3. When the temperature increases, *VDS*<sup>3</sup> (or *VGS*3) in the diode-connected topology is significantly reduced with respect to *VDS*7. Thus, the mismatch between the drain-to-source voltage of the transistors can lead to a rising current to allow for the delay in the comparator to decrease from 285.3 ns to 278.8 ns as the temperature increases, as shown in Figure 8. This feature is particularly useful for the delay compensation arising from the observation of the increase in delay through the leakage current of the switches, as depicted in Figure 4. As a result, the thermal stability of the oscillator circuit is enhanced. This will be further discussed in the next subsection. Of particularly note, the leakage current in the advanced technology node can be a serious issue.

**Figure 8.** Temperature characteristics of delay in comparators.

Since offset is critical in the comparator design, the Monte Carlo simulation, with 400 samples for the offset evaluation, is shown in Figure 9. This result indicates that the mean offset of the comparator is 0.37 mV, and its standard derivation is 5.63 mV. As observed, the offset is minimized by sizing the input transistor pair and the crosscoupled pairs with a long channel length (*L* > 4*Lmin*). Although the parasitic capacitors

in the large-size transistors will enlarge the response time, the delay, which is around 0.28 μs, including the hysteresis, contributes 3.6% of the oscillation period. Therefore, it is considered acceptable, with a low output frequency and a moderate precision requirement. Based on the result, the comparator offset cancellation scheme is not implemented in this work. The sizes of each component pertaining to the comparator in Figure 6 are given in Table 2.

**Figure 9.** Monte Carlo simulation of the comparator's offset.


**Table 2.** Size of the components in the comparator.
