*3.4. Simulation Results of the Cascaded Receiver Front-End*

The wideband receiver front-end using the clock strategy was designed and simulated in a 22 nm CMOS technology. The receiver consumes 11 mA from a 1 V supply voltage. The LNTA and TIA consume 4 mA and 7 mA, respectively.

The wideband input matching (S11) of the LNTA is shown in Figure 6, showing an S11 of less than −10 dB at up to 13 GHz, which is suitable for ultra wideband applications.

**Figure 6.** The cascaded received input matching (S11) performance versus RF.

The receiver-performance, integrated double-sideband noise-figure (NFDSB) from 10 kHz to 100 MHz, conversion gain and input-referred third-order intercept point (IIP3) versus *fLO*, which is equivalent to an input RF signal having a frequency of 4 × *fLO*, from 400 MHz to 12 GHz, is shown in Figure 7 . It shows the NFDSB is increasing in frequency from almost 1.4 dB to 3.9 dB. On the other hand, the conversion gain reduces from almost 36 dB to 26 dB as *fLO* is increased. A constant value of feedback resistor is used in the TIA. To perform the IIP3 simulation, a two-tone signal at 4 × *fLO* + 10 MHz and 4 × *fLO* + 11 MHz is applied at the input of the LNTA. This generates two third-order intermodulation products at 9 MHz and 12 MHz along with two fundamental products at 10 MHz and 11 MHz. The IIP3 performance varies over *fLO* from −10.5 dBm to −7.5 dBm.

**Figure 7.** The cascaded receiver NFDSB, conversion gain, and IIP3 performances versus *fLO*.

The TIA bandwidth can be configured with four settings using two capacitors. Figure 8 shows the receiver bandwidth can be configured from 250 MHz to almost 1 GHz. This can be changed using different values of feedback capacitors and also the shunt capacitors

after the mixer, which are 2 pF in this work. It shows that the receiver is suitable for very wideband baseband modulation.

**Figure 8.** The cascaded receiver bandwidth versus the bandwidth settings.

The harmonic rejection can be affected by the transistor process and mismatch variations. The effect of the transistor process and mismatch variation is verified using Monte-Carlo simulation over 100 runs, and the results are shown in Figure 9. The HR1, HR2, ... HRn (n = 7) are the 1st, 2nd, ... nth harmonics rejected relative to the 4th harmonic, which is the wanted signal in this work. This shows that very good harmonic rejection is achieved at all harmonics with a minimum rejection of 134 dB in HR7 using a 3× sigma calculation.

**Figure 9.** *HRn* performance of the cascaded receiver over 100 runs.

## **4. Stacked Receiver Front-End Using the Proposed Clock Strategy**

By scaling down the CMOS technology node , the threshold voltage (*VTH*) is lowered, enhancing the frequency of operation and enabling new low-power design techniques that have emerged. One effective low-power design technique is the current-reuse or stacked technique by means of stacking different circuits such as LNTA, mixer, and TIA to share the biasing current from a single supply. Thus, in the stacked receiver front-end, the LNTA, mixer, and TIA are stacked.

Although this reduces power consumption, it still has drawbacks. The LNA, mixer, and voltage controlled oscillator (VCO) are staked in [20] to improve the power efficiency, but the circuit may suffer from the injection locking of the VCO due to the large blockers. Moreover, it has high NF. An unbalanced single to differential LNA, active mixer, and baseband circuitry are cascoded to reduce power consumption in [21]. However, the active mixer degrades the linearity performance and increases the voltage headroom requirements. A simultaneous input matching and 1/ *f* NC technique is employed in [22] that results in a very low NF of less than 2 dB. However, the use of the common-source (CS) LNTA topology reduces the RF bandwidth. In addition, due to the receiver topology that connects the mixer input to the output node, the receiver is not able to operate at high frequency. Our earlier works [13,23,24], overcome the problems mentioned above. However, the mixer circuit in [13] needs to be improved to reduce the number of mixer switches. In addition, it suffers from 1/ *f* noise that does not allow the receiver to operate at low frequency with good NF performance.

To overcome the limitations mentioned above, this work proposes a stacked receiver front-end, shown in Figure 4. It includes an on-chip balun to convert the single-ended antenna to a differential signal at the input of the LNTA, a capacitive cross-coupled commongate (CG) LNTA topology to convert the RF voltage to an RF current, an active inductor (AI) and a 1/ *f* noise-cancellation (NC) technique to isolate the mixer input and enhance low-frequency noise performance, a passive mixer to down-convert the RF current to an IF current, and a TIA to convert the IF current to an IF voltage at the output. The TIA and LNTA share the current using a single supply, reducing the power consumption.
