*Article* **A 0.5 V Sub-Threshold CMOS Current-Controlled Ring Oscillator for IoT and Implantable Devices**

**Andrea Ballo 1, Salvatore Pennisi 1,\*, Giuseppe Scotti <sup>2</sup> and Chiara Venezia <sup>1</sup>**

<sup>2</sup> Dipartimento di Ingegneria dell'Informazione Elettronica e Telecomunicazioni (DIET),

Sapienza University of Rome, 00184 Rome, Italy; giuseppe.scotti@uniroma1.it

**\*** Correspondence: salvatore.pennisi@unict.it; Tel.: +39-095-7382318

**Abstract:** A current-controlled CMOS ring oscillator topology, which exploits the bulk voltages of the inverter stages as control terminals to tune the oscillation frequency, is proposed and analyzed. The solution can be adopted in sub-1 V applications, as it exploits MOSFETS in the subthreshold regime. Oscillators made up of 3, 5, and 7 stages designed in a standard 28-nm technology and supplied by 0.5 V, were simulated. By exploiting a programmable capacitor array, it allows a very large range of oscillation frequencies to be set, from 1 MHz to about 1 GHz, with a limited current consumption. Considering, for example, the five-stage topology, a nominal oscillation frequency of 516 MHz is obtained with an average power dissipation of about 29 μW. The solution provides a tuneable oscillation frequency, which can be adjusted from 360 to 640 MHz by controlling the bias current with a sensitivity of 0.43 MHz/nA.

**Keywords:** ring oscillator; body biasing; tuning range

**1. Introduction**

The Internet of Things (IoT), wireless sensor networks, and the emergence of other energy-harvested microsystems pose continuous challenges and create ever-growing interest in CMOS ultra-low-power analog and mixed-signal system-on-chip solutions. In this framework, applications such as wearable and implantable medical devices, body sensor networks, etc., often require a controlled oscillator (CO) with a minimum power consumption, small layout area, low phase noise, and adequate frequency tuning range to cope with process and/or temperature variations [1–6]. COs are also fundamental blocks of phase-locked loops (PLLs) to provide the timing basis in clock control, clock generator circuits, RFID tags, and systems that use clock-dependent circuits, such as switching power converters and so on [7–9].

CMOS COs can be categorized in two main families. The first includes LC resonant oscillators and, the second, ring oscillators. LC oscillators are mainly used in applications where both a high-phase noise and quality factor (Q) are required. Due to their spiral inductors' large area and high-power dissipation, they cannot be used in ultra-low-power systems on a chip and where physical dimensions must be limited [10]. As is well known, ring oscillators (ROs) consist of an odd number of cascaded delay elements, usually identical to each other, that form a ring where the last stage output is connected to the first stage input. A further categorization is performed based on the control variable, which is often a voltage or a current.

Controlled ring oscillator topologies exhibit a good frequency tuning range, low power dissipation, low design complexity, occupy a small area, and compatibility with CMOS processes. Moreover, ring oscillators are more power efficient compared to relaxation oscillators, although these can achieve a wider tuning range [11].

**Citation:** Ballo, A.; Pennisi, S.; Scotti, G.; Venezia, C. A 0.5 V Sub-Threshold CMOS Current-Controlled Ring Oscillator for IoT and Implantable Devices. *J. Low Power Electron. Appl.* **2022**, *12*, 16. https://doi.org/ 10.3390/jlpea12010016

Academic Editor: Orazio Aiello

Received: 8 February 2022 Accepted: 3 March 2022 Published: 9 March 2022

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**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

<sup>1</sup> Dipartimento di Ingegneria Elettrica Elettronica e Informatica (DIEEI), University of Catania, 95125 Catania, Italy; andrea.ballo@unict.it (A.B.); chiara.venezia@phd.unict.it (C.V.)

To improve the frequency-tuning range and phase-noise margin, several design approaches for low-power COs have been reported in the literature. Among these techniques, we mention the combined current-starving technique (i.e., current-controlled oscillator) with a negative skewed-delay approach to improve the power delay product (i.e., product between dissipated power and single gate delay) [12]. A conventional voltage controlled oscillator (VCO) with a negative resistance, multiple-gated circuit and bypass capacitor to suppress high-order harmonics has been reported [13], whereas a digital control circuit to manage oscillation frequency has also been described [1]. An approach that uses positive feedback in each stage to operate with only two stages, instead of three, decreasing the power consumption can be found [14], whereas a frequency tuning cell that consists of one NMOS and one PMOS to form a transmission gate, used to tune the oscillation frequency by varying the gate voltage, has been presented [15]. Finally a dynamic threshold technique (DTMOS) to reduce the threshold voltage of NMOS transistors in the inverting stage with the aim to achieve fast transition and high operating frequency has been presented [3].

The idea of exploiting the bulk terminal to control the oscillation frequency of a RO and the effect of bulk voltage variations on RO phase noise have been analyzed [16], whereas an adaptive body-bias generator for low voltage CMOS VLSI circuits in which a RO was used to estimate the delay of CMOS gates has also been presented [17].

In this work, we exploit a body-biasing technique, originally utilized in the analog domain [18–20], and recently applied to set the quiescent current of the generic inverter stage [21] to design a low-power low-voltage current-controlled ring oscillator (CCO) in 28-nm bulk CMOS technology.

The proposed approach allows to guarantee a static output voltage equal to half the supply voltage, in spite of the value of the bias current, which is tuned in order to control the oscillation frequency. In this way, since any offset in the input output voltage transfer characteristic is removed by the body bias loop, the inverter stages can be reliably cascaded, thus greatly enhancing the tuning range and robustness to PVT variations of the proposed RO.

The manuscript is organized as follows. Section 2 describes the proposed solution. Section 3 reports accurate small- and large-signal analyses of the proposed oscillator. Section 4 includes some simulation results and, finally, the authors' conclusions are summarized in Section 5.

#### **2. The Proposed Solution**

Figure 1 shows a circuit schematic of the proposed current-controlled ring oscillator (CCRO). It consists of an *N*-stage ring oscillator in which the single stage is made up of a CMOS inverter where bulk terminals of both transistors (*MPi* and *MNi*, with *i* = 1, 2, . . . *N* and *N* an odd number greater than 3) are made accessible. An output capacitor, *Ci* in the red-dashed box, is added at the output of each stage with the aim of setting the nominal oscillation frequency (coarse tuning), and to locally make the single stage insensible to parasitic capacitances, as will be clarified in the next section. The body potentials of both transistors, *VBP* and *VBN*, are generated from the auxiliary topology depicted in Figure 2, the aim of which is to establish the maximum current flowing in the reference inverter (*MPR*-*MNR*), i.e., when the input is at the logic threshold, *VDD*/2. For this purpose, in quiescent conditions, the input terminal of this reference inverter is set to *VDD*/2 and, thanks to the overall negative feedback implemented by error amplifier A2, such condition is transferred also to the output. Note that also the drain voltage of transistor *MPA* is kept to *VDD*/2 thanks to A1. This allows us to set the same nominal operating points for both *MPR* and *MPA*.

**Figure 1.** Simplified schematic of the proposed current-controlled ring oscillator.

**Figure 2.** Simplified schematic of the biasing section generating *VBN* and *VBP* for the RO in Figure 1.

As far as the quiescent current control is concerned, it is implemented through the bulk terminals via voltage *VBP* for the p-channel transistors, and *VBN* for the n-channel ones. These voltages are generated by A1 and A2, exploiting a technique proposed in [19] and utilized also in [21].

In brief, starting from the biasing current *IBIAS*, transistor *MPA* is forced to generate voltage *VBP*, which is also applied to *MPR*. Therefore, current *IBIAS* in *MPA* is mirrored by transistor *MPR* that, as already stated, together with *MNR*, constitutes the reference inverter. Note also that A2 generates the required bulk voltages, *VBN*, for *MNR* to drive the same current of *MPR* under the constraints listed in the following:


Of course, aspect ratios of *MPR* and *MNR* must be set so that the required bulk voltages are within *VDD* and ground. Moreover, the mirroring error between the biasing branch and the reference one is reduced using a careful layout style.

It should be noted that the auxiliary amplifiers A1 and A2 should provide a maximum (rail-to-rail) output voltage range, whereas input common mode range is not a concern as input voltage is kept constant to *VDD*/2. Therefore, simple symmetrical OTAs biased in subthreshold, can be effectively used. An example of implementation of this type of amplifier is found in [21,22], and is shown in Figure 3.

**Figure 3.** Simplified schematic of simple mirror OTA [21] used in this work.

Voltages *VBN* and *VBP* are then applied to the inverters forming the ring oscillator in Figure 1, limiting at the desired value the maximum current flowing when the input voltage is equal to the threshold. Indeed, consider transistor *MN*<sup>1</sup> of the first inverter stage, the exploded view of which is depicted in the red-dashed box in Figure 1. Let us remember that, in quiescent conditions, *VIN1* is equal to *VDD*/2. Consequently, *MNR* and *MN*<sup>1</sup> have respectively the same source, gate, and bulk voltage and hence the drain current of *MN*<sup>1</sup> is related to that of *MNR* in a mirror-like condition:

$$I\_{D,N1} = \frac{\left(W/L\right)\_{N1}}{\left(W/L\right)\_{NR}} I\_{BIAS} \tag{1}$$

where equality is accurately verified because the source-drain voltage of *MN*<sup>1</sup> is also equal to *VDD*/2. Similar considerations hold for all the transistors in the ring oscillator, in practice, all p-channel and n-channel devices have their current linked to *IBIAS* via the current-mirror relations

$$I\_{D,Pi} = \frac{(W/L)\_{Pi}}{(W/L)\_{PR}} I\_{BIAS} \tag{2}$$

$$I\_{D,Ni} = \frac{(W/L)\_{Ni}}{(W/L)\_{NR}} I\_{BIAS} \tag{3}$$

where (*W/L*)*Pi* and (*W/L*)*Ni*, with *i* = 1, 2, ... *N*, are, respectively, the aspect ratios of the generic p-channel and n-channel MOSFET in the ring oscillator.

#### **3. Small- and Large-Signal Analysis of the Proposed Ring Oscillator**

In order to design a conventional ring oscillator, analytical extraction of design equations is carried out by using two main approaches.

The first type of analysis considers small-signal equivalent model of the sub-blocks and Barkhausen stability criterion. In this approach the single gate is seen as working in an operating point (biasing or linearity conditions) and the whole system is analysed in the frequency domain. For this reason, hereinafter we will refer to this approach as an *analog* or *small-signal approach*. As an example, let us consider the conventional CMOS inverter in Figure 4 and its equivalent small-signal circuit.

**Figure 4.** Conventional CMOS inverter (**a**) and its equivalent small-signal circuit (**b**).

When working around an operating point, the inverter behaves as the linear network reported on the right side of Figure 4, the parameters of which are expressed below for the MOS transistors operated in the sub-threshold region.

$$\mathcal{g}\_{\mathfrak{m}} = \mathcal{g}\_{\mathfrak{m},p} + \mathcal{g}\_{\mathfrak{m},\mathfrak{n}} \simeq 2\frac{I\_D}{nV\_T} \tag{4}$$

$$r\_d = r\_{d,n} \parallel r\_{d,p} = \frac{nV\_T}{2\lambda\_{DS}I\_D} \tag{5}$$

$$\mathbb{C}\_{\mathbb{S}^{\mathfrak{s}}} = \mathbb{C}\_{\mathbb{S}^{\mathfrak{s},p}} + \mathbb{C}\_{\mathbb{S}^{\mathfrak{s},n}} \simeq \frac{2}{3} \mathbb{C}\_{OX} \left( \mathbb{W}\_p L\_p + \mathcal{W}\_n L\_n \right) + \mathbb{C}\_{OX} \left( \mathbb{W}\_p L\_{\upsilon\upsilon} + \mathcal{W}\_n L\_{\upsilon\upsilon} \right) \tag{6}$$

$$\mathcal{C}\_{\mathbb{S}^d} = \mathcal{C}\_{\mathbb{S}^d, p} + \mathcal{C}\_{\mathbb{S}^d, \mathbb{u}} \approx \mathcal{C}\_{\mathbb{O}X} \left( \mathcal{W}\_p L\_{\mathbb{O}\mathbb{v}} + \mathcal{W}\_n L\_{\mathbb{O}\mathbb{v}} \right) \tag{7}$$

$$\mathcal{C}\_{db} = \mathcal{C}\_{db,p} + \mathcal{C}\_{db,n} \approx 2 \,\mathcal{C}\_{lp/n} \Big|\_{V\_{DD}/2} \left[ 1 - \frac{1}{m\_j} \frac{V\_{DD}/2}{V\_{bi}} \left( 1 - \frac{V\_{DD}/2}{V\_{bi}} \right) \right] \tag{8}$$

where parameter *n* is the sub-threshold slope, *VT* = *kT*/*q* is the thermal voltage, with *k* the Boltzmann constant, *T* is the absolute temperature and *COX* is the oxide capacitance for unit of area. In addition, *λDS* is the channel modulation coefficient, *Lov* is the length of the overlap portion, *CJp/n* is the capacitance of the S/D junctions (evaluated at the voltage *VDD*/2 in (4e)), *mj* is the grading coefficient and *Vbi* is the built-in voltage.

The product between the transconductance *gm* (4) and the output resistance *rd* (5) yields a constant value, independent of the biasing current *ID* and equal to the maximum of the *gm*/*ID* curves [23]. In such case, only the channel modulation coefficient, *λDS*/*nVT*, can be changed by sizing the transistors, in order to (slightly) change the inverter intrinsic gain (i.e., *gmrd*). Note that the drain-induced barrier lowering (DIBL) effect is included in the channel modulation coefficient through the parameter *λDS*. Parasitic capacitance contribution accounts for three capacitances expressed in (6)–(8).

The gate-to-source equivalent capacitance is proportional to *COX* and is constituted by a first term that depends on the MOSFET active areas and by the operating condition (assumed with MOSFETs in saturation) and a second term that depends on the overlap capacitance. A similar contribution forms the gate-to-drain equivalent capacitance, *Cgd*, expressed in (7). The drain-to-bulk capacitance, unlike the previous two, is a non-linear capacitance which depends on S/D diffused areas (included in *CJp/n*) and the applied voltage, i.e., the drain-to-bulk voltage. Referring to Figure 4a, both are evaluated in the quiescent point, i.e., at *VDD*/2, and, from Figure 4b, the output node results to be loaded by the sum of the capacitances (8) and the additional one, *C*.

The above derivation, when applied to the proposed circuit, yields the same equations except for (4e) that becomes:

$$\mathbb{C}\_{db} = \mathbb{C}\_{db,p} + \mathbb{C}\_{db,n} \approx 2 \mathbb{C}\_{fp/n} \Big|\_{\mathrm{VDD}/2 - V\_{\mathbb{B}}} \left[ 1 - \frac{1}{m\_j} \frac{V\_{\mathrm{DD}}/2 - V\_{\mathrm{B}}}{V\_{\mathrm{bi}}} \left( 1 - \frac{V\_{\mathrm{DD}}/2 - V\_{\mathrm{B}}}{V\_{\mathrm{bi}}} \right) \right] \tag{9}$$

However, the effect of *Cdb* on the oscillation frequency can be neglected if an additional capacitance, *C*, sufficiently large, is connected in parallel. Analysis of the complete ring oscillator leads to closed-loop gain and phase shift which satisfy Barkhausen's criteria for the common pulsation, *ωp*, since the output node electrically coincides with the input one, therefore |*H*(*jωp*)| = 1, and the a total phase shift of 180◦ is constantly achieved for an odd number of stages *N*. The result of these concurrent conditions ensures oscillation whose frequency is expressed by:

$$f\_{\rm OSC} = \frac{\omega\_P}{2\pi} = \frac{1}{2\pi r\_d c\_{\rm tot}} \tan\left(\frac{\pi}{N}\right) \tag{10}$$

Here *ctot* gathers all the capacitive contributions (6), (7) doubled for Miller's effect, (9) and *C*. It can be noted that, being the output small-signal resistance inversely proportional to the biasing current, *ID*, a proportional control of the oscillation frequency can be operated by varying the current itself. Various works presented in literature demonstrated that such kind of analysis is inaccurate when the number of stages exceeds 3, hence (10) is rarely used to design a ring oscillator.

On the other hand, the second approach consider the oscillator as the cascade of an odd-number of digital inverting gates where the output of the last gate is fed-back to the input of the first one. In this framework, the single inverter is characterized by its propagation delay, *τPD*, and the frequency of the generated signal follows the expression:

$$f\_{OSC} = \frac{1}{2N\tau\_{PD}}\tag{11}$$

where the factor 2 derives from the fact that each single voltage node switches *N*-times *τPD*, where *N* is the number of inverters involved. For a digital gate, the propagation delay is defined as the time required to settle the output node to the middle of its dynamic range as referred to the instant of input changing. Henceforth, we call this approach *digital* or *large-signal approach*. While the simple relation in (11) and its scalability assuming general gate implementation are the strengths of this approach, evaluating *τPD* could require a great deal of effort. Therefore, designers often adopt a trial-and-error approach.

To better understand the relation between small- and large-signal behavior, propagation delay of the proposed cell should be evaluated. Figure 5 shows the working principle of the inverting gate in response to an input rail-to-rail signal and its static behavior as well. Assuming the inverter symmetrical and working in sub-threshold, which means to size transistors aspect ratios meeting the relationship

$$
\left(\frac{W}{L}\right)\_P \Big/ \left(\frac{W}{L}\right)\_N = \frac{I\_{ST0,N}}{I\_{ST0,P}} \varepsilon^{\frac{|V\_{TH,P}| - V\_{TH,N}}{nV\_T}} \tag{12}
$$

where both *IST0,N* (*IST0,P*), defined as the potential sub-threshold current of the NMOS (PMOS) if the threshold voltage are nullified, and *n* are technology-dependent parameters, and *VTH,N* (*VTH,P*) are the threshold voltage of the involved transistors. In (12), the tailing effect of drain-to-source voltages is neglected because we assume that transistors are biased in saturation, i.e., *VDD*/2 > *VT*. Moreover, *VTH,N* (*VTH,P*) implicitly depends on *VBS,N* (*VSB,P*) through the body effect, as well as on *VDS,N* (*VSD,P*) through the DIBL effect. Their contributions are taken into account by expressing *VTH,N* = *VTH0,N* − *λBS,N VBS,N* − *λDS,N VDS,N*(|*VTH,P*|=|*VTH0,P*| − *λBS,P VSB,P* − *λSD,P VSD,P*) where *VTH0,N* (*VTH0,P*) and *λBS,N* (*λBS,P*) are two technology parameters, while *λDS,N* (*λSD,P*) coincides with that used in

(5) [24]. It should be noted that, if (12) is fulfilled, the two transistors are equally strong, which means that for the same gate to source voltage they conduct the same current. Under the aforementioned considerations, a good approximation (typical error < 10%) for the propagation delay is given by [25]:

**Figure 5.** Conventional CMOS inverter (**a**) and its static transfer behavior (**b**).

In the first expression of (13), almost all the technology-dependent characteristics and transistor sizes are gathered in *IST*|*VDD* = 0 in order to be enucleated from the circuital parameters like voltages *VDD*, *VBN*, and *VBP*. Moreover, the total large-signal capacitance seen at the output node, *CTOT*, can be assumed to be equal to the small-signal one reported in (10). Finally, (13) has be re-written in the last simple form to highlight the biasing current, *ID*.

Replacing (13) in (11), the oscillation frequency is expressed as:

$$f\_{\rm OSC} = \frac{I\_D}{2N(V\_{DD}/2)\mathcal{C}\_{\rm TOT}}e^{\frac{V\_{DD}/2}{nV\_T}}\tag{14}$$

As compared with the small-signal counterpart, (14), like (10), shows a linear dependence with the bias current, therefore confirming the possibility to modulate the oscillation frequency of the RO by using the biasing circuit in Figure 2. It should be noted that (14) and (10) give similar information also when the last one loses accuracy. In fact, for *N* > 3 the tangent function can be expanded in Taylor's series, *Tan*(*π*/*N*) ≈ *π*/*N* being *π*/*N* << 1. This approximation leads to have:

$$f\_{\rm OSC} = \frac{\omega\_P}{2\pi} \approx \frac{1}{2N r\_d c\_{tot}} = \frac{I\_D}{2N c\_{tot}} \left(\frac{2\lambda\_{DS}}{nV\_T}\right) \tag{15}$$

which differs from (14) only for factor (*λDS*/*nVT*) that replaces (*e VDD*/2 *nVT* /*VDD*). Thus, it can be claimed that small-signal and large-signal analyses yield results that are similar to those obtained for a conventional topology, such as the current-starved RO [26].

In conclusion, three important metrics for a controlled oscillator are evaluated. Starting from (14), the first is the frequency-to-current first-order slope defined as the derivative function of the frequency versus the control current:

$$\frac{\partial f\_{OSC}}{\partial I\_D} = \frac{e^{\frac{V\_{DD}/2}{nV\_T}}}{2N(V\_{DD}/2)C\_{TOT}}\tag{16}$$

The second one is the total power consumption, made up of a static and a dynamic contribution. While the static part is due only to the leakage current, which coincides with the quiescent one in our case and, as it will be seen it is negligible; the dynamic part represents the major contribution to the power consumption. Consequently, the dynamic power dissipation *PD* of a *N*-stage ring oscillator is given by:

$$P\_D = \text{NC}\_{tot} f\_{\text{OSC}} (V\_{DD})^2 \tag{17}$$

Finally, in a conventional CMOS oscillator, the amount of the phase noise, *L*{Δ*f*}, (see expression (15) of [27]) is given by the flicker noise and its normalized single-sideband spectral density as given in the following equation

$$L\{\Delta f\} = 10\log\left[\frac{2FkT}{P\_{sign}}\left(\frac{f\_{\rm OSC}}{2Q\Delta f}\right)^2\right] \tag{18}$$

where Δ*f* is the offset frequency from the nominal one *fOSC*, *Q* is the quality factor and *F* is an empirical fitting parameter that takes the increased noise in Δ*f* into account. The *Q* factor is typically used in the design of high-order oscillators like *LC*-type and is defined as the ratio of the energy stored in the oscillating resonator to the energy dissipated per cycle by damping processes. Finally, *Psign* in (18) is the power of generated signal. Unfortunately, as in the conventional ring oscillator, the quality factor is poor since the energy stored in the node capacitances is reset(discharged) every cycle [27], resulting in a higher phase noise.

Finally, the trade-off between phase noise, power consumption and carrier frequency can be evaluated by using the following figure of merit (*FoM*):

$$FoM = L\{\Delta f\} + 10\log\left(P\_{\text{(mW)}}\right) - 20\log\left(\frac{f\_{\text{OSC}}}{\Delta f}\right) \tag{19}$$

where *P*(mW) is the power consumption expressed in mW, thus normalized to 1 mW.
