*Article* **Wideband Cascaded and Stacked Receiver Front-Ends Employing an Improved Clock-Strategy Technique**

**Arash Abbasi \*,† and Frederic Nabki †**

**\*** Correspondence: arash.abbasi.1@ens.etsmtl.ca

† Current address: Department of Electrical Engineering, École de Technologie Supérieure ÉTS, Montreal, QC H3C 1K3, Canada.

**Abstract:** A wideband cascaded receiver and a stacked receiver using an improved clock strategy are proposed to support the software-defined radio (SDR). The improved clock strategy reduces the number of mixer switches and the number of LO clock paths required to drive the mixer switches. This reduces the dynamic power consumption. The cascaded receiver includes an inverter-based low-noise transconductance amplifier (LNTA) using a feed-forward technique to enhance the noise performance; a passive mixer; and an inverter-based transimpedance amplifier (TIA). The stacked receiver architecture is used to reduce the power consumption by sharing the current between the LNTA and the TIA from a single supply. It utilizes a wideband LNTA with a capacitor cross-coupled (CCC) common-gate (CG) topology, a passive mixer to convert the RF current to an IF current, an active inductor (AI) and a 1/ *f* noise-cancellation (NC) technique to improve the noise performance, and a TIA to convert the IF current to an IF voltage at the output. Both cascaded and stacked receivers are simulated in 22 nm CMOS technology. The cascaded receiver achieves a conversion-gain from 26 dB to 36 dB, a double-sideband noise-figure (NFDSB) from 1.4 dB to 3.9 dB, S11 <−10 dB and an IIP3 from −7.5 dBm to −10.5 dBm, over the RF operating band from 0.4 GHz to 12 GHz. The stacked receiver achieves a conversion-gain from 34.5 dB to 36 dB, a NFDSB from 4.6 dB to 6.2 dB, S11 <−10 dB, and an IIP3 from −21 dBm to −17.5 dBm, over the RF operating band from 2.2 GHz to 3.2 GHz. The cascaded receiver consumes 11 mA from a 1 V supply voltage, while the stacked receiver consumes 2.4 mA from a 1.2 V supply voltage.

**Citation:** Abbasi, A.; Nabki, F. Wideband Cascaded and Stacked Receiver Front-Ends Employing an Improved Clock-Strategy Technique. *J. Low Power Electron. Appl.* **2023**, *13*, 14. https://doi.org/10.3390/ jlpea13010014

Academic Editor: Orazio Aiello

Received: 24 November 2022 Revised: 27 January 2023 Accepted: 30 January 2023 Published: 2 February 2023

**Copyright:** © 2023 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

**Keywords:** wireless receiver; wideband; cascaded; stacked; harmonic recombination; N-path receiver; LNTA
