*2.2. Dynamic Model*

The dynamic model of MOS transistors includes intrinsic and extrinsic capacitances. Figure 3 presents a simplified dynamic model that includes both the intrinsic and extrinsic parts.

In Figure 3a, the extrinsic capacitance *Cgse*(*de*) includes an unavoidable overlap between the gate and the source (drain) diffusion and fringing capacitances, while the substrate-source (drain) junctions modeled by (nonlinear) diode capacitances correspond to *Cbse*(*de*). A more complete model for the extrinsic part should include parasitic resistances as well [15].

The field effect of MOS transistors occurs in the intrinsic part between the source and drain. The classical MOSFET model in Figure 3b contains five capacitances added to the small-signal model of Figure 2.

**Figure 3.** MOSFET dynamic model with (**a**) extrinsic and (**b**) intrinsic parts [13].

The calculation of the intrinsic capacitance coefficients is based on the unified chargecontrol model (UCCM) and on the quasi-static charge conserving model [13]. The effect of the DIBL parameter on the five intrinsic capacitances is summarized in expressions (15)–(19) in which *Cgs*<sup>0</sup> and *Cgd*<sup>0</sup> are the gate-source and gate-drain capacitances of the long-channel model, respectively. In (13) and (14), *α* = <sup>1</sup>+*qiD* <sup>1</sup>+*qiS* is the channel linearity factor.

$$\mathcal{C}\_{\rm gs0} = \frac{2}{3} \mathcal{WLC}\_{\rm ox} \frac{1+2\alpha}{(1+\alpha)^2} \frac{q\_{iS}}{1+q\_{iS}} \tag{13}$$

$$\mathcal{L}\_{\text{S}^{\text{d}0}} = \frac{2}{3} \mathcal{W} L \mathcal{C}\_{\text{ox}} \frac{\alpha^2 + 2\alpha}{(1+\alpha)^2} \frac{q\_{\text{i}D}}{1+q\_{\text{i}D}} \tag{14}$$

$$\mathcal{C}\_{\mathbb{S}^5} = \left(1 - \frac{\sigma}{n}\right) \mathcal{C}\_{\mathbb{S}^{50}} - \frac{\sigma}{n} \mathcal{C}\_{\mathbb{S}^{50}} \tag{15}$$

$$\mathcal{C}\_{\mathbb{S}^d} = \left(1 - \frac{\sigma}{n}\right) \mathcal{C}\_{\mathbb{S}^{d0}} - \frac{\sigma}{n} \mathcal{C}\_{\mathbb{S}^{d0}} \tag{16}$$

$$\mathcal{C}\_{\rm gb} = \left(1 - \frac{1}{n}\right) \left(\mathcal{WLC}\_{\rm ox} - \mathcal{C}\_{\rm gc0} - \mathcal{C}\_{\rm gd0}\right) + \frac{2\sigma}{n} [(n-1)\mathcal{WLC}\_{\rm ax} - \mathcal{C}\_{\rm gc0} - \mathcal{C}\_{\rm gd0}] \tag{17}$$

$$\mathbb{C}\_{\mathbb{bs}} = (n-1)\mathbb{C}\_{\mathbb{S}^{\mathbb{s}}} \tag{18}$$

$$\mathbb{C}\_{bd} = (n-1)\mathbb{C}\_{\mathbb{S}^d} \tag{19}$$

Figure 4 presents plots of the five intrinsic capacitances normalized to *Cox* as functions of the pinch-off voltage. The curves were obtained for an NMOS transistor with *<sup>W</sup> <sup>L</sup>* <sup>=</sup> 0.6 <sup>μ</sup><sup>m</sup> 0.3 μm and *VDS* = 1 V.

**Figure 4.** Capacitances (15)–(19) normalized to *Cox* versus the pinch-off voltage for *VDS* = 1 V.

#### **3. Parameter Extraction**

The accuracy of the transistor's characteristics depends on both the model and the accuracy of the parameters. The model's parameters should be easily and accurately extracted; otherwise, the model will not be successful [14]. Thus, this section presents the methods to extract the four transistor parameters.
