**Appendix A**

Verilog netlist of the SC-DIGOTA is as follows: module SC-DIGOTA (input Vip, input Vin, output Out); wire INn; wire INp; wire CM; wire EN; wire not\_EN; wire OP; wire ON; IVLL IV1(.A(Vip),.Z(INn)); IVLL IV2(.A(CM),.Z(INn)); IVLL IV3(.A(Vin),.Z(INp)); IVLL IV4(.A(CM),.Z(INp)); IVLL IV5(.A(INn),.Z(OP)); IVLL IV6(.A(INp),.Z(ON)); IVLL IV7(.A(EN),.Z(not\_EN)); EOLL XOR1(.A(OP),.B(ON),.Z(EN));

BTSLL BT1(.A(OP),.E(EN),.Z(Out)); ITSLL IT1(.A(OP),.E(not\_EN),.Z(CM)); endmodule
