**1. Introduction**

Wireless standards operate over a wide frequency spectrum spanning tens of GHz and employ various modulation schemes. Wireless applications have led to the rapid growth of wireless devices in all sectors of the internet of things (IoT), such as health monitoring, agriculture, and smart cities. A wideband system such as the software defied radio (SDR) is a well-suited architecture to address several wireless standards in a single receiver module. Conventional SDRs required a high specification analog-to-digital converters (ADCs), which increased the power consumption and complexity of the design [1] . In [2], down conversion is proposed to reduce the power consumption.

In wideband operation, the wanted signal at the local oscillator (LO) frequency downconverts to the baseband, along with other components of the LO harmonics. This degrades the error vector magnitude (EVM) performance. Harmonic recombination using the N-path receiver architecture is employed to overcome this problem [3–6]. One of the drawbacks of N-path receivers is that they require a high-frequency driving clock (e.g., 8× the LO frequency) to generate the clock phases that are needed to down-convert the signal at the desired LO frequency, and they reject the harmonics of the LO signal . Similarly, the

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École de Technologie Supérieure (ÉTS), Montreal, QC H3C 1K3, Canada

N-path passive mixer-first topologies that offer input matching without using external components and high-quality filtering can be used [7–9]. However, they consume high power to achieve a low noise figure (NF). In addition, mixer-first topologies are not suitable for wideband applications. An N-path ultra-low-power mixer-first receiver is presented in [10]. Although very low power consumption is achieved, it requires an off-chip inductor and achieves a low modulation bandwidth of 3.5 MHz. A feed-forward technique with tuned LO phase was employed in [11] to reject the LO harmonics. However, the phasecorrection circuit increases the complexity of the design and reduces accuracy. A harmonic recombination technique that down-converts the signal at 3× the LO frequency is used in [12]. This technique removes all of the other harmonics at the LO frequencies such as the 1st, 2nd, 4th, and 5th harmonics. However, it consumes a significant amount of power in the baseband harmonic recombination circuitry. In addition, it uses a low noise transconductance amplifier (LNTA) with two inductors that occupy a relatively large area. Our earlier work [13] overcame the problems mentioned above. It employed a clock strategy technique to down-convert the signal at 4× the LO frequency while removing all of the other harmonics at the LO frequencies (i.e., 1st , 2nd, 3rd, 5th, 6th, and 7th harmonics). To reduce the power consumption, a current-reuse receiver topology was used. It employed the common-gate LNTA topology with a single to differential balun. In addition, an active inductor was used to improve the receiver sensitivity at higher RF. However, the clock strategy technique proposed in that prior work can be improved to reduce the mixer design complexity and the number of switches. In addition, the technique suffers from low-frequency noise due to the direct coupling of the LNTA noise to the output through the active inductor (AI).

To overcome the limitations mentioned above, this work proposes an improved clock strategy technique that reduces the number of mixer switches and the number of LO clock paths required to drive the mixer switches. This reduces the dynamic power consumption. The clock strategy technique down-converts an RF signal at 4× the LO frequency. The proposed clock strategy is verified through simulations in both cascaded and stacked receiver front-ends. In the cascade receiver front-end, very high RF bandwidth, low noise figure, and good linearity are achieved compared to the stacked receiver front-end at the cost of higher power consumption. The 1/ *f* noise problem of [13] is resolved in this work by using a 1/ *f* noise-cancellation (NC) technique. Current mode harmonic recombination is used to reduce the power consumption by avoiding the use of additional harmonic recombination circuitry.

The paper presents the clock strategy in Section 2, the cascaded receiver front-end design and its simulation results in Section 3, the stacked receiver front-end design and its simulation results in Section 4, and the comparison and discussion in Section 5. This is followed by a conclusion.

#### **2. Clock Strategy Technique**

The harmonic recombination technique has been used for wideband receiver frontends to suppress the harmonics of the LO frequency that they down-convert to the baseband along with unwanted signals and noise. A harmonic rejection mixer using a parallel mixing path with a gain ratio of 1 : <sup>√</sup>2 : 1 is proposed in [14] to reject the third and fifth harmonics at the cost of using two frequency generator circuits that consume area and power. Another approach [15] achieved higher harmonic rejection using a digital adaptive-interferencecancelling (AIC) technique to enhance harmonic rejection. However, it requires high power. In addition, it requires 4× the LO frequency to generate 8-phase clocks to down-convert the signal at the LO. In [16], a 32-phase non-overlapping LO clock is used to achieve very good harmonic rejection (HR) after LO clock-phase calibration. However, it consumes 30 mW, and it requires harmonic selective TIAs, which increases the area and power consumption. Figure 1a shows the conventional harmonic recombination technique that down-converts a wanted signal at *fLO* and rejects all of the LO harmonics (i.e., 2×*fLO*, 3×*fLO*, ..., where *fLO* = *CLKIN*/4). This requires a CLKIN signal that is equal to 4×

of the LO frequency, increasing the complexity and power draw of the clock generation circuit, due to the high clock frequencies required. To overcome these issues, this work proposes a harmonic recombination technique, shown in Figure 1b, that employs a clock strategy to down-convert the wanted signal at 4 × *fLO* and reject signals at *fLO*, 2 × *fLO*, 3 × *fLO*, 5 × *fLO* etc. For instance, using a CLKIN at 10 GHz, an RF input at 10 GHz is down-converted to baseband. This relaxes the requirements to design the LO clock generation circuits. Figure 1c shows the circuit diagram of the clock divider to generate 8-phase clocks (PH0, PH45, ..., PH316) for conventional harmonic recombination. OR-gates are used to combine the mentioned clocks to generate LO1 and LO2. The proposed clock strategy technique reduces the number of switches in the mixer to two in comparison to eight in the conventional harmonic recombination technique. This reduces the dynamic power consumption in the LO clock paths. In addition, the simplified LO routing on the chip reduces clock signal leakage to the substrate and improves signal integrity.

**Figure 1.** Harmonic recombination techniques: (**a**) cascaded approach, (**b**) stacked approach, and (**c**) clock generation circuitry.

To evaluate the proposed recombination strategy, the Fourier series coefficients are calculated using

$$\begin{cases} a\_0 = \frac{2}{N} \sum\_{k=1}^{N} s[k] \\\ a\_n = \frac{2}{N} \sum\_{k=1}^{N} s[k] .cos[\frac{2\pi}{N}nk] \\\ b\_n = \frac{2}{N} \sum\_{k=1}^{N} s[k].sin[\frac{2\pi}{N}nk] \end{cases} \tag{1}$$

where *N* is the pulse period, *k* is the sample number, *n* is the harmonic number, and *s*[*k*] is the signal given by

$$\text{s[k]} = \sum\_{m=1}^{M} (-1)^{m} P\_{m}[k] = \sum\_{m=1}^{M} (-1)^{m} (\mu[k - \frac{(m-1)\pi}{4}] - \mu[k - \frac{m\pi}{4}]) \tag{2}$$

where *u*[*k*] is the step function and *M* is the number of each shifted single pulses. The coefficients are calculated based on (1), where *a*<sup>0</sup> and *an* are zero for all harmonics, and *bn* for harmonics *<sup>n</sup>* <sup>=</sup> 4, 12, ..., 4(2i−1) is calculated by <sup>16</sup> *<sup>n</sup><sup>π</sup>* . Table 1 shows the calculated Fourier series coefficients of the proposed harmonic recombination technique for seven harmonics. It also presents the example scenario that a signal at 4 GHz is down-converted while the other LO harmonics are rejected.


**Table 1.** Fourier series coefficients of the proposed method.

#### **3. Cascaded Receiver Front-End Using the Proposed Clock Strategy**

The functionality of the proposed harmonic recombination technique is verified using a cascaded receiver front-end architecture where the LNTA, passive mixer, and TIA are cascaded. Despite previous N-path receiver architectures that use complex and powerconsuming circuits to combine the signals at the mixer output [4,17], the proposed receiver performs harmonic recombination in current-mode at the mixer output followed by a single TIA shown in Figure 2.

**Figure 2.** Cascaded receiver diagram.
