*3.2. Reference Generator*

The reference generator, which provides both the reference voltage (*VREF*) and the reference current (*IREF*), is depicted in Figure 6. The reference voltage generator is based on the two-transistor topology [25] and the cascode current mirror. This is achieved by employing voltage-to-current and current-to-voltage conversions to produce *VREF*. This is then followed by another voltage-to-current converter with a composite resistor [26] and *VREF* to generate the reference current *IREF*.

**Figure 6.** Proposed reference voltage and reference current generator.

Regarding the reference voltage generator, *M*1, *M*2, *M*3, and *M*<sup>4</sup> work in the weak inversion region, where *M*<sup>1</sup> and *M*<sup>3</sup> are identically designed native transistors with a negative threshold voltage, whereas *M*<sup>2</sup> and *M*<sup>4</sup> are identical standard transistors. It is given that, for a sub-threshold biased MOSFET, its drain current is

$$I\_{sub} = \mu \mathcal{C}\_{OX} (\eta - 1) V\_T^2 \frac{W}{L} \exp\left(\frac{V\_{GS} - V\_{TH}}{\eta V\_T}\right) \left[1 - \exp\left(\frac{-V\_{DS}}{V\_T}\right)\right] \tag{2}$$

where *μ* is the carrier mobility, *Cox* is the gate-oxide capacitance, *η* is the subthreshold slope factor, *VT* is the thermal voltage, *W* is transistor's channel width, *L* is transistor's channel length, *VGS* is the gate-to-source voltage, *VTH* is the threshold voltage, and *VDS* is the drain-to-source voltage. When *VDS* is larger than 100 mV (4 *VT*), the effect of *VDS* on *Isub* is negligible; hence, the current *Isub* can be approximated as

$$I\_{sub} \approx \mu \mathcal{C}\_{OX} (\eta - 1) V\_T^2 \frac{\mathcal{W}}{L} \exp\left(\frac{V\_{GS} - V\_{TH}}{\eta V\_T}\right) \tag{3}$$

Since the currents in *M*<sup>1</sup> and *M*<sup>2</sup> are the same, we can obtain

$$\begin{split} I\_{sub} &= \mu\_1 \mathbb{C}\_{OX1} (\eta\_1 - 1) V\_T^2 \frac{W\_1}{L\_1} \exp\left(\frac{V\_{GS\_1} - V\_{TH1}}{\eta\_1 V\_T}\right) \\ &= \mu\_2 \mathbb{C}\_{OX2} (\eta\_2 - 1) V\_T^2 \frac{W\_2}{L\_2} \exp\left(\frac{V\_{GS\_2} - V\_{TH2}}{\eta\_2 V\_T}\right) \end{split} \tag{4}$$

The current of *M*<sup>1</sup> and *M*<sup>2</sup> is the same as that of *M*<sup>3</sup> and *M*<sup>4</sup> due to the identical current copying action in the cascode current mirror *M*5–*M*8. Hence, the *VGS* of *M*<sup>2</sup> is identical to that of *M*4, which is the *VREF*. When the gates of *M*<sup>1</sup> and *M*<sup>3</sup> are connected to a ground, it suggests that the *VGS* of *M*<sup>1</sup> and *M*<sup>3</sup> are identical negative reference voltages. Thus, *VREF* can be obtained as

$$V\_{REF} = -V\_{GS1} = V\_{GS2} = \frac{\eta\_1 \eta\_2}{\eta\_1 + \eta\_2} (V\_{TH2} - V\_{TH1}) + \frac{\eta\_1 \eta\_2}{\eta\_1 + \eta\_2} V\_T \ln\left(\frac{\mu\_1 C\_{OX1} W\_1 L\_2}{\mu\_2 C\_{OX2} W\_2 L\_1}\right) \tag{5}$$

In this design, the first-order temperature effect on *VTH* is given as [7]

$$V\_{TH} = V\_{TH0} - \varkappa T \tag{6}$$

where *VTH*<sup>0</sup> is the threshold voltage at room temperature (300 K), and *κ* is the temperature coefficient of the threshold voltage. Therefore, the T.C. of *VREF* is as follows:

$$T\mathbb{C}\_{V\_{REF}} = \frac{1}{V\_{REF}} \frac{\partial V\_{REF}}{\partial T} = \frac{(\kappa\_1 - \kappa\_2) + \frac{k}{q} \ln\left(\frac{\mu\_1 \mathbb{C}\_{OX1} W\_1 L\_2}{\mu\_2 \mathbb{C}\_{OX2} W\_2 L\_1}\right)}{(V\_{TH20} - V\_{TH10}) + (\kappa\_1 - \kappa\_2)T + \frac{k}{q}T \ln\left(\frac{\mu\_1 \mathbb{C}\_{OX1} W\_1 L\_2}{\mu\_2 \mathbb{C}\_{OX2} W\_2 L\_1}\right)} \tag{7}$$

where *k* is the Boltzman constant, and *q* is the electronic charge. In (7), the temperature effect on *μ* is ignored. By selecting appropriate aspect ratios of *M*<sup>1</sup> and *M*2, while *M*<sup>3</sup> and *M*<sup>4</sup> remain the same size as *M*<sup>1</sup> and *M*2, respectively, the temperature compensation can be achieved to permit *VREF* in the first-order temperature compensation. Finally, it yields

$$V\_{REF} = \frac{\eta\_1 \eta\_2}{\eta\_1 + \eta\_2} (V\_{TH20} - V\_{TH10}) \tag{8}$$

In addition, the *VREF* has a good power supply rejection (PSR) at low frequency. Since the effect of Δ*VDD* on the flowing currents, *M*<sup>2</sup> and *M*<sup>4</sup> are negligible, as long as their *VDS* values are larger than 100 mV, while the transistors have a long channel length to reduce the drain-induced barrier lowering (DIBL) effect on *VTH*1~*VTH*4. Besides, the negative feedback formed by *M*3, *M*4, and *M*<sup>9</sup> can further stabilize *VREF*.

For the reference current, it is produced by *VREF* driving a temperature-compensated composite resistor (*Rs*). Of particular note, *Rs* comprises the series connection of an n-poly resistor (*Rn*) and a p-poly resistor (*Rp*), where *Rn* is PTAT and *Rp* is CTAT. The T.C. of *Rp*, *Rn*, and *Rs* are given as follows:

$$T\mathbb{C}\_{Rp} = \frac{1}{R\_p} \frac{\partial R\_p}{\partial T} \tag{9}$$

$$TC\_{R\text{fl}} = \frac{1}{R\_P} \frac{\partial R\_{\text{fl}}}{\partial T} \tag{10}$$

$$T\mathbb{C}\_{Rs} = \frac{1}{R\_p + R\_n} \frac{\partial \left( R\_p + R\_n \right)}{\partial T} \tag{11}$$

Substituting (9) and (10) into (11), *TCRs* can be rewritten as

$$TC\_{Rs} = \frac{R\_p}{R\_p + R\_n} TC\_{Rp} + \frac{R\_n}{R\_p + R\_n} TC\_{Rn} \tag{12}$$

where *TCRp* is negative and *TCRn* is positive. Thus, *TCRs* can be made zero when choosing *Rp*/*Rn* equal to |*TCn*/*TCp*|. This indicates that *Rs* can be independent of the first-order temperature effect. Therefore, the temperature-insensitive reference current (*IREF*) can be obtained with the temperature-insensitive voltage and the composite resistor.

$$I\_{REF} = \frac{V\_{REF}}{R\_{\rm s}} = \frac{\eta\_1 \eta\_2 (V\_{TH20} - V\_{TH10})}{(\eta\_1 + \eta\_2)(R\_p + R\_n)}\tag{13}$$

Moreover, since *Rs* is independent of *VDD*, *VREF* is insensitive to the change in *VDD*. As a result, *IREF* is also insensitive to the supply variations.

As seen in Figure 6, the capacitor *C*<sup>1</sup> is used as a frequency compensation for the negative feedback loop which is formed by *M*3, *M*4, and *M*9. In addition, the capacitor *C*<sup>2</sup> is used to stabilize *VREF* when the switches in Figure 4 are turned on and off. This is because the voltage change will be coupled to the gate of *M*<sup>9</sup> by the parasitic capacitors. The current mirror pairs *M*5–*M*<sup>8</sup> and *M*10–*M*<sup>13</sup> have a long channel length to reduce the current mismatch.

The 1.1 V supply voltage of this reference generator can ensure that all transistors still work in the proper region when there is a 10% supply voltage drop, but if the supply continuously decreases below 1 V, there will not be adequate *VDS* headroom for the current mirror pair in Figure 6 at the SS corner under a low temperature, due to the increase in *VTH*.

Finally, the size of each component pertaining to Figure 5 in the reference generator is listed in Table 1.


**Table 1.** Size of components in the reference generation.
