**4. Simulation Results**

In this section, the post-layout simulation results referring to a TSMC 180 nm CMOS process for the conventional BD-OTA, and the proposed one, are reported. The circuits are considered to operate under the same conditions, i.e., 27 °C temperature, *V*DD equal to 0.6 V, Ibias equal to 100 pA, besides the typical process parameters. Characteristics from both OTAs were obtained by simulating the four testbenches shown in Figure 9. Figure 9a shows the integrator test bench used in the AC and DC simulations. This scheme allows the evaluation and comparison of DC open-loop gain, as also the gain-bandwidth product (GBW) of each OTA version. Then, Figure 10a shows the open-loop gain AC simulation results, and Figure 10b shows the DC simulation results.

It can be noted that the use of improved mirrors increases DC gain without changing considerably the gain-bandwidth product of the OTA versions using the same differential pair, as they are biased with the same current. As expected, the proposed BD OTA with the enhanced mirror has lower transconductance, while keeping higher gain and the same linearity than the typical BD topology.

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**Figure 9.** *Cont*.

**Figure 9.** OTA testbenches. (**a**) OTA-C integrator. (**b**) Transconductor (Symmetrical). (**c**) Transconductor (asymmetrical). (**d**) OTA-C low-pass filter. (**e**) Unity gain buffer.

As the power supply rejection ratio (PSRR) is equal to the OTAs DC gain, there is a unity gain voltage between supply and output voltages. The common-mode rejection ratio (CMRR) is inherently increased by the use of improved mirrors, as the current source transistors also use improved self-biased cascode configuration. The CMRR and PSRR can be noted in Figure 10c,d, respectively. Table 3 summarizes the AC simulation results.

**Table 3.** Integrator simulation results summary.


**Figure 10.** Integrator test bench simulation results. (**a**) AC voltage gain transfer function. (**b**) DC voltage gain transfer function. (**c**) AC CMRR transfer function. (**d**) AC PSRR transfer function.

Figure 9c shows the testbench used in the DC simulations to compare the transconductance linearity of each OTA version. Figure 11a–c show, respectively, the output current, transconductance, and transconductance error for the conventional BD-OTA and for the proposed one.

**Figure 11.** Transconductor testbench simulation results. (**a**) Output current. (**b**) Tranconductance. (**c**) Transconductance error. (**d**) Normalized transconductance.

Table 4 summarizes the transconductance and impedance simulation results for Ibias equal to 100 pA. Notice that BD OTAs have finite DC input impedances (1/*G*i) as large as their output impedances (1/*G*o), which reduces considerably the effectiveness of the gain improving technique in practical use, where the OTAs are cascaded in OTA-C filters.

**Table 4.** BD-OTAs DC results.


In Figure 11d, the transconductance normalized with respect to the supply voltage *V*DD is shown. It is possible to note that both OTA versions work properly from a minimum *V*DD of about 300 mV, which is feasible for implants and wearable biomedical trends. Unlike conventional gate-driven OTA topologies, which are limited by the minimum common-mode input voltage *V*cmi, and in which frequently are set to half *V*DD to allow the current source transistors to operate in saturation, according to mentioned this limitation is mitigated in BD topologies. Besides the mentioned aspects, it is worth noticing that the

minimum operational voltage, *V*DD, is directly influenced by the current source, and the differential pair transistors channel inversion, hence which are themselves a function of the bias current, i.e., Ibias. In this way, a higher biasing current would result in a larger linear input range and greater transconductance, on the other hand, also a higher minimum *V*DD.

Figures 12a,b and 13a,b show the nominal output current and its resulting transconductance for symmetrical and asymmetrical input voltage, according to the testbenches shown in Figure 9b,c, respectively. For the asymmetrical test, the inverting input is kept constant at *V*cm = *V*DD/2, so −300 < Δ*V*in < 300 mV, while, for the symmetrical input, both OTA inputs are at *V*cm for *V*in = 0 V, and the differential input voltage excursion is doubled to −600 < Δ*V*in < 600 mV. Moreover, for the asymmetrical testbench, the common mode input voltage *V*cmi varies with the input voltage *V*in, so *V*cmi = *V*in/2 + *V*cm. For the symmetrical testbench, *V*cmi is constant, as the average of the inverting and non-inverting input voltages are the same. It can be noticed, for both cases, that as the biasing current Ibias increases, the transconductance *G*<sup>m</sup> increases almost proportionally.

**Figure 12.** Output current *Io* for (**a**) symmetrical, and (**b**) asymmetrical input voltage *V*in, as a function of Ibias.

**Figure 13.** Nominal transconductance *G*m for (**a**) symmetrical, and (**b**) asymmetrical input voltage *V*in, as a function of Ibias.

For a better comparison, for different biasing currents, the transconductances were normalized for Δ*V*in = 0, as shown in Figure 14a,b. It is clear for the asymmetrical input that the error is larger for Δ*V*in < 0. This happens for two reasons: the parasitic substrate current at the differential pair is extremely non-linear and the common-mode input voltage goes above the limit for Ibias = 10 nA. For symmetrical input, the resulting *G*<sup>m</sup> is also symmetrical and the range is twice as high. It can also be noted that the shape of the curve changes as the current increases, which is expected, as the differential pair inversion increases.

**Figure 14.** Normalized transconductance *G*m for (**a**) symmetrical, and (**b**) asymmetrical input voltage *V*in, as a function of Ibias.

It is also important to notice that for single-ended OTA applications, normally, the input is not symmetrical. This is the case with most OTA-C filters, such as those based on integrators and active loads, as depicted in the testbenches shown in Figure 9a,d. For wider range and linearity, the single-ended OTA should be converted to its fully differential version, which needs extra biasing circuits for its output common-mode definition.

As previously explained, the parasitic input current is one of the causes of transconductance asymmetry. This parasitic current is shown in Figure 15a, and is a function of the input voltage and biasing current. There is a single point where the input current is zero, which happens when the differential pair PMOS transistor bulk-terminal voltage is equal to its source-terminal voltage. For input voltages below this point, the transistor is forward-body-biased and the parasitic current grows exponentially. For voltages above this point, the parasitic current is almost constant, consequently, the input conductance is very small. Figure 15b shows the OTA output current for both inputs at *V*DD/2 and the output sweeping from 0 to 600 mV. As can be seen, the output current, even considering that the current mirrors attenuate the differential pair output current, is considerably larger than the parasitic current for a large range.

**Figure 15.** Nominal (**a**) input current Iin × input voltage *V*in, and (**b**) output current *I*<sup>o</sup> × output voltage *V*o, as a function of Ibias.

The input and output conductances can be derived from the input and output currents, as shown in Figure 16a,b, respectively. It is worth noting that for OTA-C filter applications, the OTA outputs terminals will be connected to other OTAs input terminals. The main

advantage of the proposed improved self-cascode current mirror is to decrease the output conductance as it increases the output resistance. If the input conductance of the subsequent stage is greater than the output conductance, the technique effectiveness is reduced.

**Figure 16.** Normalized (**a**) input conductance *G*i, and (**b**) output conductance *G*<sup>o</sup> as a function of Ibias.

In order to compare the linearity OTAs, the unity gain low-pass OTA-C filter testbench shown in Figure 9d was used in DC and transient simulations. Figure 17a,b show, respectively, the DC transfer functions, transient, and the total harmonic distortion (THD) for both OTAs. It is possible to observe that the BD OTAs have almost the same full input range. Figure 17b shows the total harmonic distortion versus input plotted as a function of input signal amplitude. For both OTAs, one can observe that THD is lower for smaller signal amplitudes. They exhibit approximately the same amount of distortion of 0.07% as a result of a 300 mV amplitude input signal at 100 mHz. As the input voltage amplitude increases, the proposed OTA reaches ≈ 1% THD (−39.8 dB), SNR equal to 56.6 dB for a *V*in−pp = 405 mV at 100 mHz signal.

**Figure 17.** Low-pass testbench simulation results. (**a**) Transfer functions. (**b**) Total harmonic distortion.

Figure 18 shows the input-referred noise (IRN) for both OTA versions configured as a unit-gain buffer. Since both OTA versions have the same transistor dimensions, differing only by the adopted current mirror topology, there is a slight difference in IRN of conventional BD-OTA and the proposed one. The IRN in the proposed topology is equal to 246 μVRMS, and 237 μVRMS in the other, both obtained by integrating noise from 10 mHz–1 kHz.

**Figure 18.** Unity gain buffer testbench simulation results—input-referred noise.

By using the transconductor (Figure 9c) and low-pass filter (Figure 9d) testbenches, 500 runs of Monte Carlo have been carried out for evaluation of transconductance and offset voltage, respectively. Figure 19a,b show the results for the Monte Carlo process and mismatch analysis of the proposed BD-OTA. These results are summarized in Table 5. On this basis, it is possible to conclude that the proposed BD-OTA besides a lower transconductance feature, has a considerably less input voltage offset than the conventional BD-OTA.

**Figure 19.** Five hundred runs of Monte Carlo simulations analyzing process and mismatch with the proposed BD-OTA. (**a**) Transconductance. (**b**) Offset.



Table 6 compares the performance of the proposed OTA with the state-of-art lowtransconductance OTAs. The previous work proposed by us [48] presented a 450 pA/V OTA with small power consumption but lower gain, CMRR, and PSRR, despite being based on non-unitary current gain through the splitting current technique, it achieved a poorer performance with respect to the present work. In [49], a low-transconductance amplifier has been proposed based on the channel-length-modulation effect (Early effect). This solution

shows a high IRN. Such an IRN is 3x smaller in the proposed topology while keeping lower transconductance, power consumption, and higher CMRR as also PSRR features. The OTA proposed by [28] is similar to the conventional OTA presented in this work. The difference is in the rectangular arrays used to increase the gain and in no linearization technique employed. Another low-*G*<sup>m</sup> topology presented by [50] uses a linearization technique that relies on a combination of source degeneration with an active attenuator. Despite the valuable linearity and gain achieved, the power consumption, and transconductance may not be suitable to the constraints of biomedical implants or bio-sensing operations. The architecture proposed by [51] is another channel length modulated OTA which contains the same V-I conversion scheme as presented in [49] but requires a higher supply voltage.


**Table 6.** Comparison of Low-*G*m OTA topologies.

THD @ Vin = 250 mVpp, (M): Measured, (S): Simulated.
