**4. A Standard-Cell-Based Digital–Delta (**Δ**) Modulator (**Δ**M) with Noise Shaping (NS)**

A complete and differential electrical scheme of the proposed ADC topology, a digital-ΔM employing NS, is depicted in Figure 15, complementing the description in Section 2.5. It comprises a split-capacitor DAC with embedded S/H, a pseudodifferential inverterbased Nagaraj integrator with a fully passive SC CMFB circuit (shown in Figure 12), an OAI-based comparator (whose circuit is shown in Figure 10), an accumulator, and a phase generator. Thus, a fully synthesizable ADC is demonstrated, only recurring to passive and standard-cell-based circuitry.

As described in Figure 16, its operation is based on two different frequencies. The sampling and NS function at *FS*, while the delta modulation is performed at a higher frequency.

After the DAC is reset, the sampling of the *Vin* and the noise-shaping voltage, *VNS*, is simultaneously performed in the most significant bit (MSB) section of the DAC and on the dedicated capacitor, *CNS*, respectively. After that, delta modulation starts: the comparator makes a decision that is transmitted to the accumulator to reconfigure the DAC for the next comparator decision. This action is performed during *M* averages, and the accumulator output is lastly ready. Before the new reset of the DAC, residue voltages *VRES*,*<sup>P</sup>* and *VRES*,*<sup>N</sup>* are integrated by the pseudodifferential inverter-based Nagaraj integrator scheme; consequently, *VNS*,*<sup>P</sup>* and *VNS*,*<sup>N</sup>* are updated. Then, a new sampling of the *Vin* and the *VNS* is performed, and the process continues repeatedly.

**Figure 15.** Scheme of the proposed standard-cell-based digital-ΔM with NS employing a splitcapacitive DAC, an inverter-based OTA topology, to perform NS and an OAI-based comparator.


**Figure 16.** Illustrative timing of the proposed digital-ΔM ADC employing NS.

The simulated output spectrum of the proposed converter, fully implemented in a 28 nm CMOS technology, is shown in Figure 17. With an oversampling ratio (OSR) of 32 and a 10-bit DAC, a peak of 72.5 dB in the signal-to-noise and distortion ratio (SNDR) was achieved for a ≈113 kHz input signal and a 1 MHz BW. Table 3 summarizes the simulation results. The converter dissipated ≈112 μW, which could be translated into a Walden figure of merit, FoMWalden, of 16.2 fJ/conv.-step.

These results are promising, allowing for a fully synthesizable ADC that is capable of achieving both high resolutions and good energy efficiency.

**Table 3.** Summary of simulated results of the proposed standard-cell-based digital-ΔM employing NS using a 28 nm CMOS technology.


**Figure 17.** Simulated output spectrum of the schematic of the proposed standard-cell-based digital-ΔM employing NS. This result was achieved using 2<sup>14</sup> points, *M* = 8, a BW of 1 MHz (OSR of 32), and a Fin of 113 kHz.

### **5. Conclusions**

The most-suited high-resolution ADC topologies for IoT applications were described and compared in terms of complexity, overall performance, and energy efficiency. ΔM was described because it is the basis of some well-known topologies and has inspired others, such as SAR-ADC with NS or ΔΔΣM ADC. Taking into consideration the advantages of standard-cell-based synthesizable schemes, some schematics of comparators and amplifiers were reported, and their key performance parameters were compared. An innovative topology, a digital-ΔM ADC employing NS, was detailed employing passive and standardcell-based circuitry. An SNDR of 72.5 dB was achieved for a 1 MHz BW (OSR of 32) with an estimated FoMWalden of 16.2 fJ/conv.-step. Thus, a fully synthesizable ADC that is compatible with IoT applications was clearly demonstrated.

**Author Contributions:** Conceptualization: A.C., V.G.T. and J.G.; methodology: A.C., V.G.T. and J.G.; investigation: A.C., V.G.T. and J.G.; writing—original draft preparation: A.C.; writing—review and editing: all authors; supervision: V.G.T., P.B. and J.G. All authors have read and agreed to the published version of the manuscript.

**Funding:** This work was funded by National Funds through FCT—Fundação para a Ciência e a Tecnologia, I.P., through a Ph.D. Grant (SFRH/BD/137519/2018) and the following project references: UIDB/50025/2020-2023, SMART-E-PTDC/CTM-PAM/04012/2022, IDS-PAPER-PTDC/CTM-PAM/4241/2020 and PEST (CTS/UNINOVA)-UIDB/00066/2020. This work also received funding from the European Community's H2020 program [Grant Agreement No. 716510 (ERC-2016-StG TREND) and 952169 (SYNERGY, H2020-WIDESPREAD-2020-5, CSA)].

**Data Availability Statement:** The data presented in this study are contained within the article.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**

