**4. Validation Results**

The proposed solution in the version of 3-, 5- and 7-stage CROs was designed in a 28-nm triple-well CMOS technology provided by TSMC and simulated at the schematic level. To set symmetrical behavior of the inverter, of the control bulk voltages ranges and body effect coefficients, MOS transistors with different thresholds were exploited. Specifically, HVT (high threshold) n-channel with 515-mV *VTH* and SVT (standard threshold) p-channel devices with −460-mV *VTH*, were adopted. A single power supply of 0.5 V was set and *IBIAS* was 320 nA. Reference operating temperature was in the range from 0 ◦C to 60 ◦C, suitable for implanted and wearable circuits. Transistor dimensions, together with other component values, are summarized in Table 1.

**Table 1.** Design parameters used in simulations.


a: This value will be changed to 350 nA after corner analysis.

All p-channel (n-channel) MOSFETS are equal to the reference device 8.28/0.18 (5.4/0.18) μm/μm, where channel length was slightly increased as respect to the minimum one (100 nm) to counteract the short-channel effect. With these design choices the

mirroring coefficient, *ki*, and the ratios of the transistors' form factors in (1)–(3) are all reduced to the unity. As a consequence of the transistor's dimension, the nominal quiescent current in each branch, which coincides with its short-circuit current, of 320 nA, resulting in a total nominal quiescent current of *N*-times 320 nA. Coarse tuning capacitor *Ci* was set to 10 fF for all stages. The DC gain of the auxiliary amplifiers, A1 and A2, with transistors in subthreshold, was around 30 dB and the gain-bandwidth product was 10 kHz, while consuming only 50 nA.

The robustness of the quiescent conditions was validated at first. The nominal bulk voltages, *VBP* and *VBN*, generated by the circuit in Figure 2 were 251 mV and 249 mV, respectively. The simulated quiescent current in the main ring oscillator in Figure 1 was 961, 1602 and 2243 nA on average, with a standard deviation of 48.5, 78.3, and 107 nA, respectively, for 3-, 5-, and 7-stage topology after running 1000 Monte Carlo iterations. The difference with respect to the expected values is mainly due to the low DC gains of the auxiliary amplifiers, which cause a closed-loop gain error.

Figure 6a shows the body voltages of the transistors involved in the reference inverting gate for a sweeping of the biasing current, *IBIAS*, in the range 120 nA–820 nA. The voltages fall within the supply rails and, in particular, it is easy to observe that their behaviors are symmetrical, confirming a good sizing of the block and the possibility to exploit the full dynamic range of the control voltages. Currents entering in the body terminals have been also evaluated and reported in Figure 6b to highlight that body junctions are never fully turned on during the control operation. In fact, the values of body currents in the worst case (PMOS), reach around 10 nA, corresponding to less than 2% of the biasing one.

**Figure 6.** Body voltages (**a**) and currents (**b**) in the interested current biasing range at *T* = 30 ◦C.

Figure 7a depicts the current flowing in the reference inverting gate when its input is varied from 0 to *VDD* (500 mV). As expected, the maximum is achieved for *VDD*/2 and accurately follows *IBIAS* as a validation of the effectiveness of the exploited biasing strategy and the linearity of the relation between the two quantities as well.

Figure 8 illustrates the output signal of the 5-stage CRO with *Ci* = 10 fF for three values of biasing current, 120, 320, and 820 nA, representing the minimum, nominal and maximum value, respectively.

Figure 9 shows the oscillation frequency as a function of biasing current (*Ci* = 10 fF). An oscillation range from 360 MHz to 640 MHz is found with tuning sensitivity, i.e., the ratio between (*fMAX* − *fMIN*)/(*IBIAS,MAX* − *IBIAS,MIN*), about equal to 0.43 MHz/nA. Compared with the predicted behavior (linear relationships resulting from (14) and (15)), the obtained one shows a logarithmic relationship with *IBIAS*. This is confirmed by the inset plot in the same figure, the x-axis of which is logarithmic and slightly extended to cover an entire decade. Such changing in the behavior may be due to the partial operation in moderate inversion region, where subthreshold equations lose accuracy.

**Figure 7.** Static currents flowing in the reference inverter vs. input voltage for different *IBIAS* (**a**), and static currents maxima vs. *IBIAS* (*T* = 30 ◦C) (**b**).

**Figure 8.** Output signal of 5-stage CRO for three different values of biasing current at *T* = 30 ◦C.

**Figure 9.** Oscillation frequency of the 5-stage CRO as a function of the biasing current at *T* = 30 ◦C.

Figure 10a,b shows oscillation frequency with number of stages *N* equal to 3, 5, and 7 and for different coarse tuning capacitances, *Ci*, in the considered current biasing range (Figure 10a) and for a fixed *IBIAS* = 320 nA (Figure 10b) at *T* = 30 ◦C. It is apparent that frequency varies with the bias current, independently of the number of stages and coarse tuning capacitance. Constant spacing between two adjacent curves shows that the number of stages *N* acts as a scaling constant factor in the expression of the frequency, as predicted by (14) or, equivalently, (15). Moreover, Figure 10b highlights that the coarse tuning capacitance is comparable, in the range between 10 fF and 100 fF, with the parasitic inverter capacitances, being the oscillation frequency to capacitance relation compressed in this range.

**Figure 10.** Oscillation frequencies for different coarse tuning capacitance values in the interested current biasing range (**a**) and for a fixed *IBIAS* = 320 nA (**b**) at *T* = 30 ◦C.

Figures 9 and 10 also show that the proposed solution may be used in an automatic design procedure, which, starting from the oscillation frequency specification and the nominal bias current, allows to determine the number of inverter stages (which can be taken from a standard-cell library providing access to the bulk terminals) and the coarse tuning capacitances (which can be taken from a capacitor array). The bias current is then used to perform oscillation frequency tuning to counteract process and temperature variation effects.

At this purpose, corner analyses were carried out for the 5-stage topology as an illustrative example. Figure 11 shows the two bulk-source voltages VBN and VBP as a function of *IBIAS*, at 30 ◦C. It is apparent that to ensure correct operation (i.e., to maintain bulk voltages within the supply limits) biasing current range must be limited from 240 nA to 460 nA.

**Figure 11.** Bulk−source voltage of NMOS (**a**) and PMOS (**b**) transistors vs. biasing current over the 5 basic process corners.

Specifically, NMOS transistors experience the highest process variations. In fact, the upside limit of the current range under slow NMOS corners (SS or SF) must be limited to 460 nA. Vice versa, under fast NMOS corners (FF or FS), *IBIAS* current must be larger than 240 nA.

Figure 12 shows the simulated oscillation frequency of the 5-stage ring oscillator in this range of *IBIAS*, for the five basic corners (at 30 ◦C). It can be noted that the tuning frequency range is independent of the process corners. Indeed, the tuning sensitivity is constant regardless the corner and is still approximately equal to 0.43 MHz/nA. The maximum percentage variation between the nominal oscillation frequency and that affected by corners is about 20%.

**Figure 12.** Oscillation frequency vs. biasing current over the 5 basic process corners.

Phase noise versus offset frequency (Δf) for the basic corners is illustrated in Figure 13, which clearly shows the close overlap of the five curves, indicating that also the phase noise is process independent.

**Figure 13.** Phase noise vs. offset frequency over the 5 basic process corners.

Phase noise was also simulated in the 0 ◦C to 60 ◦C temperature range and across the five corners. The minimum value of the simulated phase noise is −91.86 dBc/Hz when *T* = 0 ◦C in the FF corner, while the maximum value of the simulated phase noise is −93.72 dBc/Hz when *T* = 0 ◦C in the SS corner (both values are evaluated at the nominal bias current *IBIAS* equal to 350 nA).

Tables 2–4 summarize the corner analysis results of the main parameters of the simulated 5-stage current-controlled ring oscillator (nominal *IBIAS* equal to 350 nA and at 30 ◦C) for three values of the supply voltage *VDD*.

**Table 2.** Corner analysis of the 5-stage current-controlled ring oscillator performed at 30 ◦C and at *VDD* = 475 mV.


**Table 3.** Corner analysis of the 5-stage current-controlled ring oscillator performed at 30 ◦C and at *VDD* = 500 mV.


**Table 4.** Corner analysis of the 5-stage current-controlled ring oscillator performed at 30 ◦C and at *VDD* = 525 mV.


Due to process variations, oscillation frequency varies of about 20%. However, tuning range variations across the five corners are limited to 8% and both phase noise and average power consumption variations are 5%. Regarding power consumption, the typical (TT) value is accurately predicted by (14), where *Ctot* can be estimated to be 88.6 fF, including the additional load capacitance of 10 fF. This value agrees with the results shown in Figure 10b.

Mismatch Monte Carlo simulations of the oscillation frequency in typical conditions (*VDD* = 0.5 V, *IBIAS* = 350 nA and *T* = 27 ◦C) are reported in Figure 14, showing the limited impact of mismatches on the oscillation frequency of the proposed CRO.

**Figure 14.** Mismatch Monte Carlo simulations of the oscillation frequency in typical conditions (*VDD* = 0.5 V, *IBIAS* = 350 nA and *T* = 27 ◦C).

As already mentioned, the tuning capabilities of the proposed CRO can be exploited to compensate for the effects of temperature variations (in a non-exclusive alternative to process variations). To give an example, Figure 15 shows some isofrequency curves (at 557 MHz, 538 MHz, 516 MHz, 491 MHz, and 462 MHz) in *IBIAS* vs. temperature plot. Each point of the curves establishes the current *IBIAS* needed to set the target frequency between around 450 MHz and 557 MHz in the operating range from 0 ◦C to 60 ◦C.

**Figure 15.** Isofrequency curves in the *IBIAS* vs. temperature plot (TT).

The tuning capabilities of the proposed CRO can be exploited also to compensate the effects of supply voltage (*VDD*) variations. To give an example, Figure 16 shows some isofrequency curves (at 557 MHz, 538 MHz, 516 MHz, 491 MHz, and 462 MHz) in the *IBIAS* vs. *VDD* plot. Each point of the curves establishes the current *IBIAS* needed to set the target frequency between around 450 MHz and 557 MHz in the operating range from 475 mV to 525 mV.

**Figure 16.** Isofrequency curves in the *IBIAS* vs. *VDD*, (TT).

The layout of the five stage CRO is reported in Figure 17, showing an area footprint of 12.4 μm × 7.5 μm. To better assess the reliability of the above results, post layout simulations have been carried. The main effect of the layout resulted in a parasitic capacitance of 6.5 fF at the output node of the CRO. Once reduced the explicit coarse tuning capacitance of an amount equal to the parasitic capacitance, post layout simulations resulted to be in very good agreement with schematic level simulations.

Table 5 compares some recent controlled oscillator topologies presented in the literature with the proposed one, which provides the best performance in terms of phase noise and power consumption, determining the best FoM as defined by (19).

**Figure 17.** Layout of the five stage CRO.

**Table 5.** Comparison with the state-of-the-art.


a: see (16); b: simulations.

#### **5. Conclusions**

A novel approach to tune the delay of the basic inverter cell of CROs has been presented in this paper. The approach allowed to accurately set the maximum current of all the inverters in the CRO through a body bias loop and to tune the oscillation frequency by controlling the value of a reference current. Small-signal and large-signal analysis of the proposed CRO topology have been carried out to provide insight into circuit behavior and to provide useful design equations.

Current controlled ring oscillators made up of 3, 5, and 7 stages have been designed referring to a commercial 28-nm technology and with a supply voltage of 0.5 V.

Simulation results demonstrated that the proposed approach allows to optimize the tradeoff between tuning range, phase noise and power consumption, as demonstrated by the value of the FoM which outperforms all the similar designs in the literature. Extensive parametric and corner simulations have demonstrated a good robustness of the proposed CROs to PVT variations despite the adoption of a very short channel process node.

**Author Contributions:** Conceptualization: S.P. and G.S.; data curation: A.B. and C.V.; original draft preparation: A.B. and C.V.; writing—review and editing: all authors; supervision: S.P. and G.S. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research received no external funding.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** The data presented in this study are available in article.

**Conflicts of Interest:** The authors declare no conflict of interest.
