*3.2. Extraction of Drain-Induced Barrier-Lowering Factor (σ)*

The DIBL factor *σ* is a small-signal parameter that affects the intrinsic voltage gain of the common source amplifier. Figure 6 presents a schematic to determine the commonsource intrinsic gain (CSIG) and the equivalent small-signal model [17] of the amplifier.

**Figure 6.** (**a**) Circuit to determine the CSIG and (**b**) its equivalent small-signal model.

In saturation, the use of the transconductance-to-current characteristics (11) and (12) yields the CSIG in (23).

$$A\_{V,CS} = \frac{\upsilon\_d}{\upsilon\_\mathcal{S}} = -\frac{\mathcal{g}\_{\text{nr}}}{\mathcal{g}\_{\text{md}}} = -\frac{1}{\sigma} \tag{2.3}$$

To determine the common-source intrinsic gain through a simulation, an ideal operational amplifier was included, as shown in Figure 6a, to set the DC operating point required for the small-signal measurement.
