*2.1. Stage*<sup>1</sup>

The topology of the blocks denoted as stage1 in Figure 1 is reported in Figure 2, and is made up of transistors *M*1*A*, *M*1*<sup>B</sup>* and *M*2*A*, *M*2*B*. This input stage has the same topology adopted for the OTA in [40]. It is a bulk-driven stage in which the bias current is accurately set through the *VGN* voltage applied to the gate of transistor *M*2*A*. The bias voltage *VGN* is generated by the biasing circuit reported in Figure 3. The current flowing in *M*2*<sup>A</sup>* is mirrored through *M*1*<sup>A</sup>* and *M*1*B*, so that the standby current of all MOS devices is accurately set. The body terminals of transistors *M*1*<sup>A</sup>* and *M*1*<sup>B</sup>* are connected to the input voltages, *VIP* and *VIM*, respectively. The output of stage <sup>1</sup> is loaded through a body–diode connection on the transistor *M*2*<sup>B</sup>* whose gate voltage is connected to the bias voltage *VGN*, and results in an output impedance lower than the one of conventional input stages. This stage thus provides limited gain, but allows achievement of a rail-to-rail input common mode range and improvement of the bandwidth. As a consequence, noise and mismatch of the second stage contributes to the total input referred noise and offset. However, even if noise and offset performance are suboptimal, the OTA can still be designed to exhibit acceptable noise and offset, while achieving very good bandwidth efficiency.

**Figure 2.** Stage <sup>1</sup> used in the proposed OTA architecture.

**Figure 3.** Biasing circuit used in the proposed OTA architecture.
