**2. Current Mirrors**

Current mirrors are the essential component of CMOS OTAs, and their output impedance improvement leads to OTAs with superior voltage gain and common-mode rejection. Implementing current mirrors with series-parallel associations of transistors is a design solution that allows for high current gain, reduced area usage, and less process variability compared to parallel-only current mirrors [22]. This technique was employed by [23] to achieve very low transconductance OTAs without sacrificing linearity and process variability tolerance [13,14]. Since the output transistor array has a large equivalent channel length (*L*eq), the output current *I*o is less dependent on the output voltage *V*out variation.

Rectangular transistor arrays as illustrated in Figure 1 can be considered understood as a single transistor [31] with a higher output impedance [2,23,39]. The rectangular array, shown in Figure 1, is an *m* by *n* matrix of single transistors composed of *m* parallel columns of *n* series single transistors. The rectangular equivalent transistor aspect ratio *S*eq−<sup>R</sup> is a function of the single transistor aspect ratio *S*u, as shown in Equation (1). The total gate area of the rectangular array is *A*<sup>T</sup> = (*mn*)*A*u, where *A*<sup>u</sup> is the gate area of the single transistor.

$$\mathcal{S}\_{\text{eq}-\mathbb{R}} = \frac{\mathcal{W}\_{\text{eq}}}{L\_{\text{eq}}} = \frac{m\mathcal{W}\_{\text{u}}}{nL\_{\text{u}}} = \frac{m}{n}\mathcal{S}\_{\text{u}}.\tag{1}$$

Figure 2 represents an N-type improved composite transistor. It consists of a series connection of two independently forward-body-biased N-type MOS transistors MN1 and MN2, as first proposed in [35], and described in detail in [13,14,37], by using the ACM (advanced compact model) all-region transistor model [40].

**Figure 1.** Rectangular 1 × *m* : *n* transistor array.

**Figure 2.** Improved composite transistor.

The improved composite transistor equivalent aspect ratio *S*eq is defined as:

$$S\_{\rm eq} = \frac{S\_{\rm N1} \cdot \beta S\_{\rm N2}}{S\_{\rm N1} + \beta S\_{\rm N2}} = \frac{\beta k}{\beta k + 1} \cdot S\_{\rm N1} \tag{2}$$

where

$$\mathcal{B} \approx \mathcal{e}^{\frac{(n-1)\Delta V\_{\rm B}}{n\rho\_{\rm f}}} \tag{3}$$

represents a correction factor for the current drain ID definition due to the difference between the body-bias of the series transistors MN2 and MN1 Δ*V*<sup>B</sup> = *V*B2 − *V*B1, assuming the transistors are operating in weak inversion, and

$$k = \frac{\mathcal{S}\_{\rm N2}}{\mathcal{S}\_{\rm N1}} \tag{4}$$

is the ratio between transistors MN1 and MN2 and physical aspect ratios *S*N1 and *S*N2. Figure 3a shows the conventional current mirror (CM). The ratio between transistors M1B, and M1A aspect ratios *S*1A and *S*1B define the current mirror gain *A*<sup>I</sup> = *S*1B/*S*1A and attenuation 1/*A*I. In order to have a better matching for non-unity current gain, the current mirror transistors should be replaced with rectangular transistor arrays [22].

A higher current attenuation is achieved by combining parallel transistor arrays at the current mirror input, and series transistor arrays at the output. This scheme is a desirable feature for ultra-low transconductance OTAs [21,23], as it provides transconductance attenuation without decreasing linearity.

The typical cascode current mirror is a variation of the Wilson current mirror first proposed by [41]. The topology increases the output impedance in order to decrease the output current gain error. On the other hand, its drawback is a lower output voltage swing, which will be solved by the proposed current mirror as follows.

An alternative topology to a typical cascode, is the self-biased self-cascode current mirror (SCCM), first proposed by [42], which uses composite transistor arrays in a trapezoidal shape, which are equivalent to single transistors with increased output impedance. The trapezoidal geometry means that the top composite transistors, i.e., those related to drain portion must have a greater aspect ratio than the bottom transistors, i.e., corresponding to source portion, so this kind of composite transistor can be made by arranging their drain transistors in an array connected to a series array corresponding to source transistors (the smaller base of the trapezoid) [43]. This topology is recommended for low input currents and unity current mirror gain, but it is not appropriate for higher currents or very large current gains, since it would require a very large area. Nevertheless, the trapezoidal current mirror can still use the parallel-series technique for current attenuation [21,22] by replacing the output series transistor array with a trapezoidal transistor array, as shown in Figure 3b. This is possible because there is no need for trapezoidal arrays at the mirror input for non-unity gains.

**Figure 3.** Self-biased current mirrors: (**a**) conventional current mirror with rectangular transistor arrays (CM) [22], (**b**) trapezoidal output current mirror (SCCM) [42], and (**c**) improved self-cascode current mirror (ISCCM).

By taking (2), *β* = 1, and since M1B and M2B bulk terminals are connected to each other, the current gain *A*<sup>I</sup> can be expressed as

$$A\_{\rm I} = \left(\frac{S\_{\rm 2B}}{S\_{\rm 1B} + S\_{\rm 2B}}\right) \cdot \frac{S\_{\rm 1B}}{S\_{\rm 1A}}\tag{5}$$

For *S*2B *S*1B, the SCCM current gain is approximately *S*1B/*S*1A, as in the conventional parallel-series current mirror. However, this current mirror has a relatively larger output resistance, consequently, it is more tolerant to output voltage variation.

The SCCM output resistance can be further increased by independently forward-bodybiasing transistors M1B and M2B by connecting their shared gate terminals to their shared bulk-terminals [37], as shown in Figure 3c. In its turn, the *k* factor is increased by a *β* factor function of the bulk-to-source voltage *V*BS2, accordingly to (3), and hence the gain of the current mirror, *A*<sup>I</sup> is defined as

$$A\_{\rm I} = \frac{S\_{\rm 1B} \cdot \beta S\_{\rm 2B}}{S\_{\rm 1B} + \beta S\_{\rm 2B}} \cdot \frac{S\_{\rm 1A} + \beta S\_{\rm 2A}}{S\_{\rm 1A} \cdot \beta S\_{\rm 2A}} = \left(\frac{S\_{\rm 1A} + \beta S\_{\rm 2A}}{S\_{\rm 1B} + \beta S\_{\rm 2B}} \cdot \frac{S\_{\rm 2B}}{S\_{\rm 2A}}\right) \cdot \frac{S\_{\rm 1B}}{S\_{\rm 1A}}\tag{6}$$

Again, considering a high value of *β*, the current gain *A*<sup>I</sup> is approximately *S*1B/*S*1A.

For proof of concept, the above current mirrors were designed for the TSMC 180 nm technology and simulated for typical process parameters and room temperature. Table 1 summarizes the transistor arrays dimensions for each circuit.

First, by considering a fixed 1.6 nA input current Iin and an output voltage *V*<sup>o</sup> sweeping from 0 to 600 mV, Figure 4a shows the output current mirrors. According to the transistor arrays dimensions, the conventional rectangular parallel-series current mirror (CM) should attenuate the input current by a 16× factor, and provide a 100 pA current. However, due to non-ideal behavior, it outputs about 125 nA, which is close to 13× attenuation. The selfcascode current mirror (SCCM) behaves similarly to CM, as *S*2B = 16 × *S*1B. The improved self-cascode current mirror (ISCCM) has a slightly smaller attenuation, close to 12×. The

main difference between these current mirrors is the output resistance *R*<sup>o</sup> = 1/(*dI*o/*dV*o), shown in Figure 4b. At the saturation region, the SCCM *R*o is much higher than CM, while the ISCCM is more than one order of magnitude higher.


**Figure 4.** Current mirrors comparison: (**a**) output current × output voltage, and (**b**) output resistance × output voltage for Iin = 1.6 nA.

Nonetheless, the ISCCM is not perfect. Figure 5 shows the current attenuation 1/*A*<sup>I</sup> as a function of the input current Iin. As can be seen, the current attenuation is practically constant for the CM and SCCM, but it varies for the ISCCM, as the *β* is indirectly a function of the input current.

**Figure 5.** Current mirrors attenuation as a function of input current for *V*out = 0.3 V.

The ISCCM differential bulk voltage is defined as Δ*V*<sup>B</sup> = *V*BS2 = *V*in − *V*DS1. As the input current Iin increases exponentially, *V*in increases linearly, as shown in Figure 6a. For 1 nA input, Δ*V*<sup>B</sup> is approximately 100 mV. As *V*BS2 is always positive, the transistors M2A and M2B are forward-body-biased. In spite of that, the drain current ID is orders of magnitude higher than IB (see Figure 6b), so Iin ≈ ID.

**Figure 6.** Improved self-cascode current mirror: (**a**) *V*in and *V*DS1 voltages × input current, and (**b**) drain (ID) and bulk currents (IB) × input current.

#### **3. Bulk-Driven Symmetrical Operational Transconductance Amplifiers**

Bulk-driven OTA topologies as illustrated in Figure 7 take advantage of the transistor bulk terminal of the differential pair to achieve higher transconductance linearity and input range rather than conventional gate-driven topologies [25,28].

**Figure 7.** Symmetrical OTA topologies: (**a**) with parallel-series current mirrors [21], bulk-driven inputs and active source degeneration [1,38], and (**b**) proposed topology with the addition of improved current mirrors.

The intrinsic drawback of this scheme is the reduced transconductance due to its equivalent gate-driven OTA, hence, a lower DC voltage gain. Nonetheless, biomedical applications frequently involve slow varying quantities and the supposed disadvantage, i.e., the very-low transconductance turns beneficial as analog signal filters with very low cutoff frequencies using relatively small-sized integrated capacitors are essential. Moreover, the lower voltage gain can be addressed with techniques such as positive feedback [25], cascode gain stages [44], and transistor arrays [31,45].

Figure 7b shows the proposed topology which relies on the conventional symmetrical OTA shown in Figure 7a with a key aspect. The current mirrors are built by improved selfcascode configuration [36], according to Figure 3c. This scheme allows increasing the OTA DC voltage gain as also the CMRR. Further, in this work, the conventional BD-OTA (see Figure 7b) makes use of the same active source degeneration technique [1,38,46] employed in the input differential pair to keep fair comparisons between the topologies.

To describe the topology behavior, we use the ACM transistor model (more details in [47]), hence the BD-OTA topology can be explained as follows: the transconductance *G*mB is a function of the differential pair transconductance *g*mb1, the source degeneration factor *a* [46], and the current mirror factor *N*, as defined by (7). The differential pair transconductance *g*mb1, defined by (8) and is attenuated relative to the gate-driven OTA by a factor of (*n* − 1).

$$G\_{\rm mB} = \frac{\mathcal{S}\_{\rm mb1}}{aN} \,\prime \tag{7}$$

$$\mathbf{g\_{mb1}} \approx \frac{n-1}{n} \mathbf{g\_{ms1}} \approx \frac{n-1}{n} \frac{2I\_{\mathbf{S}}}{\Phi\_{\mathbf{f}}} \left(\sqrt{1+i\_{\mathbf{f}}}-1\right). \tag{8}$$

Another advantage of the bulk-driven topology over the gate-driven approach is the reduced minimum supply voltage needed for operation,since the differential pair transistors M1A−<sup>B</sup> and source degeneration transistors M2A−<sup>B</sup> gate terminals are connected to the ground instead of to the input signal voltages, which has a typical common-mode voltage of half the supply voltage. It is worth noting that, in order to M1A−<sup>B</sup> operate in the saturation region, *V*GS1 should be greater than the sum of *V*GS4 and *V*DSAT1, which is achieved by assuring that *i*f1 is sufficiently greater than *i*f4 [38,46].

The differential pair is composed of the transistors M1A−B, and the active source degeneration transistors M2A−B. The ratio between the differential pair and the source degeneration transistor aspect ratios *S*1/*S*<sup>2</sup> is 4 for the earlier explained reasons and is achieved by using rectangular transistor arrays with the same area. The ratio between the differential pair and the tail current source transistors aspect ratios *S*1/*S*<sup>3</sup> is sixteen, consequently, since the drain currents are the same, the ratio of their forward inversion level *i*f1/*i*f3 is also 16. The current mirrors use the series-parallel technique [23] to achieve a 16× current attenuation.

As sketched in Figure 7, the conventional BD-OTA, and the proposed one differs because of their body biasing and their current mirror schemes according to Figure 7a,b, respectively. Both the designed conventional and proposed OTAs are composed of the same transistors with the same dimensions. The transistors' sizes of both topologies are summarized in Table 2.


**Table 2.** Transistor sizes (Figure 7).

Figure 8 illustrates the layout of the conventional and the proposed BD-OTA. It is possible to observe a very small difference between both topologies, with the tiny occupied area of only 0.00867 mm<sup>2</sup> and 0.0143 mm2, for conventional BD-OTA and the proposed BD-OTA, respectively.

**Figure 8.** Layout designs of the BD-OTAs. (**a**) Conventional BD-OTA layout. (**b**) Proposed BD-OTA layout.
