**3. Proposed Linearized Transconductor**

The circuit schematic of the proposed transconductor, consisting of a linearization resistor and two voltage followers, is illustrated in Figure 7. The input signals, *v*<sup>+</sup> *IN* and *v*− *IN*, are applied to the bulk terminal of the driver transistors MD1 and MD2, producing a buffered replica of these voltages, *v*<sup>+</sup> *IN*,*<sup>B</sup>* and *v*<sup>−</sup> *IN*,*B*, at their source terminal. The bootstrapping action applied to the bulk-driven transistors leads to a gain close to unity for the voltage followers, as detailed in the previous section. The corresponding DM signal, *v*+ *IN*,*<sup>B</sup>* − *v*<sup>−</sup> *IN*,*B*, is applied to a pseudo-resistor, implemented by transistors MR1 and MR2, where voltage-to-current (*V*-to-*I*) conversion takes place.

**Figure 7.** Proposed linearized transconductor.

Assuming that the parallel connection of transistors MR1 and MR2 leads to a resistor with an approximately constant value *RLIN* for small values of their source-to-drain voltage, the effective transconductance of the *V*-to-*I* converter has been determined by means of a hand analysis, and can be expressed as:

$$G\_{m,eff} = \frac{2}{R\_{LIN}} \cdot \alpha\_{BD} \cdot \frac{1}{1 + \frac{2}{R\_{LIN}} \cdot \frac{1}{\xi\_{mb,MD} + \xi\_{m,MD}} \cdot \frac{\xi\_{o,MD} + \xi\_{o,MS}}{\xi\_{m,MF}}} \approx \frac{2}{R\_{LIN}}\tag{8}$$

where *gmb*,*Mi*, *gm*,*Mi*, and *go*,*Mi* are the bulk transconductance, gate transconductance, and output conductance of transistor M*i*, respectively, and *αBD* is the intrinsic gain of the bulkdriven follower. In the case of a conventional bulk-driven FVF, *αBD* = *gmb*,*MD*/(*gmb*,*MD* + *gm*,*MD*), causing a noticeable signal attenuation that leads to a transconductance degeneration. The signal attenuation can result adequate in a low-voltage environment, as it reduces the signal swing at the intermediate nodes of the transconductor. Nevertheless, this decrease of the effective input transconductance leads to an increase of input-referred magnitudes, such as the noise or the offset voltage. Alternatively, when the proposed bootstrapped bulk-driven FVF is used, it happens that *αBD* ≈ 1 and, hence, there is an enhancement of the transconductance of the cell.

The response of the transconductor is linearized by connecting the bulk terminals of the transistors in the active resistor, MR1 and MR2, to the input terminals of the transconductor, *v*+ *<sup>I</sup>* and *v*<sup>−</sup> *<sup>I</sup>* , whereas the gate terminals are connected to the bootstrapping network in order to also benefit from this effect. This solution, first proposed in [32] and adapted to operate with bulk-driven transistors in [22], is modified here to also take advantage of the bootstrapping effect. Indeed, the common connection of the gate, source, and bulk terminals of transistors MD1-MR1 and MD2-MR2 in the core of the transconductor leads to equal *VSG* and *VSB* voltages for each pair of devices and, hence, to a linearized response that is also insensitive to variations in the input CM voltage [22]. The general expression of the drain current of a MOS transistor operated in the subthreshold region, given by (1), can be approximated by means of the Taylor series when the transistor operates in triode, i.e., when *vDS* is very small. In particular, the Taylor series can be truncated at the linear term, thus obtaining

$$i\_{D,tricode} = \frac{I\_T}{V\_T} \left(\frac{W}{L}\right) \exp\left(\frac{V\_{SG} + V\_{th}}{nV\_T}\right) v\_{SD} \tag{9}$$

Similarly, the expression of the threshold voltage can be linearized as [23]

$$V\_{\rm th} = V\_{\rm th0} - (n - 1)v\_{\rm BS} \tag{10}$$

Considering the expressions in (9) and (10), the output conductance of a MOS transistor biased in the subthreshold region and operated in triode can be written as:

$$\mathbf{g}\_o \equiv \frac{d i\_D}{d v\_{DS}} \approx \frac{I\_T}{V\_T} \left(\frac{W}{L}\right) \exp\left(\frac{V\_{SG} + V\_{th0} - (n-1)v\_{DS}}{n V\_T}\right) \tag{11}$$

As transistors MR1 and MR2 in Figure 7 are connected in parallel, the effective conductance of the composite structure, *gLIN* = *R*−<sup>1</sup> *LIN*, is the sum of the individual conductances of both devices. Assuming that the signal *vBS* applied at the bulk terminals of devices MR1 and MR2 has a CM DC component, *VBS*, and a purely DM signal contribution, *vi* and −*vi*, respectively, the value of the linearization resistor can be approximated as:

$$\begin{split} R\_{LIN} &= \frac{1}{\mathcal{g}\_{LIN}} = \frac{1}{\mathcal{g}\_{o, MR1} + \mathcal{g}\_{o, MR2}} = \\ &= \left[ \frac{I\_T}{V\_T} \left( \frac{W}{L} \right) \exp\left(\frac{V\_{SG} + V\_{th0} - (n-1)V\_{DS}}{nV\_T}\right) \cdot 2 \left(1 + \left(\frac{(n-1)v\_i}{nV\_T}\right)^2 + \left(\frac{(n-1)v\_i}{nV\_T}\right)^4 + \dots \right) \right]^{-1} \end{split} \tag{12}$$

The odd-power terms of the signal cancel out each other, whereas the even-power terms are summed. Taking into account only the linear term of *vi* signal, the expression of the linearization resistor can be further approximated as

$$R\_{LIN} = \left[ 2\frac{I\_T}{V\_T} \left( \frac{W}{L} \right) \exp\left(\frac{V\_{SG} + V\_{lth0} - (n-1)V\_{BS}}{nV\_T} \right) \right]^{-1}.\tag{13}$$

The circuit section used to bias the transconductor is shown in Figure 8. In particular, voltages *VBN* and *VBP* are used to generate the different replicas of the biasing current *IB* required in the *V*-to-*I* converter. Furthermore, voltages *VCN* and *VCP* allow for biasing NMOS and PMOS cascode devices. An ultra-low-voltage environment connecting the gate of NMOS and PMOS cascode transistors to *VDD* and ground, respectively, seems to be a straightforward biasing solution leading to a reduction of the total current consumption. Nevertheless, appropriate bias conditions would be only ensured in typical mean conditions and at the nominal value of the supply voltage and the temperature. The use of the simple and well-known structure in Figure 8 allows for tracking PVT variations and translate them to the bias voltage of the cascode transistors. A similar situation arises in the biasing of the gates of the bulk-driven MOS transistors through the bootstrapping network, the reason why the DC signal *VBIAS* is also generated.

**Figure 8.** Circuit section used to generate biasing voltages and currents.

Conventionally, the transconductance of the *V*-to-*I* converter illustrated in Figure 7 is tuned by modifying the value of the tail current of the FVF cells. As current *IB* changes, the *VSG* of the driver transistors also does, modifying the effective value of *RLIN* and, hence, of *Gm*,*eff* . Here, a different tuning mechanism, based on controlling the gain of the PMOS current mirrors formed by transistors MF1-M1 and MF2-M2, is proposed. The bulk terminal of the input transistors of the current mirror, MF1 and MF2, is connected to a fixed DC voltage *VBULK*, whereas a variable voltage *VTUN* is applied to the bulk terminal of the output transistors, M1 and M2. When *VTUN* > *VBULK*, the effective threshold voltage of the output transistors is higher and the current flowing though the output branch is lower, thus having a current attenuation. Conversely, for *VTUN* < *VBULK*, the effective value of *Vth* of the output transistors of the current mirror becomes lower than that of the input transistors, obtaining a higher output current and, hence, a signal amplification. The voltage *VTUN* finds its upper bound in the supply voltage *VDD* and, theoretically, can be decreased until the ground level is reached. Nevertheless, considering that the source and the bulk of these transistors form a *pn* junction, deep forward biasing of this parasitic diode must be avoided. To this end, the exponential behavior of the current flowing through the bulk terminal of a PMOS transistor when the bulk voltage is changed has been considered in order to determine a practical lower bound for the tuning range of voltage *VTUN*. In particular, in Figure 9, the bulk current of transistors M1 and M2 in Figure 7, *IBULK*, is represented as a function of the tuning variable *VTUN*. A current level equal to 1% of the biasing current, i.e., 0.01*IB*, has been selected as a reasonable limit in order to avoid deep forward operation

of the source-bulk *pn* junction of transistors M1 and M2. As a result, a value of 200 mV for *VTUN* is selected as the lower bound of the tuning variable.

**Figure 9.** Bulk current over the tuning variable *VTUN*.
