*3.3. Extraction Results*

The *gm*/*ID* and CSIG methods presented herein were used to extract the four parameters of each transistor used throughout this work. The four parameters were also extracted for various temperatures and corners of process variation.

Figure 7 shows the dependence of the parameters of the 4PM on the temperature of an NMOS transistor with *<sup>W</sup> <sup>L</sup>* <sup>=</sup> <sup>1</sup> <sup>μ</sup><sup>m</sup> 0.3 <sup>μ</sup><sup>m</sup> . As expected, the threshold voltage is a linearly decreasing function of the temperature [18], whereas the DIBL factor increases linearly with temperature [19,20]. The slope factor is, for practical purposes, independent of the temperature. The dependence of the specific current on the temperature is, in general, not predictable due to uncertainty in the variation of the mobility with the temperature.

**Figure 7.** Parameters of the 4PM vs. temperature of a medium (nominal) *VT* NMOS transistor with *W*/*L* = 1 μm/0.3 μm.

Tables 1 and 2 summarize the extracted values for NMOS and PMOS long-channel (*W <sup>L</sup>* <sup>=</sup> <sup>1</sup> <sup>μ</sup><sup>m</sup> <sup>1</sup> <sup>μ</sup><sup>m</sup> ) and short-channel (*<sup>W</sup> <sup>L</sup>* <sup>=</sup> <sup>1</sup> <sup>μ</sup><sup>m</sup> 0.3 <sup>μ</sup><sup>m</sup> ) transistors, respectively, from a 0.18 μm technology. The four parameters were extracted at room temperature for extreme corners (slow and fast) and for the typical (nominal) condition.

**Table 1.** Extracted parameters for medium-*VT* NMOS/PMOS transistors with *<sup>W</sup> <sup>L</sup>* <sup>=</sup> <sup>1</sup> <sup>μ</sup><sup>m</sup> <sup>1</sup> <sup>μ</sup><sup>m</sup> .



**Table 2.** Extracted parameters for medium-*VT* NMOS/PMOS transistors with *<sup>W</sup> <sup>L</sup>* <sup>=</sup> <sup>1</sup> <sup>μ</sup><sup>m</sup> 0.3 <sup>μ</sup><sup>m</sup> .

As expected, the parameters that varied the most were threshold voltage and specific current. The threshold voltage varied 8.6% in relation to the nominal value of the NMOS transistors and 13.3% in relation to the PMOS transistors. The specific current varied around 13% in relation to the nominal value in long-channel transistors and up to 29.3% in short-channel transistors. The effects of these variations in a circuit are presented in Section 5.

#### **4. Including the 4PM in Cadence**

To simulate MOS circuits through the 4PM in a commercial simulator, the model was carried out in Verilog-A, an HDL that describes the electrical behavior of analog devices, circuits and systems. The Verilog-A compiler handles every required interaction between the model and the simulation software. Furthermore, Verilog-A supports various functions to assist in descriptions, such as standard mathematical functions, transcendental and hyperbolic functions as well as a set of statistical functions [14].

The inversion levels in the UICM (7) simplify the design of various MOS circuits; however, for a simulator, the voltages at the device's terminals are the inputs, while the current flowing through the device is the output.

When solving (7) for the drain current, a transcendental equation arises, which can be solved numerically. Nonetheless, the simulator solves the equations point by point; thus, iterative calculations to find the solution of one single point waste time and processing power.

Siebel [21] explored some algorithms to improve the implementation of (7) in simulators, reaching the conclusion that algorithm 443 [22] finds an accurate solution for the drain current in only one iteration.

Algorithm 443 solves transcendental equations of the form *x* = *wew*. To resemble such a form, the UCCM in (3) can easily be rewritten as (24).

$$\mathfrak{e}\left(\frac{{}^{V\_P - V\_{S(D)B}} + 1}{}\right) = q\_{IS(D)} \mathfrak{e}^{q\_{IS(D)}} \tag{24}$$

Owing to the similarity of (24) to *x* = *wew*, algorithm 443 is employed to determine the drain current by following a few steps: first, the normalized forward and reverse charge densities *qIS*(*D*) are determined; then, by applying their values in (6), we obtain the respective inversion levels *if*(*r*), which, at last, are applied in (1), resulting in the drain current *ID*. A sample of the Verilog-A description is presented in Appendix A to clarify how algorithm 443 was implemented to solve (24).

For the dynamic model, expressions (13)–(19) were implemented in Verilog-A just after the drain current was calculated. The overlap capacitances were also included as extrinsic capacitances. The transconductances were used as design parameters that could easily be derived from the current–voltage relation, namely UICM.

## *Model Results*

For the sake of comparisons with BSIM 4.5 results, the four-parameter model described in Verilog-A was simulated employing single transistors in typical conditions at room temperature. Figures 8 and 9 present the *ID* × *VGS*@*VDS* = 200 mV and *ID* × *VDS*@*VGS* = 200 mV, respectively, for long-channel (*<sup>W</sup> <sup>L</sup>* <sup>=</sup> <sup>1</sup> <sup>μ</sup><sup>m</sup> <sup>1</sup> <sup>μ</sup><sup>m</sup> ) and short-channel (*<sup>W</sup> <sup>L</sup>* <sup>=</sup> <sup>1</sup> <sup>μ</sup><sup>m</sup> 0.3 <sup>μ</sup><sup>m</sup> ) transistors. Note that in both figures, ACM refers to the 4PM.

**Figure 8.** *ID* × *VGS* @ *VDS* = 200 mV for (**a**) medium (nominal) *VT* long-channel NMOS and (**b**) PMOS transistors and for (**c**) medium (nominal) *VT* short-channel NMOS and (**d**) PMOS transistors.

**Figure 9.** *ID* × *VDS* @ *VGS* = 200 mV for (**a**) medium (nominal) *VT* long-channel NMOS and (**b**) PMOS transistors and for (**c**) medium (nominal) *VT* short-channel NMOS and (**d**) PMOS transistors.

Simulations carried out for *VDS* and *VGS* with 100 mV, 500 mV and 1 V led to current– voltage characteristics similar to those in Figures 8 and 9; therefore, they were not included herein.

Overall, the Verilog-A simulation for long- and short-channel transistors provided results close to BSIM's. Notably, for high values of *VDS*, the drain current of the 4PM drifts away from BSIM's due to effects that are not taken into account in the ACM model used herein.

#### **5. Circuit Examples and Simulation Results**

Four circuits were simulated through either the 4PM in Verilog-A descriptions or BSIM 4.5 [23]: the classic CMOS inverter, an 11-stage ring oscillator, a self-biased current source (SBCS) and a common-source amplifier.
