*2.5. Proposed Hybrid ADC: Digital–Delta (*Δ*) Modulator (*Δ*M) with Noise Shaping (NS)*

A digital-ΔM employing NS was initially proposed by the authors of this paper in [18]. It utilizes oversampling and NS to improve the overall performance by minimizing the impact of thermal and quantization noise. As depicted in Figure 5, it comprises a 1-bit comparator, an accumulator, an *N*-bit DAC, an S/H circuit, and an integrator in the NS section.

**Figure 5.** Diagram of the proposed digital-ΔM ADC employing NS.

This architecture was initially inspired by an SAR-ADC. However, instead of the typical SAR logic, this topology uses an accumulator in the digital domain. Therefore, the search algorithm is based on the prediction of the next *Vin* working as a ΔM.

Comparing the block diagram of the proposed ADC architecture, depicted in Figure 6a, with other topologies shows that the comparator also connects to the sampled *Vin* to perform a direct comparison with the estimation. Additionally, this architecture employs an accumulator placed between the comparator and the DAC, which is a relevant advantage to achieve a fully synthesizable ADC. However, since this topology utilizes delta modulation, *Smax* is dependent on the frequency (Figure 6b).

**Figure 6.** Proposed digital-ΔM employing NS: (**a**) block diagram and (**b**) illustrative magnitude of STF, NTF and *Smax*.

## *2.6. Comparison among the Most-Suited Architectures*

All the described architectures are qualitatively compared in Table 1.

In all the described topologies, the most critical building blocks are the comparator, integrator, and the DAC, since their nonidealities impact ADC performance. However, depending on the ADC architecture and the circuit location, their effect can be distinct.

Generally, SAR-ADC and digital-ΔM, both employing NS, present higher complexity when compared with ΔΣM or ΔΔΣM ADCs because the specifications of the main building blocks (metastability, comparator's accuracy and comparison times, noise, etc.) have strong repercussions on ADC performance. However, they present very good energy efficiency, increasing their attractiveness. ΔΣM or ΔΔΣM ADCs are also popular for high-resolution applications. However, the integrator design can, in some cases, be problematic for circuit stability and efficiency.

The magnitude of *Smax* can show different behaviors depending on the architecture; therefore, despite the conclusions depicted in Table 1, this aspect should be taken into account to ensure that it does not represent a strong limitation for the specific IoT application.


**Table 1.** Comparison of the most-suited ADC architectures for IoT applications.

#### **3. Standard-Cell-Based Active Building Blocks**

The implementation of the different architectures presented earlier demands different specific circuits to implement the distinct functional blocks that each topology requires. Typically, integrator synthesis encompasses the design of OTAs, and quantizers involve comparator design. Among others, these are fundamental building blocks of converters.

Over the years, different standard-cell-based circuits, recurring to automated digital design flows and standard cells, have been proposed to implement these well-known analog functions, enabling faster design, and synthesis and layout automation based on standard cells.

Despite the importance of the DAC in all architectures, its design has preferably been passive, facilitating the converter porting between different nodes or technologies. Furthermore, the passive characteristics allow for good energy efficiency, which is extremely relevant for IoT applications. For these reasons, this building block is not described here.
