*2.4. Delta–Delta–Sigma (*ΔΔΣ*) Modulator (*ΔΔΣ*M) ADC*

ΔΔΣM is another example of a hybrid architecture. Combining delta modulation with a 1st-order ΔΣM, ΔΔΣM was proposed in [5]. As depicted in Figure 4a, two integrators are used in this topology, one in the feedforward and another in the feedback paths.

**Figure 4.** ΔΔΣM ADC [5]: (**a**) block diagram and (**b**) illustrative magnitude of STF, NTF and *Smax*.

Since two integrators are involved, the complexity of the architecture is higher. Furthermore, the nonidealities of the DAC (placed in the feedback path) impact the ADC linearity. Thus, a high dynamic resolution is difficult to achieve, especially with low energy efficiency. Despite the inherent complexity, small modifications can be performed to the architecture, such as changing the relative position of the DAC and integrator in the feedback path. The integrator becomes a digital accumulator, reducing the complexity and rendering the architecture more suitable for IoT.

As represented in Figure 4b, while the NS imposes an inclination to the NTF curve, shaping the noise for higher frequencies, delta modulation impacts the *Smax* (similarly to the ΔM topology).
