*5.3. Self-Biased Current Source (SBCS)*

The design of the self-biased current source (SBCS) in Figure 16, for the output current *IOUT* = 100 nA and supply voltage *VDD* = 1.8 V, was based on the ACM model [25–27].

**Figure 16.** Self-biased current source (SBCS) circuit.

The core of the SBCS in Figure 16 is the self-cascode MOSFET (SCM), composed of transistors *M*<sup>1</sup> and *M*2, which operate in a moderate inversion. Transistors *M*<sup>3</sup> and *M*<sup>4</sup> form the second SCM biased in a weak inversion to generate the proportional to absolute temperature (PTAT) voltage *VY* [26,27].

Transistors *M*2(4) are in a saturation, while *M*1(3) is in a triode; therefore, *ID*<sup>2</sup> ∼= *IS*2*if* <sup>2</sup> and *ID*<sup>1</sup> = *IS*1(*if* <sup>1</sup> − *ir*1) = *Iref*(*N* + 1). Since *VP*<sup>1</sup> = *VP*<sup>2</sup> = *VP* and *VD*<sup>1</sup> = *VS*2, we have *ir*<sup>1</sup> = *if* 2.

The specific current *IS* can also be written as *IS* = *ISHS*, where *ISH* is the sheet normalization current and *S* is the aspect ratio *<sup>W</sup> <sup>L</sup>* , which, combined with (1), yields the relationship (25).

$$\alpha\_{12(34)} = \frac{i\_{f1(3)}}{i\_{f2(4)}} = 1 + \frac{S\_2(4)}{S\_1(3)}(1 + \frac{1}{N}) \tag{25}$$

The SCM intermediate voltage *VX*(*Y*) relates to the inversion level through the design Equations (26) and (27), which can be directly derived from the ACM using (7) and (25).

$$\frac{V\_X}{\Phi\_l} = \sqrt{1 + \mathfrak{a}\_{12}i\_{f2}} - \sqrt{1 + i\_{f2}} + \ln\left(\frac{\sqrt{1 + \mathfrak{a}\_{12}i\_{f2}} - 1}{\sqrt{1 + i\_{f2}} - 1}\right) \tag{26}$$

$$\frac{V\_Y}{\phi\_t} = \ln \alpha\_{34} \tag{27}$$

To simplify the design, we chose *if* <sup>2</sup> = 15 and *S*<sup>1</sup> = *S*2, which results in *α*<sup>12</sup> = 3. From this starting point, it is sufficient to extract the sheet normalization current of *M*2, as shown in Section 3.1, and to use (1) to determine the aspect ratio. Once *VX* is determined, *α* and the inversion levels of the other transistors can be calculated, along with their aspect ratios.

Table 6 summarizes the sizes, series/parallel associations and inversion levels of the transistors. Table 7 presents the four parameters extracted for the three transistors used in the SBCS.


**Table 6.** Sizes and and inversion levels of the transistors of the SBCS.



The DC simulation results in Figure 17 were obtained through the use of either BSIM or the 4PM for a voltage sweep on *VDD* from 0 to 1.8 V. Both models yielded similar results for *IOUT*, *VX* and *VY*. The SBCS started up for supply voltages above 650 mV. The average values of *VX* and *VY* for a *VDD* higher than 650 mV were approximately 86 mV and 81 mV, respectively, which were very close to the calculated value of 88 mV. The design of the SBCS can be improved and optimized; however, the main goal herein was to compare the results of the 4PM with those of BSIM.

**Figure 17.** Results of DC analysis for voltage sweep on *VDD*: (**a**) output current, (**b**) *VX* and (**c**) *VY*.

### *5.4. Common-Source Amplifier*

The common-source amplifier in Figure 18 was designed to demonstrate the suitability of the 4PM in the frequency domain in comparison to BSIM. The amplifier was designed for a maximum gain at a frequency of 2 MHz, a bias current of 200 nA and a supply voltage of 1.8 V.

**Figure 18.** Common-source amplifier.

Table 8 presents the transistors' dimensions and extracted parameters employed in the design. The resistor *R* of 500 kΩ isolates the node *VG* from the bias circuit, while the capacitor *C* of 150 fF blocks the DC level from the input signal at *VG*.

**Table 8.** Transistor dimensions for the common-source amplifier and extracted parameters.


An AC simulation from 1 kHz to 10 GHz was run for a capacitive load of 10 fF. The results using BSIM and 4PM are depicted in Figure 19, where it is evident that the 4PM managed to follow the BSIM curves in the AC simulation.

**Figure 19.** Frequency response of the common-source amplifier using BSIM and 4PM: (**a**) open-loop gain in dB and (**b**) phase.

The center frequency for the 4PM was around 2.14 MHz with a peak gain of 26 dB, while BSIM presented a maximum gain of 25.3 dB at 1.9 MHz. The phase curves presented in Figure 19 show that the 4PM managed to follow BSIM very closely. Two poles were found at 700 kHz and 4.7 MHz for BSIM and at 850 kHz and 5.5 MHz for the 4PM. These differences were expected since the 4PM in Verilog-A does not consider the complete dynamic transistor model.

### **6. Conclusions**

The simulation results of MOS circuits depend on the accuracy of both the MOS model and the extracted transistors' parameters.

The authors of [28] employed an ACM expression of charge density to calculate currents but did not extract the required parameters that should be available in the simulator. Nonetheless, despite using VHDL (the hardware description language VHSIC) to facilitate the widespread use of the model in other simulators, the charge density equations are not familiar to most designers; thus, a gap between hand-design and simulation remains.

This paper introduced a truly compact MOS model composed of only four parameters enough to describe the DC and small-signal low-frequency characteristics of MOSFET. The 4PM in Verilog-A was used to calculate the current from the UICM, which contains parameters familiar to IC designers. This is significant because a first-order understanding of the MOSFET model along with its associated parameters is indispensable for IC designers since the MOSFET parameters of simulators are numerous and most of them are quite hard to understand.

Besides presenting the 4PM, this paper also introduced the extraction methods employed to obtain accurate parameters, reflected in the consistent results obtained through the simulations of different circuits presented in Section 5.

The four-parameter model is a minimalist model that helps electronic engineers to design MOS circuits and to rapidly find approximate solutions to the circuits' electrical behavior in a way that the troubleshooting can easily be done by directly relating the design parameters to the obtained results before fine tuning through more complex and time-consuming simulations.

The 4PM is particularly useful for the design by hand of low-voltage circuits because fewer parameters are required for accurate results while still maintaining a foundation in physics. Therefore, all things considered, the 4PM helps to bridge the gap between the hand design and simulation of MOS circuits.

**Author Contributions:** Conceptualization, C.G.-M. and M.C.S.; methodology, C.G.-M., M.C.S., C.M.A. and D.G.A.N.; software, C.M.A. and D.G.A.N.; validation, C.M.A. and D.G.A.N.; writing original draft preparation, C.M.A. and D.G.A.N.; writing—review and editing, C.G.-M. and M.C.S.; visualization, C.M.A. and D.G.A.N.; supervision, C.G.-M.; funding acquisition, C.G.-M. and M.C.S. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by the Brazilian agencies CAPES (finance codes 001 and print #698503P) and CNPq.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** The data are contained within the article.

**Acknowledgments:** The authors would like to thank the Brazilian agencies CAPES and CNPq for supporting this work.

**Conflicts of Interest:** The authors declare no conflict of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretations of data; in the writing of the manuscript, or in the decision to publish the results.
