*3.4. Leakage Current in Switches and Delay Compensation*

The four switches controlling the charging and discharging actions, as depicted in Figure 5, are arranged in the inverted style, as shown in Figure 10.

**Figure 10.** Four transistor switches for charging and discharging the matched capacitor pair.

Since *IREF* is quite small, the leakage currents in the advanced technology node, flowing through the switch transistors, can be significant when charging *C*<sup>1</sup> and *C*2. With the increase in temperature, the delay caused by the transistor switches is increased from 1.9 ns to 9.8 ns, as shown in Figure 11, and this effect is particularly pronounced. Therefore, this will cause the reduction in the output frequency. Thus, according to the reverse shortchannel effect, high threshold-voltage transistors with the smallest channel length can be used as switches. This is also in conjunction with introducing the body effect in pmos to maximize the threshold voltage. Finally, the leakage current effect can be reduced by introducing the CTAT delay, as discussed in Section 3.3, such that the output frequency can be kept constant. The size of each transistor and capacitor shown in Figure 10 are given in Table 3.

**Figure 11.** Temperature characteristics of the delay in transistor switches.

**Table 3.** Size of components in Figure 10.


#### **4. Results and Discussions**

The proposed ROSC, with leakage current compensation, is simulated using TSMC-40 nm CMOS process technology. The output frequency is 64.59 kHz at *VDD* = 1.1 V under room temperature, and the transient simulation result of the output signal is depicted in Figure 12. All analog-biased transistors in the proposed ROSC work in the subthreshold region, the bias current of the comparators can be made small for low frequency design, and the current derives from the dedicated *IREF* instead of from the addition of an extra current source. This permits the current consumption of 552 nA at room temperature in a typical corner. However, there is always a performance tradeoff between *IREF* and low current consumption.

Figures 13 and 14 illustrate the respective simulation results of the output frequency against the temperature variation from −20 ◦C to 80 ◦C at different supply voltages and process corners. The T.C. of the output frequency of the proposed ROSC is obtained as 12.4 ppm/◦C, 13.3 ppm/◦C, and 21.8 ppm/◦C at the TT corner, SS corner, and FF corner, respectively, at a 1.1 V supply. Regarding the 1 V supply, the obtained T.C. is 14.3 ppm/◦C, 26.7 ppm/◦C, and 22.2 ppm/◦C, respectively. Of particular note, the T.C. is observed with some degradation at the 1 V supply with respect to that of the 1.1 V supply at the SS corner. This is mainly because the transistors in the reference generator are stressed under limited *VDS*. Therefore, the proposed ROSC can still work properly when the supply is slightly lower than 1.1 V. Considering the operation margin, 1.1 V is regarded as the minimum

supply voltage for the oscillator. Regarding the low T.C. values achieved by the ROSC with respect to those of prior-art works, the T.C. improvement is attributed to the compensation for the delay drift resulting from temperature, as seen in Figures 8 and 11. By calculation, without the delay compensation, this T.C. will increase to about 19.1 ppm/◦C.

**Figure 12.** Output signal in time domain.

**Figure 13.** Temperature characteristic of output frequency at different process corners under the 1.1 V supply: (**a**) @TT corner; (**b**) @SS corner; (**c**) @FF corner.

**Figure 14.** Temperature characteristic of output frequency at different process corners under the 1 V supply: (**a**) @TT corner; (**b**) @SS corner; (**c**) @FF corner.

Considering the parasitic effect arising from the layout issues, some model capacitors ranging from a few tens to one hundred fF are intentionally added to the critical points in each comparator, reference generator, and SR latch. The comparator displays relatively higher sensitivity due to the low bias current, while there is no significant effect from other nodes. Figure 15 shows the simulated temperature characteristic of output frequency with intentionally added parasitic capacitors in the design under the TT corner. Of particular note, the estimated capacitance from the routing for each comparator is around 18fF. Therefore, the total capacitance of several model capacitors being added in each comparator is modeled as 20 fF. The output frequency changes from 64.59 kHz to 64.04 kHz, and the T.C. is degraded from 12.4 ppm/◦C to 13.7 ppm/◦C. This confirms that the potential parasitic effect arising from the layout made no significant impact on the current simulation results, without incorporating layout due to the low-frequency design. Additionally, the silicon area of this design is approximated as about 4x the total active area of the components. This yields about 0.0234 mm2, or 153 <sup>μ</sup><sup>m</sup> × <sup>153</sup> <sup>μ</sup>m.

**Figure 15.** Temperature characteristic of output frequency with simulated parasitic capacitors at the TT corner.

The T.C. results of Monte Carlo simulation used to verify the impact of mismatch and process variations are shown in Figure 16. There are 200 samples simulated, and each sample is simulated with 11 temperature points, from −20 ◦C to 80 ◦C, resulting in 2200 points in total. The T.C. varies from 9.35 ppm/◦C to 77.13 ppm/◦C, with an average value of 25 ppm/◦C and a standard deviation of 11.1 ppm/◦C, where 75% of the samples present a T.C. smaller than 30 ppm/◦C. This confirms that the output frequency of the proposed ROSC exhibits good stability under temperature change.

**Figure 16.** Monte Carlo simulation of output frequency T.C.

The supply dependence of the output frequency is depicted in Figure 17. The line sensitivity of the output frequency achieves 0.045%/V, 0.059%/V, and 0.081%/V at the TT corner, SS corner, and FF corner, respectively, from a 1.1 V to 1.6 V supply, which is

attributed to *VREF* with good PSR at low frequency and the cascode transistors shielding the variation of supply in the comparators to stabilize the response time.

**Figure 17.** Supply dependence of output frequency at different process corners: (**a**) @TT corner; (**b**) @SS corner; (**c**) @FF corner.

The Monte Carlo simulation of the output frequency, with process variation and mismatch at different temperatures, is shown in Figure 18. The average values of the output frequency under different temperatures remain almost the same: 64.84 kHz, 64.95 kHz, and 64.9 kHz, with the standard deviation of 6.42 kHz, 6.42 kHz, and 6.41 kHz at −20 ◦C, 30 ◦C, and 80 ◦C, respectively. This yields the average process sensitivity (σ/μ) of 9.88%. The output frequency is eventually dependent on the value of the composite resistor *Rs* in Figure 6 and the capacitors *C*<sup>1</sup> and *C*<sup>2</sup> in Figure 10. The process variation displays the moderate value, which is targeted for moderate precision applications. However, to cater to a precision design, this can be achieved by trimming the passive MoM capacitors *C*<sup>1</sup> and *C*2, which are less affected by temperature.

The performance of the proposed ROSC is compared to that of the previously reported representative works using advanced process technology nodes, as shown in Table 4, and with longer channel length technology nodes, as shown in Table 5. It can be seen that the proposed relaxation oscillator, with the dynamic current consumption of 552 nA at a 1.1 V supply voltage, exhibits the best T.C. for one sample. The same goes for the Monte Carlo 200-sample result, with process variation and mismatch. Regarding line sensitivity, the proposed work a displays lower value due to the use of the cascode current mirror plus the two-transistor-based voltage reference topology, which has the feature of small line sensitivity.

**Figure 18.** Monte Carlo simulation of output frequency: (**a**) @−20 ◦C; (**b**) @30 ◦C; (**c**) @80 ◦C.

**Table 4.** Performance comparison with previously reported ROSC works in advanced technology nodes.


The process sensitivity of the output frequency is comparable and can be improved by trimming the two capacitors. To evaluate the stability of the output frequency, with both temperature and supply variations, a figure-of-merit (FoM), including the temperature coefficient and the line sensitivity [9], is defined as

$$FoM = T.\text{C.} \times 100 \, ^\circ \text{C} + Line.\text{Sens.} \times 10\% \, V\_{DD\,\text{min}}\tag{17}$$

where T.C. is the one sample value at the typical corner. The FoM of the proposed ROSC is 0.129%, which displays the best result when compared to the prior-art works shown in Table 4. Therefore, the proposed design can offer a stable frequency while providing a good tradeoff between stability and power consumption. Finally, in view of the larger leakage current, as well as the lower transistor intrinsic gain in this 40 nm technology with respect to those of technology nodes having a longer channel length, the frequency stability of the proposed work, as shown in Table 5, also shows excellent FoM. This demonstrates the usefulness of the circuit.

**Table 5.** Performance comparison with previously reported ROSC works employing technology nodes with longer channel length.

