*3.2. Open Loop Simulations*

The amplifier has been simulated assuming a 0.55-V nominal supply voltage and a 250-pF load capacitance. The results of the open loop AC simulations of the proposed OTA are reported in Figure 5, showing that the digital OTA exhibits an overall DC gain and GBW of about 87 dB and 3.15 MHz, respectively. The phase margin of the amplifier results is higher than 65◦ with all the standard cells sized for minimum area. Figure 6 reports the input-referred noise plot of the proposed digital OTA showing an input-referred Flicker noise of about 4.82 <sup>μ</sup>V/√Hz @ 100 Hz and an input-referred white noise of about 175 nV/√Hz @ 100 kHz.

**Figure 5.** Frequency response of the SC-DIGOTA for CL = 250 pF, magnitude (**a**), phase (**b**).

**Figure 6.** Equivalent input noise of the SC-DIGOTA.
