*2.1. Block Diagram*

Different approaches to implement a differential IA have been previously reported [9,17–20,23–25,29]. Among them, there are solutions based on the ICF technique, as the pseudo-differential (PD) IA proposed in [29], the block diagram of which is illustrated in Figure 2a. The sections *GmI* and *GmO* are an input and an output (or feedback) transconductor, used, respectively, to process the input signal and establish the current feedback. When the input signal, *vI*,*DM*, is applied to the transconductor *GmI*, a current *iI* is generated. Similarly, an output current *iO* is produced when the voltage *vSENSE* − *VREF* is applied to the input terminals of the voltage-to-current (*V*-to-*I*) converter *GmO*. The voltage *vSENSE* is used as feedback signal and *VREF* is a reference voltage used to set the DC component of *vO* to the intended level. In the particular case of Figure 2a, a single-stage structure is represented, in which an unitary feedback loop is established. Indeed, the output voltages, *v*<sup>+</sup> *<sup>O</sup>* and *v*<sup>−</sup> *<sup>O</sup>*, are shorted to the feedback terminals, *<sup>v</sup>*<sup>+</sup> *SENSE* and *v*<sup>−</sup> *SENSE*, whereas two copies of the block *GmO* are required to stablish the differential feedback loop. The feedback action around each output transconductor controls individually the DC level at the two output terminals and; hence, no CMFB is needed.

**Figure 2.** Block diagram of (**a**) a pseudo-differential and (**b**) a fully-differential ICF IA.

The block diagram of the proposed FD IA is depicted in Figure 2b. As observed, the feedback network is implemented differentially and, hence, only one output transconductor is required. Nevertheless, it is well known that the establishment of a differential feedback loop relies on the assistance of a CM control network, in order to dynamically set the CM component of the output voltage to the intended level. With this purpose, the CMFB section illustrated in Figure 2b has been included. As observed, the DC component of the output voltage is induced to be equal to *VREF* by the CMFB circuit, rather than being applied to the output transconductor, as it is done in the PD structure in Figure 2a. The existence of well-differenced signal paths for the DM and CM components in the FD approach allows the individual optimization of their response, which is not possible in the PD solution, where the control of the output CM voltage is embedded in the implementation of the output section of the circuit.

A hand analysis of the block diagram in Figure 2b led to the following transfer function for the system:

$$H(\mathbf{s}) \equiv \frac{v\_0(\mathbf{s})}{v\_i(\mathbf{s})} = \frac{G\_{mI} \cdot \begin{pmatrix} R\_{out} \ \parallel \ \frac{1}{s \gets L} \end{pmatrix}}{1 + G\_{mO} \begin{pmatrix} R\_{out} \ \parallel \ \frac{1}{s \gets L} \end{pmatrix}} \tag{1}$$

where *Rout* and *CL* are the output resistance and the load capacitance, respectively, of the summing stage. Assuming a high gain for the loop around the transconductor *GmO*, the voltage gain, *Av*, and the BW of the IA are inferred from (1) and can be expressed as:

$$A\_v \equiv \frac{v\_o}{v\_{i,dm}} = \frac{G\_{mI}}{G\_{mO}} \tag{2}$$

$$BW = \frac{G\_{mO}}{\mathbb{C}\_L} \tag{3}$$

The voltage gain of the IA is adjusted by means of the ratio of *GmI* and *GmO*. In addition, a proper value of *CL* has to be selected in order to ensure an optimal phase margin and, hence, appropriate frequency and time responses.

## *2.2. Transistor Level Implementation*

The transistor level implementation of the proposed FD IA is illustrated in Figure 3, where the different circuit sections are labelled at the bottom. The *V*-to-*I* conversion at the input (output) transconductor is carried out by a resistor and two voltage followers. The input (output) voltage is applied to resistor *RI* (*RO*) through two super-source-follower (SSF) sections, which act as voltage buffers. The SSF block incorporates an implicit feedback loop, implemented by transistors MDI and MFI (MDO and MFO), that reduces the effective output resistance of the block and makes its voltage gain very close to unity, regardless of the value of the linearization resistor. As a result, the value of *RI* (*RO*) can be greatly reduced without hardly affecting the operation of the SSF sections, which allows a reduction in the noise contribution of the resistor to be made, as well as the silicon area occupied by this passive component. The SSF structures are biased by means of devices MSUI and MSDI (MSUO and MSDO), which are single-transistor current sources providing tail currents 2*IB* and *IB*, respectively. The gate terminals of these transistors are connected to the corresponding bias voltage, *VBN* or *VBP*, in the biasing network represented at the left of Figure 3. Capacitors *CC*<sup>1</sup> to *CC*<sup>4</sup> are used to optimize the phase margin of the feedback loop inherent in each SSF cell. The effective transconductance of the input and output *V*-to-*I* cells is equal to:

$$G\_{m,eff} \equiv \frac{i}{v\_{DM}} = \frac{2}{R} \frac{1}{\left[1 + \left(1 + \frac{2}{R} \frac{1}{\mathcal{S}\_{m,MD}}\right) \left(\frac{\mathcal{S}\_{\sigma,MD} + \mathcal{S}\_{\sigma,MD}}{\mathcal{S}\_{m\mathcal{F}}}\right)\right]} \approx \frac{2}{R} \tag{4}$$

where *gm*,*Mi* and *go*,*Mi* are the transconductance and output conductance, respectively, of transistor *Mi*, at the input and the output transconductor, *R* is the linearization, or source degeneration, resistor (*RI* or *RO*), and *gm go* has been assumed. The factor of 2 in (4) indicates that the current signal generated in the input and the output transconductor, *iI* and *iO*, respectively, is conveyed to the output terminals of the IA by the two branches of the circuit section. In addition, the second term in (4), multiplying the main contribution 2/*R*, represents the load regulation effect of resistor *R* on the voltage buffers. In first order of approximation, the effective transconductance of each *V*-to-*I* converter is approximately equal to two times the inverse of the linearization resistor.

**Figure 3.** Transistor level implementation of the proposed fully-differential IA.

The current signals generated at *GmI* and *GmO* are mirrored to the output nodes of the IA by using current mirrors with gains *1* : *1*. Cascode transistors are used in the output branches in order to increase the output resistance and, hence, the open-loop voltage gain. In addition, cascode devices MFCI and MFCO are used in *GmI* and *GmO*, respectively, to ideally cancel out the systematic offset in the current reflections. Additional design flexibility to adjust the voltage gain and bandwidth of the IA to the intended values can be obtained by sizing the current mirrors with a gain different from unity [29]. The voltage gain and the BW of the proposed IA can be specified by considering the general expressions (2) and (3), along with the equation of the effective transconductance in (4), and can be rewritten as:

$$A\_{\upsilon} \approx \frac{R\_O}{R\_I} \tag{5}$$

$$BW \approx \frac{2}{\mathbb{C}\_L R\_O} \tag{6}$$

The input CM voltage of the FD IA in Figure 3 can be adjusted over a reasonably wide range. Indeed, the operation for input signals around the midsupply is ensured by adequately setting the aspect ratio of the input devices, so that the upper current source transistors, MSUI, can operate in saturation. Thus, the maximum level of the input CM voltage that can be achieved close to *VDD* is constrained by the operation in saturation of transistors MSUI. Furthermore, the operation for *vI*,*CM* around ground can be easily achieved by proper sizing of transistors MFI. Indeed, the voltage at the drain of transistors MDI, which could force their operation in the triode region, can be reduced to an appropriate level by increasing the aspect ratio of transistors MFI, thus ensuring the operation of the input drivers in saturation.

The structure of the CMFB network used to control the DC level of the output voltage is depicted in Figure 4. A current-mode approach, based on generating a CM current signal that is a function of the output CM voltage, has been followed. The output voltages of the FD IA are used as input signals in the CMFB section and are applied to the inputs of two cross-coupled differential pairs. The other two input terminals of the CMFB are connected to the reference voltage *VREF*. Assuming the voltage difference *v*<sup>+</sup> *<sup>O</sup>* − *v*<sup>−</sup> *<sup>O</sup>* small and, hence, the differential pairs operating within their linear region, a current signal *icm*, proportional to the output CM voltage, is generated. This current, superimposed to a DC level nominally equal to 2*IB*, is mirrored by a NMOS and a PMOS current mirror and injected into the FD IA through the terminal *vCMFB*. The CM loop is closed through the output branches of the IA, which are connected to the input of the CMFB network. The action of the feedback loop forces the CM component of the output voltage to be equal to *VREF*, setting the DC level of the output voltage to this value. The dominant pole of the feedback loop established for the CM signal is the same to that of the DM loop and is determined by the load capacitor. The secondary poles in both cases, DM and CM signals, are associated to low impedance nodes, that is, the corresponding time constants are the product of a low resistance, in general the inverse of a transconductance, and a parasitic capacitance. As a consequence, the frequency compensation of the DM and CM loops in the FD IA can be easily achieved by properly setting the value of the load capacitor. Indeed, the value of *CL* must be adjusted to have a phase margin higher than 60º in both the CM and the DM feedback loop.

**Figure 4.** Transistor level implementation of the CMFB network.
