**2. Proposed Standard Cell Implementation of Digital OTA**

The implementation of the analog amplifier presented in [9] is reported in Figure 1. As explained in [9], the common mode (CM) extractor part in Figure 1 generates a common mode compensation analog signal to be added to the external inputs resulting in a common mode compensation method which is very similar to the common mode rejection mechanism of the conventional analog CMOS differential pair.

The CM compensation signal (*VCMP*) is added to the external input signals by a summing network so that the actual input signals of the digital buffers can be expressed as:

$$INp = \frac{Vip + V\_{CMP}}{2}; \; INn = \frac{Vin + V\_{CMP}}{2} \tag{1}$$

and their differential mode (DM) and CM components are related to external DM (*vD* = *Vip* − *Vin*) and CM (*vCM* = (*Vip* + *Vin*)/2) components as:

$$v\_D' = \frac{v\_D}{2}; \; v\_{CM}' = \frac{v\_{CM} + V\_{CMP}}{2} \tag{2}$$

**Figure 1.** Implementation of the digital-based analog amplifier presented in [9].

In Figure 1, a resistive summing network is included for the sake of simplicity, nonetheless, such a function can be conveniently implemented in CMOS technology by quasifloating gate (QFG) techniques [9].

The evolution of the circuit in Figure 1, which avoids the passive components, but uses Muller C-elements reported in Figure 2. This idea was proposed in [10] and analyzed in detail in [12].

**Figure 2.** Implementation of the DIGOTA presented in [10].

The Muller C-elements in Figure 2 implement, in a fully digital fashion, the compensation of the common-mode without requiring any calibration circuitry [10,11].

Even if QFG resistors and Muller C-elements can be implemented in CMOS processes, they are usually not available in the standard cell libraries provided by IC manufacturers, and all the previously reported digital OTA implementations are therefore not immediately suitable for automatic place and route within a semi-custom design flow.

The schematic of the proposed pure standard cell implementation of the digital OTA is reported in Figure 3. In particular, the circuit in Figure 3 is based on the following types of logic gates:


**Figure 3.** Proposed fully standard cell Implementation of the digital OTA.

Despite its pure standard cell implementation, the circuit operation is very similar to the one of the original implementations of the digital OTA in [9].

The CM extractor is implemented through the XOR1, the IV7 and the IT1 gates in Figure 3 and generates a common mode compensation signal (*VCMP*) which is then added to the external inputs through the summing network implemented by inverter gates IV1, IV2, IV3 and IV4, thus compensating the common mode as happens in the conventional analog CMOS differential pair.

To explain the summing mechanism, it is sufficient to note that a CMOS inverter acts as a transconductor when its input voltage is close to the logic threshold, therefore, the output current of *IV1* and *IV2* (*IV3* and *IV4*) are summed at their common output node and converted into a voltage through the equivalent resistance at node *INn* (*INp*).

#### **3. Simulation Results**

The proposed standard cell-based digital OTA (SC-DIGOTA) has been designed in the 130-nm STMicroelectronics CMOS technology adopting the standard cell library provided by the IC manufacturer. The circuit schematic has been described by using structural Verilog language (see Appendix A), and the layout has been automatically generated within the Cadence InnovusTM environment. Transistor level simulations on the post layout netlist have been carried out within the Cadence Virtuoso framework for analog design, exploiting AC and transient simulations. For AC simulations a bias point is established by applying the input signal on a DC level equal to about VDD/2 in order to have also the DC output voltage around VDD/2.
