**4. Experimental Results**

The fully-differential IA illustrated in Figure 3, along with the CMFB section in Figure 4, has been designed and fabricated in 180 nm CMOS technology to operate with a singlesupply voltage of 1.8 V. The microphotograph of the chip, including details on the layout, is depicted in Figure 5a, and the aspect ratios of the main transistors in the circuit are reported in Table 1. The measurements have been carried out over 10 samples of the silicon prototype. The testbench implemented for the experimental characterization is represented in Figure 5b, where the on-chip and the PCB levels have been highlighted. An on-chip differential voltage buffer, referred to as ×1, has been included for test purposes in order to isolate the output terminals of the FD IA from heavy loads. The buffer consists of two PMOS source followers including low-*Vth* transistors, so that operation with the general 1.8-V supply is possible. Auxiliary circuits AD8475 and AD8429 in Figure 5b are used to carry out, respectively, a single-to-differential signal conversion at the input of the IA and a differential-to-single signal conversion at the output in order to facilitate measurements. Even though these commercial components have been selected with a bandwidth higher that the circuit under test, their influence on the measurement procedure is unavoidable. The value of the reference voltage *VREF* used to set the DC level of the output voltage was set to 0.9 V. In addition, this voltage is also used to bias the gate terminal of the cascode transistors. The biasing current of each *V*-to-*I* converter, i.e., *GmI* and *GmO*, was adjusted as *IB* = 10 μA. The source degeneration resistors *RI* and *RO* were implemented with nonsalicided high-resistance polysilicon having values equal to *RI* =5kΩ and *RO* = 20 kΩ, thus leading to a nominal voltage gain of 4 V/V (12.04 dB).

**Figure 5.** (**a**) Chip microphotograph and (**b**) measurement setup.


**Table 1.** Transistor aspect ratios (*μ*m/*μ*m) for the FD IA (Figure 3).

The load capacitors, *CL*, were built on-chip as metal-insulator-metal devices to make stable the feedback loop established around the transconductor *GmO*. The design criterion selected was to ensure a phase margin of 60º considering the nominal value of the load capacitors, equal to 1.33 pF each, and the parasitic capacitance also connected to the output terminals due to the test buffer. In addition, it is worth to point out that the effective value of the parasitic capacitance introduced by the test buffer slightly relies on the value of the total external capacitance, associated to the PCB and the test probe used for measurements. This external capacitance has been estimated to be around 30 pF in most of the test configurations followed. Under these conditions, the open-loop frequency response of the DM and CM signal paths has been simulated and is represented in Figure 6. For the DM signal *LGDM* = 58.0 dB and *LGBWDM* = 5.9 MHz with a phase margin of 52.8º and a gain margin of 17.6 dB, whereas the CM signal response provides *LGCM* = 64.2 dB and *LGBWDM* = 18.1 MHz with a phase margin of 75.5º and a gain margin of 14.3 dB. These results show the stability of both the DM and the CM feedback loop and confirm the requirements imposed in (7a) and (7b) to the CM signal path. The bandwidth of the CM signal is noticeably higher than that of the DM component. This is due to the fact that the linearization carried out in the input differential structure of the IA leads to a lower effective transconductance as compared to the CMFB section, which results in a narrower frequency range.

The DC measurements on the 10 available samples allowed to obtain an average DC supply current for the IA equal to 266.4 μA, with a standard deviation of 2.6 μA. The DC voltage level shift introduced by the on-chip buffer did not allow characterizing the actual output voltage of the IA, expected to be very close to *VREF*. Hence, only the standard deviation of the buffered output voltage, equal to 3.63 mV, is reported in order to determine the variability of the output voltage among the different samples. The experimental *vI* − *vO* DC transfer characteristic of the IA is represented in Figure 7. The CM level of the output voltage, defined as (*v*<sup>+</sup> *<sup>O</sup>* + *v*<sup>−</sup> *<sup>O</sup>*)/2, has been used to shift all plots from their original DC level down to zero, so that results can be more easily interpreted. A linear voltage range at DC larger than ±50 mV can be inferred for the differential output response. As observed in Figure 7, the non-linearity appreciable in *v*<sup>+</sup> *<sup>O</sup>* and *v*<sup>−</sup> *<sup>O</sup>* is cancelled out when the overall output signal is obtained as the difference of the individual responses, i.e., *vO* = *v*<sup>+</sup> *<sup>O</sup>* − *v*<sup>−</sup> *O*.

**Figure 6.** Simulated open-loop frequency response of the DM and CM signal paths in the proposed IA.

**Figure 7.** Input−output DC transfer characteristic.

The simulated and experimental frequency response of the IA is illustrated in Figure 8, where the magnitude of the DM voltage gain is depicted. From the experimental response the voltage gain in the passband, *Av*, and the BW of the IA can be extracted, obtaining values equal to 3.78 V/V (11.4 dB) and 5.83 MHz, respectively. The gain value is in close agreement with the design value of 4 V/V or 12.4 dB (relative error of 5.0%) and with the simulated value of 3.69 V/V or 11.34 dB (relative error of 2.4%), whereas the measured BW deviates from the corresponding simulated value, equal to 7.76 MHz (relative error of 24.8%). The difference between the simulated and the experimental responses in Figure 8 has two possible reasons. On the one hand, it has been found that the on-chip voltage buffer is more sensible to external load capacitors than expected from simulations. On the other

hand, the BW of the IA is determined by the on-chip load capacitors illustrated in Figure 3, the value of which can suffer important absolute variations during the fabrication process. The nominal simulated value of the BW has been complemented with the result extracted from a 1000-run Montecarlo analysis, considering mismatch and process variations, which has been found to be equal to 10.27 ± 4.70 MHz. Considering the standard deviation as a suitable error margin, the lower bound of the statistically simulated BW encloses the values of both the nominally simulated and the measured BW. The time response of the proposed IA, depicted in Figure 9, has been used to confirm its stability. In particular, a 100-mV*pp* input signal (yellow plot) is applied and an appropriate establishment of the output voltage (green plot) can be observed.

The response to CM signals has also been obtained. The CMRR has been simulated and measured as a function of the frequency of the input signal and is shown in Figure 10. In the simulated plot (in green color), the average value, extracted from a 1000-run Montecarlo analysis including mismatch and process variations, is represented, whereas the error bars indicate the standard deviation, *σ*. As observed, the experimental CMRR lays below the error margin when the standard deviation is considered, but it has been proved that is enclosed by a 3-*σ* error region. The measured CMRR at low frequencies and at the frequency of the BW is equal to 73.3 dB and 42.0 dB, respectively. Furthermore, the impact of process, voltage, and temperature (PVT) variations on the CMRR at DC has been determined by nesting a 100-run Montecarlo analysis and a corner analysis. In particular, typical-typical (*tt*), slow-slow (*ss*), fast-fast (*ff*), fast-n-slow-p (*fs*), and slow-n-fast-p (*sf*) corners were considered for the active devices, whereas the temperature was set to values (0,27,80) ºC and the supply voltage was adjusted to (1.62,1.8,1.98) V, i.e., a variation equal to ±10% was assumed. The corresponding results are summarized in Figure 11, where in the axis corresponding to the temperature the considered range has been replicated for each corner of the active devices. As observed, the CMRR varies between 74.8 dB and 90.5 dB.

**Figure 8.** Simulated and measured frequency response of the proposed IA.

**Figure 9.** Transient response of the IA output voltage (green) to a 100-mV*pp* input square wave (yellow).

**Figure 10.** Simulated and measured CMRR vs. frequency.

**Figure 11.** CMRR extracted from a Montecarlo analysis for the different corners.

The noise response of the FD IA has also been characterized. In particular, the spectral density of noise has been simulated and measured and is depicted in Figure 12. In addition, the noise has been integrated over a frequency band between 100 Hz and the frequency of the BW, obtaining a value equal to 86.4 *μ*V*rms*. The calculated experimental noise is slightly higher than the actual value, due to the finite approximation followed to integrate the noise. In any case, the simulated noise, equal to 74.7 *μ*V*rms* (relative error of 15.7%), is much lower. The reason of the noise increase in measurements is ascribed to the experimental setup and to the contributions of the different auxiliary circuits used for the test, as illustrated in Figure 5b and already indicated at the beginning of this section. The THD has been used to asses the linearity of the dynamic response of the FD IA. In Figure 13 the simulated and experimental THD of the output voltage is represented as a function of the input DM signal amplitude for frequencies of 1 kHz and 10 kHz. The simulated THD is reduced as compared to the experimental response for small values of the input signal due to the lower noise floor level in simulations. Nevertheless, for high input signals the measured response results even more linear. Using the widespread criterion of considering the 1%-THD as a limit to determine the maximum input signal that can be processed with reasonable linearity, experimental values of 59.6 mV and 57.6 mV were obtained for input frequencies of 1 kHz and 10 kHz, respectively.

**Figure 12.** Spectral density of noise vs. frequency: simulated (green) and measured (blue) responses.

**Figure 13.** Simulated and experimental THD vs. *vI*,*DM* for *fI* equal to 1 kHz and 10 kHz.

The performance of the designed and fabricated FD IA is summarized in Table 2, where simulated and measured results are reported. The data expressed as the mean value plus/minus the standard deviation were obtained from a 1000-run Montecarlo analysis with mismatch and process variations in the case of simulations and from the measurements on 10 samples in the case of experimental results. In general, there is a good agreement between the simulated and the measured metrics, being the corresponding differences due to the variations of the process parameters during fabrication. One exception is the case of the noise, which, as discussed previously, greatly increases in measurements with respect to simulations.

The comparison of the previous metrics for different IAs is done usually in terms of a widespread figure-of-merit (FoM) known as noise efficiency factor (NEF) [4]. This parameter indicates how large is the noise of a system as compared to the white noise of a single MOS transistor with the same drain current and bandwidth, and is defined as:

$$NEF = V\_{iN,rms} \sqrt{\frac{2I\_{DD}}{\pi V\_T 4kT BW}}\tag{12}$$

where *IDD* and *VT* are the supply current of the IA and the thermal voltage, respectively. Nevertheless, this parameter does not take into account the amplitude of the signals to be processed. Indeed, when large input signals must be handled, a high biasing current is required, thus resulting in a penalty in therms of NEF. In this case, the dynamic range (DR), defined as

$$DR = 20 \cdot \log \left( \frac{\upsilon\_{I,DM\_{max}}}{V\_{iN,rms}} \right) \tag{13}$$

can be used as a complementary FoM for performance comparison.


**Table 2.** Simulated vs. experimental performance of the FD IA (Technology: 180 nm CMOS, *VDD* = 1.8 V, *Av*,*nom* = 4 V/V).

The FD IA presented is compared in Table 3 to other works previously reported and with similar characteristics, i.e., based on current feedback and presenting a wide bandwidth. The work by Worapishet et al. [11] presents very good values of NEF and DR, especially considering that measured results are given, but the BW is more limited than in the other solutions. The IAs in [12,22] have a good response in general, even tough they are solutions supported by simulated results. In [26] a very high bandwidth is achieved but no data regarding the size of the processed signals and the noise are reported. The IA proposed in [29] has also a differential structure and achieves a higher BW than the IA proposed here, but the signal processed are smaller and the noise is higher, thus resulting in a higher NEF and a lower DR. The proposed IA has a BW suitable for electrical bioimpedance analysis and is able to process the largest input differential signals for similar supply currents. In addition, it is a compact solution in terms of silicon area as compared to most of the other solutions, especially considering that it has a FD structure. Finally, it is worth to point out that the increase of the experimental noise, previously indicated, leads to a noticeable reduction of the measured DR and to an increase of the experimental value of the NEF. Indeed, the simulated characterization of the IA reported values for the NEF and the DR equal to 14.6 and 57.1, respectively.


**Table 3.** Performance comparison of the proposed IA with other works previously reported.

(∗) LCF: local current feedback; ICF: indirect current feedback; *Gm*-TI: transconductance-transimpedance.
