*3.1. MLI Control Subsystem*

MLI switching power losses are kept low by taking advantage of low-frequency space vector modulation (SVM) or step modulation (ST). However, these modulation techniques must be suitably modified to allow for a direct periodical connection between the *N* − 1 energy sources connected to the MLI dc-bus and the TLI. This is necessary to enable independent voltage control on each of the *N* − 1 MLI dc-bus capacitors. According to (1), the space diagram of the transformer primary phase voltage *Vjp* is obtained by combining the voltage space vector diagrams of the two inverters. The simplest MMC configuration that can be obtained according to the proposed approach encompasses a three-level inverter (3LI + TLI), which provides six voltage levels if *VDC* = *VDC* /(*N* − 1). Such an MMC may take 3<sup>3</sup> = 27 switching states; however, only 19 different voltage vectors can be generated, because some of the switching states are redundant. The MMC voltage space vector diagram can be obtained by adding the voltage space vector diagram of the TLI at the top of each voltage vector of the 3LI, as shown in Figure 4 [27]. Each input dc source can be independently managed by exploiting its periodical connection to the transformer's primary winding, which occurs when the 3LI generates one of the twelve possible low-voltage vectors (LVVs), namely PPO, OON, POO, ONN, ONO, POP, NNO, OOP, NOO, OPP, NON, and OPO, according to Figure 4 and Table 2. As an example, Figure 5 shows that when the voltage vector PPO is generated, the capacitor *C*1, which represents the output capacitor of the energy source *ES*1, is directly connected to the TLI. Hence, when the voltage vector PPO is generated, *VC*1, that is, the voltage across *C*1, can be regulated by controlling the power stream between the 3LI and the TLI. This is accomplished through a closed loop voltage controller managing the power exchange between *ES*<sup>1</sup> and the TLI dc-bus capacitors through a specific set of components *Vkj* of the TLI reference voltage, as shown in Figure 5c. In practice, the voltage regulator, by processing the difference between the *C*<sup>1</sup> reference voltage *Vc*<sup>1</sup> \* and the actual value *Vc*1, generates a coefficient *I*, which is multiplied by the actual values of the transformer's primary currents to obtain *Vkj*. Therefore, if *I* is positive, an additional power transfer is instated directed towards *C*1, thus increasing *Vc*1. If *I* is negative, the additional power flow is directed from *C*<sup>1</sup> to the TLI dc-bus capacitors, thus discharging *C*<sup>1</sup> and reducing *Vc*1. Hence, it is possible to charge or discharge *C*<sup>1</sup> when the MLI generates the vector PPO. The same applies for the other dc bus capacitors when the MLI is generating the specific LVV.

**Figure 4.** Three-level neutral point clamped (NPC) + TLI voltage space vector diagram (*VDC*/*VDC* = 1/2). **Table 2.** Six-level MMC low voltage vectors.


In general, for a *N*-level NPC converter, *N* − 1 space vectors can be exploited for controlling *N* − 1 input dc sources. For instance, Figure 6 shows the space phasor diagram of a 10-level MMC composed of a five-level NPC and a TLI (5LI + TLI) as that shown in Figure 3, where *VDC/VDC* is set to 0.25. The energy sources that can be managed in this case are four, namely *ES*1, *ES*2, *ES*3, and *ES4*, each one connected to the MLI dc-bus through an output capacitor *Cj* (*j* = 1 ... 4). The voltage *VCj* across the output capacitor *Cj* can be regulated by acting on the six LVVs shown in Figure 6, being *P*1, *P*2, *O*, *N*1, and *N*<sup>2</sup> the possible states of the j-leg, as shown in Table 3. When the vector *R*<sup>2</sup> *(P*2*P*2*P*1*)* is generated, the capacitor *C*<sup>1</sup> is directly connected to the TLI through the primary windings of the transformer, as shown in Figure 7, making possible the regulation of the voltage *Vc*<sup>1</sup> by controlling the power stream between the two converters.

**Figure 5.** Three-level inverter (3LI) + TLI: *C*<sup>1</sup> voltage control when the PPO vector is generated: (**a**) discharging; (**b**) charging; (**c**) equivalent voltage control loop during PPO.

**Figure 6.** Five-level inverter (5LI) + TLI voltage space vector diagram (*VDC*/ *VDC* = 1/4).


**Table 3.** Five-level NPC j-leg states.

**Figure 7.** Five-level inverter (5LI) + TLI: *C*<sup>1</sup> voltage control when the *P*2*P*2*P*<sup>1</sup> vector is generated: (up) discharging; (down) charging.

For low modulation indexes, it is possible to regulate the voltage of the *N* − 1 dc-bus capacitors without modification of the conventional multilevel SVM or SM strategies, because the top of the reference voltage vector *Vm* \* always lies inside the hexagon encompassing *R*1, *R*2, *R*3, *R*4, *R*5, and *R*6. According to the basic multi-level SVM strategy, the voltage–time Equation (5) referred to a stationary *q,d* reference frame gives the switching times *ta*, *tb*, and *tc* from the voltage reference *Vm* \* and the switching period *Tm*. As shown in Figure 8a, for low modulation indexes, *Va* coincides with the null state *V*0, while *Vb* and *Vc* are those LVVs whose tops coincide with the vertices of the triangle in which the top of the reference voltage vector lies. However, as shown in Figure 8b, for medium and high modulation indexes, no LVVs are selected according to the conventional SVM strategy; thus, they must be purposely introduced in the inverter switching path. This can be obtained by substituting one of the vectors *Va*, *Vb*, or *Vc* of Equation (5) with a switching sequence including the LVV that must be activated, and other two voltage vectors *V*<sup>1</sup> and *V*2. If, as shown in Figure 8c, the LVV *R* 1must be activated, the switching times *tR*, *t*1, and *t*<sup>2</sup> are given by Equation (6), being *Ta* obtained by solving Equation (5). A similar procedure can be adopted to modify the switching patterns generated according to the standard multi-level SM.

$$\begin{cases} T\_m V\_{m\alpha} \*= t\_a V\_{a\alpha} + t\_b V\_{b\alpha} + t\_c \, V\_{c\alpha} \\ T\_m V\_{m\beta} \*= t\_a V\_{a\beta} + t\_b V\_{b\beta} + t\_c \, V\_{c\beta} \\\ T\_m = t\_a + t\_b + t\_c \end{cases} \tag{5}$$

$$\begin{cases} \begin{array}{c} T\_a V\_{a\alpha} = \ t\_1 V\_{1\alpha} + \ t\_2 V\_{2\alpha} + \ t\_R \ V\_{R1\alpha} \\ T\_a V\_{a\beta} = \ t\_1 V\_{1\beta} + \ t\_2 V\_{2\beta} + \ t\_R \ V\_{R1\beta} \\ T\_a = \ t\_1 + \ t\_2 + \ t\_R \end{array} \tag{6}$$

**Figure 8.** Five-level inverter (5LI) + TLI. (**a**) Space vector modulation (SVM) at a low modulation index. (**b**) SVM at a high modulation index. (**c**) Modified SVM.

#### *3.2. TLI Operation and 3LI + TLI Control Algorithm*

Transformer primary voltage harmonics generated by low-frequency modulation of the main inverter are then cancelled by the TLI. In fact, the TLI working at a high switching frequency plays the role of an active power filter while also managing the power flows originating from the *N* − 1 energy sources connected to the MLI dc-bus and compensating for possible imbalances caused by different dc-bus capacitor voltages. This makes it possible to avoid the introduction of additional dc/dc converters, which otherwise would be necessary to connect each energy source to the system. The MMC control system encompasses a synchronous *qd* current controller regulating the transformer's primary current and the *N* − 1 voltage controllers to manage the energy sources connected to the MLI dc-bus [28]. A schematic of the control system developed for the proposed MMC is shown in Figure 9 for a 3LI + TLI configuration. It consists of three main blocks, namely TLI dc-bus current (battery) control, NPC dc-bus voltage (energy sources) control, and regulation of active and reactive power at the primary side of the transformer. Moreover, a *N* − 1 channels maximum power point tracking function can be provided in order to cope with PV arrays connected as energy sources. In this case, according to Figure 5, the MPPT sets the reference voltages *Vc*<sup>1</sup> and *Vc*2, whose sum *VDC* \* constitutes the reference for the q-axis 3LI current regulator. The reactive power is instead controlled by acting on the d-axis current. An independent control on *Vc*<sup>1</sup> and *Vc*<sup>2</sup> is obtained by two voltage controllers, whose outputs are processed in order to obtain the components *Vkja* of the TLI reference voltages as shown in Figure 5c. Whenever one LVV is active, *k* is set to 1 and the reference

coefficient *I* is computed to charge or discharge the considered capacitor. At the same time, the correct MLI voltage vector path is selected according to Equations (5) and (6) in order to connect the specific energy source to the TLI, thus establishing a power stream from the energy source to the TLI d-bus. Further components of the TLI reference voltage *Vhj* and *Vbattj* are computed dealing, respectively, with the compensation of harmonics generated by the low-frequency operation of the MLI (Equation (7)) and control of the battery current *iDC*. Hence, the *j*-phase TLI reference voltage is given by Equation (8) while *Vhj* is written in (7).

$$V\_{\rm hj} = |V\_{\rm NPCj} - V\_{\rm 1NPCj}| \tag{7}$$

$$V\_{TLIj} \* = \; V\_{hj} + \; V\_{Battj} + \; V\_{kj} \tag{8}$$

being *V1NPCj* the fundamental component of the NPC output phase voltage *VNPCj.* The TLI current control is also able to compensate for imbalanced voltages on the 3LI dc-bus by adapting the duty cycle of the TLI at each half-cycle. This capability depends on the value of *VDC*, which is the maximum capacitor voltage deviation value that can be compensated for. Hence, the TLI ensures a sinusoidal grid-current during *Vc* = *Vcn* ± *VDC* for all NPC dc-bus capacitors.

**Figure 9.** Six-level MMC (3LI + TLI).

### **4. Simulation Results**

The effectiveness of the proposed topology was first evaluated through a simulation, taking into account a scaled model of a hybrid renewable energy generator tailored around an open-end winding 5 kVA-230/400 V three-phase transformer, a three-level NPC inverter exploiting a 1 kHz SVM strategy with a 400 V dc-bus voltage, a TLI PWM operating at 10 kHz, and a three-phase grid. The parameters of the system components are listed in Tables 4–11. These include the main data of the IGBT and diodes on the NPC MLI and those of the power MOSFET devices present on the TLI.



#### **Table 5.** Three-phase transformer.


#### **Table 6.** PV modules (STC).


#### **Table 7.** Wind Turbine.


#### **Table 8.** Battery.


#### **Table 9.** Diodes.


#### **Table 10.** MLI-IGBT (STGW40N120K).



**Table 11.** TLI-MOSFET (IRFB5615PBF).

Two cases are taken into consideration: a fully PV system with an ESS; and a hybrid PV– wind one with an ESS. The system model was developed using the MATLAB/Simulink environment and setting a 1 μs sample time. Output power characteristics of the PV modules are shown in Figure 10. Each PV string consists of five modules in order to achieve a peak voltage of 200 V on the NPC dc-bus capacitors *C*<sup>1</sup> and *C2*. Operation of the first configuration is shown in Figure 11, dealing with NPC dc-bus voltages *Vc*<sup>1</sup> and *Vc*2, the output power of *ES*1, *ES*2, and the battery, the irradiances of PV strings *GPV*<sup>1</sup> and *GPV*2, the transformer's primary and secondary voltages, the NPC output voltages *VNPCj*, the grid currents, the TLD bus voltage *VDC* and current *iDC* , the battery's state of charge (SOC), and the qd-axes current components. At *t* = 0.5 s, the solar insolation on the ES2 PV string falls down from 1000 W/m2 to 700 W/m2. Then, the ES2 output power decreases from 600 W to 560 W. According to Figure 10, the voltage *Vc*<sup>2</sup> is then reduced to track the maximum power point by acting on the TLI according to the voltage control scheme of Figure 5c. Once *Vc*<sup>2</sup> has reached the new optimal value, an imbalanced voltage condition (*Vc*<sup>1</sup> = 200 V, *Vc*<sup>2</sup> = 165 V) occurs. However, the three-phase grid currents are kept sinusoidal by the TLI current control system by drawing power from the ESS, as the SOC diagram confirms. In this case, in fact, the TLI dc-bus voltage *VDC* = 210 V is sufficient to compensate for the Δ*Vc*<sup>2</sup> = (200 − 165) V = 35 V voltage deviation. Figure 12 deals instead with operation of the second configuration, when the rotor speed of the wind turbine *ωrm* drops from 1500 to 0 rpm. Additionally, in this case, the TLI dc-bus voltage *VDC* = 210 V is sufficient to compensate for the Δ*Vc*<sup>2</sup> = (200 − 200) V = 0 V voltage deviation. The proposed system is able to manage a bidirectional power stream towards/from the energy storage system as shown in Figure 13. The irradiances considered for PV1 and PV2 are not the same, being respectively 1000 W/m2 and 700 W/m2, while the battery current varies from 2.5 A to −2.5 A. The battery SOC trend demonstrates the bidirectional power capability of the proposed configuration.

**Figure 10.** P-V diagrams of photovoltaic modules.

**Figure 11.** Six-level MMC-*GPV*<sup>2</sup> drop from 1000 W/m<sup>2</sup> to 700 W/m2. (**a**) String voltages *Vc*<sup>1</sup> and *Vc*2. (**b**) ES1, ES2, and energy storage system (ESS) output power. (**c**) *GPV*<sup>1</sup> and *GPV*2. (**d**) Grid voltage. (**e**) NPC output voltage. (**f**) Primary voltage. (**g**) Grid current. (**h**) Battery voltage. (**i**) Current. (**j**) State of charge (*SOC*). (**k**) Output *d*,*q* axes currents.

**Figure 12.** Six-level MMC-wind turbine (WT) shut-down *GPV*<sup>1</sup> = 1000 W/ m2. (**a**) *Vc*<sup>1</sup> and *Vc*2. (**b**) ES1, ES2, and ESS output power. (**c**) *GPV*<sup>1</sup> and PMSG rotor speed *ωr*. (**d**) Grid voltage. (**e**) NPC output voltage. (**f**) Primary voltage. (**g**) Grid current. (**h**) Battery voltage. (**i**) Current. (**j**) *SOC*. (**k**) Output *d*,*q* axes currents.

**Figure 13.** Si-level MMC-battery current transition from 2 A to −2 A with *GPV*<sup>1</sup> = *GPV*2. (**a**) String voltages *Vc*<sup>1</sup> and *Vc*2. (**b**) Output power of PV1, PV2, and the battery. (**c**) Solar power *GPV*<sup>1</sup> and *GPV*2. (**d**) Battery current. (**e**) Battery *SOC*.

#### **5. Experimental Assessment**

Experimental tests were accomplished on a six-level MMC encompassing an open-end winding 5 kVA–230 V/400 V three-phase transformer, a 3LI-NPC inverter with a 200 V dc-bus voltage exploiting an SM strategy, and a two-level inverter PWM operating at 10 kHz. A 100 V, 40 Ah Lithium-ion battery was connected to the dc-bus of the TLI. All system parameters are listed in Table 4, Table 5, Table 6, Table 7, Table 8, Table 9, Table 10, and Table 11. The control system was realized around a DSpace/1103 board running at 10 kHz. The primary winding of the transformer was connected, on one side, to the NPC MLI and, on the other side, to the TLI. Programmable PV module emulators played the role of two PV strings connected to the NPC dc-bus. Steady-state operation under balanced and imbalanced conditions is shown in Figure 14a,b, dealing with the 3LI + TLI output voltage, grid voltage, grid current, and 3LI output step voltage. In Figure 14a, a balanced condition is considered with *Vc*<sup>1</sup> = 100 V, *Vc*<sup>2</sup> =100 V. Hence, the TLI acts only as an active power filter in order to compensate for the low-order harmonic generated by the NPC low switching frequency modulation. Figure 14b instead deals with the imbalanced condition with *Vc1* = 100 V, *Vc*<sup>2</sup> =70 V, and *VDC* = 100 V. Although the NPC dc-bus voltages are imbalanced, the grid current is sinusoidal with a THD as low as 1.5%. In this case, the TLI not only works as an active filter but also as a voltage imbalance compensator. A reduction in the dc voltage generated by PV1 string is shown in Figure 15a, where *Vc*<sup>1</sup> is changed from 100 V to 70 V. Such an imbalance causes a variation in the peak voltage in the positive half-cycle of *VjNPC*, but the current is kept sinusoidal by the TLI. Figure 15b deals with power generated by the two PV strings *PPV1* and *PPV*<sup>2</sup> provided by the battery *PTLI* and the output one *Pg*. The reduction in *Vc*<sup>2</sup> causes a reduction in *PPV*<sup>2</sup> from 320 W to 180 W according to the P–V profile of Figure 10. The same power variation is present in the grid power *Pg* because the active power produced by the TLI's battery is kept constant. Figure 16 shows a detailed view of the waveforms of *VaNPC* and *iag* in the test of Figure 15. The TLI compensates for the unbalanced voltages and almost perfectly shapes the grid current.

**Figure 14.** The (3LI + TLI) steady state. (**a**) Balanced voltage, *VDC* = 200 V, *Vc*<sup>1</sup> = 100 V, *Vc*<sup>2</sup> = 100 V, *VDC* = *VDC* /2 = 100 V. (**b**) Unbalanced voltage, *VDC* = 170 V, *Vc*<sup>1</sup> = 70 V, *Vc*<sup>2</sup> = 100 V, *VDC* = 100 V. Secondary phase voltage *Vsj*, grid phase voltage *ej*, grid phase current *igj*, and NPC output voltage *VNPCj*, (*Vg* = 150 V, 50 Hz, TLI PWM 10 kHz).

**Figure 15.** The (3LI + TLI) photovoltaic (PV) power variation. (**a**) PV voltages *Vc*<sup>1</sup> and *Vc*2, NPC output voltage *VNPCj*, and grid current *igj*. (**b**) PV power *PPV*<sup>1</sup> and *PPV*2, TLI output active power *PTLI*, and grid active power *Pg*. (*Vg* = 150 V, 50 Hz *VDC* = 100 V, TLI 10 kHz PWM).

**Figure 16.** The (3LI + TLI) steady state. (**a**) Balanced voltage, *VDC* = 200 V, *Vc*<sup>1</sup> = 100 V, *Vc*<sup>2</sup> = 100 V, *VDC* = *VDC* /2 = 100 V. (**b**) Unbalanced voltage, *VDC* = 170 V, *Vc*<sup>1</sup> = 70 V, *Vc*<sup>2</sup> = 100 V, *VDC* = 100 V. Secondary voltage *Vsj*, grid voltage *ej*, grid current *igj*, and NPC output voltage *VNPCj* (*Vg* = 150 V, 50 Hz, TLI 10 kHz PWM).

A further test was performed dealing with battery current control, as shown in Figure 17, dealing with battery current, voltages *Vc*<sup>1</sup> and *Vc*2, and grid current. The voltages are kept balanced at *Vc*<sup>1</sup> = 100 V and *Vc*<sup>2</sup> = 100 V, while the battery current is changed from −3 A to 2 A. Hence, the battery is first discharged and then charged. A negative battery current means that the battery feeds power *Pbatt* to the grid according to Figure 17. Vice-versa, a positive battery current means that the battery is charged from the grid. The harmonic spectrum of the grid current at a rated load is shown in Figure 18, fully complying with the IEC 61000-3-2 standard on power quality.

**Figure 17.** The (3LI + TLI) battery current variation from 2 A to −2A with *GPV*<sup>1</sup> = *GPV*2. (**a**) String voltages *Vc*<sup>1</sup> and *Vc*2. Battery current iDC. Grid current *igj* (**b**) String power *PV*1, *PV*2. Battery power PBatt, grid active power *Pg*.

**Figure 18.** The (3LI + TLI) grid current spectrum vs. IEC 61000-3-2 l limits.

#### **6. Power Losses Analysis**

A power losses analysis was accomplished by considering the efficiency *η3LI + TLI* of the 3LI + TLI converter and that of the transformer *ηTR*. Hence, the total efficiency is obtained as Equation (9). The efficiency of the converter was estimated by computation of the power devices conduction *Pc* and the switching *Psw* losses. According to [29], the 3LI is equipped with a high-voltage and low-frequency IGBT, while a low-voltage, high switching frequency MOSFET is used in the TLI. The main data on these power devices are listed in Tables 9–11. Conduction losses of the IGBT and MOSFET were computed according to Equations (10) and (11), respectively, while switching losses were evaluated by Equation (12) for both power switches. Furthermore, the diodes' reverse recovery power losses are also considered in Equation (13) and were included in the total power losses calculation.

$$
\mathfrak{u}\_{\text{Tot}} = \mathfrak{u}\_{\text{3LL} + \text{TLL}} \mathfrak{u}\_{\text{TR}} \tag{9}
$$

$$P\_{c\\_MLI} = \delta V\_{cc(on)} i\_{RMS} \tag{10}$$

$$P\_{\mathcal{C}\_{-}TLI} = R\_{DS(on)} i\_{RMS}^2 \tag{11}$$

$$P\_{sw} = 0.5 V\_{ct} i\_{RMS} f\_{sw} (t\_{rise} + t\_{fall}) \tag{12}$$

$$P\_D = V\_{DR} f\_{sw} (t\_{rd} i\_{RMS} + Q\_r) \tag{13}$$

$$\eta\_{TR} = \frac{A\_n \cos(\varphi)}{A\_n \cos(\varphi) + i P\_{fcn} + P\_{cun}/i} \tag{14}$$

where *δ* is the duty cycle, *tr* and *tf* are the rise and fall times of the power switches, *iRMS* is the Root Mean Square (rms) value of the switch current, *Vce* is the collector-to-emitter voltage, *Vce(on)* is the collector-to-emitter saturation voltage, *RDS(on)* is the static drain-tosource on resistance, *fsw* is the switching frequency, *VDR* is the diode's reverse voltage, *trd* is the diode's reverse recovery time, and *Qr* is the reverse recovery charge. The efficiency of the three-phase transformer was computed as a function of iron losses *Pfen*, rated copper losses *Pcun*, power factor cos(ϕ), rated power *An*, and load coefficient *I=ig/ign*, being *ign* the rated current of the transformer, Equation (14). Figure 19 shows the conduction and

switching losses of the two inverters as a function of the load coefficient *i*. Specifically, *P3LI\_cond* and *PTLI\_cond* are the conduction losses of 3LI and TLI, respectively, while *P3LI\_sw* and *PTLI\_sw* are the switching losses, which increase with the load current from 2.6% at *i* = 0.1 to 8% at *i* = 1. The switching power losses of the 3LI are quite low due to the low switching frequency. The total efficiency of the two inverters *η3LI + TLI* and that of the transformer *ηTR* are shown in Figure 20 as function of the load ratio. The peak efficiency of the converter is 98.9% at *i* = 1, while the minimum is 95.2% at *i* = 0.2. The efficiency of the transformer, *ηTR*, reaches its peak value of 96.5% for *i* = 3/4. Finally, the total efficiency was obtained according to Equation (9) and is shown in Figure 20c. It reaches the maximum value of 95% at *i* = 0.7.

**Figure 19.** Power losses of 3LI + TLI vs. load current.

**Figure 20.** Efficiency vs. load current. (**a**) Three-level inverter (3LI) + TLI efficiency. (**b**) Transformer efficiency. (**c**) Total efficiency.

#### **7. Discussion**

Simulation and experimental results confirm that independent management of *N* − 1 power sources and an ESS can be accomplished by using an AHMLI structure composed of a N-level inverter, an open primary winding transformer, and a two-level inverter. This makes unnecessary the introduction of additional dc–dc converters to connect the input ES and the ESS to the grid inverter. Such a structure is also able to compensate for a possible imbalance among the output voltages of energy sources, provided that it does not exceed the dc-bus voltage of the auxiliary TLI. Under this limit, the proposed configuration is also able to cope with a full shut-down of one of the input ESs. Moreover, an independent N-1-channel MPPT can be provided to manage multi-string PV arrays. As proved by experimental tests, the proposed configuration produces an almost perfectly sinusoidal grid current, despite the fact that the main inverter is operated at a low switching frequency in order to improve the efficiency. In fact, the current shaping is accomplished by the auxiliary TLI, which operates at a high switching frequency, but at a remarkably lower dc-bus voltage. This allows us to equip the TLI with fast and powerful MOSFET devices producing low switching and conduction power losses. The efficiency performance of the proposed structure is confirmed by a power losses analysis, which gives global efficiency levels similar to those obtainable with conventional conversion systems for HRESs, but with a more simple and less expensive structure.

### **8. Conclusions**

The goal of this work was to prove that a multi-input conversion system can be constructed from an AHMLI topology exploiting an open-end primary winding transformer. The coherence of such a concept was confirmed first theoretically and then by simulation and experimental tests. Applied to hybrid renewable energy systems exploiting multiple energy sources and an energy storage system, the proposed approach allows us to largely reduce the complexity and cost of the power conversion systems, avoiding the introduction of additional dc–dc converters to interface each energy source with the grid-connected inverter. Further developments of the proposed concept will deal with applications in other sectors, such as electric vehicles and the aerospace industry.

**Author Contributions:** A.T. and S.F. conceived the original idea. A.T., S.F. and L.D.T. developed the theory and performed the computations. S.D.C., G.S. and M.C. verified the analytical methods. All authors discussed the results and contributed to the final manuscript. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research received no external funding.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Informed consent was obtained from all subjects involved in the study.

**Data Availability Statement:** Not applicable.

**Conflicts of Interest:** The authors declare no conflict of interest.
