*5.1. Impact of SM Faults on MMC Operation for Di*ff*erent Control Schemes*

This subsection presents time-domain simulations that illustrate the behaviors of the 20-cell MMC in Figure 7 under SM faults. The parameters of the simulated MMC are listed in Table 1. In this study, two faulted SMs represented 10% of the total SMs per arm, and the SM fault was applied at the upper arm of phase-leg A at 0.4 s, and the two faulty SMs were bypassed.

**Figure 7.** Simplified single line diagram of the 40 kV, 40 MVA, and 20-cell MMC connected to ac grid.


**Table 1.** Simulation Parameters.

Figures 8 and 9 show simulation waveforms for the control schemes A and B, respectively. These results are obtained when the MMC injects a 1.0 pu (40 MW) active power into the ac grid and regulates reactive power at zero. In contrast, Figures 10 and 11 display simulation waveforms when the MMC injects 0.6 pu (24 MVAr) capacitive reactive power and zero active power into the ac grid, with control schemes A and B, respectively. The 0.6 pu (24 MVAr) represents the maximum capacitive reactive power, which the simulated MMC can inject into the ac grid.

**Figure 8.** Simulation waveforms of the MMC under submodule (SM) fault and control scheme-A operates in active power mode: (**a**) dc current, (**b**) ac current, (**c**) leg A upper and lower arm voltages superimposed on its common-mode voltage, (**d**) leg A upper and lower arm currents, (**e**) leg A upper and lower capacitor voltage sums, (**f**) common-mode capacitor voltage sums of three phase-legs, (**g**) differential-mode capacitor voltage sums of three phase-legs, and (**h**) leg A upper arm SM voltages.

**Figure 9.** Simulation waveforms of the MMC under SM fault and control scheme-B operates in active power mode: (**a**) dc current, (**b**) ac current, (**c**) leg A upper and lower arm voltages superimposed on its common-mode voltage, (**d**) leg A upper and lower arm currents, (**e**) leg A upper and lower capacitor voltage sums, (**f**) common-mode capacitor voltage sums of three phase-legs, (**g**) differential-mode capacitor voltage sums of three phase-legs, and (**h**) leg A upper arm SM voltages.

**Figure 10.** Simulation waveforms of the MMC under SM fault and control scheme-A operates in reactive power mode: (**a**) dc current, (**b**) ac current, (**c**) leg A upper and lower arm voltages superimposed on its common-mode voltage, (**d**) leg A upper and lower arm currents, (**e**) leg A upper and lower capacitor voltage sums, (**f**) common-mode capacitor voltage sums of three phase-legs, (**g**) differential-mode capacitor voltage sums of three phase-legs, and (**h**) leg A upper arm SM voltages.

**Figure 11.** Simulation waveforms of the MMC under SM fault and control scheme-B operates in reactive power mode: (**a**) dc current, (**b**) ac current, (**c**) leg A upper and lower arm voltages superimposed on its common-mode voltage, (**d**) leg A upper and lower arm currents, (**e**) leg A upper and lower capacitor voltage sums, (**f**) common-mode capacitor voltage sums of three phase-legs, (**g**) differential-mode capacitor voltage sums of three phase-legs, and (**h**) leg A upper arm SM voltages.

The observations drawn from results of Scheme-A presented in Figure 8 can be summarized as follows:


Simulation waveforms of the 20-cell MMC in Figure 7, with the Scheme-B, are presented in Figure 9. The observations drawn from the results in Figure 9 are as follows:

1. MMC with the use of Scheme-B exhibits slightly different behavior from that with the control scheme A. The dc-link current displayed in Figure 9a exhibits smaller increase, and SM capacitor voltage sum of the faulty leg (an upper arm of phase-leg A) exhibits slightly small under-shoot and over-shoot compared to those with Scheme-A. The smaller increase in the dc current with control scheme B can be attributed to the absence of vertical controllers, which actively inject additional active powers and fundamental currents into the common-mode loops in order to enforce equalization of the arm capacitor voltage sums.


In addition, the results of fast Fourier transform (FFT) analysis presented in the appendix for the MMC in Appendix A, when it is controlled using the control schemes A and B, respectively, show that the amplitudes of the fundamental frequency component in dc-link current are 11.3 A and 4.1 A, respectively. These results confirm the effectiveness of the Scheme-B in dealing with fundamental frequency ripples in the dc loop (common-mode and dc-link currents) compared to that of the Scheme-A.

The observations, drawn from Figures 10 and 11 when control schemes A and B are used to control the 20-cell MMC in Figure 7, are as follows:

Figures 10a and 11a show that theMMC dc current for the two control schemes is zero, as anticipated during pure reactive power exchange. In line with previous cases, these results show that the dc current of Scheme-A exhibits a brief period of larger temporary over-current due to actions of arm balancing controllers, which force the dc voltages across all arms to be equal.

Figures 10b–d and 11b–d display the three-phase output currents and phase-leg A upper and lower arm voltages superimposed on the common-mode capacitor voltage sum of phase A. Notice that reactive power output reaches the limit as the arm voltage synthesized nearly touches the limits in both cases.

Although the common-mode capacitor voltage sums of the schemes A and B exhibit similar behaviors, the capacitor voltage sums of the upper and lower arms of the faulty phase-leg exhibit slightly different behaviors, see Figure 10e,f and Figure 11e,f. Besides, the differential-mode capacitor voltage sums in Figures 10g and 11g present different convergence patterns, as Scheme-A controls the differential-mode capacitor voltage sum actively.

#### *5.2. Parametric Studies of Asymmetric MMC Operation*

To further generalize the findings of the above detailed quantitative studies on asymmetries introduced by the MMC SM faults, additional parametric studies are conducted on a 50-cell MMC using control schemes A and B. The test system parameters are listed in Table 2. To reproduce more representative MMC asymmetries that may arise from SM faults or severe deviations in the values of passive parameters from their nominal values, the SM capacitance (*Cu* and *Cl*) and arm inductance (*Lu* and *Ll*) of the upper and lower arms are varied within ±10% of their nominal values, *C0* and *L0* (i.e., 0.9*C0* ≤ *Cu, l* ≤ 1.1*C0* and 0.9*L0* ≤ *Lu, l* ≤ 1.1*L0*). In the parametric studies, the 50-cell MMC in Figure 12 injects 100 MW into the ac grid at a unity power factor.


**Table 2.** Simulation Parameters.

**Figure 12.** Test system employed in parametric studies with a 50-cell MMC, in which 5 faulty SMs represent 10% of the total number of SMs per arm.

Figures 13 and 14 present side-by-side comparisons of the normalized fundamental frequency ripple in the dc current by its average and maximum achievable modulation range versus average asymmetries in the SM capacitances and inductances between the upper and lower arms of the same phase-leg, for control schemes A and B. The observations drawn from these parametric studies are:


voltage sums are no longer sufficient to synthesize the required ac voltage to exchange the desired active and reactive powers. These observations are in line with the discussions above.

**Figure 13.** Variation of fundamental frequency dc-link current ripple magnitude (pu) with SM capacitance tolerances *TC* and arm inductor tolerances *TL*: (**a**) Scheme-A and (**b**) Scheme-B.

**Figure 14.** Variation of fundamental frequency dc-link current ripple magnitude (pu) with SM capacitance tolerances *TC* and arm inductor tolerances *TL*: (**a**) Scheme-A, and (**b**) Scheme-B.

It is worth emphasizing that the 20-cell MMC in previous studies is a good representation of the scenario with low SMs numbers per arm. In such a scenario, the loss of 10% of total SMs per arm in absolute term, namely, two SMs, is of practical significance, particularly from the following point of views: (1) Increased duties on remaining and healthy SMs (frequency of insertion and bypass of SM capacitors). (2) Increased sampling errors in the synthesis of the dc, arm, and output ac voltages. (3) Average switching frequency per device. (4) Increased likelihood of occurrence in a practical system. On the other hand, the 50-cell MMC is a relatively good representation for upper MV applications, in which the likelihood of loss of 10% of the total number of SMs per arm is much lower but remains possible with less impact on the quality of the ac and dc side waveforms and duties on SM capacitors.
