**1. Introduction**

The electrical power demand has increased in all applications, such as transportation, industry, household, and the commercial sectors [1]. We are in fact becoming more and more hungry for electric power: on one hand, this is provoked by the constant increase in the world population, and consequently the urban centers are increasing in size with more people living in cities; on the other hand, the hunger for energy, especially in developing countries always in need of new infrastructure such as hospitals, schools, and transport, comes from the middle class. Thus, the increased demand of energy should be addressed by both significantly increasing the use of renewable energy sources and improving the efficiency of energy systems [2]. Currently, the most abundant renewable energy sources are wind and solar [3,4]; for both of them, adequate conversion equipment is needed. For example, wind energy requires turbines and generators, which leads to variable frequency and variable voltage electricity. As a result, between the generator and the grid, a power conversion system is needed in order to meet the grid requirement of a fixed frequency of 50 or 60 Hz at certain standard voltage levels. Concerning solar energy, a photovoltaic (PV) cell provides a DC source at unregulated low voltage, and thus power electronics systems must be able to adjust this DC voltage level to one suitable for supplying the load [5]. In the 21st century, therefore, modern solutions based on different energy sources coming from wind, solar, energy storage and micro-turbines have been used to feed the load or different loads [6,7]. Particularly, in a stand-alone microgrid, more energy sources are connected to

**Citation:** di Benedetto, M.; Lidozzi, A.; Solero, L.; Crescimbini, F.; Grbovi´c, P.J. High-Performance 3-Phase 5-Level E-Type Multilevel–Multicell Converters for Microgrids. *Energies* **2021**, *14*, 843. https://doi.org/10.3390/en14040843

Academic Editor: Massimiliano Luna Received: 12 January 2021 Accepted: 2 February 2021 Published: 5 February 2021

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**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

petar.grbovic@uibk.ac.at

a single DC-bus to supply the load, as shown in Figure 1. The photovoltaic system and the battery system are connected to the DC-bus thanks to a DC/DC power converter [8,9], while the wind system and the micro-turbine are connected to the DC-bus through an AC/DC converter. The power flows from the DC-bus to the load thanks to the DC/AC converter connected to a power filter.

**Figure 1.** Structure of stand-alone microgrid with the integrated renewable energy source.

It is evident that the modern renewable energy system could not operate, and the microgrid could not be realized, without power electronics. In fact, power electronics converters and controllers are the most important elements in this application, and the efforts of power conversion designers consistently focuses on improving the efficiency and reducing the volumes of the conversion system [10,11]. These goals can be reached thanks to the continuous improvement of power electronics technologies and power converter topologies. Indeed, on one hand the industrial manufacturing of power components keeps introducing new high-performance modules and power semiconductors on the market [12,13]; on the other hand, newer and emerging power converter topologies are constantly proposed in literature. For example, in high power and/or high voltage applications, the limit of the power conversion system is attributed to the power semiconductors capable of withstanding limited voltage and current stresses. To overcome this problem, academia and industry are working on new solutions of power converters [14–16]. Thus, the use of multilevel configurations allows the arrangement of power conversion systems with power semiconductors that are required to withstand only a fraction of both the overall DC-bus voltage and the converter output current. This usually allows higher switching frequency *fsw* and, therefore, multilevel configurations lead to significant improvements in terms of quality of both voltage and current waveforms without giving up the benefit of high efficiency and high-power density. Furthermore, the weight and volume of the converter passive components are likely to be reduced [14–17], which is very appealing for several applications, where the overall size and weight of the electrical generating system needs to be minimized. Given the high number of benefits, more and more multilevel converter topologies are proposed in the literature [17–21]. It is understood that multilevel topology can act on the voltage stress of the power semiconductors, leaving their current ratings unchanged. To reduce the current stress flowing through the power semiconductors, more parallel cell converters can be used. Thus, the power semiconductors with low current rating can be chosen, leading to an improvement in the conduction losses. As another advantage, parallel converters enhance the current ripple, resulting in a further improvement of the waveform quality. Obviously, the multilevel converters present some disadvantages, such as the reliability and cost. In fact, the number of power semiconductors in multilevel converters increases as the number of the voltage levels increases, and, therefore, we could think that cost and reliability worsen. However, some multilevel topologies proposed in the literature have fault tolerance capability [22–24]. Additionally, even if the number of power devices increases, there is a reduction in passive devices, which leads to less use of copper and iron. These materials, actually, are more expensive than power semiconductors. Naturally, the real disadvantage of having many devices could lie in the driver circuits used for switching the devices [25]. Moreover, tuning the control algorithm could also be more complicated, given the difficulty in finding an analytical model of the multilevel converter [26,27]. Nevertheless, apart from the analytical effort required to find the control law, the continuous trend of increasing the controller performance and memory size along with the reduction in the cost has now reached a point where the increase in the number of power semiconductors is not such a disadvantage. Multilevel converters based on Neutral Point Clamped (NPC) and T-Type topologies have been proposed using Super-junction MOSFETs [17,18]. Here, the peak efficiency is estimated to be above 99%. A five-level T-Type converter able to reach an efficiency of 99.2% using only SiC technology is presented in [19]. In this paper, the confirmed power density and specific power are 1.4 kW/dm3 and 2.5 kW/kg. In [20] a three-phase T-Type converter, called Swiss Rectifier, has been designed using SiC power devices. The declared peak efficiency and power density were 99.26% and 4 kW/dm3, respectively. A hybrid Five-Level Active NPC Inverter that uses SiC and is able to achieve a peak efficiency above 98% has been proposed in [21].

One of the goals of the proposed paper is analyzing, designing, and testing the 3Φ5L E-Type MMR and the 3Φ5L E-Type Multilevel–Multicell Inverter (MMI) to obtain high, efficiency, power density and specific power by using only silicon (Si) power semiconductors. For this purpose, the operation modes of the proposed converters are clearly explained and a solution to balance the DC-bus voltages is discussed. Then, the investigation focused on the design of the proposed converters; an analytical approach to calculate the device stress is presented to select the suitable power semiconductors. Starting from this analysis, the power semiconductors have been selected and the efficiency as a function of the power has been analytically calculated for both converters. The theoretical investigation has been supported by the model of the converters created in the Matlab/Simulink and Plexim/Plecs environments. A prototype of the converters has been built and the proposed MMR and MMI are integrated on the same power board to reduce the power density. Furthermore, the control structures for both MMR and MMI to be used in microgrid applications have been implemented and verified through preliminary simulations. Finally, experimental tests have been performed in order to confirm the obtained theoretical analysis. This paper is organized as follows: the topology, the operation principle, and the voltage unbalancing issue of the 3Φ5L E-Type MMR and 3Φ5L E-Type MMI are presented in Section 2. The hardware aspect design of the proposed rectifier and inverter are illustrated in Section 3. Based on the proposed rectifier and inverter, the control strategies regarding stand-alone microgrid applications have been discussed in Section 4. Simulation results and experimental results from a laboratory prototype are shown in Sections 5 and 6, respectively. Conclusions are presented in Section 7.

#### **2. Operation Structure of 3-Phase 5-Level E-Type MMC**

#### *2.1. 3*Φ*5L E-Type MMR and MMI*

The circuit of the 3Φ5L E-Type MMR is illustrated in Figure 2. A single-phase of the rectifier has two cells: cell 1 and cell 2. This converter is based on both *I-Type* and *T-Type* topology [28–30]. In fact, each cell is composed of two I-Type legs connected to the T-Type leg. The power flows in one direction in the 3Φ5L E-Type MMR due to the presence of the diode into the T-Type cell. The two cells are connected in an interleaving manner, using an intercell transformer (ICT). The advantages of paralleling the cells using the ICT lies in the fact that the phase current is equally shared between the cells, the amplitude of the total current ripple is reduced, and the harmonic contents of the voltage at high frequency is shifted at twice the switching frequency. The 3Φ5L E-Type MMI is also composed of the I-Type and T-Type topologies like the rectifier, as illustrated in Figure 3. Each phase has two cells connected through the ICT.

**Figure 2.** Circuit of 3Φ5L E-Type Multilevel–Multicell Rectifier (MMR).

**Figure 3.** Circuit of 3Φ5L E-Type Multilevel–Multicell Inverter (MMI).

According to the modulation control scheme, both converters show five voltage levels on a single cell, while each phase has nine voltage levels, as shown in Figures 4 and 5. Thus, the line-to-line voltage shows seventeen voltage levels. A carrierbased pulse width modulation (PWM) method has been implemented, taking into account the multiple power semiconductors of the converters. The gate signals of the power devices are generated by the comparison of the modulating signals with the carriers, as shown in Figure 6. Considering the interleaving concept, a phase displacement is applied between the parallel cells in order to achieve highest quality of the output waveforms. Thus, four carrier signals, ct11, ct12, ct13 and ct14 (solid line) control the power devices in cell 1, and the other carrier signals ct21, ct22, ct23 and ct24 (dashed line) in the opposite phase control the power semiconductors in cell 2. Furthermore, as can be seen from Figure 6, two devices are controlled by a single carrier signal. The switching frequency of each power semiconductors is *fsw* while the output waveform effective switching frequency is

twice *fsw*. This phenomenon, present in the interleaved converters, is usually called the multiplicative effect of the effective switching frequency, and leads to a drastic reduction in the output filter.

**Figure 5.** Line-to-line switching voltage *ua*(*sw*) (or *uu*(*sw*)).

**Figure 6.** Modulation control scheme for power semiconductors located in a single-phase of the inverter.

## *2.2. Balancing Circuit*

The main problem of the multilevel converter based on T-Type or E-Type topologies is the unequal voltage across the DC-bus capacitors [31–33]. This problem cannot be solved in a simple way with a control algorithm due to the uncontrollable current flow through the internal nodes [28] of the capacitors. The only chance to balance the DC-bus capacitors of the 3Φ5L E-Type converters is to use an external circuit. The focus of this paper was not to study the unbalanced voltage capacitor problem. Here, two series resonant balancing circuits (SRBCs) have been used to solve the voltage unbalancing problem. Figure 7 illustrates the circuit and the implemented prototype of the SRBCs.

**Figure 7.** Series resonant balancing circuit prototype.

The SRBCs were built with four Semitop3 SK75GB066T modules (rated 60 A—600 V), 4 μH and 16 μF as resonant total inductance (*LR*1/*LR*2) and total capacitance (*CR*1/*CR*2), respectively. Furthermore, one DC-bus film capacitor and two DC-bus electrolytic capacitors were used as a DC link. The energy was transferred from the capacitor *CB*<sup>1</sup> to *CB*<sup>2</sup> and from the capacitor *CB*<sup>3</sup> to *CB*<sup>4</sup> through the capacitors *CR*<sup>1</sup> and *CR*2. The auxiliary inductors *LR*<sup>1</sup> and *LR*<sup>2</sup> were used to achieve a zero-current switching (ZCS) condition. The power semiconductors were driven with complementary control signals with a constant duty cycle at 50%; no control loops and sensors were required with the system being self-balanced. These two SRBCs were used to balance the voltage across the capacitors to ensure equal DC currents *iC*<sup>1</sup> = *iC*<sup>2</sup> = *iC*<sup>3</sup> = *iC*4.

#### **3. Hardware Design and Prototype of E-Type Topology**

The 3Φ5L E-Type MMR and MMI have been designed to maximize the efficiency, power density, and specific power, without sacrificing the quality of the voltage and current waveforms. To accomplish these tasks, different actions have been carefully carried out.

The capacitors of the DC-bus have been chosen considering the maximum peak-topeak voltage ripple Δ*VBUS* equal to 100 V and the estimated Root Mean Square (RMS) current flow through the capacitors in the case of an asymmetric load condition. The DC-bus current harmonics were compensated by the SRBCs except the 100 Hz component, which had to be compensated by the capacitors. For this reason, the DC-bus capacitors were selected according to (1), where *NS* and *NP* were the numbers of series and parallel

capacitors, and *ICBUS* was the RMS current at double fundamental frequency defined in Equation (2).

$$\mathcal{C}\_{BUS} = \frac{2\sqrt{2}N\_S N\_P}{(2\pi 100)\Delta V\_{BUS}} I\_{CBUS} \tag{1}$$

$$\left.I\_{\rm CBUS}\right|\_{100Hz} = \frac{\mathcal{U}\_0 I\_0}{\sqrt{2}V\_{\rm BUS}}\tag{2}$$

In (2), *U*<sup>0</sup> is the RMS voltage, *I*<sup>0</sup> is the RMS load current, and *VBUS* is the total voltage across DC-bus capacitors. According to (1) and (2), six parallel and four series electrolytic capacitors, each one equal to 220 μF, 220 V were chosen as DC-bus capacitor tanks.

The power semiconductors were carefully selected considering the maximum voltage and current stress that the power components are able to withstand. Figure 8 shows the maximum voltage stress across the power semiconductors of a single cell of the inverter and rectifier.

**Figure 8.** Maximum voltage stress that each cell of the E-Type Rectifier and Inverter can withstand at a steady state.

As can be seen, the switches *Sx*,21, *Sx*,22 and the diodes *Dx*,21, *Dx*,22, with *x* ∈ *{1R, 2R}* and *<sup>x</sup>* ∈ {1*I*, 2*I*}, have the maximum voltage stress equal to 3/4*VBUS* compared to the other power semiconductors. Naturally, the overvoltage related to the commutated current must be added to this blocking voltage but, as explained in [34], the overvoltage commutation only appears when the blocking voltage at a steady state is equal to <sup>1</sup> <sup>4</sup>*VBUS*. Concerning the current stress, the use of parallel cells helps to reduce the current stress of the power semiconductors. To obtain the current stress of each power semiconductors, an analytical procedure has been performed. Particularly, the average (AVG) and the root mean square (RMS) currents flowing in the power semiconductors located in the rectifier and inverter are expressed in Equation (3), where *M*0*<sup>R</sup>* is the modulation depth of the rectifier, *Iin* is the RMS phase current of the rectifier, *M*0*<sup>I</sup>* is the modulation depth of the inverter, *I*<sup>0</sup> is the RMS phase current inverter, and *aRMS,i*, *bRMS,i*, *aAVG,*i, *bAVG,i*, *aRMS,j*, *bRMS,j*, *aAVG,j*, *bAVG,j* are the coefficients related to the switches of the rectifier (i-index) and inverter (j-index). The derivation of Equation (3) requires very complex analysis, and it is beyond the scope of this discussion. A simplified discussion to obtaining the Equation (3), including the coefficients, is discussed in detail in Appendix A.

$$\begin{split} |i\_{RMS,R}(t)| &= \sqrt{\frac{\frac{I\_{in}}{24\pi}M\_{0R}}{24\pi} \left(\frac{a\_{RMS,i}}{M\_{0R}} + b\_{RMS,i}\right)}\\ |i\_{AVG,R}(t)| &= \frac{\sqrt{2I\_{in}M\_{0R}} \left(\frac{a\_{AVG,i}}{M\_{0R}} + b\_{AVG,i}\right)}{4\pi} \\ |i\_{RMS,I}(t)| &= \sqrt{\frac{I\_{on}^{2}M\_{0I}}{24\pi} \left(\frac{a\_{RMS,j}}{M\_{0I}} + b\_{RMS,j}\right)} \\ |i\_{RMS,I}(t)| &= \frac{\sqrt{2I\_{out}M\_{0I}} \left(\frac{a\_{AVG,j}}{M\_{0I}} + b\_{AVG,j}\right)}{4\pi} \end{split} \tag{3}$$

Starting from this analysis, the selected power semiconductors of the 3Φ5L E-Type Rectifier and Inverter are listed in Table 1. To improve the power density and the specific power, the 3Φ5L E-Type MMR and MMI were integrated on the same power board. The power switches of the rectifier and inverter were driven by three boards, each one controlling a single-phase of the rectifier and inverter.

**Table 1.** Power semiconductors used to build the 3Φ5L E-Type MMR and MMI with *x*∈ {1*R*, 2*R*} and *y*∈ {1*I*, 2*I*}.


The Infineon integrated circuit (IC) (part number 1EDI60I12AF) was employed as a gate driver chip. The printed circuit boards (PCBs) of the power board and the gate driver board have been optimized to reduce the current path during the commutations; in this way, the commutation inductance, i.e., the resulting inductance in the commutation circuit, has been reduced, and with it also the overvoltage commutation.

Additionally, because the high gate driver signals result from the high number of the power switches located in the 3Φ5L E-Type MMR and MMI, the interconnecting board which routes all the signals between the diver boards to the control board has been built.

Finally, the input and output filters have been designed to reduce the volume and to obtain high quality of the input currents in the rectifier side and high quality of the output voltages in the inverter side. Thus, the input and output ICTs and the input and output inductors have been built according to the analysis proposed in [30]. The complete prototype of the 3Φ5L E-Type MMR and MMI is illustrated in Figure 9, and features a power density of 8.4 kW/dm3 and a specific power of 3.24 kW/kg.

**Figure 9.** Prototype of the 3Φ5L E-Type Rectifier and Inverter including the input and output power filters, measuring 580 mm <sup>×</sup> 300 mm <sup>×</sup> 45 mm. The power density is 8.4 kW/dm3 and the specific power is 3.24 kW/kg.
