*Article* **Scalable and Configurable Electrical Interface Board for Bus System Development of Different CubeSat Platforms**

**Marloun Sejera 1,2,\*, Takashi Yamauchi 1, Necmi Cihan Orger 1, Yukihisa Otani <sup>1</sup> and Mengu Cho <sup>1</sup>**


**Abstract:** A flight-proven electrical bus system for the 1U CubeSat platform was designed in the BIRDS satellite program at the Kyushu Institute of Technology. The bus utilizes a backplane board as the mechanical and electrical interface between the subsystems and the payloads. The electrical routes on the backplane are configured by software using a complex programmable logic device (CPLD). It allows for reusability in multiple CubeSat projects while lowering costs and development time; as a result, resources can be directed toward developing the mission payloads. Lastly, it provides more time for integration and system-level verification, which are critical for a reliable and successful mission. The current trend of CubeSat launches is focused on 3U and 6U platforms due to their capability to accommodate multiple and complex payloads. Hence, a demonstration of the electrical bus system to adapt to larger platforms is necessary. This study demonstrates the configurable electrical interface board's scalability in two cases: the capability to accommodate (1) multiple missions and (2) complex payload requirements. In the first case, a 3U-size configurable backplane prototype was designed to handle 13 mission payloads. Four CPLDs were used to manage the limited number of digital interfaces between the existing bus system and the mission payloads. The measured transmission delay was up to 20 ns, which is acceptable for simple serial communications such as UART and SPI. Furthermore, the measured energy consumption of the backplane per ISS orbit was only 28 mWh. Lastly, the designed backplane was proven to be highly reliable as no bit errors were detected throughout the functionality tests. In the second case, a configurable backplane was implemented in a 6U CubeSat with complex payload requirements compared to the 1U CubeSat platform. The CubeSat was deployed in ISS orbit, and the initial on-orbit results indicated that the designed backplane supported missions without issues.

**Keywords:** CubeSat; electrical interface; scalability; bus system development

### **1. Introduction**

A CubeSat is a class of satellites with a defined size and form factor. A 1U CubeSat, for example, has dimensions of 10 × <sup>10</sup> × 11.35 cm<sup>3</sup> and a mass of up to 2 kg, as defined in the CubeSat Design Specifications from California Polytechnic State University (CalPoly) [1]. The document describes the mechanical, electrical, and operational specifications of Cube-Sats from 1U to 12U. However, it does not cover how the components in a CubeSat, i.e., both the bus and the payload, are interfaced. This lack of such a definition allows CubeSat developers the freedom to choose which interface method to use. More importantly, this aspect could cause incompatibility issues between components, and solving these issues could considerably consume time that could be used for other verification activities to ensure mission success [2]. Furthermore, CubeSat projects can be developed by multiple collaborators, and clearly defining an interface standard between developers during the initial phase could prevent project delays, compatibility issues, and increased costs while improving overall mission success.

**Citation:** Sejera, M.; Yamauchi, T.; Orger, N.C.; Otani, Y.; Cho, M. Scalable and Configurable Electrical Interface Board for Bus System Development of Different CubeSat Platforms. *Appl. Sci.* **2022**, *12*, 8964. https://doi.org/10.3390/ app12188964

Academic Editors: Filippo Graziani, Simone Battistini and Mauro Pontani

Received: 27 July 2022 Accepted: 5 September 2022 Published: 6 September 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

The first CubeSats developed used the stacking approach, where components were placed on top of each other using a connector. This interfacing method follows the PC/104 specifications [3] employed in embedded computers. The adoption of this specification to CubeSats defines the wiring harness, the printed circuit board (PCB) footprint, and the mechanical mounting of the boards, while the boards are stacked using 104-pin connectors. One of the first developers to employ the PC/104 specification in CubeSat applications is Pumpkin, Inc., who introduced the CubeSat Kit Bus (CSKB) [4]. The CSKB has become the de facto standard in CubeSat design and has been adopted by many commercial CubeSat developers.

However, using the PC/104 specification in CubeSats has several issues. According to a survey in [5], 51% of 36 respondents agreed that the size of the connector is too big. Ref. [6] confirmed that the connector occupies up to 20% of the PCB space. This limits the board designers in placing components on the board, resulting in low PCB utilization. The stacking height of the connector is also considerable, making the spacing between boards particularly wide. Another issue is that the number of pins interconnecting the board is often not utilized to its fullest extent. This may increase the risk of human error when assigning pins and mapping during the development and integration phases. Even though there could be many unused pins, a harness is extensively used in stacked systems. Lastly, top boards need to be disassembled if there is a need to take out a middle board, especially during troubleshooting. This leads to additional development and integration time.

There have been multiple efforts to resolve issues in using PC/104, specifically in terms of its connector. ISIS, for example, started to consider alternatives to CSKB connectors [7]. The company introduced CSKB Lite, two 28-pin connectors with just enough pins for full utilization. It is also backward-compatible with the standard CSKB connector. In the case of Nagoya University's NUcube satellites, where high-density interfaces are necessary [8], 144-pin connectors were used but with only a 9 mm stack-up height to reduce the volume occupied by the PCBs and a pitch of 0.50 mm to allow more space for components on the boards. This, in turn, made the connector incompatible with CSKB. Lastly, Korea Space University's KAUSAT-5 CubeSat used a flexible flat cable (FFC) connector instead of PC/104 to save volume and mass [6]. Despite these efforts, issues such as extensive use of harnesses and difficulty when assembling and disassembling were not addressed.

Another interface method uses a dedicated PCB called a backplane board that provides mechanical and electrical connections between the bus and the payloads. UWE-3, a 1U CubeSat from the University of Würzburg in Germany, first carried out the use of a backplane and became the reference for UNISEC Europe's CubeSat specification interface document (CSID) interface [9,10]. The BIRDS satellite program at the Kyushu Institute of Technology (Kyutech) in Japan also adopted the backplane board approach to its 1U CubeSats as an interface to the bus and the payload [11]. The bus and payload boards have 50-pin male connectors connected to the 50-pin female connectors of the backplane board. These connectors have a smaller form factor, which provides more space for electronic components on the bus and payload boards. The spacing between boards can also be adjusted by moving the female connectors on the backplane board. This provides efficient utilization of the limited volume of a CubeSat. In addition, power lines, as well as analog and digital signals, are routed through the PCB. This greatly reduces the use of the wiring harness, which is considered one of the fundamental reasons for satellite failure. Lastly, the backplane approach makes satellite assembly and disassembly significantly more straightforward. Therefore, it allows integration and troubleshooting to be performed in a shorter time.

A survey was conducted to determine the interface method used in CubeSats launched from 2003 to 2019 [12]. Of the 397 CubeSats surveyed, only 170 CubeSats had an identified interface since the sources of information (e.g., web pages, papers, conference papers, etc.) did not provide the details. A total of 137 CubeSats used the PC/104 interface, which is about 80% of the total identified CubeSats. However, the use of backplanes on CubeSats started gaining favor in 2013, with 24 satellites launched from then until 2019. For example, CalPoly's Aerospace Engineering Department developed its own kit as an educational platform for satellite development known as CalPoly CubeSat Kit MK1. Its internal configuration uses a backplane that can connect five boards through its 48-pin female connectors [13]. However, this backplane's design lacks flexibility because of changes in interface definition from one CubeSat project to the other. These changes lead to the complete reproduction of the backplane, adding cost and development time [14].

The third generation of the BIRDS project introduced a standard software-configurable backplane board as one of its technology demonstrations [14]. A complex programmable logic device (CPLD) was placed on the backplane, and digital signals between the bus and the payload were routed through the CPLD. By reprogramming the chip, rerouting can be performed without changes in the hardware design. This makes the backplane flexible and reusable by future satellites with minimal modification while saving time and cost. The configurable backplane was proven to work in space during satellite deployment at the International Space Station (ISS) in June 2019 until it was deorbited in October 2021. The software-configurable backplane has become an integral part of the BIRDS 1U bus architecture. The standard bus, however, has limited digital interfaces that constrain the number of payloads a CubeSat can carry out.

The demand for launching CubeSats is on a continuous uptrend, and most CubeSats being launched are 3U and 6U platforms mainly because they can accommodate multiple and complex payloads. Implementing a configurable interface board on larger CubeSat platforms could provide benefits similar to those in the 1U platform, such as a reduction in development throughput and cost.

This paper aims to demonstrate how the configurable interface board can be scaled up and adapted to different CubeSat sizes using the BIRDS 1U standard bus system. The novelty of the present work is described as a confirmation of the configurable interface board's flexibility in absorbing challenges encountered when scaling up to larger CubeSat platforms. Since implementing a configurable backplane to larger platforms such as 3U or 6U CubeSats has not been achieved before, several challenges such as managing communication between the existing standard bus system and multiple mission payloads, as well as meeting the mission requirements of complex payloads, are extensively covered in this study. In addition, the contribution of this paper is that it presents a 3U configurable backplane designed to manage several missions on the limited number of available electrical interfaces of a standard bus. The design concept could benefit satellite developers who provide hosted payload services where bus resources are maximized to accommodate as many payloads as possible. This paper also demonstrates the modifications in a bus system necessary to scale up and handle complex missions in a W6U CubeSat. The CubeSat was deployed from the ISS in March 2022, and it has been successfully supporting the execution of the missions.

This paper is composed of five sections. Section 2 discusses the standard 1U bus system. It also discusses two backplane designs in different CubeSat platforms—a 3U backplane prototype for multiple payloads and a backplane for a W6U CubeSat with complex mission requirements. Section 3 discusses the tests conducted and the results of the two backplane designs. Lastly, Sections 4 and 5 present the Discussion and Conclusion.

### **2. BIRDS 1U Standard Bus System**

The BIRDS Program of Kyutech is an educational, capacity-building satellite program that aims to empower participants from non-space-faring countries to lead or start satellite projects in their home countries [15]. In the program, the graduate students from the participating countries gain hands-on experience on how to design, develop, test, and operate CubeSats. A total of thirteen countries have participated in the program, nine of which built the first satellite in their countries. The program has deployed a total of seventeen satellites in its five generations of constellations from 2015 to 2022—five in BIRDS-1 and three each in BIRD-2, BIRDS-3, BIRDS-4, and BIRDS-5. A total of sixteen satellites are 1U CubeSats, while one of the three satellites in BIRDS-5 is a 2U CubeSat.

Kyutech has made the BIRDS 1U bus system available as open-source information [16,17]. CubeSat developers can gain full access to all information necessary to build a 1U satellite, and these include technical drawings, source code, PCB design, assembly and testing procedures, test reports, and interface control documents (ICDs). This effort allows more people to develop their satellites in an easier, faster, and cheaper way. At present, there are two universities, two high school projects, and a company in Japan that are benefiting from this initiative. In addition, BIRDS members from Malaysia, Mongolia, the Philippines, and Sri Lanka are making satellites in their countries using the BIRDS 1U bus.

Figure 1 shows the internal boards of a 1U BIRDS satellite. The components are described below.

**Figure 1.** BIRDS 1U satellite internal boards.


employs Gaussian minimum-shift keying (GMSK) modulation with a baud rate of 4800 bps in both directions and an AX.25 protocol for data format. The frequency of operation is in the ultra-high frequency (UHF) amateur band.


**Figure 2.** Backplane board (top side).

The antenna panel and four solar panels are connected to the backplane via 12-pin male connectors with a 2.54 mm pitch (SP1 to SP5). The fifth solar panel is connected directly to the FAB. The connectors in the solar panels route the generated power and temperature readings to the FAB, and the connector on the antenna panel provides an unregulated power line to the antenna deployment system. In addition, the backplane also includes two-pin male connectors (SW1 to SW4) for the deployment switches connected to the satellite structure.

The space between the COM (C103) and RAB (C104) connectors is allocated for the mission payload. The maximum board thickness of the payload that can be accommodated is 22.35 mm. Up to two mission boards (C104, C105) can be placed in the given space. It is possible to customize the backplane board to reduce the number of 50-pin female connectors to one and shift its position.

A satellite ICD contains the overall information on the mechanical and electrical interfaces between the components. The connector pin assignment is an example of an electrical interface specification found in this document, and the satellite developer can use the pin assignment to determine how components are connected. Table 1 shows the pin assignment of the 50-pin connector on the OBC/EPS board. In addition, it specifies the name of each pin, the connected microcontroller, the pin route, the rated voltage and current, and the protocol and baud rate for digital pins. The pins are named according to their function or connection. For example, PROG\_GIO\_1 denotes the first general I/O pin for programming. Another example is OBC-COM\_1, which denotes the first pin connecting the OBC/EPS board and COM board. Pins 9–12, 21, 22, 27, 28, 37, 38, and 42 are linked to the main PIC and routed to the mission board. These 11 pins serve as digital interfaces for the bus and the payload, whereas pins 31–34 are serial peripheral interface (SPI) connections to the flash memory (FM) that the main PIC and mission payload share.

**Table 1.** OBC/EPS board pin assignment.


Figure 3 shows the bottom side of the backplane, where all active devices are placed. This is to avoid interference with the components at the top. One of the active components is a CPLD that can be programmed to perform specific logical functions. The CPLD is a lattice semiconductor ispMACH LC4256ZE, an ultralow power device that uses 1.8 V LVCMOS (low-voltage CMOS) technology with a standby current of 13 uA. A voltage regulator that uses 3.3 V input from one of the power lines supplies 1.8 V to the integrated circuit. In addition, a joint test action group (JTAG) connection is used to program the chip.

**Figure 3.** Backplane board (**bottom** side).

Table 2 represents the list of CubeSats with their CPLD families and corresponding functionalities. The CPLDs are most commonly implemented within the telemetry command and data-handling subsystem. On the other hand, the CPLD in BIRDS-3 was implemented on the backplane board as an interface between the PIC and the mission payloads. The table also shows the propagation delay and internal voltage supply of the CPLD according to the datasheet. The propagation delay varies depending on the chip package, and the data are based on the 144-pin quad-flat package (QFP) chip if not indicated by the resources. The ispMach4000 ZE CPLD was chosen for its optimal performance in terms of propagation delay and power consumption in addition to ease of availability, implementation, and cost.

Figure 4 illustrates how data communication is performed between the bus system and mission boards. The 11 digital interfaces from the bus are routed to the mission boards through the CPLD. Depending on the implementation, these interfaces can be UART, SPI, digital input/output (DIO), or their combination. There is also an SPI line for transferring mission data to the shared FM in the OBC/EPS board, and the CPLD manages these digital interfaces to allow mission payload communication to the bus system. In addition, Figure 5 shows how a CPLD on the backplane operates where the CPLD is programmed as a voltage follower, with the output pin logic levels matching the paired input pin. Digital interfaces can be rerouted without requiring hardware changes by reprogramming the CPLD. This

saves both cost and time when redesigning the board. This also makes the backplane significantly more adaptable, especially during the initial development phase when routing changes are expected.


**Table 2.** Comparison of CPLD family used in CubeSats.

**Figure 4.** Block diagram of data handling between the bus and the payload.

**Figure 5.** Digital line routing using a CPLD.

Using this standard bus system, the configurable interface board can be scaled up and adapted to different CubeSat sizes. As a result, resources can be more focused on developing the mission payload and instruments. Lastly, it allows more time for integration and system-level verification, which are critical for a reliable and successful mission [22,23]. Since implementing a configurable backplane to larger platforms has not been achieved before, challenges such as managing communication between the existing standard bus system and multiple mission payloads, as well as meeting the mission requirements of complex payloads, may occur. To prove that the standard bus system can be scaled and address the challenges encountered when scaling up to larger CubeSat platforms, two cases have been studied. In Section 2.1, a backplane prototype was developed to handle several missions based on the limited number of available electrical interfaces of a standard bus. In Section 2.2, an actual implementation of a backplane that can handle missions with complex requirements was demonstrated.

### *2.1. 3U-Size Configurable Backplane*

The BIRDS bus system is not only intended for 1U CubeSats but is designed to scale up to a 3U platform with minor modifications [24]. One modification is in the design of the backplane, where a larger CubeSat provides more space for mission boards than in a 1U. A 3U configurable backplane prototype was developed, as shown in Figure 6. The backplane is a six-layer PCB and measures 320 mm × 90 mm × 1.6 mm, and all internal boards and deployment switch connectors are placed on the top side of the board, which is the same as the 1U standard bus. In addition, the bus system components (FAB, OBC/EPS, COM, and RAB) and their arrangement were kept unchanged. Lastly, the space between the COM board and the RAB was allocated for the 13 mission boards. Since the 3U platform would require more power for the mission payloads, the battery capacity would also increase, leading to a bigger battery box than in the 1U. Therefore, the space for the battery box, which is between the FAB and OBC/EPS board, is wider than in the 1U backplane.

A standard pin assignment for all mission boards is described in detail in Table 3. While 12 power pins are pre-assigned based on the power distribution from the OBC/EPS board, the developers have the flexibility to assign the remaining pins to CPLD, miscellaneous, and umbilical connections. In addition, the 20 pins assigned to CPLD connections are configurable even after the backplane is fabricated. This number of pins allows the payload developers to assign any kind of serial digital interface to link over the bus.

**Table 3.** Standard 50-pin assignment for mission boards.


**Figure 6.** The 3U configurable backplane (**top** and **bottom** sides).

Four CPLDs are laid on the bottom side of the backplane, while the battery is placed on the other side. Cumulatively, the CPLDs provide the interface between the bus system and mission payloads. A voltage regulator supplies 1.8 V to all CPLDs, and each device has its JTAG pins for programming. Figure 7 shows the logical connections between the bus and the mission payloads. The SPI (from the shared FM) and 11 digital interfaces (from the main PIC) in the bus system are directly connected to CPLD1. The CPLDs are cascaded to each other through the 15 I/O pins. These are later configured to correspond to the bus system SPI and 11 digital interfaces. The remaining I/O pins of the CPLD are distributed to the mission (MSN) boards. CPLD1 to CPLD3 manage three mission boards, while CPLD4 manages four. To manage the bus system digital interfaces, the CPLDs are programmed to function as four-to-one multiplexers with four select (SEL) lines.

**Figure 7.** Logical connection of bus system and payload through CPLDs.

Table 4 shows the truth table of how the CPLDs function. A total of 4 of the 11 digital interfaces (SEL0 to SEL3) in the bus are used as select pins of the multiplexer function of the CPLDs. A specific logic state of the select pins allows a mission payload to access the seven remaining digital interfaces and the SPI in the bus system. For example, if the select pin logic values are 0001, CPLD1 allows MSN1 to access the bus system. Conversely, if the select pin logic values are 0110, CPLD1 routes all 15 digital lines to CPLD2. CPLD2 then routes the digital lines to MSN6. There are 13 combinations of select pin logic states corresponding to the 13 mission boards.


**Table 4.** The 3U backplane truth table.

Verifications were conducted on the backplane to test the performance. First, a functional test was performed to check whether the multiplexing function worked. Signal propagation delay and overall power consumption were also measured. Lastly, a bit error check was performed. The results and discussions of the test are given in Section 3.1.

### *2.2. KITSUNE W6U CubeSat*

The previous section explained how a configurable backplane is designed to handle multiple payloads with relatively basic requirements that are related to power and data communication to the bus system. As a result, the bus system is not modified for integration. In addition, the payload operation does not require control of the satellite attitude. Therefore, the attitude determination and control subsystem (ADCS) was not included in the bus system. To implement payloads with advanced requirements, this section describes how a configurable backplane was modified, including additional subsystems.

KITSUNE satellite is a W6U CubeSat platform designed and developed in Japan as a collaboration project by the Kyushu Institute of Technology (Kitakyushu, Japan), Harada Seiki Co., Ltd. (Hamamatsu, Japan), and Addnics Corp. (Tokyo, Japan) [25]. The satellite project kicked off in September 2019, and KITSUNE was delivered to the Japan Aerospace Exploration Agency (JAXA) in November 2021. The satellite was deployed from the ISS on 24 March 2022 and is now in operation.

Figure 8 shows the 3D model of the W6U CubeSat. The CubeSat is divided into three sections: a 3U section for the camera payload that can capture 5 m class resolution images, a 1U section with technology demonstration and scientific experiment missions, and a 2U section for the main bus system. The 1U section is known as SPATIUM-II. It is basically a 1U satellite with its own bus that manages the missions. In addition to drawing power from the main bus, SPATIUM-II can work independently. A configurable backplane, developed to serve as the interface to all three sections, was placed in the middle of the satellite.

**Figure 8.** A 3D model of the W6U CubeSat bus system rack assembly (**left**) and the integrated rack assembly in the structure (**right**).

The main bus system was modified according to the mission requirement. The modifications were as follows:


sensors, and three electromagnets [27]. An adapter board was used to connect the module to the backplane.

On the SPATIUM-II side, the components are as follows:


The backplane board is a six-layer PCB with dimensions of 250.5 mm × 90 mm × 1.6 mm, as shown in Figure 9. The top side has connectors to the internal components of the main bus and the SPATIUM-II. All are 50-pin male connectors with a 2 mm pitch. The OBC/EPS, EPS1, and ADB in the main bus have additional 4-pin female connectors on each end of the 50-pin connector, which are allocated for the additional power lines, system ground, and battery power. The additional pins make the total pin count 58 for the three boards.

The two biggest solar panels (+X and −X) are connected to the backplane via 13-pin male connectors (A), while the −Y and +Z panels are connected via a 26-pin male connector (B). All connectors have a 2.54 mm pitch between pins. The fourth solar panel (+Y) is connected directly to the EPS1 board. In addition to routing the generated power and temperature readings to the EPS1 board, the connectors connect to the sun sensors and antenna deployment circuits. Additionally, B has a route to the two GPS modules. Lastly, C denotes two-pin male connectors for the deployment switches connected to the satellite structure.

At the bottom side of the backplane, there is a two-pin connector (D) that connects the sun sensor in the -Z panel and a 30-pin connector (E) that connects the camera controller to the backplane. There are two CPLDs for the main bus and SPATIUM-II working independently. A voltage regulator in the main bus converts 3.3 V from the power line to 1.8 V. There are two voltage regulators on the SPATIUM-II side. The first regulator converts 5 V from the power line to 3.3 V. Then, the second regulator converts 3.3 V to 1.8 V. The CPLD uses 3.3 V as the output supply voltage, whereas 1.8 V is the LVCMOS supply voltage.

Both CPLDs in the KITSUNE satellite function as voltage followers. The available interfaces on the bus are enough for the payloads to use. Thus, the multiplexing function is not necessary. The main bus CPLD has 43% utilization, while the SPATIUM-II CPLD has 35% utilization. This means that, out of the 96 I/O pins in a CPLD, the main bus and SPATIUM-II utilized 42 and 34 pins, respectively. These digital connections are combinations of DIO, SPI, and UART interfaces. Ground verification and on-orbit results are discussed in Section 3.2.

**Figure 9.** KITSUNE configurable backplane (**top** and **bottom** sides).

### **3. Tests and Results**

This section discusses the tests that were conducted and the results. The first subsection covers the 3U backplane. The second subsection covers the KITSUNE backplane ground tests and on-orbit results.

### *3.1. 3U Backplane Verification*

The four CPLDs in the backplane served as multiplexers, allowing the 13 mission boards to access the bus system's digital interfaces. Each CPLD's code was generated using very high-speed integrated circuit description language (VHDL). Lattice ispLEVER Classic was the design environment tool used to complete device design, including concept, synthesis, and simulation, as well as to generate the device joint electron device engineering council (JEDEC) programming file. Lastly, the JEDEC file was loaded into Lattice Diamond Programmer to program the CPLD via its JTAG pins.

The backplane board's functionality was validated by comparing the input and output signals of the OBC/EPS and mission board interfaces. To pass the functionality test, the two signal waveforms must be identical. The combination of logic levels on the four select pins determined which mission board had access to the bus interfaces. For example, in Figure 10, the select pins (9–12) were set to 0001. This combination allows Mission 1 access to the bus. The Digilent Digital Discovery instrument was used in the test as both a pattern generator and a logic analyzer. The instrument generated a 1 MHz clock as input to the OBC/EPS board, and the output signal from Mission 1 was compared to the input clock using the logic analyzer function. According to the waveforms, the output signal followed the logic values of the input signal. The same test was run on each of the 13 mission boards, and no differences were found.

**Figure 10.** Functional test setup.

A bit error test was also performed to further validate the functionality of the backplane. For this test, a data stream was sent to the OBC/EPS digital interface and received by a mission through a CPLD. The data received from the mission were then compared to the data transmitted to check for possible bit differences. As illustrated in Figure 11, the Raspberry Pi module transmitted a bit array every 300 ms, and it reported the number of bit errors when it detected differences between transmitted and received data. This method was repeated for three different baud rates, such as 1 Mbps, 2 Mbps, and 4 Mbps, on each

mission board. While all mission boards had no bit differences recorded, the findings demonstrated the reliability and integrity of the backplane. One important note from this test is that the time difference between the transmission and reception of the data stream does not represent the transmission delay, which is explained next.

**Figure 11.** Bit error check test setup.

The transmission delay, defined as the time it takes for the data packet to arrive at the mission board, is another validated parameter. A significant delay may result in errors in the received data. Figure 12 shows the input and output signals as observed in the oscilloscope. The right photo shows that the two signals were identical. The waveforms were zoomed in for accurate delay measurements. All mission boards had their measurements taken, and Table 5 summarizes the measured transmission delay. The measured values were grouped based on the number of CPLDs through which the signal passed. In addition, the delay was measured twice for each mission board using different signal input sources—a Digilent Analog Discovery pattern generator (Test 1) and a function generator (Test 2). According to the results, the transmission delay of a single CPLD was approximately 5.0 ns. When a signal was transmitted through all four CPLDs, the transmission delay was measured as approximately 20.0 ns. Lastly, it is concluded that the measured transmission delay could not produce bit errors in data arrays.

Lastly, the power consumption of the backplane board was investigated since the available power for a small satellite platform such as CubeSats with limited resources determines survivability in orbit as well as the ability to support multiple payloads. The current consumption was measured at the 3.3 V input to the voltage regulator under two conditions as idle mode and active CPLDs. When all four CPLDs were active, the measured current increased from 4.3 mA to 5.6 mA. As a result, the maximum power consumption was determined as approximately 18.5 mW. This result confirmed two important points. First, the power drawn by the backplane would have negligible impact on the overall power consumption of a satellite. For instance, the backplane would only need 28.0 mWh of

energy per cycle in ISS orbit. Second, the four CPLDs consumed significantly low power compared to the voltage regulator. According to datasheets, the voltage regulator quiescent current was 4.0 mA, whereas the CPLD quiescent current was only 13 uA. Therefore, if it is necessary to reduce the power consumption of the backplane even further, the focus should be on the voltage regulator rather than the CPLD.

**Figure 12.** Input and output signals on a CPLD.


**Table 5.** Summary of the measured transmission delay.

### *3.2. KITSUNE Backplane Verification*

During the satellite's development, board- and system-level verifications were performed. In addition, satellite on-orbit data were available. The subsections that follow discuss both ground and on-orbit results.

### 3.2.1. Ground Tests

The main bus, as well as the SPATIUM-II CPLDs in the backplane, served as voltage followers. The input and output signals were compared during the board-level verification. The same test method as was used on the 3U backplane prototype was used. Table 6 lists the digital interfaces that were routed to the CPLD. The main bus CPLD routed four pairs of UART, two sets of SPI, and five DIO lines. The SPATIUM-II CPLD routed three pairs of UART, one SPI, and seven DIO lines. The data confirmed that the CPLD could route serial interfaces such as UART and SPI.

**Table 6.** Summary of digital interfaces routed through CPLD.


A functional test to check for bit errors was performed in the KITSUNE backplane, which is similar to the 3U backplane prototype. In the test, the Raspberry Pi module transmitted a data stream to the OBC/EPS every 300 ms, and the device then compared the signal received from the ADCS adapter board. When a difference between the two datasets was detected, the Raspberry Pi module displayed the number of bit errors. The test was conducted at temperatures ranging from −10 ◦C to +70 ◦C in a vacuum chamber. There was no recorded bit error during the entire 12 h test.

Two backplane-related failures were observed during system integration. During the engineering model (EM) development, a line connecting an umbilical in the ADB to the EPS1 was accidentally routed through the main bus CPLD. It was found that the line was used to monitor the battery voltage. The CPLD was severely damaged due to the error, so the ICD was thoroughly reviewed before finalizing the design to prevent the incident from reoccurring. Another recorded failure was in one of the main bus SPI interfaces. The ADCS adapter board's microcontroller could not obtain data from the ADB's magnetometer placed on the ADB, and it was found that the memory input slave output (MISO) line's signal direction was incorrect. This issue was quickly resolved by updating the VHDL code and reprogramming the CPLD.

The operation and performance of the flight model (FM) satellite were tested in various space environment conditions to demonstrate that the satellite could operate properly in low Earth orbit. A summary of the thermal vacuum and vibration tests is shown in Table 7.

**Table 7.** Space environment test parameters.


The telemetry reading from the thermal vacuum test (TVT) in Figure 13 shows that the main bus CPLD temperature was about 2 ◦C higher than that of the SPATIUM-II CPLD. This is because the main bus CPLD was placed right below the battery, which is a heat source, for the entire test duration. The TVT ran for two cycles, and the recorded minimum and maximum CPLD temperatures were −3 ◦C and +50 ◦C. There was no recorded anomaly in the performance of the backplane for the entire 87 h duration.

**Figure 13.** TVT CPLD temperature profile.

### 3.2.2. On-Orbit Results

Since the deployment of KITSUNE in March 2022, data communications between components in the main bus have been confirmed. For example, a ground command to activate the ADCS and set a specific ADCS mode was sent to the satellite. When the command was received, the main PIC sent a trigger through a DIO interface to activate the overcurrent protection (OCP) circuit that powered up the ADCS PIC. The main PIC then used UART lines to communicate with the ADCS PIC. The satellite log confirmed this set of actions. When a ground command to download ADCS telemetry data was sent to the satellite, the data stored in the ADCS FM were transferred to the bus system's shared FM. The data from the shared FM were then accessed by the COM PIC (via SPI) and downloaded to the ground. The downloaded satellite log and ADCS telemetry data confirmed that the routes between the bus and the ADCS were operational. DIO, UART, and SPI interfaces were connected to the CPLD. As a result, the CPLD was carrying out its function. Table 8 summarizes the on-orbit data communications via the main bus CPLD; the circles (-) in the last column indicate that all 21 digital lines were verified to be working.

**Table 8.** Summary of on-orbit data communications in the main bus through CPLD.


The same verification was performed in the SPATIUM-II section. For example, a ground command to activate the LoRa payload was sent to the satellite. When the command was received, the main PIC sent a trigger through a DIO interface to activate the overcurrent protection (OCP) circuit that powered up the LoRa MCU. The main PIC then used UART lines to communicate with the LoRa MCU. The data from the LoRa payload were directly stored in the bus system's shared flash memory. The data from the shared flash memory were then accessed by the COM PIC (via SPI) and downloaded to the ground. The downloaded satellite log and LoRa data confirmed that the routes between the bus and the LoRa payload were operational. DIO, UART, and SPI interfaces were connected to the CPLD. As a result, the CPLD was carrying out its function. Table 9 summarizes the on-orbit data communications via the main bus CPLD. The circles in the last column indicate that all 15 digital lines were verified to be working.

**Table 9.** Summary of on-orbit data communications in the SPATIUM-II bus through CPLD.


Figure 14 shows that the on-orbit power consumption of the main bus and the SPATIUM-II was comparable to the ground data. The average power consumption per orbit of SPATIUM-II was 65 mW, while that of the main bus was 16 mW. The number of voltage regulators explains the difference in power consumption between the main bus and SPATIUM-II. The main bus has a 1.8 V regulator, whereas SPATIUM-II has 3.3 V and 1.8 V regulators. We can recall that CPLD uses 1.8 V as the supply for its LVCMOS and 3.3 V as the supply for the output logic voltage. Since SPATIUM-II does not have a 3.3 V power line, it uses the 5 V power line and first converts it to 3.3 V, then 1.8 V. The 1.8 V and 3.3 V regulators have standby currents of 4 mA and 8 mA, respectively.

**Figure 14.** Ground data vs. on-orbit data power consumption for 2U main bus (**left**) and SPATIUM-II (**right**).

In Figure 15, four temperature profiles of the CPLDs per one orbit in different Sun beta angles were plotted. All graphs show that the main bus CPLD (CPLD1) temperature was at least 3 ◦C higher than that of the SPATIUM-II CPLD. This observation was the same as the TVT result, where the temperature difference was attributed to the main bus CPLD being placed close to the battery. The direct relation of the Sun beta angle to the device temperature was also evident in all four graphs.

**Figure 15.** On-orbit CPLD temperature profile at different Sun beta angles.

### *3.3. Summary of Tests and Results*

From the two cases above, the configurability of the backplane was demonstrated, and the following parameters were confirmed:


### **4. Discussions**

The present paper studied the scalability of configurable electrical interfaces for two cases. In the first case, a 3U-size configurable backplane prototype was designed to support 13 mission payloads. The backplane contained four CPLDs that served as multiplexers, allowing the bus system to control all payloads with a limited number of digital interfaces. Several tests were conducted to verify its functionality and performance. The results showed that the backplane would only consume 28 mWh of energy per cycle in ISS orbit. This is considerably low and does not affect the overall power consumption of a CubeSat. A total transmission delay of up to 20 ns was measured, which is acceptable for serial communications such as UART and SPI. The short transmission delay also ensured data integrity after it was transmitted through the CPLDs. This was validated further in the bit error check, where the transmitted signal (of up to 4 Mbps) was compared to the received signal, and no bit errors were detected throughout the test.

In the second case, a configurable backplane was used in a W6U satellite that carried out complex missions. The electrical bus system was modified as needed to meet the mission requirements. Additional power lines, integration of commercial ADCS and high-speed transceivers, and an autonomous bus system for the 1U SPATIUM-II section were among the modifications. According to the on-orbit results, no anomalies were detected on any of the 21 digital connections in the main bus or on any of the 17 digital connections in SPATIUM-II, which passed through the CPLDs. Furthermore, the power consumption of the satellite's main bus and SPATIUM-II sections in orbit was comparable to the ground results.

The advantage of this study is that the scalable standard bus allows more time for integration and system-level verification, which is critical for a reliable and successful mission. The design concept could also benefit satellite developers who provide hosted payload services where bus resources are maximized to accommodate as many payloads as possible. UART and SPI communications were extensively used in the study since the bus system's command and data handling are based on these protocols. However, other protocols have not been supported by the configurable backplane. According to Cho et al. [2], other protocols, such as I2C, CAN, USB, and Ethernet, can be used and are

expected to be used by CubeSat developers and vendors. A programmable backplane that supports these protocols should be developed in future work.

Turmenjargal et al. [14] recommended that the backplane is reconfigurable after the satellite has been fully assembled or even after the satellite has been launched into orbit. The former is easily implemented by inserting the JTAG pins into the umbilical. The 3U backplane prototype partially meets the latter recommendation. The preconfigured multiplexing function of the CPLDs in the backplane allows the selected payload(s) access to the bus system by sending ground commands to the satellite. Full on-orbit reconfiguration of the backplane CPLD as a contingency is still under investigation.

Kim et al. [24] stated that the flexibility of the BIRDS 1U electrical bus system is one of its key features. The BIRDS bus system was designed to be compatible with up to 3U platforms, with minimum modifications. The BIRDS bus command and data-handling architecture were retained in the 3U backplane prototype and the KITSUNE backplane. UART and SPI are the interfaces between the bus system and the payload. However, other protocols may be required by mission payloads. A bridge circuit capable of translating different protocols between the bus and payload is needed to keep the existing architecture. The bridge circuit can be implemented in the configurable backplane.

### **5. Conclusions**

A backplane board provides an electrical interface among CubeSat components. It has additional advantages, such as ease of assembly/disassembly and fewer harnesses than a de facto standard PC/104 style interface. To confer more flexibility to the interface, a software-configurable backplane was developed. The backplane with an ispMACH LC4256ZE CPLD was demonstrated onboard a 1U CubeSat for more than 2 years in orbit. Through a CPLD, digital interfaces can be rerouted without requiring hardware changes by reprogramming the CPLD. This saves both money and time when redesigning the board.

The designed configurable interface board was verified to be scalable and adaptable to different CubeSat sizes while absorbing the challenges in the process. While a hardwired backplane is applied to a specific satellite, the scalable standard bus in this study exhibited its reusability in multiple satellite projects. Hence, it has the advantage of providing additional time for system-level integration and verification, which are essential for a reliable and successful mission. The design concept could also be advantageous to satellite manufacturers that offer hosted payload services, where bus resources are utilized to support many payloads.

Several future studies have been identified to fully realize the configurable backplane's scalability. The first is to verify that it can support communication protocols other than UART and SPI. Protocols such as I2C, CAN, and Ethernet are currently being used and are desired to be utilized in future projects by CubeSat developers and vendors. Secondly, a bridge circuit that translates different protocols can be incorporated into the configurable backplane. The bridge circuit will allow the use of the BIRDS electrical bus architecture on missions that require protocols other than UART and SPI. Lastly, on-orbit reconfiguration of the CPLD as a contingency could be explored.

**Author Contributions:** Conceptualization, M.S.; methodology, M.S.; software, M.S. and Y.O.; validation, M.S., Y.O., and N.C.O.; formal analysis, M.S.; investigation, M.S. and N.C.O.; resources, M.C.; data curation, M.S.; writing—original draft preparation, M.S.; writing—review and editing, N.C.O., T.Y., Y.O., and M.C.; visualization, M.S. and N.C.O.; supervision, M.C.; project administration, M.C.; funding acquisition, M.C. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was partially funded by JSPS Core-to-Core Program B: Asia–Africa Science Platforms (JPJSC2020005) and the "Acquisition and dissemination promotion project consignment fee for international standards related to energy conservation" by the Ministry of Economy, Trade and Industry, Japan.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** Not applicable.

**Acknowledgments:** The authors would like to express gratitude to the KITSUNE team members, particularly Jose Rodrigo Cordova Alarcon, Victor Hugo Schulz, Pooja Lepcha, Tharindu Lakmal Dayarathna Malmadayalage, Abhas Maskey, Adolfo Javier Jara Cespedes, Anibal Antonio Mendoza Ruiz, Cosmas Kiruki, Daisuke Nakayama, Dmytro Faizullin, Dulani Chamika Withanage, Ei Phyu Phyu, Eyoas Ergetu Areda, Fatima Gabriela Duran Dominguez, Hari Ram Shrestha, Hoda Awny A. A. Elmegharbel, Ibukun Oluwatobi Adebolu, Kateryna Aheiev, Kentaro Kitamura, Makiko Kishimoto, Mariko Teramoto, Mark Angelo Cabrera Purio, Masui Hirokazu, Mazaru Ariel Manabe Safi, Muhammad Hasif Bin Azami, Ofosu Joseph Ampadu, Sangkyun Kim, Takashi Oshiro, Victor Mukungunugwa, Yuma Nozaki, and Yuta Kakimoto. Their contributions to the development and operation of the satellite are highly appreciated.

**Conflicts of Interest:** The authors declare no conflict of interest.

### **References**


## *Article* **Development of Innovative CubeSat Platform for Mass Production**

**Eyoas Ergetu Areda \*, Jose Rodrigo Cordova-Alarcon, Hirokazu Masui and Mengu Cho**

Department of Electrical and Space System Engineering, Kyushu Institute of Technology, Kitakyushu 804-8550, Japan

**\*** Correspondence: areda.eyoas-ergetu811@mail.kyutech.jp

**Featured Application: The presented innovative design concept significantly impacts the development of nanosatellites such as CubeSats, particularly for mass production missions that demand high efficiency and fast delivery.**

**Abstract:** With the recent increase in CubeSats' ability to undertake complex and advanced missions, they are being considered for missions such as constellations, which demand high development efficiency. From a satellite interface perspective, productivity can be maximized by implementing a flexible modular structural platform that promotes easy reconfigurability during the integration and testing phase. Thus, the structural design of a CubeSat plays a crucial role in facilitating the satellite integration process. In most cases, the mechanical interface implemented between the primary load-supporting structure and internal satellite subassemblies affects the speed and efficiency of satellite integration by adding or reducing complexity. Most CubeSat structural designs use stacking techniques to mount PCBs onto the primary structure using stacking rods/screws. As a result, the internal subsystems are interconnected. This conventional interface method is observed to increase the number of structural parts, while increasing complexity during integration. In this study, flexible 3U and 1U CubeSat platforms are developed, based on the slot concept. This innovative mounting design provides a simple method of mounting PCBs into the slots. The concept is evaluated and verified for its feasibility for mass production applications. Count and complexity analysis is carried to evaluate the proposed design against the conventional type of structural interface methods. The assessment reveals that this new concept demonstrates a significant improvement in the efficiency of the mass production process.

**Keywords:** flexible integration; CubeSat structure; slot; efficient; mass production

### **1. Introduction**

A CubeSat is a standardized, modular nanosatellite class satellite with a basic dimension of a cubic decimeter [1]. Over the last decade, CubeSats have been used as a fundamental tool for academic institutions to conduct innovative in-orbit technology demonstration missions [1] (p. 59) within a limited budget and human resources. Recently, small space businesses started looking at the business potential in the area by engaging in the development of CubeSats' subsystems. The continuous innovation in small satellite technology has been the driving force behind an increase in the capability of these classes of satellites in recent years. These tremendous advancements are mainly due to the continual miniaturization of microprocessors [1,2]. As a result, various missions are being executed on a single CubeSat platform, with increasing mission sophistication. For these reasons, subsystems are designed to have multi-functionality requirements within stringent mass and volume constraints.

As a result of this increased capability, CubeSats' applications have gradually expanded from simple technology demonstration missions and remote sensing mission platforms to more advanced and sophisticated missions. Mega-constellations using distributed space systems (DSS) [1] and deep space exploration [3] are some examples of

**Citation:** Areda, E.E.; Cordova-Alarcon, J.R.; Masui, H.; Cho, M. Development of Innovative CubeSat Platform for Mass Production. *Appl. Sci.* **2022**, *12*, 9087. https://doi.org/10.3390/ app12189087

Academic Editors: Simone Battistini, Filippo Graziani and Mauro Pontani

Received: 28 July 2022 Accepted: 5 September 2022 Published: 9 September 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

current possibilities. These mega-constellation missions require the deployment of a massive number of CubeSats for the intended aims. Constellations using the CubeSat platform guarantee more ground coverage, greater built-in redundancy, and shorter revisit times, available for the same price as conventional big satellites [4].

Table 1 lists commercial CubeSat constellations with more than two functional spacecraft in orbit as of July 2022. This shows the gradual increase in CubeSat constellation missions in different application areas. The stakeholders are predominantly private space companies with commercial purposes to provide space-based satellite solutions by utilizing state-of-the-art technologies in the field. These services aim to provide affordable space-based solutions, while maintaining a profit margin [1] (p. 15).

The cost of mega-constellation development depends on several cost driver factors with different levels of effect on the total project cost. The supply chain is a crucial factor which should be managed strictly to avoid any delay in the schedule. However, efficiency during the design and development phase also plays a decisive part in determining the project time and cost. Inefficiency in the development process leads to unnecessary costs that lead to potential bankruptcy [5]. In addition, it causes unwanted workmanship errors. Incorporating the design for assembly and manufacturing (DFAM) principle during the conceptual design phase of the satellite development leads to an increased efficiency and/or productivity [6] (p. 19). By observing further down to the level of the structure of the subsystems in satellite development, improvement in efficiency can be attained by reducing the assembly steps and simplifying the effort required during the integration, assembly, and testing processes. This is done by modularizing and standardizing the design process, while keeping a certain level of flexibility [6] (p. 74–82). Therefore, it is vital to critically evaluate all design processes and identify inefficiency in the process as much as possible.

Design modularity is an essential element in satellite development which significantly affects the level of effort in the project team and its effect on development costs can be quantified [7]. A modularized satellite bus has standardized and reconfigurable components [7]. The reduction in design effort allows for shorter development time and this in turn results in an improvement in productivity and efficiency, particularly for mass production applications [7].

Mass production, by nature, requires frequent design iteration and continuous testing during the beginning phase, when a new batch of satellites is produced due to the required tests and verifications to verify the design [1]. These necessitate the frequent assembly and disassembly of satellite subsystems. Here, easy reconfigurability plays a key factor in determining the speed of the integration. The arrangement of components and the nature of interconnectedness inside the satellite affects the speed of the development when it comes to easy access. However, in the subsequent development, as the learning curve increases, the ease and small number of assembly steps become significant.



On the other hand, an increase in the number of structural parts increases the interconnectivity of parts, which also increases interdependency. Any problem with one of the components may affect the adjacent connected parts. Hence, the implemented mechanical interface between the internal subsystems and structure plays a crucial role in speeding up the integration and delivery of the final products. In the present paper, a unique interface design is introduced to tackle the issues associated with the most common mechanical interface.

### *Literature Review*

The primary function of a CubeSat's structure is to provide support and protection to the internal and external satellite bus system and payload components throughout the satellite's lifetime, during development on the ground, during launch, and in the orbit environment [9] (p. 133). Besides this basic requirement, the CubeSat structure is also required to provide an easy and flexible platform for quick integration during frequent testing phases [1] (p. 322), especially for missions involving mass production. Satellite assembly and integration in a mass production environment is unique from mass production of products for ground use, as it is often limited by various tight constraints, such as time due to the fixed launch and specific market windows to meet the targeted customer demand. In constellation missions, however, as reliability gradually increases, generation by generation, the first batch of the satellite often requires extensive functional and environmental testing [1] (p. 324).

CubeSat structures can be developed from a custom design or procured from the CubeSat market as commercially off-the-shelf (COTS) designs. Several companies offer a set of ready-mades and verified CubeSat subsystems, including a fully assembled structural platform. This approach reduces the development time, since testing and verification requirements can be skipped in most cases, when the subsystems have already been verified and demonstrated in an orbit environment. Verification, however, is a mandatory requirement for custom structural designs to conduct rigorous screening and reliability tests/inspections [10]. The ready-made CubeSat platforms, to some extent, help to shorten the development time [9]. However, their fixed designs impose limitations on the flexibility in defining the placement of mission payloads that are unique in size. CubeSat vendors such as GOMSPACE [11], PUMPKIN [12], ISIS [13], and Complex system and small satellite (C3S) [14] provide several standard design options for CubeSat structures.

These COTS structural designs have several predefined attachment points, providing freedom when mounting the internal subassembly. Some of these COTS structures are made of several modular frames or plates which can easily be expanded to other CubeSat form factors. Examples can be found in references [12,13]. Most of these structural designs accommodate satellite subsystems that were developed on their own to satisfy their specific interface requirements. Custom structural design addresses these interface limitations by developing a structure that is tailored to specific satellite mission requirements. Despite its flexibility, the development and design verification steps take a comparatively long time. The decision to invest is mostly made based on the available budget and time.

Even if these design solutions are aimed at solving a specific problem, they still utilize many structural components/parts. The number of structural parts is one of the critical issues that should be addressed, particularly for an efficiency-demanding mass production application. Therefore, a standard, flexible platform with a minimum number of parts and joints is very important for mass-producible, fast-delivery applications.

The internal configuration of subsystems mostly depends on the type of electrical interface implemented. Commonly, there are two main electrical interface methods implemented in CubeSats, such as PC/104 and the backplane board interface. The first is the PC/104 interface, where PCBs are stacked one on top of the other through an extended "stack-through" connectors module. Images of this interface can be found in [15]. In this case, standoffs between the subsystems are used to provide mechanical support and transfer the load to the main structural frames. Many commercial companies make this PC/104 interface.

On the other hand, the backplane board (BPB) approach uses a common interface board, where all the other internal PCBs are connected to a motherboard, as shown in Figure 1.

**Figure 1.** BIRDS satellite BPB interface [16].

In terms of mechanical support, similar to the PC/104, four long stacking rods connect all of the individual PCB boards once electrical connection has been established with the connectors on the BPB. Cylindrical spacers are inserted into the rods between each consecutive PCB stack to constrain their position, as shown in Figure 2. Recently, several universities and some commercial vendors have increasingly adopted this interface approach, as it provides better flexibility in electrical connections. For instance, the University of Würzburg in Germany developed a UWE-4 satellite in collaboration with other institutions that implements a backplane board electrical interface [17]. The backplane board type of interface is also the currently preferred approach used on most of the satellite missions at the Kyushu Institute of Technology (Kyutech) due to its high modularity [16]. So far, 19 CubeSats have been built based on the backplane style and 16 satellites have already been launched.

**Figure 2.** Stacking of PCBs with long rods.

However, from a fast delivery and quick assembly point of view, both electrical interface approaches with a stacking-type mechanical interface still pose some fundamental problems, mostly due to the mounting method of internal subsystems using long stacking rods. The method of inserting these long screws through the PCBs and the structure generally requires some level of effort for maintaining the alignment in this conventional type mechanical interface. The placement of the spacers between the PCBs particularly is often a challenging task during assembly, due to the required simultaneous task of inserting the stacking rods and placing the spacers, aligned with the holes in the PCBs, not to mention the substantial number of structural parts utilized, which consumes time during assembly. This potentially introduce workmanship errors to the assembly process, damaging the connector pins, etc. In addition, the additional frames used to connect these stacking rods to the structural frames, as shown in Figure 3, increase the total part count of the structure.

**Figure 3.** (**a**) Exploded 3U model based on conventional interface methods and (**b**) connecting rods for mounting internal subassemblies.

Both the above electrical interface approaches characterize the most conventional CubeSat interfaces. Several design solutions have been proposed to address the issues of flexibility and modularity. This study investigates similar design concepts available and tries to analyze their feasibility for the assumed applications.

A commercial space company developed a card-slot-type structural design in which individual subsystems are inserted into defined slots using special spacers holding the internal subsystems. An example can be seen on the company's website [14]. This design concept can solve the above issue of interdependency between subsystems during integration. However, the retractable PCB holder/spacer used to prevent the direct contact of the subsystems with the main structural frames increases the total structural part count and possibly the complexity during assembly.

Another study conducted by Istanbul Technical University for the PSAT-II mission [18] considered a modular 3U structure design with evenly spaced slit features on the interior faces of the four main frames to mount the internal subsystems. The PCBs were inserted into these tacks. The design in the study aimed to increase flexibility in rearranging internal subsystems, without the need to change the design of the structure, and to demonstrate it on a standardized bus in orbit. However, despite its concept of modularity, the study did not clearly show the electrical interface methods, nor the mechanical interface used to mount the internal PCB into the slots. insertion of PCBs directly into the given slits could potentially damage the PCB as well as the sensitive components, especially in the launch environment.

In general, the most important efficiency parameters, such as structural part count and number of assembly steps, which directly influence the level of complexity of the integration, have not been adequately addressed in either design. In fact, the complexity and the number of assembly steps has a direct relationship with the number of parts that exist. In addition, complexity can be a result of the mechanical interface method implemented. Therefore, it is important to have a platform where few parts and joints are needed for integration, with an assembly procedure easy to comprehend for someone who is not familiar with the tasks.

Once a design is optimized to the point where it has few structural parts and subsystems with little interdependence, it is important to standardize the platform so that few design changes are required in subsequent developments. This can be achieved by defining the interface between the satellite subsystems and the structure. At the same time, it is

also important to allow some level of flexibility for subsystems or payloads with unique dimensions to fit into the structure without difficulty.

The goal of this research is to develop a flexible standard efficient 3U STM (structure and thermal model) which is suitable for mass production applications. The design concept is developed as an STM for an ongoing 3U CubeSat project.

Recalling the common conventional type of structure, which is made up of several structural frames, rods, and plates, it is important to address the associated challenges. Therefore, a slot-based structural design is proposed with a unique interface between the internal PCB and the structure. The following are design parameters defined to evaluate the design objective.

The design goals:


These design goals are used as evaluation parameters to compare the new design concept against the existing traditional, conventional CubeSat structural designs. After this initial phase of design, an EM and FM models are currently being developed with further design optimization. In this study, the initial STM development, from concept design to manufacturing and testing, is explained.

The purpose of the present paper is to develop a flexible and modular standard 3U CubeSat structure that is suitable for highly efficiency-demanding mass production applications. The novelty of this paper is the interface method used to mount the internal subsystems onto the slots, which provides a much lower part count with an easy assembly technique compared to the existing slot-type structural platforms. In addition, the slots are standardized to reduce the need for a change in the interface design of internal components, while at the same time facilitating the easy relocation of subsystems within the platform during the configuration definition phase.

This paper consists of seven sections. The second section describes the conceptual development of the structural design. The suitability of the proposed design is evaluated against the existing structural platform in the third section. The assessment results are analyzed in the fourth section. The fifth and the final sections provide the conclusion and directions for future work.

### **2. Conceptual Development of Structural Design**

To come up with a design that solves the aforementioned issues, several design concepts are considered at the beginning of development based on the defined design goals. The CubeSat standard interface developed by California Polytechnic State University is used as a design reference [19]. An example of a design specification document is the JAXA's Japanese Experimental Module (JEM) Payload Accommodation Handbook, for those CubeSats that are released from the JEM Remote Manipulator System using the JEM Small Satellite Orbital Deployer J-SSOD installed in [20]. In addition, constraints from previous heritage subsystems are taken into account during the development of the design concept. Satellite bus subsystems, such as the electrical and power subsystem (EPS), onboard computer (OBC), and communication (COM) boards, have been used for several previous projects. Since design modification of these subsystems costs a significant amount of money, the basic shape and dimensions of these internal PCBs are kept and used as additional design constraints.

During the development of this new design, Fusion 360 software is used to model the structure. After a series of design iterations and evaluations, a slot-based design concept is chosen for a 3U STM using a total of eight aluminum structural components, as shown in Figure 4. Two parallel mirror slot plates are designed to mount the satellite's internal bus and payload. They are attached to the two bottom and top plates. Additionally, for this STM, two side frames on the Plus and Minus X axis are used to connect the top and bottom plates to give the structure extra stiffness and provide additional support for PC/104 standard subsystems such as the ADCS units.

**Figure 4.** Exploded view of the Slot-based 3U structural model.

### *2.1. Standardizing the Slots*

Greater attention is given to standardizing the width of the slot rails to reduce the variety of spacers used. To allow easy interchangeability between subsystems, three standard slot widths are defined, as shown in Figure 5: 6 mm, 9 mm, and 18 mm. Besides these standard slot widths, free-sized slots are also considered to accommodate a few oversized components, depending on the type of mission. In this particular design, the battery and the communication payload are assumed to have relatively large sizes; therefore, slots of 27 mm and 85 mm in width were adopted.

**Figure 5.** Slot plate with standardized slot width for 3U model.

### *2.2. PCB Holder (Spacers)*

Internal subsystem components, mostly PCB boards, are inserted into these standard slots using a set of special PCB holders (spacers) made of softer plastic material to protect the sensitive surface of the PCB. The spacer removes the need for long screw rods to mount the internal subsystems, as in the case of conventional CubeSat design. The spacers' width is derived from the defined slot width. The spacers also have a cutout slit according to the thickness of each PCB or component, as shown in Figure 6. They are attached to the PCBs at four corners by just applying a small push force for a snap-fit. The tolerance of the cutout on the spacers should correspond to that of the PCB/components' thickness tolerance. Similarly, the tolerance of the spacers' width should also correspond to the tolerance of the slot width on the structure.

**Figure 6.** Standard 6 mm, 9 mm, and free-size spacers.

Regarding the spacer material, different plastic materials were assessed. However, PEEK (polyether ether ketone) was chosen due to its high strength and stiffness.

### *2.3. Internal Subsystem Interface Method*

When the PCBs are to be inserted into the slots, the spacers are simply attached to the PCB edges at the four corners. The PCBs lock themself between the slot plates and bottom plate once the connection has been established electrically to the backplane board (BPB). The tolerance of the spacers is designed to allow the easy slide action of the PCBs during insertion and removal. The top plate fully encloses the PCB assembly, constraining the movement inside, as shown in Figure 7.

**Figure 7.** (**A**) PCB insertion into the slots. (**B**) The top plate encloses the satellite assembly.

### *2.4. Finite Element Analysis (FEA) and Environmental Test*

After developing the 3D model of the STM, finite element analysis (FEA) was carried out to check the stiffness both on individual components and assembly levels using the Autodesk Fusion 360 simulation environment. The model was simplified by removing rounds and chamfers. A total weight of approximately 3.6 kg was assumed to resemble the actual total weight of the satellite at the time of the STM phase. In addition to the frequency analysis, static analysis was also conducted. All the boundary conditions were applied according to the JAXA requirement handbook [20].

The production of the STM was ordered after confirming the analysis results (Figure 8). The lesson learned when placing the production order was that the tolerance requirement of the slots as well as spacers should be carefully specified and checked, as the spacers must easily slide into the slot when assembling the PCBs. The parts were assembled using dummy internal and external subsystems, which have similar mass. Then, a vibration test

was conducted to verify whether the satellite could survive the severe launch environment. Different launch loads, such as random and quasi-static vibration loads, were applied to the satellite. Since the satellite is expected to be deployed from ISS, a shock test was not necessary. Qualification-level random and sine-burst vibrations were applied to the test article. Modal surveys were taken on each occasion before and after the random and sine-burst vibration to check whether the signature of the fundamental frequency had shifted. The vibration results are discussed in Section 4.1.

**Figure 8.** Structural and full satellite assembly of STM 3U.

### **3. Design Assessment Methods**

The proposed 3U STM design was critically assessed against the design goals. Since a 3U satellite has not been developed by Kyutech in the past and an actual satellite was not available to evaluate with, for assessment purposes, a demo 3U CubeSat model based on the conventional type was modeled with a backplane board electrical interface. The structure utilizes several long rods to stack up the PCBs, as shown in Figure 9. To avoid any design merits due to the design difference between the two concepts during the assessment, the quantity and shape of the basic structural parts, such as the top, bottom, and side plates, are kept similar. This helps the assessment to focus on the interface method used between the main structure and internal subassembly instead of the change in design. However, often the conventional design may only have four rails along the Z axis instead of plates and connecting rods in actual case.

**Figure 9.** Conventional demo 3U model.

As previously described, important evaluation parameters, such as part and assembly count analysis and complexity analysis, were used to assess the design goals to measure the impact of the change in design on the integration efficiency of mass production missions. First, the count analysis was conducted by comparing the total quantity of only structural parts, such as plates, frames, spacers, and fasteners. The internal subsystem components were not included in this analysis because that may vary depending on the mission type. Second, complexity analysis was carried out to measure the level of difficulty encountered

during the integration phase. Then, the scalability of the design concept to other CubeSat form factors was demonstrated using a 1U platform. Since this study focuses on 3U CubeSat, due to the satellite mission requirement, the new design concept was developed for that purpose. However, it is important to assess its scalability. Due to the popularity of the 1U CubeSat platform in the CubeSat community, checking the scalability of the 3U slot-based design is particularly important. A similar assessment of count and complexity analysis was conducted by comparing this platform with the previous 1U conventionaltype BIRDS-3 satellite platform, which was developed by Kyutech. The BIRDS-3 satellite has already finished its two-year mission in ISS orbit. Finally, the assembly step count was used to evaluate the speed at which each assembly action was carried out. Here, the steps are for the complete satellite assembly only, without the solar panels.

### *3.1. Count Analysis*

In this analysis, the quantity of primary structural parts of both the 3U flexible structure and conventional-type demo model is considered, as shown in Figures 9 and 10. For easy visualization, the structural parts are categorized into four groups: the main structural frames, which include rods and rails; spacers; long rods; and fasteners. This helps to visualize the major changes that contributed to the total difference. Since the quantity of screws affects the assembly process, structural screws for both designs are included in the analysis. These screws are the one that are used to secure the internal satellite components onto the structural frame. The screw count reflects the existing number of joints in the design and how parts are interconnected in the system.

**Figure 10.** Slot-based 3U model.

### *3.2. Complexity Analysis*

To evaluate design complexity, complexity metrics developed for the industrial assembly were used based on a modified version of Hückel's Molecular Orbital Theory. This metric is used to calculate the complexity of systems from different perspectives [21]. In this complexity measurement, total system complexity has three variables: The first variable, *Cs* <sup>1</sup>, measures the complexities of each component on the individual level. The second complexity variable, *C<sup>s</sup>* <sup>2</sup>, measures the complexity during a pairwise interaction (liaison relationship) of two or more components. The last variable, *C<sup>s</sup>* <sup>3</sup>, is a topology complexity that measures the effect of system architecture or the arrangement of the different interfaces. Thus, the total complexity of the satellite can be calculated with a combination of these three variables using Equation (1). The detailed derivation and explanation of the metrics and each variable can be referred to in [22] (p. 48). The total complexity of the structural assembly of the satellite provides a very good piece of information about the complexity/difficulty level of the two design concepts, especially during integration. System complexity can also easily be visualized using a liaison diagram, as shown in Figure 11.

**Figure 11.** Elements of the overall complexity metrics shown with a liaison diagram.

The first complexity variable of the satellite is the summation of the complexity value *α<sup>s</sup> i* for all satellite components, and can be calculated using Equation (2), where α<sup>s</sup> <sup>i</sup> represents the complexity of the satellite components, and *i* and *Ns* denote the total number of parts forming the satellite. This indicates the technical/agronomical difficulty/efforts associated with the development and management of each of the assembly components in isolated conditions.

$$\mathbf{C}^{s} = \mathbf{C}\_{1}^{s} + \mathbf{C}\_{2}^{s}\mathbf{C}\_{3}^{s} \tag{1}$$

$$C\_1^s = \sum\_{i=1}^{N\_s} \alpha\_i^s \tag{2}$$

Similarly, the liaison's complexity of assembly, *C<sup>s</sup>* <sup>2</sup>, is the sum of all the complexities in the pairwise interaction between two linked structural components and is calculated using Equation (3) below. The variables *βij* and *ASMij* denote a binary adjacency matrix derived from the components that have physical interaction in the assembled state.

$$C\_2^s = \sum\_{i=1}^{N\_s^t} \sum\_{j=1}^{N\_s^t} \beta\_{ij}^s AS \mathcal{M}\_{ij}^{minimal} \tag{3}$$

$$[ASM]\_{ij} = \begin{cases} \begin{array}{c} 1, \quad \text{if } i \text{ and } j \text{ are connected} \\ 0, \quad \text{otherwise} \end{array} \tag{4}$$

$$\beta\_{ij}^p = \frac{f\_f^E + f\_f^F + f\_f^G + f\_f^H + f\_f^I + f\_f^J + f\_f^k}{\beta\_{max}^p} \tag{5}$$

On the other hand, in the last term, *C<sup>s</sup>* <sup>3</sup> is a global measure that encapsulates the inherent arrangement of connections and is calculated by the graph energy [23]. Note that the term *C<sup>s</sup>* <sup>3</sup> requires knowledge of the complete system architecture and signifies a global effect, the influence of which could be perceived during the system integration phase [22].

The complexity of the product's topology, *C<sup>s</sup>* <sup>3</sup>, is computed by

$$C\_3^\varepsilon = \frac{E\_{ASM}^\varepsilon}{N\_s^\varepsilon} \tag{6}$$

$$E\_{ASM} = \sum\_{i=1}^{N\_s^c} \sigma\_i \tag{7}$$

The assembled system can be expressed graphically using a combination of components and liaisons. The components can be essential components that behave as a single unit, quasi-components that are used to connect the essential components, and virtual components, which are non-mechanical components such as solders or glues. However, for simplicity, the graphical expression of the satellite only shows the essential components in compact form. In the diagram, the components are denoted by circular nodes, whereas the liaisons are denoted by edges, as shown in Figures 12 and 13. The spacers and screws are considered quasi-essential components and therefore are not taken into consideration in this liaison diagram. The satellite components represented by the nodes are listed in Appendix A in Table A5.

**Figure 12.** Liaison diagram of 3U demo conventional model.

**Figure 13.** Liaison diagram of 3U slot-based model.

### **4. Results**

### *4.1. Structural Analysis and Vibration Test Results*

The results of frequency analysis show that the first mode of vibration in the fully assembled state of the satellite is 251.9 Hz, as shown in Figure 14, which is well above the minimum requirement of 60 Hz specified in the JAXA accommodation handbook document [20]. On the other hand, the maximum von Mises stress when the expected launch load is applied is 96.09 MPa, 111.8 MPa, and 99.22 MPa in the X-, Y-, and Z-axis, respectively. The safety margin is calculated using these stress values.

**Figure 14.** Frequency analysis of the 3U model.

In addition, random and sine-burst vibration tests were conducted at the Kyutech Nanosatellite development facility. All the test results show that the satellite's fundamental frequency did not change before and after the vibrations, as shown in Figure 15.

**Figure 15.** Modal survey before and after random vibration on Y-axis.

### *4.2. Evaluation Result for Count Analysis*

The count analysis results for the 3U CubeSat are shown in Table 2. Both the part and screw count show a considerable amount of change in favor of the slot-based design concept. A 42% reduction is achieved by changing the interface method of internal subsystem, since the design merit is out of the equation because the designs of major structural parts in both concepts are similar in shape and quantity. Such a significant improvement, from 14 to 8, attained due to the reduction in the number of structural parts, such as the connecting frames and long rods that hold the PCB stacks and spacers. The conventional design utilizes many spacers that must be mounted between each stack, whereas in the case of the slot design, only four spacers are used for each PCB. The number of structural screws, however, does not show substantial improvement, being only 5%. This is because this STM utilizes several redundant structural screws. This point was taken as a potential area for improvement on the current EM model.



### *4.3. Evaluation Result for Complexity Analysis*

The complexity of both satellite design concepts is computed using Equation (1). Figure 16 shows the comparative value of each complexity variable of both 3U designs. The complexity analysis reveals that the overall complexity of the slot-based design is reduced by 40.43%. All the sub-complexity variables show an improvement in comparison with the conventional-type structural design. The reduction in the component complexity by 23.98% shows a reduction in the level of difficulty when handling individual components in the case of the slot-based design. The improvement in liaison complexity is rather noticeable, being approximately 61.03%. Due to the small number of structural screws and

components, as well as the way they are brought together, without the need for long screws, it is possible to reduce the liaison complexity. From a global perspective, the intricateness of the overall integration is also improved, but by a small amount.

### *4.4. Evaluation Result of Assembly Steps*

As described before, the steps taken to assemble all satellite components, except the structure, are counted. The process of attaching screws and spacers is not considered during the count. Assuming that the spacers are already attached to the PCBs, the total number of steps required to assemble the conventional structure is 29, whereas it is only 12 for the slot-based structure. This represents an improvement of around 58%.

### *4.5. Evaluation Result of Design Concept Scalability*

In addition to the above evaluations performed on the 3U CubeSat, the scalability of the concept down to the lower CubeSat form factor was verified. The BIRDS-3 satellite (shown in Figure 17) is used for this assessment. BIRDS-3 is a 1U CubeSat with a structure based on the conventional design concept. Similar evaluation methods were employed to check its suitability for highly efficiency-demanding mass production applications. For the purpose of this evaluation, a slot-based 1U STM was designed (shown in Figure 18) and manufactured. Then, it was compared with an existing conventional-type BIRDS-3 platform. A similar liaison representation is used to show the relationship between components in the assembly in Figures 19 and 20.

**Figure 17.** Conventional-type BIRDS-3 1U model.

**Figure 18.** Slot-based 1U model.

**Figure 19.** Liaison diagram of 1U BIRDS-3 conventional model.

**Figure 20.** Liaison diagram of the 1U slot-based STM.

### 4.5.1. Count Analysis

In the count analysis, only the primary structural parts, such as rails, plates, rods, spacers, and fasteners, are considered. They are subcategorized accordingly in a similar way for the 3U models, as shown in Table 3.


**Table 3.** Count analysis of 1U structure.

A similar result is obtained for the 1U-size design. The total number of screws is reduced by 33.33% for the slot structure, whereas a 50.98% reduction is achieved in the total part count, which includes structural parts and spacers. The BIRDS-3 CubeSat uses 51 structural parts, including the long mounting rods, whereas the total number of structural parts of the slot-based design is only seven. This significant reduction is due to the withdrawal of the staking rods and the associated support frames.

### 4.5.2. Complexity Analysis

During integration, there is also an impact on the overall reduction in complexity. In the case of the slot-type design, the individual PCBs and payload components are independently mounted in their designated slots using a special spacer, avoiding interdependency between the subsystems, which increases easiness of accessing components quickly. This effect can be easily observed with the value of the liaison parameters, which shows a 78.45% reduction. The total complexity of the conventional design of BIRDS-3 is 8.59, whereas it is only 2.73 for the slot-type concept, which is, overall, 68.22% drop. Figure 21 below illustrates the general comparison of the complexity of both 1U designs.

**Figure 21.** Complexity comparison of 1U conventional and slot-type structures.

### 4.5.3. Assembly Steps

In terms of the number of assembly steps, assembling the BIRDS-3 model requires a total of 16 steps. On the other hand, only five steps are required for the 1U slot-type design. This notable difference is due to the reduction in the number of structural parts. The slot-based design utilizes 25 structural parts, which is approximately half of that for the BIRDS-3 structure.

### **5. Discussion**

The new slot-type structural design concept was manufactured and verified with environmental tests to confirm its bottom-line requirement. Both the random and sineburst vibration shows its compliance to the minimum mechanical strength and stiffness requirements. According to the JAXA accommodation handbook, the minimum natural frequency of satellites is defined as 60 Hz. The measured natural frequency of the STM design for 3U was around 310 Hz.

The assessment results from the count and complexity analyses strongly suggest that the new slot-based structural design showed superior advantages by providing a more efficient integration process. It was possible to reduce the structural part count of the conventional design by 42% and 51% for the 3U and 1U satellites, respectively. The improvement in the part count provides three major benefits. First, the few required assembly steps to finish integrating the satellite led to an increase in the speed of the entire process of satellite development. On the other hand, having fewer structural parts also means a reduction in manufacturing costs. The cost is also directly related to the amount of tolerance required. A higher stack-up tolerance also leads to higher tolerance on individual parts level. As the number of parts increases, the stack-up tolerance increases to achieve the tolerance requirement defined by the CubeSat design specification, which causes a dramatic increase in production costs. The last advantage acquired with the minimum part count is its contribution to the reduction in complexity during integration.

Complexity is a key factor that decides the level of simplification of the integration that impacts productivity. The complexity analysis shows a similar improvement as the part count analysis. The 3U slot design provides 40.43% reduction as compared to the conventional-type designs. On the other hand, a 68.02% change in the complexity for the case of the 1U slot design shows a significant change.

As discussed before, the complexity of the assembly increases with the number of components and joints. An increase in complexity usually leads to workmanship errors due to difficulty grasping the assembly process. Despite the overall improvement achieved, the amount varies in terms of the level of sub-complexity variables. The minimum recorded improvement is in topological complexity, which indicates the need for further refinement in design. Based on the identified issues, further refinement in the design is being carried out for the current FM model. It is expected that upon the completion of the current FM model, the count and complexity values shall improve even further. In this design, the internal subsystems are standardized within the dimensions of 90 mm (about 3.54 in) by 86 mm (about 3.39 in); however, future work will consider enhancing the flexibility to accommodate components that are not standard enough to fit into the defined standard slot widths.

Besides these major assessments, the implication of the reduction in part count and complexity, of the assembly step was evaluated. It takes 12 steps to complete the 3U slot structure assembly which is 58% reduction. The reduction in the number of assembly steps by more than half shows the method's suitability in terms of efficiency for fast integration missions. The scalability of the concept to lower the CubeSat factor demonstrates that this highly efficiency-demanding mission has potential feasibility on a 1U or higher form factor CubeSat platform.

### **6. Conclusions**

As mass production applications using CubeSats are expanding, it can be deduced that an increase in productivity through the enhancement of flexibility and integration speed looks particularly important for the profitability and success of these missions. In this study, a highly flexible and easy-to-use 3U and 1U slot-based structure was developed, which facilitates easy and quick integration. It is believed to increase the reliability of satellite

integration by reducing the complexity that case human errors during the integration and testing phases. Both structural analysis and vibration tests show that the developed model is stiffened and strong enough to withstand expected severe launch loads.

Finally, the design goals are evaluated against the conventional CubeSat structural design using the part and assembly step count, as well as complexity analysis. The results show significant improvements in the critical design parameters. The scalability of the concept is also examined by developing an equivalent 1U slot-type model showing similar design outputs. This 3U design concept is currently being implemented on one of Kyutech's mass production CubeSat projects, with additional improvements.

However, the acquired advantages are more noticeable, especially for missions where the total mass of the satellite is not critical. However, in addition to an improvement in the design, several other options are being explored to reduce the total weight of the structure. In future work, the employment of new production techniques such as additive manufacturing is believed to provide further enhancement for this design concept.

**Author Contributions:** Conceptualization, E.E.A. and H.M.; methodology, E.E.A., H.M. and M.C.; software, E.E.A.; validation, E.E.A., H.M. and M.C.; formal analysis, E.E.A.; investigation, E.E.A. and H.M.; resources, M.C. and H.M.; data curation, E.E.A., J.R.C.-A. and H.M.; writing—original draft preparation, E.E.A.; writing—review and editing, E.E.A., J.R.C.-A., H.M. and M.C.; visualization, E.E.A.; supervision, H.M. and M.C.; project administration, J.R.C.-A., H.M. and M.C.; funding acquisition, H.M. and M.C. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by Ministry of Economy, Trade and Industry (METI), Japan under the grant. "International Standard Development for Energy Conservation (International Standardization of CubeSat Interface)" with grant number [FY2021-10]. The APC was funded by METI.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** Not applicable.

**Acknowledgments:** The authors would like to acknowledge the support of the Japanese Ministry of Economy, Trade, and Industry through the Promotion of Energy Saving and Related International Standards.

**Conflicts of Interest:** The authors declare no conflict of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript; or in the decision to publish the results.

### **Appendix A**

**Table A1.** The 3U conventional-type demo satellite complexity values.





**Table A3.** The 1U BIRDS satellite complexity values.

**Table A4.** The 1U slot-based satellite complexity values.


**Table A5.** Nodal definition of the 1U and 3U slots and conventional designs.


### **References**

