**3. Reduced Switch Count Multilevel Inverters (RSC-MLIs) Topologies**

A. Generalized RSC-MLI Topologies

Generalized RSC-MLI topologies can be further divided into subcategories depending on the similarity of their structures and the switching devices used. The categorization is as follows:

(1) Separate Level and Polarity Generator Topologies

Each phase-voltage level has its own independent polarity and level generators, which results in an unusually high number of levels. Popular combinations include the MLDCL, SSPS, RV, SCSS, and MLM topologies, according to [2]. Figure 11 depicts the per-phase architecture of these three-source arrangements. An isolated DC supply is used in each basic unit, which uses bidirectional switches to generate levels in the MLM topology. It is important to note that MLDCL and SSPS topologies need identical device-blocking voltages. Adding a new basic unit to an RV, SCSS, or MLM topology increases voltage stress. As a result, the total DC-link voltage is equal to the blocking voltage of each device. Except for the SCSS and MLM topologies, all of these topologies offer symmetric and asymmetric configurations.

**Figure 11.** Separate level and polarity generator topologies: (**a**) MLDCL; (**b**) SSPS; (**c**) SCSS; (**d**) RV; (**e**) MLM.

It is acquired from the polarity generator in the SSPS topology since the level generator cannot make it. Only two devices in the level generator are in conduction to obtain any positive or negative voltage level in the SSPS topology depicted in Figure 11b. Because the output voltage is raised by charging all of the DC-link capacitors in series or parallel operation, the output voltage is also increased. This SSPS function is ideal for charging batteries and storing energy. For grid-connected PV systems, series or parallel operation maximizes the use of DC sources. Adding an H-bridge to an SSPS topology RSC-MLI reduces switch counts and further losses. An asymmetrical improvement architecture with a voltage gain is presented by the SSPS topology with minimal modifications. To expand the RV architecture to higher levels, just duplicate the encircling intermediate stage of the level generator illustrated in Figure 11d. In the topologies presented in Figure 11, level generators can only use additive DC source combinations.

(2) T-Type Structure Topologies

A T-type topological structure interconnects numerous DC-link nodes by a phase-leg of full-/half-bridge structures on the burden side. These designs use unidirectional and bidirectional switches. Figure 12 depicts typical T-type topology combinations through complete bridge, cascaded, and half-bridge structures. The T-type with complete bridge construction is the most common, owing to its simplicity and reduced switch count [131,132].

**Figure 12.** Topologies with T-type structures: (**a**) H-bridge T-type; (**b**) cascaded T-type; (**c**) T-type three-phase half-bridge.


topology is shown in Figure 12c as an example of this structure. To obtain larger levels, just increase the DC sources using bidirectional switches, which may provide even and odd phases of voltage. In Figure 12c, two devices per leg are in conduction at any one moment, and the voltage rating of bidirectional switches is smaller than the devices in a phase-leg. Due to minor conduction losses and a reduced total blocking voltage, this design is preferred over a DCMLI and ANPC in terms of efficiency. Many PV and grid-connected applications have used this design. When an open-circuit switch malfunction occurs, this inverter can be reconfigured to withstand the problem [2,132].

(3) HSC Structure Topologies

A hexagon switch cell (HSC) structure is constructed using unidirectional switches, and the DC link is connected to this structure using bidirectional switches.

> (*i*) Topology-I: A mix of T-type with HSC RSC-MLI topology with two stiff DC sources, i.e., ES and ER, on each side of the HSC. Figure 13a illustrates that more bidirectional switches or several modules cascaded together may expand this topology's capabilities further. According to Figure 13a, this topology is similar to the five-level T-type MLI when short-circuiting and open-circuiting the unidirectional switches H5 and H2, as shown. Since there are now unidirectional switches, we can work in asymmetrical configurations with the H-bridge to HSC. Asymmetrical behavior occurs only when ES is less than or equal to the number of elements in the configuration. DC-link capacitors "n" in the asymmetrical design of this architecture can provide (4n + 1) levels of phase voltage. Other voltage levels can be operated by using an asymmetrical arrangement with suitable voltage ratios.

**Figure 13.** Hybrid T-type topologies and extended HSC structures: (**a**) Hybrid T-type MLI with a bidirectional switch on one side of the HSC; (**b**) hybrid T-type MLI with a bidirectional switch on both sides of the HSC.


A few authors have developed feasible topologies with drastically reduced switch numbers compared to conventional MLIs to reduce the topological size, price, and complexity. There are a limited number of output voltage values that these topologies can provide. These setups function as RSC-MLIs with fixed topologies and output voltage values.

(1) Basic Unit RSC-MLI Topology

Separate polarity and level generators are used in this H-bridge topology [108,110]. A five-level unipolar voltage can be obtained by using an RSC-MLI basic unit. The basic unit in Figure 14 is made up of three-cell and one-cell structures. The three-cell structure has three voltage sources coupled by five unidirectional switches.

**Figure 14.** Basic unit RSC-MLI topology.

(2) Symmetrical Unit-Based Topology

There are two unit-based topologies that function with a reduced device sum for a specified number of output voltage levels [2]. These setups are detailed below.

> (i) Five-level configuration: To produce nine-level inverters, just cascade two units as indicated in Figure 15a. In each cycle, the cascaded units exchange switching pulses. Consequently, the units perform uniformly.

**Figure 15.** Symmetrical unit-based topologies: (**a**) Five-level; (**b**) nine-level.


Figure 16 shows a 17-level MLI circuit with an asymmetrical design. It has ten unidirectional switches with anti-parallel diodes and three asymmetrical DC voltage sources in a 1:2:5 ratio to produce the expected 17-level output voltage. It is described in detail in the aforementioned [134].

**Figure 16.** An asymmetrical 17-level RSC MLI.

To produce the desired output voltages of 19 levels in a 1:3:5 ratio [135], an asymmetrical design of the MLI circuit is shown in Figure 17. The design employs ten unidirectional switches with anti-parallel diodes and three asymmetric DC voltage sources. Tables 2 and 3 provide information on how 17-level and 19-level MLIs are built, how they compare with each other, and summarize the various recent topologies. Similarly, Figure 18 compares the parameters of the 17-level MLI topologies that have recently been developed, while Figure 19 compares the parameters of the 19-level MLI topologies that have recently been developed [134–137].

**Figure 17.** An asymmetrical 19-level RSC MLI.

**Table 2.** Parametric comparisons of the recently developed 17-level MLIs.



**Table 3.** Parametric comparisons of the recently developed 19-level MLIs.

(**a**) Number of switches

**Recently developed 17-Level MLI Topologies**

**Figure 18.** *Cont*.

**Figure 18.** Parametric comparisons of recently developed 17-level MLI topologies [3,5,134,138–144].

**Figure 19.** *Cont*.

(**d**) Factor of component count per level

(**e**) Cost factor per level

**Figure 19.** *Cont*.

(**f**) Efficiency

**Figure 19.** Parametric comparisons of recently developed 19-Level MLI topologies [135,136,145–150].

*a.* Power loss efficiency calculations:

Power losses are the main constraints in inverters, such as conduction losses (PCond) and switching losses (PSwi) [134–136]. The net amount of conduction losses can be obtained by considering losses in the IGBT switch (PCIGBT) and anti-parallel diode (PCDI) in the current conduction state and is represented as follows:

$$P\_{\rm Cond}(t) = P\_{\rm CIRBT}(t) + P\_{\rm CDI}(t) \tag{1}$$

$$P\_{\rm cond}(t) = \left\{ \left[ V\_{IGBT} + R\_{DI} i\_n^{\mathcal{G}}(t) \right] + \left[ V\_{DI} + R\_{DI} i\_n(t) \right] \right\} i\_n(t) \tag{2}$$

where *VIGBT*, *VDI*, and *in* are the *IGBT* threshold voltages and peak current, respectively. If the diodes *(NDI)* and switches *(NIGBT)* are conducted at the same intervals (t), *RIGBT* and *RDI* are the IGBT and diode on-state resistance, respectively, *β* is the IGBT constant. The average power loss is:

$$P\_{\rm Cond} = \frac{1}{2\pi} \int\_0^{2\pi} \left\{ N\_{\rm IGBT}(t) P\_{\rm CIRBT}(t) + N\_{\rm DI}(t) P\_{\rm CDI}(t) \right\} dt \tag{3}$$

The energy losses such as energy turn-on (*Enon*) and turn-off (*Enoff*) for IGBT turn-on and -off states during power consumption are:

$$E\_{noff} = \frac{1}{6} V\_{\text{IGBT}j} \text{It}\_{off} \tag{4}$$

$$E\_{\rm non} = \frac{1}{6} V\_{\rm IGBTj} I^{\prime} t\_{\rm on} \tag{5}$$

The *j* is the loss in *IGBT* and *tnoff* and *tnon* are the turn-on and -off, *Enoff* and *Enon* I and *I* of the *IGBT* switches, respectively.

$$P\_{Swi} = f\left\{ \sum\_{j=1}^{N\_{IGBT}} \left[ \sum\_{j=1}^{N\_{nonj}} E\_{nonji} + \sum\_{j=1}^{N\_{noff}} E\_{noffji} \right] \right\} \tag{6}$$

The *Nnonj* and *Nnoffj* are IGBT turn-on and -off *j*th time intervals with fundamental (*f*) in one complete cycle.

$$P\_{Tloss} = P\_{cond} + P\_{swi} \tag{7}$$

To calculate the inverter efficiency by Equation (8):

$$\% \eta = \frac{P\_{outn}}{P\_{inn}} = \frac{P\_{outn}}{P\_{outn} + P\_{Tloss}} \times 100\tag{8}$$

where both *Poutn* and *Pinn* are abbreviations used to denote output and input power, respectively. The output power can be calculated using Equation (9) as follows:

$$P\_{\text{outn}} = V\_{\text{rms}} \times I\_{\text{rms}} \tag{9}$$

### *b.* Switch stress total standing voltage (TSV) calculations:

To produce the largest blocking voltage via each switch, the multilevel inverter is crucial, and the TSV is the most essential factor in switch selection. There is a pairing between the maximum voltage across the switches and the TSV values. A voltage-blocking stress has been applied across the switch. Differences in voltage stress exist between unidirectional and bidirectional switches.

According to [134], it is possible to calculate the TSV per unit (TSVPU) as:

$$TSV\_{PI} = \frac{V\_{TSV}}{V\_{oma}}\tag{10}$$

#### *c.* Cost function (CF) parameter calculations:

The cost function (CF) can be used to make educated guesses about the financial viability of various MLI design alternatives, which is useful for highlighting budgetary constraints and showcasing design tradeoffs. The following equation provides a means through which the cost factor can be determined:

$$\mathcal{C}F = \left(N\_{\rm SWT} + N\_{\rm DD} + N\_{\rm CAP} + N\_{\rm DCS} + N\_{\rm DK} + \mathfrak{a}TSV\_{\rm PL}\right) \tag{11}$$

where *NSWT* indicates the number of switches, *NDD* indicates the number of diodes, *NCAP* indicates the number of capacitors, *NDCS* indicates the number of DC sources, *NDK* indicates the number of driver circuits, and *TSVPV* indicates the total standing voltage, if *TSVPU* is multiplied by the "α" weighting factor. In order to calculate the cost function (CF) can be used Equation (12) can be used as follows:

$$CF = \left(N\_{SWT} + N\_{DK} + N\_{DCS} + \mathfrak{a}TSV\_{PL}\right) \tag{12}$$

For the best cost factor computation, 0.5 and 1.5 will be explored. The component count per level factor (FCC/L) can be calculated by using Equation (13):

$$\text{FCC}/\text{L} = \frac{\left(N\_{\text{SWT}} + N\_{\text{DCS}} + N\_{\text{CAP}} + N\_{\text{DD}} + N\_{\text{DK}}\right)}{\text{Levels}}\tag{13}$$

#### *C. Switched capacitor (SC) unit-based topologies*

Basically, a DC source, diodes, capacitors, and switches make up the building blocks of an "SC unit". SPSC units, SC voltage doubler units, SC half-mode units, SC bipolar units, and SC voltage triple units are all subsets of basic SC units. The SC-MLIs can be categorized as single and multiple DC-source SC-MLIs, mid-point-clamped SC-MLIs, common ground switched-capacitor (CGSC)-based MLIs, and hybrid SC-MLIs [151–161].

### 1. Single DC-source SC-Unit-based MLIs

a. SPSC Units

There are two main types of SPSC units utilized in SC-MLIs, and they are depicted in Figure 20; Figure 20a depicts the minimal component count for Type-I of this device, which consists of just two switches, one capacitor, and one power diode [162–166]. The output voltage can be set to one of two discrete positive values, VDC or 2VDC, depending on the value of the input DC source. SPSC Unit-II, represented in Figure 20b, employs the same capacitor charging and discharging principle, although with an extra capacitor and a power switch in place of the diode and four-quadrant switch. The SPSC Unit-I is different from the SPSC Unit-II in that it can only send power in one direction. Furthermore, unlike the SPSC Unit-I, the SPSC Unit-II uses charged capacitor voltages to create both discrete voltage levels, which eliminates the possibility of a DC offset during the formation of the output voltage level in SC-MLIs. In this case, in addition to the paralleled conventional power switches in SPSC Unit-II, four-quadrant power switches with a back-to-back connection of two standard MOSFETs can be employed [167–171].

**Figure 20.** Categorization of different SC-based basic units.
