a. Three-level CGSC-based inverter

The inverters are based on CGSC and have been recently practiced. Taking into consideration Figure 24a, [202] proposed a three-level CGSC-based inverter with five power switches and a virtual DC-link capacitor, where the capacitor, C, was charged to the input DC source, Vdc, during the positive and zero levels of the output voltage and discharged during the generation of the negative output voltage. Siwakoti-H inverters were proposed in [203] that reduced the number of switching devices for this type of threelevel CGSC-based inverter, as illustrated in Figure 24b,c, where one additional diode was employed in Type-I of this converter and two RB-IGBTs were used in its Type-II variation. In [204], a three-level, four-switch CGSC-based inverter is presented; the virtual DC-link capacitor is charged indirectly to Vdc through a diode-aided CPC cell.

**Figure 24.** CGSC-based inverters: (**a**–**c**) Three-level inverters; (**d**,**e**) five-level inverters; (**f**) seven-level inverter; (**g**) nine-level inverter.

### b. Five-level CGSC-based inverter

There are two distinct CGSC-based inverter topologies, as can be seen in Figure 24d,e, one employing six power switches and the other employing eight power switches, both of which are capable of producing five levels of double voltage conversion gain output. A five-level CGSC-based inverter, recently presented by Ardashir et al. [197], is comprised of six power switches. The negative output voltage levels are generated using a similar virtual DC-link SC approach, but the total gain of the voltage conversion is unity.

#### c. Seven-level CGSC-based inverter

The authors of [134] described a further inverter design based on a seven-level CGSC by considering Figure 24f, with fewer switches. By charging capacitors C1, C2, and C3 to Vdc, 2Vdc, and 3Vdc, respectively, the whole seven-level inverter output voltage range can be made with a voltage gain of three. This construction is based on the virtual DC-link principle, just like the aforementioned five-level CGSC-based inverters. Only six power switches are needed, but an extra four power diodes are essential. Since C2 and the input DC source are connected in series, C3 can be charged from either. This charging action is feasible both at zero and at the highest positive output voltage level, +3 Vdc, just as in the five-level CGSC-based inverters given in [86–91]. Additionally, in positive and negative half-cycles of the output voltage, the direction of the load current charges and discharges the DC-link capacitor Cdc. As a result, a higher Cdc and C3 capacitance may be required to reduce the voltage ripple caused by these lengthy discharging cycles.

d. Nine-Level CGSC-based inverter

A nine-level quadruple-voltage-gain CGSC-based inverter is shown in Figure 24g. The consistent MVSs across all the FB-cell switches and the lowered balanced voltage value of the related capacitors make this a compelling design, despite the high number of switching devices it employs. Because bigger values of the capacitance are required in the case of increased power injection requirements, the converter's lengthy discharging cycle for the capacitors may be a major drawback.

The scope of use for SC-MLIs can be expanded as shown in Figure 25, and SC-MLIs are appealing for grid-tied PV-based low-power applications because of their single-stage voltage step-up capability, despite their pulsing input current [86–88]. Other developed applications of SC-MLIs with restricted output power performance include motor drives, electric vehicles, energy storage systems, and balancing in battery strings.

**Figure 25.** Various applications of SC-based multilevel converters/inverters.

As can be seen in Figure 26, we take into consideration ten characteristics to present a comprehensive qualitative overview of the circuit properties of various SC-MLIs.

**Figure 26.** Qualitative comparison analysis of different SC-MLIs in various characteristics.
