*Article* **Synthesis and Characterization of Sn/SnO2/C Nano-Composite Structure: High-Performance Negative Electrode for Lithium-Ion Batteries**

**Jaffer Saddique 1, Honglie Shen 1,\*, Jiawei Ge 1, Xiaomin Huo 1, Nasir Rahman 2, Muhammad Mushtaq 3, Khaled Althubeiti <sup>4</sup> and Hamza Al-Shehri <sup>5</sup>**


**Abstract:** Tin oxide (SnO2) and tin-based composites along with carbon have attracted significant interest as negative electrodes for lithium-ion batteries (LIBs). However, tin-based composite electrodes have some critical drawbacks, such as high volume expansion, low capacity at high current density due to low ionic conductivity, and poor cycle stability. Moreover, complex preparation methods and high-cost carbon coating procedures are considered main challenges in the commercialization of tin-based electrodes for LIBs. In this study, we prepared a Sn/SnO2/C nano-composite structure by employing a low-cost hydrothermal method, where Sn nanoparticles were oxidized in glucose and carboxymethyl cellulose CMC was introduced into the solution. Scanning electron microscope (SEM) and transmission electron microscope revealed the irregular structure of Sn nanoparticles and SnO2 phases in the conductive carbon matrix. The as-prepared Sn/SnO2/C nano-composite showed high first-cycle reversible discharge capacity (2248 mAhg−1) at 100 mAg−<sup>1</sup> with a first coulombic efficiency of 70%, and also displayed 474.64 mAhg−<sup>1</sup> at the relatively high current density of about 500 mAg−<sup>1</sup> after 100 cycles. A low-cost Sn/SnO2/C nano-composite with significant electrochemical performance could be the next generation of high-performance negative electrodes for LIBs.

**Keywords:** Sn/SnO2/C composite anode material; lithium-ion battery (LIBs); energy storage; synthesis; electrochemical performance

### **1. Introduction**

Rechargeable lithium-ion batteries (LIBs) have been used during the last few decades as the main power source of choice with tremendous applications in many fields, such as portable optoelectronics devices, mobile phones, laptops and cameras, etc. [1–4]. However, given the high demands and rapid development of electric vehicles, lithium-ion batteries are now urgently required, especially those with high energy density, a long cycle life, and fast charging capacity [5–7]. A lot of expectations are on LIBs in terms of stable performance to meet the high demands of the current electronic market. However, the conventional anode material graphite (372 mAhg−1) used commercially is incapable of fulfilling the requirement of the current demands of power due to its low theoretical capacity [8–10].

**Citation:** Saddique, J.; Shen, H.; Ge, J.; Huo, X.; Rahman, N.; Mushtaq, M.; Althubeiti, K.; Al-Shehri, H. Synthesis and Characterization of Sn/SnO2/C Nano-Composite Structure: High-Performance Negative Electrode for Lithium-Ion Batteries. *Materials* **2022**, *15*, 2475. https://doi.org/10.3390/ma15072475

Academic Editors: Marc Cretin, Sophie Tingry and Zhenghua Tang

Received: 26 January 2022 Accepted: 15 March 2022 Published: 27 March 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

According to the current demands, it a priority to explore new-generation electrode materials with excellent electrochemical performances, including high lithiation capacity, long cycle lifespan, low cost, and that is eco-friendly, to boost up the overall performances of LIBs. In this context, much work has been done to introduce high-performance electrode materials for LIBs. Among these, metallic tin is a non-toxic, environmentally friendly, lowcost and highly abundantly available metal with outstanding specific theoretical capacity (994 mAhg−1) for LIBs [11,12]. However, metallic tin electrodes have some serious drawbacks concerning the dramatic volume expansion >300% during the lithiation/delithiation process resulting in capacity fading, rapid capacity decay, and low coulombic efficiency, which always limits their potential applications [13,14]. Tin oxide SnOx, specifically SnO2 and SnO, have attracted attention as a potential next-generation anode owing to their high theoretical capacity of 1494 mAhg−<sup>1</sup> and 1273 mAhg−1, respectively [15,16]. In the literature, different strategies have been applied to obtain different structures of tin oxide in order to improve the electrochemical performance [17,18]. By controlling and manipulating important parameters of the SnO2, such as the size of the electrode nanostructure and the confinement of the active material in a carbonaceous matrix to prevent the agglomeration of the nanostructures upon cycling, it is possible to increase the amount of lithium-ion reversibility during conversion reactions [19–21]. During lithiation, the reaction mechanism of SnO2 can be described as two stages: the (1) conversion reaction and (2) alloying reaction, which are given as follows:

In the conversion stage, SnO2 is converted to form Li2O and the elemental Sn as expressed by the following equation:

$$\text{SnO}\_2 + 4\text{Li}^+ + 4\text{e}^- \leftrightarrow 2\text{Li}\_2\text{O} + \text{Sn} \tag{1}$$

which contributes to a capacity of 711 mAhg<sup>−</sup>1.

In the second stage, the alloying reaction taking place can be expressed as the following equation:

$$\text{Sn} + \text{xLi}^+ + 4\text{e}^- \leftrightarrow \text{LixSn} \ (0 < \text{x} < 4.4) \tag{2}$$

to which a further 783 mAhg−<sup>1</sup> can be added over its theoretical capacity, and it can reach as high as 1494 mAhg−<sup>1</sup> [22,23]. Besides these, SnO2 has some drawbacks when used as a negative electrode for LIBs, such as high volume expansion during lithiation, poor conductivity, and large first-cycle capacity, which lead to electrode pulverization and electrical exfoliation of the active material from the current collector and further hinder their application, resulting in poor cycle performance, rapid capacity decay, and low coulombic efficiency [24–26]. Different morphology and nanostructures, and the introduction of Sn-based anode into the carbon matrix are helpful to overcome all these obstacles while utilizing and introducing a negative electrode material for LIBs with such high theoretical capacity [27,28]. Herein, an Sn/SnO2/C nano-composite anode, prepared by facile hydrothermal method, is expected to be able to enhance the performance of LIBs, especially in its real capacity with stable cyclability and coloumbic efficiency. Structural characterizations confirm the existence of Sn and SnO2 in the carbon conductive framework, ensuring Sn/SnO2/C-based LIBs that possess considerable enhancement in terms of cycle stability as well as other enhanced performances.

#### **2. Experimental**

#### *2.1. Preparation of Sn/SnO2/C in Carbon Matrix*

A typical hydrothermal method was used for the preparation of Sn/SnO2/C nanocomposite materials. In detail, the desired molar ratio of tin chloride dehydrate SnCl2·2H2O (99.9%, Aladdin) and Glucose C6H12O6 (99%, Aladdin Nanjing Chemical Reagent Co., LTO) of about 0.02 mole (4.51 g) and 0.02 mole (3.6 g), respectively, were mixed in 50 mL deionized water. The solution was stirred for 15 min and then 4 g (weight %) carboxymethyl cellulose CMC was added slowly and gradually into the solution and continually stirred for more than 2 h in order to get a homogenous solution milky in color. All the reagents

were of the analytical grade and used without any further purification. The solution was then transferred to a 100 mL Teflon-lined autoclave and heated to 200 ◦C and kept at this temperature for 24 h to get the SnOx nanoparticles. The solution was cooled naturally to room temperature and was then centrifuged at 9000 r/min several times. Then, the solution was washed thoroughly by using de-ionized water and ethanol to obtain more pure products. Finally, the products were transferred to a vacuum oven and kept at a temperature of 90 ◦C overnight to dry them. To get the Sn/SnO2/C, the resultant products were ground with the help of a pestle and mortar and then annealed at 800 ◦C at the rate of 5 ◦C/min for 4 h under argon atmosphere. The used carboxymethyl cellulose CMC polymer was converted into carbon after high-temperature treatment by following the annealing process. The experimental steps were exercised repeatedly to make it more accurate.

#### *2.2. Materials Characterization*

The crystalline structure and phase confirmation of the as-synthesized Sn/SnO2/C material was characterized via room temperature powder X-ray diffractometer (XRD) in the range of 10–80◦ on Broker D8 with Cu Kalpha radiation. Scanning Electron Microscopy (SEM model FEI, Quanta 650, HITACHI, Japan) was carried out to analyze the morphological structure of the as-synthesized material. Energy dispersive spectroscopy (EDS) along with SEM was performed to confirm the elemental distribution mapping of the elements contained by the prepared materials. Transmission electron microscopy (TEM) along with selected area electron diffraction (SAED) and high-resolution transmission microscopy (HRTEM, Tokyo, Japan) was performed on EFI Tecnai G2s-Twin instrument with electron gun operating at 200 KV to further confirm the atomic distribution and size of the synthesized Sn/SnO2/C material. X-ray photoelectron spectroscopy (XPS, PHI-5000 VersaProbe Ulvac–Phi Thermo Fischer Scientific Multilab 2000 spectrometer with an Al Kα radiation monochromator at 1486.6 eV) was carried out to confirm the composition and oxidation state of the prepared Sn/SnO2/C material.

#### *2.3. Electrochemical Measurement*

In order to investigate the electrochemical performance of the synthesized Sn/SnO2/C material, working electrodes were prepared by a slurry of 70% active materials, 20% carbon black (conductive agent), and 10% polyvinyl difluoride (PVDF) used as a binder in Nmethy1-2-pyrrolidone (NMP). The mixture was then stirred with a magnetic stirrer for 2 h to obtain a homogenous solution. After that, the slurry was bladed on copper foil (current collector) and then transferred to a vacuum oven at 80 ◦C overnight. The prepared dry electrode was cut into a 12 mm round shape with an active mass of about 1.4 mg, and was pressed at 20 MPa. The coin cells (CR-2032) were assembled inside the glovebox (water and oxygen content < 1), where lithium metal foil was used as a reference and counter electrode. The propylene was used as a separator and 1M LiPF6 in EC:DEC = 1:1 (volume ratio) was used as an electrolyte. The galvanostatic charge/discharge curves were tested using a Land automatic batteries tester (LAND-CT2001A, Wuhan, China) in the potential range of 0–3 V as well at different current densities. The cyclic voltammetry (CV) was tested at a scan rate of 0.1 V at the electrochemical workstation (CHI660D, Shanghai, China). The electrochemical impedance spectroscopy (EIS) tests were also performed in the frequency ranging from 0.01 Hz to 1 MHz to check the ionic conductivity of the prepared electrodes.

#### **3. Results**

We first prepared a Sn/SnO2/C nano-composite by using the facile hydrothermal method along with high-temperature post-treatment of about 800 ◦C. In order to investigate the crystalline and phase confirmation of the prepared materials, X-ray diffraction Broker D8 with Cu Kalpha radiation was performed. Figure 1 shows the XRD pattern of the synthesized Sn/SnO2/C. The XRD pattern shows the prominent diffraction peaks of tin (JCPDS No 90-08570) with high intensity, where some of the diffraction peaks of the SnO2 phase structure were also observed and matched well with the SnO2(JCPDS No 14-1445), which had comparatively very low intensity. The diffraction peaks belonging to the SnO2 crystal structure can be observed in the XRD pattern. The observed diffraction peaks have very low intensity when compared with the prominent phase structure of tin. The X-ray diffraction pattern shows the existence of both structures in the composite, where the low intensity diffraction peaks suggest that the SnO2 phase shows their existence in the synthesized composite material in a low ratio, or the high-intensity peaks depressed their execution in the pattern.

**Figure 1.** XRD pattern of Sn/SnO2/C.

To investigate and characterize the surface and morphological characteristics of the prepared Sn/SnO2/C nano-composite, scanning electron microscope (SEM) was performed and the results are presented in Figure 2. Figure 2a contains the typical low-magnification images of the Sn/SnO2/C nano-composite. It also shows particles irregular in shape as well as size, which may be due to the two different phases generated during the synthesis process. No obvious agglomerates were observed for the tin particles in the pattern. From the high-magnification images presented in Figure 2b, it can be seen clearly that the irregularity in terms of size and shape is due to the transformation of glucose and carboxymethyl cellulose (CMC) into carbon matrix during carbonization and the hightemperature (800 ◦C) treatment. The observed irregularity of the particles in the presented Figure 2a,b, suggests that the prepared Sn/SnO2/C nano-composites were inter-connected with each other, which created short pathways and more chances for the penetration of electrolytes and more Lithium-ion diffusion. Energy dispersive spectroscopy (EDS) along with SEM was performed to confirm the elemental mapping for the Sn/SnO2/C nanocomposite and the results are shown in Figure 2c–f. It can be seen in the figure that tin agglomerates are distributed in the carbon matrix; the existence of oxygen mapping in Figure 2f can also be observed. No other contaminations were observed for other particles, which confirms that Sn and SnO2 particles were distributed in the carbon matrix and further clarifies the even distribution of the Sn in the carbon matrix.

**Figure 2.** (**a**,**b**) SEM images; and (**c**–**f**) EDS and the corresponding elemental mapping Sn, C and O of as-prepared Sn/SnO2/C nano-composite.

Transmission electron microscope (TEM) analysis along with high-resolution transmission electron microscope (HRTEM) and selected area electron diffraction (SAED) analysis was performed to investigate and obtain more structural information of the as-prepared Sn/SnO2/C nano-composite anode, as shown in Figure 3. The presented TEM image in Figure 3a shows the even distribution of Sn and SnO2 nanoparticles in the carbon matrix. The SAED pattern in Figure 3b shows different lattice fringes, where in fact no obvious patterns can be differentiated easily for any specific phases, which further confirms and indicates the formation of a complex composite structure. A high-resolution TEM was used to reveal the lattice fringes of the prepared Sn/SnO2/C nano-composite as shown in Figure 3c–e. In the HRTEM image of Figure 3c, two different crystalline domains are embedded in the carbon matrix and are enlarged in the selected area of the image and are further presented in Figure 3d,e to confirm information about their lattices. In Figure 3d, the crystalline structure of Sn with its (200) planes can be identified. Figure 3e contains a SnO2 crystalline structure with its (110) planes. The inter-atomic spacing distance of 0.293 nm [29] and 0.334 nm [30] corresponding to (200) and (110) for both Sn and SnO2 match well with the XRD results. The observed lattice fringes of the SnO2 crystal structure in Figure 3e confirm their existence in the carbon matrix as well in the composite. The corresponding TEM and HRTEM images confirm the Sn/SnO2/C nano-composite phase and distinguish two crystalline structures embedded in the carbon matrix. As the literature reports, Sn itself as an anode suffers from high volume expansion, whereas SnO2 tends to agglomerate into large particles, both of which induce the fading of the performance of the battery. So, fabricating a composite structure has advantages such as controlling the volume expansion of Sn and depressing the agglomerates of the SnO2, which is expected to improve the reaction efficiency of the Sn/SnO2/C composite structure.

The chemical composition and oxidation states of the as-prepared Sn/SnO2/C nanocomposite was further scrutinized via X-ray photo electron spectroscopy (XPS), as shown in Figure 4a–d. In the low-resolution survey spectra depicted in Figure 4a, the typical peaks of carbon, tin, and oxygen can be identified, indicating the purity of the synthesized Sn/SnO2/C nano-composite samples. As shown in Figure 4b, two strong characteristic peaks belonging to Sn3d5/2 and Sn3d3/2 of Sn/SnO2/C can be observed at 487.2 and 496.6 eV [31]. These characteristic bands of Sn/SnO2/C confirmed the oxidation of Sn into Sn+4 states [32]. Figure 4c represents the high-resolution spectra of Cs1 at 286.1 eV, which

further confirm the existence of carbon in the composite sample. The major peak of carbon in the spectra indicates the existence of C species in the Sn/SnO2/C nano-composite.

**Figure 3.** (**a**) TEM image of the Sn/C composite; (**b**) SAED pattern of the composite; and (**c**–**e**) HRTEM and enlarged image of the Sn/SnO2/C nano-composite.

Figure 4d shows the high-resolution spectra of Os1 with maximum intensity at 533.6 eV attributed to the C–O bonding functional group, which further contributes to the reversibility of LiO2 during the cycling process [33].

In order to explore the electrochemical performance of the prepared Sn/SnO2/C nano-composite, half-coin cells were assembled in a glovebox where metallic Li foils were used as counter and reference electrodes, and the corresponding synthesized Sn/SnO2/C nano-composite materials were used as a negative electrode. The measured electrochemical performance of the Sn/SnO2/C nano-composite is depicted in Figure 5a–c. The cyclic voltammetry (CV) results were tested in the potential window ranging from 0.01 to 3 V (vs. Li+/Li) at a scanning rate of 0.1 mV s−<sup>1</sup> for the initial five cycles for LIBs and are shown in Figure 5a. As observed in Figure 5a, in the first cycle there were six cathodic peaks appearing at different voltages and are identified at 0.338 V, 0.76 V, 1.5 V, 1.7 V, 1.8 V and 2.8 V, respectively. All the observed peaks in the first cycle disappeared, which was attributed to the solid electrolyte interphase (SEI) layer forming on the surface of the active electrodes. Moreover, all the observed oxidation and reduction peaks in the subsequent cycles are distinct and overlap each other, which indicates a stable electrochemical performance. The

characteristic electrochemical reduction and oxidation peaks reflect the electrochemical behavior of the Sn and SnO2 anodes in one electrode system for LIBs.

**Figure 4.** XPS spectra of Sn/SnO2/C: (**a**) survey scan; (**b**) Sn3d spectra; (**c**) C1s spectra; and (**d**) O1s spectra.

The measured electrochemical impedance (EIS) of the Sn/SnO2/C nano-composite for LIBs is shown in Figure 5b. In general, a Nyquist plot contains a semicircle and a straight line representing charge transfer in high frequency and lower frequency regions, respectively. The depicted EIS results in Figure 5b show lower resistance with a high rate diffusion of Li-ion in the Sn/SnO2/C nano-composite's negative electrode for LIBs. The inset in Figure 5b represents the EIS results measured for pure Sn as a negative electrode for LIBs, which show high conductivity in a low-frequency range. The absence of the high-frequency region may be due to the ESI layer formation/ decomposition in the pure Sn electrode system which further enhanced the diffusion rate of Li-ion in the Sn/SnO2/C nano-composite electrode for LIBs. Figure 5c represents the cycle performance of the Sn/SnO2/C nano-composite electrode and pure tin electrode for LIBs measured at 100 and 500 mAg−<sup>1</sup> current densities in a potential range 0–3 V for 100 cycles. The first 5 cycles were measured at 100 mAg−<sup>1</sup> and the remaining 90 cycles were measured at 500 mAg−1. The initial discharge capacity of the Sn/SnO2/C nano-composite was 2248 mAhg−<sup>1</sup> with coulombic efficiency 70% of first charge/discharge capacity and a 99% capacity was maintained for the remaining cycles, even at high current density. In Figure 5c, we can also see the cycle performance of the pure tin electrode measured at same current densities in order to compare the cycle performance of both electrodes. Here, we can see the capacity drops after a few cycles at high current density; high capacity decay may be due to the high volume expansion or because of the low ionic conductivity of the tin electrode for LIBs. On the other hand, the discharge capacity decreased to 1685 mAhg−<sup>1</sup> in the second cycle for the Sn/SnO2/C nano-composite electrode and then maintained

up to 95% for the remaining cycles. The first high discharge capacity may be attributed to the SEI layer on the surface of the electrode which further decomposed in subsequent cycles as a result of a large amount of capacity decay. It is believed that such a high capacity with excellent coulumbic efficiency may be attributed to the combination of Sn and SnO2 in the conductive carbon matrix [34]. The Sn/SnO2/C nano-composite shows a high reversible capacity of about 489 mAhg−<sup>1</sup> at the 100th cycle. As a result, the Sn/SnO2/C nano-composite showed enhanced electrochemical performance for LIBs and could be a promising candidate as a negative electrode for future prospects.

**Figure 5.** Electrochemical performance of Sn/SnO2/C nano-composite for LIBs: (**a**) initial five cyclic voltammetry curves scanned from 0.01 to 3 V at a rate of 0.01 mV s<sup>−</sup>1; (**b**) EIS of Sn/SnO2/C nano–composite; and (**c**) cycle performance of Sn/C electrode acquired at two different current densities of about 100 mA g−<sup>1</sup> and 500 mAg<sup>−</sup>1.

#### **4. Conclusions**

In this work, a Sn/SnO2/C nano-composite was synthesized via a hydrothermal method as an anode for LIBs. The basic structural characterization performed using SEM and TEM revealed the existence and homogenous distribution of the Sn nano-particles and SnO2 in the carbon matrix, which significantly enhanced the ionic conductivity of the electrode and buffered the volume expansion during repeated lithiation/delithiation processes. Moreover, the synthesized Sn/SnO2/C nano-composite showed high initial first-cycle discharge capacity (2248 mAhg−1) at 100 mAg−<sup>1</sup> with a first-cycle coulombic efficiency of 70% and also displayed 489 mAhg−<sup>1</sup> at a relatively high current density of about 500 mAg−<sup>1</sup> after 100 cycles. As a result, high electrochemical active and crystalline nanoparticles embedded in the carbon matrix anode were achieved. The improved electrochemical performance of the prepared Sn/SnO2/C nano-composite enables it to be a promising anode for next-generation LIBs.

**Author Contributions:** Conceptualization and formal analysis, J.S., J.G.; investigation, J.S. and X.H.; Methodology, J.G. and X.H.; writing-origional draft preparation, J.S.; editing, N.R. and M.M.; writing review, J.S., M.M.; formal analysis, N.R. and H.A.-S.; Investigation, H.A.-S. and K.A.; project administration, K.A. and H.S.; funding acquisition, K.A. and H.S.; Supervision, H.S. All authors have read and agreed to the published version of the manuscript.

**Funding:** The authors gratefully acknowledge the National Natural Science Foundation of China (Grant No. 61774084), the Special Scientific Innovation Found of Sihong County (H201901) and the open project of Key Laboratory of Materials Preparation and Protection for Harsh Environment, Ministry of Industry and Information Technology (XCA20013-3). In addition, the authors extend their appreciation to Taif University Researchers Supporting Project number (TURSP-2020/241), Taif University, Taif, Saudi Arabia.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** Data sharing is not applicable for this article.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


### *Article* **New n-p Junction Floating Gate to Enhance the Operation Performance of a Semiconductor Memory Device**

**Yi-Yueh Chen \*, Su-Jien Lin and Shou-Yi Chang**

Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan; sjlin@mx.nthu.edu.tw (S.-J.L.); changsy@mx.nthu.edu.tw (S.-Y.C.)

**\*** Correspondence: yychen@mxic.com.tw; Tel.: +886-3-578-6688

**Abstract:** To lower the charge leakage of a floating gate device and improve the operation performance of memory devices toward a smaller structure size and a higher component capability, two new types of floating gates composed of pn-type polysilicon or np-type polysilicon were developed in this study. Their microstructure and elemental compositions were investigated, and the sheet resistance, threshold voltages and erasing voltages were measured. The experimental results and charge simulation indicated that, by forming an n-p junction in the floating gate, the sheet resistance was increased, and the charge leakage was reduced because of the formation of a carrier depletion zone at the junction interface serving as an intrinsic potential barrier. Additionally, the threshold voltage and erasing voltage of the np-type floating gate were elevated, suggesting that the performance of the floating gate in the operation of memory devices can be effectively improved without the application of new materials or changes to the physical structure.

**Keywords:** semiconductor device; memory cell; floating gate; n-p junction; charge leakage

#### **Citation:** Chen, Y.-Y.; Lin, S.-J.; Chang, S.-Y. New n-p Junction Floating Gate to Enhance the Operation Performance of a Semiconductor Memory Device. *Materials* **2022**, *15*, 3640. https:// doi.org/10.3390/ma15103640

Academic Editors: Zhenghua Tang, Marc Cretin and Sophie Tingry

Received: 1 April 2022 Accepted: 16 May 2022 Published: 19 May 2022 Corrected: 28 September 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

#### **1. Introduction**

Memory devices, one of the most typical and popularly used electronic devices, generally comprise a plurality of gate structures, which include a control gate and a floating gate [1,2]. The floating gate is a conductive layer normally fabricated from polysilicon that is positioned between the control gate and a silicon substrate [1,2]. The floating gate is not attached to any electrodes or power sources and is generally surrounded by an insulation material [1,2]. The operation of the memory cells is dependent upon the charge stored in the floating gate at the threshold voltage to represent information in these memory devices [3,4]. The performance of the memory cells is determined by the programming speed, which is dominated by the speed of the erasing and writing operations [1,2]. The speed is basically limited by the rate at which electrons can be pumped into (writing) and out of (erasing) the devices without causing damage to the device [1,5–7]. Typically, writing and erasing operations must be capable of operating within 1 ms at a specified applied voltage [1,6,8–11].

Aiming at a higher capability but a smaller chip size, the semiconductor industry has been increasingly driven towards smaller and more numerous electronic devices, including memory cells [2,12,13]. To reduce the size and accordingly increase the number of such devices, while simultaneously maintaining or even improving their respective capabilities, the size of components and the distance between such components need to be reduced [2,14,15]. However, as the cell size is reduced, some other issues arise that prevent a further reduction in size [15,16]. One of these issues is that charge leakage from the floating gate may increase, thereby deteriorating the performance of the devices as the individual layers of the gate structures are made smaller and placed closer to each other [15]. In particular, the tunneling oxide will be more seriously damaged with more programming and erasing sequences, resulting in more charge leakage [15]. In order to overcome the issue of charge leakage, many device structures have been proposed, e.g., SONOS, BE-SONOS, TAHOS and 3D FLASH [6,17–20]. The 3D NAND FLASH structure was proposed as a solution when 2D NAND FLASH reached the scaling limit of a 15 nm process node [21]. Furthermore, the ReRAM [8,22], PCRAM [23,24], FeRAM [25,26] and MRAM [27,28] devices have also attracted much attention in the past two decades as promising candidates for the next generation of nonvolatile memory cells with improved performance. However, new semiconductor devices with markedly shrunken gate structures and reduced charge leakage that do not sacrifice their performance or suffer from environmental contamination are still elusive.

Hence, in this study, two new floating gate structures, including a p-n junction and an n-p junction, were designed, investigated and processed on 300 mm wafers. In these new designs, no extra new material needs to be employed, no new process needs to be developed and no contamination risk needs to be considered when the devices are processed at the semiconductor manufacturing factory. By forming an n-p junction instead of a p-n junction in the first conductive layer (the floating gate), the charge leakage across the second dielectric layer (the inter-polysilicon dielectric layer) may be reduced. This n-p junction interface is anticipated to provide an intrinsic potential barrier to inhibit the leakage path, successfully reducing the charge leakage and enlarging the programming and erasing window. Additionally, upon the reduction of the charge leakage across the second dielectric layer, the second dielectric layer can be made thinner and/or even be completely removed from wrapping the first conductive layer. The gate structure can thereby be made more compact, allowing a smaller semiconductor device without sacrificing the performance of the device.

#### **2. Materials and Methods**

#### *2.1. Device Fabrication*

NAND FLASH memory devices with two new floating gate structures were fabricated on p-type 300 mm silicon (Si) wafers with n+ junctions. As shown in Figure 1, the memory devices comprise the Si substrate, the first dielectric layer (tunneling oxide, denoted as TUN OX) disposed along the substrate, and the first conductive layer (floating gate, FG) disposed along the first dielectric layer (Figure 1a,c, schematically illustrated from the Xand Y-direction cross-sections, respectively). The second dielectric layer (inter-polysilicon dielectric, IPD) is disposed along the sidewall of the first conductive layer, and the second conductive layer (control gate, CG, such as n-type polysilicon) is afterwards deposited. Two new types of the first conductive layer, i.e., the floating gate, were proposed, including the pn-type (a bottom "p+" region followed by a top "n+" region) polysilicon and the np-type (bottom "n+" followed by top "p+") polysilicon, for which a high-temperature chemical vapor deposition (CVD) boron-doping polysilicon process and a high-temperature furnace phosphorous-doping polysilicon process were applied at 500 ◦C, in sequence or vice versa. The thickness ratio of the bottom-to-top regions of the pn-type or np-type polysilicon was designed to be around 1:3. For comparison, a conventional floating gate (the control split) was also prepared, with single n+ polysilicon as the first conductive layer. The concentration of dopants in the n-type and p-type polysilicon was around <sup>1</sup> × <sup>10</sup><sup>19</sup> cm−<sup>3</sup> and 1 × <sup>10</sup><sup>21</sup> cm<sup>−</sup>3, respectively.

**Figure 1.** (**a**) Schematic illustration and (**b**) cross-sectional TEM image of memory cells around floating gates with np-type polysilicon from the X-directional view; (**c**) schematic illustration of memory cells from the Y-directional view; (**d**) SIMS depth profile of elemental distribution along the floating gate.

#### *2.2. Characterization and Measurement*

Thin foils (cross-sectional) of the memory devices around the floating gates were cut by using a focused ion beam system (USA, FIB, FEI Expida1265) and milled with an ultralow current, and the microstructure was observed by using a transmission electron microscope (Netherlands, TEM, FEI Osiris). The depth profile of elemental compositions along the floating gates for understanding the distribution of dopants was determined by using a secondary ion mass spectrometer (France, SIMS, AMETEK ims-6f). The sheet resistance (Rs) of the floating gates, programing threshold voltage (Vth) and erasing voltage (Ver) were measured by using a WAT system (USA, Keysight, 4082F). The charge simulation of the floating gates was performed by the TCAD (Technology Computer-Aided Design).

#### **3. Results and Discussion**

#### *3.1. Microstructure and Chemical Composition*

Figure 1b shows the cross-sectional TEM microstructure of the memory cells around the floating gates with np-type polysilicon from the X-directional view. Clearly, the tunneling oxide layer is disposed between the floating gates and the substrate, and the interpolysilicon dielectric layer is uniformly deposited on the floating gates. The image contrast indicates two regions in the floating gates: the bright region at the top and the dark region

at the bottom, and the thickness ratio of the bottom-to-top regions is roughly estimated to be around 1:3. As further illustrated in Figure 1d, the SIMS depth profile along the floating gate confirms four regions of elemental distribution along the floating gate, from top to bottom: (1) the top p+ polysilicon for a thickness of about 60 nm, with a silicon element; (2) the bottom n<sup>+</sup> polysilicon for 20 nm, with silicon and a high concentration of phosphorous dopants; (3) the tunneling oxide and (4) the silicon substrate. It was noted that in region (1), boron dopants were not present due to the improper collection condition of light-ionized boron signals from the uneven film structure of the sample instead of a planar/blanket one. However, the gradually dropping intensity of silicon might reveal the existence of other elements that were very likely boron.

#### *3.2. Sheet Resistance and Charge*

Figure 2 presents the cumulative probability plot and box plot of sheet resistance for three different floating gates, including the control split and the new pn-type and np-type floating gates. Clearly, the sheet resistance of the new floating gates was higher than that of the control split, (i.e., about 1.7 times for the pn-type floating gates and 2.1 times for the np-type floating gates), which was plausibly caused by the formation of a depletion zone and the narrowed channels for current flow. When a forward bias was applied to the np-type floating gate, or a reverse bias was applied to the pn-type floating gate, a depletion zone of carriers would be formed at the n-p or p-n junction interface [28–32], leading to an open circuit at the bottom region of the floating gates. Current flow was therefore allowed only through the top p<sup>+</sup> or n<sup>+</sup> polysilicon paths, respectively, and the narrowed channel would thus result in increased resistance, particularly for the np-type floating gates, as the mobility of holes in the p<sup>+</sup> polysilicon path was lower than that of electrons in the n+ polysilicon path [29,30].

**Figure 2.** (**a**) Cumulative probability plot of sheet resistance of floating gates (30 data points for pn FG and np FG, and 20 data points for the control split). (**b**) Box plot of sheet resistance (center line: median of the data; top line: Q3, the upper quartile; bottom line: Q1, the lower quartile).

As illustrated in the band diagrams of the neutral and charged states of these three floating gates in Figure 3a,c, different band structures are expected. For the conventional ntype polysilicon floating gate (the control split, Figure 3a) at a programing voltage (positive bias, ΔV) applied to the control gate, the energy band near the control gate will bend downward for ΔV to form a channel near the tunneling oxide for carriers to tunnel through the tunneling oxide into the floating gate for programming [1,2]. The charge in the floating gate depends on the gate coupling ratio (GCR) to influence the efficiency of the device programming [13,33]. In comparison, for the pn-type polysilicon floating gate (Figure 3b) and the np-type polysilicon floating gate (Figure 3c) at a thermal equilibrium state, the Fermi level (Ef) is close to the valence band in the p+ region (conduction by holes) and close

to the conduction band in the n+ region (conduction by electrons). At a constant Fermi level, the distributions of carriers as well as the energy levels of the conduction band (Ec) and valence band (Ev) are thus different in the p<sup>+</sup> and n+ regions at the neutral state, and a depletion zone (a thin region with very few carriers) of high electrical resistance will accordingly be formed at the p-n or n-p junction interface [29–32].

**Figure 3.** Band diagrams of the natural and charge states of (**a**) conventional n-type polysilicon floating gate (the control split), (**b**) pn-type polysilicon floating gate, and (**c**) np-type polysilicon floating gate. Charge simulations for (**d**) conventional n-type floating gate (the control split), (**e**) pn-type floating gate, and (**f**) np-type floating gate (Vg 20 V: programming state, Vg 0 V: retention state).

When a programming voltage ΔV is applied to the control gate, the energy band bends downward, and the carriers will tunnel through the tunneling oxide into either the pnor the np-type floating gate in the same way as the conventional floating gate. However, owing to the different space charge distributions in the p+ and n<sup>+</sup> regions, electrons stay mainly in the n+ region [29,34]. The carriers (electrons) into the pn-type floating gate will induce a reverse bias in the p-n junction to cause the expansion of the depletion zone and the shrinkage of the top n<sup>+</sup> region for carrier storage, therefore reducing the total stored charge. On the contrary, in the np-type floating gate case, a forward bias will lead to the contraction of the depletion zone and the extension of the bottom n+ region for carrier storage, which in turn increases the total stored charge. In addition, because the bottom n<sup>+</sup> region is close to the tunneling oxide channel and has a low energy barrier for programming, and the top p+ region is adjacent to the inter-polysilicon dielectric and has a high energy barrier, the charge leakage of the control gate is expected to be inhibited, which aids in improving the programming efficiency and elevating the programming threshold voltage (Vth) of the np-type floating gate as investigated below.

Furthermore, the charge simulations given in Figure 3d–f confirm the aforementioned assumption regarding charging in the three different floating gates. When the voltage applied to the control gate (Vg) is switched from 20 V (the programming state) to 0 V (the retention state), as expected, there is no change in the amount or distribution of charge in the conventional floating gate (the control split, Figure 3d), since the n-type floating gate is simply composed of a single material (n+ polysilicon). However, the charge is obviously redistributed, and a part of the charge is lost in the pn-type and np-type floating gates when the gate voltage Vg is switched. Clearly, at Vg = 20 V, the charge in the n<sup>+</sup> or p+ region of the np-type floating gate is larger than that of the pn-type floating gate. At Vg = 0 V, in addition to the fact that more charge in the n<sup>+</sup> region of the np-type floating gate is retained, a portion of charge in the p<sup>+</sup> region is retained as well, suggesting that this n-p junction design in the floating gate will benefit the retention of charge, particularly because the p<sup>+</sup> region is much farther away from the tunneling oxide, making it less likely that a charge leakage will occur.

#### *3.3. Threshold Voltage and Erasing Voltage*

Two other important factors dominating the programming (writing) window and performance of memory devices include the threshold voltage (Vth, the gate voltage required to create strong inversion under the gate when the floating gate contains the electrons [35]) and the erasing voltage (Ver, the voltage required for removing the stored charge (electrons) in the floating gates [36]). When the gate voltage is below the threshold voltage, this device is no longer in strong inversion. This region of device operation is called the "cutoff", which corresponds to a logical "0" stored in the cell [37]. A higher threshold voltage yields a wider programming window and thereafter benefits more precise control over the read operation state of the devices. For example, two states with programming threshold voltages of 4 V and 2 V define a memory window, ΔV, of 2 V, which is clearly better than a window of 1.5 V attained in the case where the programming threshold voltages of the 0 and 1 states are, respectively, 3 V and 1.5 V. On the other hand, a higher erasing voltage is conducive for a more stable state and more effective retention of the stored charge in the memory devices. However, a higher programming threshold voltage may also cause a more serious impact on the tunneling oxide and induce larger current leakage to lower the erasing voltage.

As mentioned above and presented below in Figure 4, the new types of floating gates, in particular the np-type, are observed to effectively improve the performance of the memory devices fabricated without the application of any new materials or changes to their physical structure. As clearly seen in the cumulative probability plot and box plot, the programming threshold voltage of the np-type floating gate was as high as about 1.2 times that of the conventional one (the control split) and much higher than that of the pn-type one (Figure 4a,b), while the erasing voltage of the np-type floating gate was close to that of the conventional one and also higher than that of the pn-type one, both suggesting the better performance of the np-type floating gate in controlling the operation of the memory devices (Figure 4c,d). The erasing voltages of the floating gates that we showed in Figure 4 were actually measured with a deliberately designed test key to check the floating gate state after the charges of the floating gate were cleaned up by applying a high voltage on the substrate. The lower the |Ver|, the easier it is for the cell to be turned on, which typically corresponds to a logical "1" stored in the cell. The degradations of the programming and erasing operation (after 3000 cycles) were also investigated to understand the performance of the different types of floating gates, as given in Figure 5. It was clear that the np-type floating gate showed a much better performance than the pn-type one and had the same performance as the control split, indicating no extra current leakage from the tunneling oxide even at a higher threshold voltage.

**Figure 4.** (**a**) Cumulative probability plot of programming threshold voltage of floating gates. (**b**) Box plot of programming threshold voltage. (**c**) Cumulative probability plot of erasing voltage of floating gates. (**d**) Box plot of erasing voltage (center line: median of the data; top line: Q3, the upper quartile; bottom line: Q1, the lower quartile).

**Figure 5.** (**a**) Cumulative probability plot of degradation of programming voltage of floating gates. (**b**) Box plot of degradation of programming voltage. (**c**) Cumulative probability plot of degradation of erasing voltage of floating gates. (**d**) Box plot of degradation of erasing voltage (all after 3000 cycles; center line: median of the data; top line: Q3, the upper quartile; bottom line: Q1, the lower quartile).

#### **4. Conclusions**

In summary, a new np-type floating gate with n-p junction polysilicon (bottom "n+" followed by top "p+" with a thickness ratio of 1:3) was developed in this study to reduce the charge leakage and improve the operation performance of memory devices. A depletion zone of carriers was formed at the n-p junction interface, leading to a narrowed channel and thus an increased sheet resistance that was 2.1 times that of the conventional floating gate. The relatively high charge storage and retention in the np-type floating gate is able to inhibit the charge leakage, owing to the high energy barrier at the n-p junction interface. Moreover, the programming threshold voltage difference between the 0 and 1 states (i.e., the memory window) of the np-type floating gate was effectively elevated by 1.2 times, while the erasing voltage and its degradation were close to that of the conventional one, indicative of no extra current leakage even at a higher programming threshold voltage and the better operation performance of the memory devices.

**Author Contributions:** Conceptualization, Y.-Y.C.; methodology, Y.-Y.C.; formal analysis, Y.-Y.C.; investigation, Y.-Y.C.; resources, Y.-Y.C.; data curation, Y.-Y.C.; writing—original draft, Y.-Y.C. and S.-Y.C.; writing—review & editing, Y.-Y.C. and S.-Y.C.; supervision, S.-J.L. and S.-Y.C.; project administration, Y.-Y.C.; funding acquisition, S.-J.L. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by Macronix International Co., Ltd.

**Institutional Review Board Statement:** Not Applicable.

**Informed Consent Statement:** Not Applicable.

**Data Availability Statement:** The data presented in this study are available on request from corresponding author.

**Acknowledgments:** The authors gratefully acknowledge Macronix International Co., Ltd. for their support and technical discussions about this work.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**

