**1. Introduction**

Photovoltaic generation has been paid more attention recently because of the shortage of fossil fuels and the increasingly serious levels of environmental pollution, which play an important role in PV systems [1]. Compared with previous 1000 V systems, the 1500 V system reduces the number of cables and PV plants, and decreases the line cost and conduction loss [2,3]. Moreover, it provides more voltage range which is used to ensure maximum power point (MPPT) availability by controlling front-end circuits or adjusting the grid-connected voltage [4,5].

Nowadays, multilevel inverters such as the five-level inverter have gained much attention for their high equivalent switching frequency and low voltage stress, which are benefits for increasing the inverter's power density [6,7]. The neutral-point-clamped (NPC) inverter, flying capacitor (FC) inverter and T-type inverter are traditional three-level inverters which have been widely employed in industrial application. The NPC inverter is generally adopted in centralized PV grid-tied inverters because of its simple operation principle and high power level capability [8,9], which are different from the demands of PV string inverters. When used in low bus voltage applications, the T-type inverter is suitable on account that it can reach a higher work frequency, higher conversion efficiency, and higher power density [10,11]. The unbalance of neutral-point voltage is the main issue in multilevel inverters, except in the FC inverter [12]. However, one more floating capacitor is added in each phase, resulting in a larger volume and poorer power density, and its control scheme is more complex.

**Citation:** Chen, G.; Yang, J. A Modified Modulation Strategy for an Active Neutral-Point-Clamped Five-Level Converter in a 1500 V PV System. *Electronics* **2022**, *11*, 2289. https://doi.org/10.3390/ electronics11152289

Academic Editors: Luis Hernández-Callejo, Jesús Armando Aguilar Jiménez and Carlos Meza Benavides

Received: 18 June 2022 Accepted: 19 July 2022 Published: 22 July 2022

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**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

Many efforts have been made on topologies for photovoltaic multilevel inverters. Five-level topology reduces both the voltage stress of semiconductor devices and the volume of filter inductance compared with three-level topology due to its better harmonic performance, which may lead to loss reduction and system cost reduction. NPC-5L is the usual topology used for five-level topology [13], in addition to other topologies such as cascaded H-bridge five-level (CHB-5L) and FC five-level (FC-5L). Problems such as relatively large switching losses, unbalanced voltages of capacitors, and poor stability have promoted research into five-level topologies [14]. Other different topologies of multilevel inverters have also been adopted in industrial application: the stacked multi-cell (SMC) [15], the H-bridge NPC (H-NPC) [16], the neutral-point piloted (NPP) [17], and the modular multilevel converter (MMC).

The ANPC-5L converter, as shown in Figure 1, has been paid more and more attention since it was proposed [18,19], and is the combination of two types of inverters. One is the FC three-level inverter, the other is the active NPC three-level inverter. The advantages of this inverter consist of low switching losses and the convenience of capacitor voltage balance [20,21]. Switches which are connected in series in this topology switch at fundamental frequency, while the others switch at carrier frequency. Meanwhile, the switching cost of this topology is low because the stress of the switches is VDC/4, while VDC is the voltage of DC-link. Moreover, if different switching states are chosen appropriately, the voltage of floating capacitors is easy to balance.

**Figure 1.** Topology of the ANPC-5L inverter.

Researchers have carried out a lot of work on ANPC-5L modulation technology, flying capacitor voltage control, neutral-point voltage control, and other issues [22,23]. The modulation strategy of the ANPC-5L inverter is simple and reliable most of the time. However, less attention has been paid to the voltage stress of switching devices in ANPC-5L converters, and the voltage stress of switching devices is very important for the safe and reliable operation of inverters. Document [24] analyzes the operation state of inverters based on space vector pulse-width modulation, including 125 vector combinations, and limits the stress of the switching devices by using the safe switching state switching process. Meanwhile, under the conventional modulation scheme, the analyzed inverter has the security risk of overvoltage in the power device when switching to dead time at the zero-crossing point of voltage when the output current is inductive, which affects the commutation safety [25].

In this article, this issue is analyzed in detail and a modified modulation strategy is proposed. In comparison with other modulations, this method provides several free degrees which are used to ensure the elimination of the voltage stress of power devices by choosing favorable circuit states and controlling current commutations. Additionally, it can realize the flying capacitor voltage balance in several carrier wave periods. The implementation of the proposed strategy in digital systems is rather simple. Meanwhile, a novel soft start-up method adopted to the ANPC-5L inverter is also proposed. Experimental results prove that the proposed strategy is valid.

The rest of the paper is organized as follows. Section 2 presents the traditional switching states. Section 3 analyzes the power device's overvoltage issue in detail. Section 4 proposes the modified modulation strategy to solve the potential safety hazards. Section 5 proposes a control method for soft start-up. Section 6 illustrates an inverter prototype for analysis verification. The conclusions are given in Section 7.

#### **2. Traditional Modulation Strategy**

As shown in Figure 1, the ANPC five-level inverter has eight power switches S1–S8, a floating capacitor CF, a upper capacitor CUP, and a lower capacitor CDOWN. For the ANPC-5L inverter, as shown in Table 1, the conventional modulation scheme uses eight basic switching states to produce five voltage levels. There are redundant states at the +E and −E levels (E is 1/4 of bus voltage VDC) which affect the charging or discharging states of the floating capacitors. The balance of the floating capacitor voltages can be realized by choosing appropriate switching states.


**Table 1.** Traditional switching states of the ANPC-5L inverter.

The harmonics of the phase disposition (PD) contain a few carrier harmonics because of the different phases of the four carrier waves, as well as DC components, fundamental components, and carrier sidebands. However, some other modulation schemes, such as alternative phase opposition disposition (APOD), phase opposition disposition (POD), and two kinds of phase-shift carriers (PSC), have no carrier harmonics. In terms of singlephase inverters, the harmonic performance of the above-mentioned modulation is just the same due to the signal–energy conservation law. As far as the three-phase system is concerned, the harmonics are quite different. When the carrier waves of the three-phase system are synchronous, the carrier harmonics of the adjacent phases will exactly coincide, which represents that this harmonic will not appear in line voltage. However, carrier sidebands have no similar features. The harmonic performance of PD is the best. The next is APOD and PSC. The worst is POD. The characteristics of line voltage spectrums are far more diverse in the cause of common mode voltage. Eventually, considering the harmonic performance, the PD-PWM method is preferable among various methods. Under the traditional PD modulation of the ANPC-5L inverter, there are four cascaded carrier waves. As shown in Figure 2, comparison with the first carrier wave makes the output voltage change between +2E and +E. Switching between these states changes only two switch devices, and the switching processes are safe. Similarly, the switching processes in comparison with the other carrier waves are also reliable.

**Figure 2.** Traditional modulation strategy of the ANPC-5L inverter.

#### **3. Overvoltage Issue of Traditional Modulation**

However, there are potential overvoltage issues in the conventional modulation scheme. As shown in Figure 3, according to the counter mode of up–down or down– up, the output voltage will change from +E to −0 or from +0 to −E. Unlike the former switching process, switching between these two states changes six switch devices. Although the dead time of each pair of devices' switch exists, there will be safety problems under certain circumstances.

**Figure 3.** Switching process at zero crossing point.

As shown in Figures 4 and 5, taking the change from +0 to −E as an example, the circuit changes from state V5-1 to V2-1. Due to the existence of the dead zone, all the devices are turned off and there will be an intermediate state (VDANGER (S1-S8:01000000)), which will cause the overvoltage issue.

**Figure 4.** Traditional switching process of the ANPC-5L inverter.

**Figure 5.** Switching states V5-1 and V2-1 at zero crossing point. (**a**) Switching states V5-1. (**b**) Switching states V2-1.

A detailed analysis is presented as below. In the state of V5-1, the initial states of the parasitic capacitance of the MOSFETs are shown in Figure 6; S3 has a potential difference of E while S6 has 2E. During the dead time of S5, assuming the output current IO is greater than zero, S3 and S4 are all off. The continuous current path is shown in Figure 6, and the final states of the parasitic capacitance decide the safety of the commutation process.

**Figure 6.** (**a**) Initial potential difference of V5-1. (**b**) Potential difference of VDANGER. (**c**) Equivalent circuit of the charging process from V5-1 to VDANGER.

During the dead time, S3, S5 and S6 are all off, closed switches equivalent to parasitic capacitances. Therefore, as shown in Figure 6, the equivalent circuit of the switching process is equal to the charging of parasitic capacitances.

Because of the charge–balance principle, increased charge on S3 should be equal to the summation of increased charge on S5 and reduced charge on S6. Moreover, the sum of the voltages of the S5 and S6 constants is equal to 2E, and the increased voltage on S5 is equal to the reduced voltage on S6. According to the capacitance definition:

$$dQ = \mathbb{C} \cdot d\mathcal{U} \tag{1}$$

Equation (2) can be obtained:

$$\mathbf{C}\_p \cdot d\mathbf{U}\_{S5} + \mathbf{C}\_p \cdot d\mathbf{U}\_{S6} = \mathbf{C}\_p \cdot d\mathbf{U}\_{S6} + \mathbf{C}\_p \cdot d\mathbf{U}\_{S6} = 2\mathbf{C}\_p \cdot d\mathbf{U}\_{S3} \tag{2}$$

The voltage of endpoint O changes from +E to −E by focusing on the steady state of −E, and according to Kirchhoff's Voltage Law (KVL) Equation (3) can be obtained:

$$2E - d\mathcal{U}\_{\mathbb{S}\delta} = E + d\mathcal{U}\_{\mathbb{S}\mathbb{S}} + (-E) \tag{3}$$

Combining the above two formulas, increased voltage on S3 can be obtained:

$$dIL\_{\mathbb{S}3} = E \tag{4}$$

Therefore, as shown in Figure 7, the final voltage of S3 will be 2E. The voltage stress will be higher than the voltage the device can withstand, which may cause overvoltage breakdown and influence the normal operation of the circuit.

**Figure 7.** The overvoltage stress issue. (**a**) Experimental waveforms. (**b**) Experimental circuit.

Before the switching process of S5, there are three possible states for S3 and S4. As shown in Figure 8, when S4 is on and S3 is off, or S3 and S4 are both off, assuming the output current IO is greater than zero, the conduction path and the charging process are analyzed as above.

**Figure 8.** Conduction path of S3 and S4 equals to 0.1 or 0.0. (**a**) Positive current. (**b**) Negative current.

However, when S4 is off and S3 is on, as shown in Figure 9, the switching process is different. If the IO is greater than zero, turning off S5 causes the conduction of S6's reverse diode, the voltage of point O changes from +E to −E and the initial voltage on S8 is 2E. The process seems similar to the above situation, but the direction of S4 decides that the charging current IC reduces its voltage to zero; then, the reverse diode will conduct and there will be no overvoltage risk. However, the output voltage goes through 0, +E, −E. The

ideal process is 0 to −E, although the commutation is not perfect. Therefore, a modified switching method is proposed to achieve the best commutation.

**Figure 9.** (**a**) Conduction path and potential difference when S3, S4 equals to 1.0 (**b**) Equivalent circuit of the charging process.

#### **4. Proposed Modified Modulation Strategy**

The conventional modulation scheme only considers eight simple states. After analyzing the switching states and overvoltage issues, eight other states (V2-2, V2-3, V4-2, V4-3, V5-2, V5-2, V7-2, V7-3) are obtained, as shown in Table 2, which can be included in the state cutover.


**Table 2.** The ANPC-5L converter's switching states and influence on the voltage of the flying capacitors.

<sup>a</sup> C: charging; D: discharging.

By combining additional circuit states, a modified modulation strategy and complete state machine are proposed, as shown in Figure 10. Under the proposed modulation scheme, a safe switching process within a power circle can be achieved and there will be no overvoltage stress, as shown in Figure 11.

**Figure 10.** Complete state machine for the ANPC-5L process.

**Figure 11.** Reliable switching process of proposed modified modulation strategy.

The presented modulation strategy for the ANPC-5L converter is deeply researched in this section. Consisting of modulation signal, output current, driving signal and the voltage of the flying capacitors, Figure 4 shows the schematic diagram. With the scheme that is proposed, the switches, which are series-connected in the ANPC-5L converter, switch at fundamental frequency while the others switch at carrier frequency, which results in low switching losses. In the meantime, low switching and conduction loss can be achieved because the stress of all devices can be restricted to Vdc/4.

#### A. Flying capacitor voltage balance

The voltage of floating capacitors can be affected by different circuit states. One is E and the other is −E (V6, V7-1 and V2-1, V3), which can cause the capacitor to charge or discharge. To go a step further, we can use +E and −E levels within a sinusoidal voltage wave. If circuit states are selected appropriately, the balance of the voltage of FC will be achieved during the whole cycle.

Figure 12 shows that with a positive output current in V6, the flying capacitor is charging, and with a negative output current in V7-1 the flying capacitor is in a discharging state. With the increasing carrier frequency in each fundamental period, the balance of FC voltage will be better controlled in several carrier periods. Because the carrier wave period is much shorter than the fundamental period, the capacity value of the flying capacitor in the ANPC-5L inverter can be significantly reduced for a definite maximal permissible voltage range, compared with those inverters controlling a fundamental period. Ultimately, with the reduced volume of the flying capacitor, the power density of the inverter increases significantly.

**Figure 12.** The waveform of the floating capacitor voltage.
