**Application of Innovative Power Electronic Technologies**

Editors

**Ching-Ming Lai Yitao Liu**

Basel • Beijing • Wuhan • Barcelona • Belgrade • Novi Sad • Cluj • Manchester

*Editors* Ching-Ming Lai Department of Electrical Engineering, National Chung Hsing University Taichung, Taiwan

Yitao Liu College of Mechatronics and Control Engineering, Shenzhen University Shenzhen, China

*Editorial Office* MDPI St. Alban-Anlage 66 4052 Basel, Switzerland

This is a reprint of articles from the Topic published online in the open access journals *Energies* (ISSN 1996-1073), *Electricity* (ISSN 2673-4826), and *Electronics* (ISSN 2079-9292) (available at: https://www. mdpi.com/topics/power electronic).

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## **Contents**





### *Article* **Starter for Voltage Boost Converter to Harvest Thermoelectric Energy for Body-Worn Sensors**

**Grzegorz Blakiewicz, Jacek Jakusz and Waldemar Jendernalik \***

Faculty of Electronics, Telecommunications and Informatics, Gda ´nsk University of Technology, 80-233 Gda ´nsk, Poland; grzegorz.blakiewicz@pg.edu.pl (G.B.); jacek.jakusz@pg.edu.pl (J.J.)

**\*** Correspondence: waldemar.jendernalik@pg.edu.pl

**Abstract:** This paper examines the suitability of selected configurations of ultra-low voltage (ULV) oscillators as starters for a voltage boost converter to harvest energy from a thermoelectric generator (TEG). Important properties of particularly promising configurations, suitable for on-chip implementation are compared. On this basis, an improved oscillator with a low startup voltage and a high output voltage swing is proposed. The applicability of n-channel native MOS transistors with negative or near-zero threshold voltage in ULV oscillators is analyzed. The results demonstrate that a near-zero threshold voltage transistor operating in the weak inversion region is most advantageous for the considered application. The obtained results were used as a reference for design of a boost converter starter intended for integration in 180-nm CMOS X-FAB technology. In the selected technology, the most suitable transistor available with a negative threshold voltage was used. Despite using a transistor with a negative threshold voltage, a low startup voltage of 29 mV, a power consumption of 70 μW, and power conversion efficiency of about 1.5% were achieved. A great advantage of the proposed starter is that it eliminates a multistage charge pump necessary to obtain a voltage of sufficient value to supply the boost converter control circuit.

**Keywords:** CMOS; low voltage; low power; starter; boost DC-DC converter; energy harvesting; Colpitts oscillator

#### **1. Introduction**

Rapid development of body-worn sensors systems integrated on a chip imposes a significant demand on small and efficient power supply circuits. Batteries are avoided in these types of applications because of their relatively large size and limited life span. Among alternative energy sources such as photovoltaic cells [1], vibration transducers [2], or the thermoelectric generators (TEGs) [3–5], the latter ones are widely used due to their small size, portability and suitability for on-body applications. TEGs exploit temperature gradient between the human skin and the ambient environment in practical situations. Small TEG size and low temperature difference (typically 1–2 ◦C) limit the upper voltage bound below 100 mV. Such a low voltage can be applied to slow circuits based on MOS transistors operating in the subthreshold region. However, many systems-on-chip implementing sophisticated functions require MOS transistors operating in the strong inversion region, which involves the use of supply voltages of around 1 V. Although boost converters can be used to raise voltages as low as 20–40 mV [6–11] to the required supply level, they also need a voltage within 1 V for efficient energy conversion. For this reason, an additional starter is used to allow "cold start" of the converter at low voltages. Such a circuit is turned on for a short time needed to start the converter, and then turned off once the converter supplies sufficient voltage to its own control circuits. In practical implementations of ULV boost converters, very significant difficulties are associated with realization of their starters.

Starter solutions designed to initialize the operation of on-chip boost converters are described in the literature [7–10,12–17]. The solutions can be classified into two major groups: starters based on classic ring oscillators using only transistors [12,16,17], and

**Citation:** Blakiewicz, G.; Jakusz, J.; Jendernalik, W. Starter for Voltage Boost Converter to Harvest Thermoelectric Energy for Body-Worn Sensors. *Energies* **2021**, *14*, 4092. https://doi.org/10.3390/ en14144092

Academic Editor: Ching-Ming Lai

Received: 1 June 2021 Accepted: 4 July 2021 Published: 6 July 2021

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

starters based on oscillators with inductors or transformers [7,9,10,12–14]. In ring oscillators, each stage must have a gain greater than one in order to start and sustain oscillations. Satisfying this condition at very low supply voltages is very difficult, where all transistors have relatively low transconductance and drain-source resistance [18–21]. The lowest supply voltage reported for this type of starter is 60 mV [13]. This level was achieved by applying a mechanism for technology corner detection and automatic reconfiguration of the ring oscillator to achieve almost optimal operating conditions. The ring oscillator using only transistors generates output voltages that are limited by the supply voltage, therefore, they need an additional multistage (in some solutions up to 40 stages [13]) charge pump to obtain a sufficiently high voltage. As a result, ring-oscillator-based starters are fairly complicated and have a relatively low efficiency. On the other hand, they can be fully integrated on a chip.

Inductor or transformer-based starters support much lower supply voltages. In these circuits, a transformer or inductor acts as a load for a MOS transistor, allowing for voltage swing greater than the supply voltage and eliminating the inevitable voltage drop across the active load as in the case of a transistor-only ring oscillator. Consequently, they are capable of self-starting at supply voltages as low as 25–40 mV [7,9]. Moreover, an output voltage within 1 V can be achieved without additional charge-pump-based voltage multipliers owing to boosting voltage in a transformer or a LC resonant tank. In this regard, such starters are preferable over ones based on ring oscillators owing to their reliability, even with the supply voltages of only 25–40 mV. The disadvantage of these solutions is the need for inductors, which often have to be implemented as off-chip components to meet the high quality factor requirement.

In terms of the feasibility of reducing the startup voltage, the starters based on the Colpitts oscillator are particularly promising [12,14,18,19]. The paper [19] gives an example implementation of a low-voltage Colpitts oscillator that operates even at 3.5 mV supply voltage. This circuit has indeed a very low inrush voltage but reveals a limitation of the output voltage swing. As a result, the circuit requires an additional multi-stage voltage multiplier to achieve a voltage close to 1 V.

This paper describes a low voltage starter based on an improved Colpitts oscillator featuring a high output voltage swing, which allows using only a few stages of a charge pump.

#### **2. Ultra-Low-Voltage Oscillators**

Three configurations of ULV oscillator potentially suitable as a boost converter starter are depicted in Figure 1.

**Figure 1.** Ultra-low-voltage oscillators: (**a**) ESCO; (**b**) ESILRO; (**c**) proposed HSCO.

The oscillators in Figure 1a,b are ULV solutions discussed in [18,19], referred to as enhanced swing Colpitts oscillator (ESCO) and inductive-load enhanced swing ring oscillator (ESILRO). The circuit in Figure 1c is a proposed high swing Colpitts oscillator (HSCO). The common feature of all the ULV circuits is the application of the full supply voltage (*VDD*) to bias the transistor gate and drain. In this way, a sufficiently high intrinsic gain of the transistor can be achieved at a relatively low supply voltage. For this reason, two inductors are necessary to avoid voltage drop between the *VDD* rail, drain and gate of the transistor. An unavoidable disadvantage of ESCO and ESILRO is limited voltage swing at the drains of the transistors. The reason for this effect is the pn junction between the drain and the substrate, which is forward biased during the negative halves of the generated periodic voltage waveform.

This undesirable effect is avoided in HSCO by connecting the resonant tank with the inductor *L*<sup>1</sup> to the transistor gate and design the feedback loop (*C*1, *C*2) so that the voltage scaling factor *vG*/*vS* is much larger than unity. Under such conditions, the voltage swing on the resonant tank is virtually unlimited. At the same time, voltage across the pn junction formed between the source and the substrate is highly reduced, which prevents it from forward bias. In the small-signal model of the circuit, shown in Figure 2, the biasing inductor *L*<sup>2</sup> is represented by its dynamic resistance *RL*<sup>2</sup> at oscillation frequency *ω*0.

**Figure 2.** Small-signal model of HSCO shown in Figure 1c.

In Figure 2, the transistor M1, represented by *gm*<sup>1</sup> and *gds*1, together with the capacitors *C* 1, *C* <sup>2</sup> and the dynamic resistance *RL*<sup>2</sup> form a circuit that implements the admittance *Yi* with negative real part (conductance). The negative conductance allows compensation for the losses of inductor *L*1, represented by *RL*1. The real and imaginary parts of the admittance *Yi*(*ω*) seen from the gate of M1 are

$$\operatorname{Re}\{Y\_i(\omega)\} = \frac{\omega^2 \mathcal{C}\_1^{\prime 2} R\_0 \left[1 - \mathcal{g}\_{m1} R\_0 \frac{\mathcal{C}\_2^{\prime}}{\mathcal{C}\_1^{\prime}}\right]}{\left(1 + \mathcal{g}\_{m1} R\_0\right)^2 + \omega^2 \left(\mathcal{C}^{\prime}1 + \mathcal{C}\_2\right)^2 R\_0^2} \tag{1}$$

$$\operatorname{Im}\{Y\_i(\omega)\} = \omega \mathbb{C}\_{\mathfrak{g}d1} + \frac{\omega \mathbb{C}\_1^{'} \left[1 + \mathcal{g}\_{m1} \mathcal{R}\_0 + \omega^2 \mathcal{R}\_0^2 \mathcal{C}\_2^{'} \left(\mathbb{C}\_1^{'} + \mathcal{C}\_2\right)\right]}{\left(1 + \mathcal{g}\_{m1} \mathcal{R}\_0\right)^2 + \omega^2 \left(\mathcal{C}\_1^{'} + \mathcal{C}\_2\right)^2 \mathcal{R}\_0^2} \tag{2}$$

where: *C* <sup>1</sup> = *C*<sup>1</sup> + *Cgs*1, *C* <sup>2</sup> <sup>=</sup> *<sup>C</sup>*<sup>2</sup> <sup>+</sup> *Csb*<sup>1</sup> − 1/(*ω*2*L*2), *R0* = 1/(*gds*<sup>1</sup> + 1/*RL*2). The negative real part of the admittance *Yi*(*ω*) can be obtained when the following condition is satisfied

$$\frac{C\_2'}{C\_1'} > \frac{1}{R\_0 g\_{m1}}\tag{3}$$

For a transistor operating at low supply voltage, this condition also means that *C* <sup>2</sup> >> *C* 1, due to the fact that 1/*R0* >> *gm*1. Therefore, further considerations are restricted to such a case. The *L*<sup>1</sup> inductor losses will be compensated and oscillations with frequency *ω*<sup>0</sup> will start if the following conditions are met

$$\operatorname{Re}\{\mathcal{Y}\_{i}(\omega\_{0})\} < -1/R\_{L1} \tag{4}$$

$$\operatorname{Im}\{\mathcal{Y}\_i(\omega\_0)\} = -\frac{1}{\omega\_0 L\_1} \tag{5}$$

With the condition *C* <sup>2</sup> >> *C* 1, the Equation (1) can be simplified to

$$\operatorname{Re}\{Y\_i(\omega)\} \cong \frac{\omega^2 \mathcal{C}\_1'^2 R\_0 \left(1 - \mathcal{g}\_m R\_0 \frac{\mathcal{C}\_2'}{\mathcal{C}\_1'}\right)}{1 + \omega^2 \mathcal{C}\_2'^2 R\_0^2} \tag{6}$$

The simplified Equation (6) was derived under assumption that *gds*<sup>1</sup> >> *gm*<sup>1</sup> which is satisfied when M1 operates at very low supply voltages. To satisfy the Equation (4), transconductance of M1 must fulfill

$$\mathcal{g}\_{m1} \ge \left(\frac{C\_1'}{C\_2'}\right)\frac{1}{R\_0} + \left(\frac{C\_2'}{C\_1'}\right)\frac{1}{R\_{L1}} + \frac{1}{\omega\_0^2 C\_1' C\_2' R\_0^2 R\_{L1}}\tag{7}$$

The absolute minimum transconductance *gm*<sup>1</sup> can be achieved when both inductors are lossless (*RL*1, *RL*<sup>2</sup> → ∞). In such a case, oscillations will start when the transconductance of M1 meets the condition

$$\mathcal{g}\_{m1} > \left(\frac{\mathcal{C}\_1'}{\mathcal{C}\_2'}\right) \frac{1}{R\_0} \stackrel{\mathcal{G}\_{d1} \gtrless 1/R\_{12}}{\rightarrow} \left(\frac{\mathcal{C}\_1'}{\mathcal{C}\_2'}\right) \mathcal{g}\_{d s 1} \tag{8}$$

It is worth noting that in theory by minimization of *C* 1/*C* <sup>2</sup> ratio an arbitrarily small value of *gm*<sup>1</sup> can be achieved, and thus an arbitrarily low supply voltage can be obtained. In practice the inductors are lossy, therefore *gm*<sup>1</sup> can be reduced by minimizing the last component of Equation (7) and by selecting the optimal value of the *C* 2/*C* <sup>1</sup> ratio. Reduction of the last component in Equation (7) requires that

$$
\omega\_0^2 \mathcal{C}'\_1 \mathcal{C}'\_2 \mathcal{R}\_0^{2 \stackrel{\mathcal{G}\_{ds1} \gg\_1}{\to} 1/\mathcal{R}\_{l2}} \stackrel{\omega\_0^2 \mathcal{C}'\_1 \mathcal{C}'\_2}{\mathcal{S}\_{ds1}^2} >> 1 \tag{9}
$$

Under the assumption that Equation (9) is fulfilled, the optimal value of the capacitance ratio is given as

$$\frac{C\_2'}{C\_1'} = \sqrt{\frac{R\_{L1}}{R\_0}} \stackrel{\mathcal{S}\_{d \times 1} \gg 1/R\_{L2}}{\to} \sqrt{\mathcal{S}\_{d \times 1} R\_{L1}} \tag{10}$$

and the minimum transconductance required to start the oscillations is

$$g\_{m1,min} > \frac{2}{\sqrt{R\_{L1}R\_0}} > 2\sqrt{\frac{1 + \mathcal{g}\_{ds1}R\_{L2}}{R\_{L1}R\_{L2}}} \stackrel{\mathcal{G}\_{ds1} \gg 1/R\_{L2}}{\rightarrow} 2\sqrt{\frac{\mathcal{G}\_{ds1}}{R\_{L1}}}\tag{11}$$

Note that according to Equation (9), it is advantageous to choose the highest possible oscillation frequency (*ω*0) and the largest capacitances *C* 1, *C* 2. Thus, in order to minimize the transconductance required to start oscillations in Equation (7), small inductances *L*<sup>1</sup> and *L*<sup>2</sup> and large capacitances *C* 1, *C* <sup>2</sup> are advantageous, which is also very beneficial for integration of the oscillator.

#### **3. Minimum Supply Voltage Required to Start ULV Oscillators**

Low supply voltage and high output swing are important criteria for choosing an oscillator as a starter for ULV boost converter. To identify which of the configurations shown in Figure 1 is best suited as a starter, the minimum supply voltages of these circuits were determined and compared. In further considerations ESILRO is omitted due to the need for four inductors, which is difficult to integrate. N-channel MOS transistors with near-zero threshold voltage as well as negative threshold voltage are good candidates for implementing ULV oscillators because they provide relatively high drain current at supply voltages below a few tens of mV [18,19,21]. Therefore, the minimum supply voltages of ESCO and HSCO were determined for the transistor operating in the weak and strong inversion regions.

For the sake of simplicity, in the compared oscillators it was assumed that both inductances as well as their losses are identical (*L*<sup>1</sup> = *L*2, *GL*<sup>1</sup> = *GL*2). According to the analysis presented in [19], oscillations will start in ESCO if the following condition holds

$$\frac{\mathcal{g}\_{ms1}}{\mathcal{g}\_{md1}} > a + \frac{a^2 + 1}{a - 1} \frac{G\_{L1}}{\mathcal{g}\_{md1}} \tag{12}$$

where

$$a = 1 + \sqrt{\frac{2G\_{L1}/\mathcal{g}\_{md1}}{G\_{L1}/\mathcal{g}\_{md1} + 1}}\tag{13}$$

where *gms*<sup>1</sup> and *gmd*<sup>1</sup> are the source and drain transconductances [19,20]. The ratio of these conductances for strong and weak inversion regions can be approximated [19,20] by

$$\frac{\mathcal{g}\_{ms1}}{\mathcal{g}\_{md1}} = \frac{V\_{DS}V\_{T0}}{V\_{DS}(1-n) - V\_{T0}}\tag{14}$$

$$\frac{\mathcal{G}\_{ms1}}{\mathcal{G}\_{md1}} = \exp\left(\frac{V\_{DS}}{l I\_T}\right) \tag{15}$$

where *VT*<sup>0</sup> is the threshold voltage, *n* is the slope factor of the current-voltage characteristic in the weak inversion region, *UT* is the thermal voltage, and *VDS* is the drain-source voltage.

The minimum supply voltage necessary to start oscillations in ESCO can be determined from Equations (12)–(15) for the strong and weak inversion regions, respectively [19]

$$V\_{DD,min} > \frac{\left(1 - \frac{G\_{L1}}{\mathcal{S}\_{md1}}\right) V\_{T0}}{1 - (1 - n)\frac{G\_{L1}}{\mathcal{S}\_{md1}}}\tag{16}$$

$$V\_{DD,min} > lI\_T \ln\left(a + \frac{a^2 + 1}{a - 1} \frac{G\_{L1}}{g\_{md1}}\right) \tag{17}$$

In HSCO, oscillations start when Equation (11) is satisfied. Based on this equation, the minimum ratio of the gate transconductance (*gm*1) to the output conductance (*gds*1) of the transistor can be determined as

$$\frac{\mathcal{G}\_{m1,min}}{\mathcal{G}\_{ds1}} > 2\sqrt{\frac{G\_{L1}}{\mathcal{G}\_{ds1}}}\tag{18}$$

where *GL*1/*gds*<sup>1</sup> represents the ratio of *L*<sup>1</sup> losses, modeled by *GL*<sup>1</sup> = 1/*RL*1, to the transistor output conductance. The ratio of the transistor transconductance to its output conductance for the strong and weak inversion regions can be defined [19,20] as

$$\frac{\mathcal{g}\_{m1}}{\mathcal{g}\_{ds1}} = \frac{nV\_{DS}}{V\_{DS}(1-n) - V\_{T0}} \tag{19}$$

$$\frac{\mathcal{G}\_{m1}}{\mathcal{G}\_{ds1}} = \frac{1}{n} \left( \exp\left(\frac{V\_{DS}}{lI\_T}\right) - 1 \right) \tag{20}$$

The minimum supply voltage for HSCO, *VDD,min*, determined based on Equations (18)–(20), is for the strong and weak inversion regions, respectively

$$V\_{DD,\min} > \frac{-2V\_{T0}\sqrt{G\_{L1}/\mathcal{g}\_{ds1}}}{n - 2(1 - n)\sqrt{G\_{L1}/\mathcal{g}\_{ds1}}}\tag{21}$$

$$V\_{DD,min} > lI\_T \ln\left(1 + n\sqrt{G\_{L1}/g\_{ds1}}\right) \tag{22}$$

The comparison of the minimum supply voltage, *VDD,min*, defined by Equations (16), (17), (21) and (22), for ESCO and HSCO is plotted in Figure 3a,b, for the strong and weak inversion regions, respectively. The calculations for the strong inversion region are based on extracted values of *VT*<sup>0</sup> and *n* for particular *VGS* = *VDS* = *VDD* voltage values for a native n-channel MOS transistor (W/L = 2500 μm/1 μm) in X-FAB 180-nm CMOS technology. The plots for the weak inversion were made for *UT* = 26 mV and similar values of the parameter *n*.

**Figure 3.** The minimum supply voltage, *VDD,min*, required to start oscillations in ESCO and HSCO as a function of *GL*1/*gmd*<sup>1</sup> (*GL*1/*gds*1), for the transistor operating in: (**a**) the strong inversion region; (**b**) the weak inversion region.

The results in Figure 3a,b show that HSCO requires significantly lower supply voltage compared to ESCO. This feature is particularly evident for high values of *GL*1/*gds*1, which corresponds to use of low quality factor inductors. The general Equations (16), (17), (21) and (22), defining the minimum startup voltage, were derived based on a simplified linear model. To provide more in-depth investigation of the considered oscillators properties, number of HSCO and ESCO oscillator designs using native n-channel MOS transistors with negative threshold voltage were prepared for a 180-nm X-FAB technology. For each oscillator design, the component parameters were optimized to obtain the minimum startup voltage, *VDD,min*, for selected values of: *GL*1/*gmd*<sup>1</sup> (*GL*1/*gds*1), inductances *L*<sup>1</sup> = *L*2, and inductor quality factors *QL*. A summary of the oscillators parameters is shown in Table 1.



Based on the data from Table 1, one can see that HSCO oscillator, compared to the ESCO, exhibits lower inrush voltage for similar values of *GL*1/*gds*<sup>1</sup> and inductor quality factor *QL*. For the variants *GL*1/*gds*<sup>1</sup> = 0.001, *QL* = 255, and *GL*1/*gds*<sup>1</sup> = 0.005, *QL* = 51 a series of simulations for HSCO and ESCO were performed showing the peak-to-peak value of the output voltage, *vOUT-PP*, as a function of the supply voltage *VDD* (Figure 4). For the high inductor quality factor case, a noticeable limitation of the output voltage is observed as the ESCO supply voltage increases. This effect is caused by forward biasing of the pn junction between the transistor drain and substrate.

**Figure 4.** Peak-to-peak values of the output voltage, *vOUT-PP*, as a function of the supply voltage, *VDD*, for HSCO and ESCO.

For all the considered ULV oscillators, the main factor limiting amplitude of the output voltage is a relatively large drain to source conductance of a transistor. Due to this fact, the transistor internal gain is relatively small, especially in HSCO. The gain in this configuration can be increased by increasing the supply voltage *VDD*, but this is unfavorable because ULV oscillators should operate for the lowest possible supply voltage. To overcome this limitation, an improved version of HSCO was developed, as shown in Figure 5.

**Figure 5.** Improved version of HSCO.

In this oscillator, two transistors connected in parallel are used. M1 is a transistor with negative or near-zero threshold voltage, whereas M1a is a low-threshold-voltage transistor. The transistor M1 plays the same role as in the circuit of Figure 1c and serves mainly to initiate the oscillation, while M1a acts as an additional booster which is activated when the output voltage *vOUT* reaches a sufficient amplitude. Notice that introduction of M1a does not lead to noticeable increase of the output conductance of the composite transistor (M1 + M1a), because it is switched off for most of the time of the periodic waveform. This transistor is only turned on for short periods of time when the voltage at its gate exceeds a threshold value. Time waveforms illustrating operation of the circuit are shown in Figure 6.

**Figure 6.** Time waveforms of the signals in the improved HSCO.

To demonstrate the advantage of the improved oscillator, the peak-to-peak values of the output voltage as a function of the supply voltage for ESCO, HSCO and improved HSCO are plotted in Figure 7.

**Figure 7.** Peak-to-peak values of the output voltage, *vOUT-PP*, as a function of the supply voltage, *VDD*, for ESCO, HSCO and improved HSCO (*GL*1/*gds*<sup>1</sup> = *GL*1/*gdm*<sup>1</sup> = 0.0025, *QL* = 100).

#### **4. Starter Based on the Improved HSCO**

The key component of the proposed starter is the improved HSCO oscillator (Figure 5) which is capable of generating the highest output voltage at low supply voltages (Figure 7). As the plots in Figure 3 show, the most advantageous is to use a transistor with a near-zero threshold voltage that operates in the weak inversion region. In the chosen X-FAB 180 nm CMOS technology a zero-threshold-voltage transistor is not available. Thus, the most suitable transistor available was used, namely a n-channel native MOS transistor with a negative threshold voltage of approximately −180 mV. The starter consists of the improved HSCO and a 3-stage voltage multiplier, as shown in Figure 8.

**Figure 8.** Starter based on the improved HSCO.

This solution is additionally equipped with a shutdown circuit which allows its disabling when the main boost converter starts running. The shutdown circuit, consisting of M2, M3, M4, and *C*<sup>4</sup> is placed in the main current path and allows for complete cutoff of the supplying current. With this solution, when the main boost converter is running, the starter does not increase power consumed from the supply source. M2 in the shutdown circuit requires a negative voltage to be turned off. This voltage is obtained through rectification (by means of M3, M4, and *C*4) the square wave voltage applied to control the boost converter switches. The parameters of the starter components are given in Table 2.


**Table 2.** Parameters of the starter components.

The HSCO startup process is illustrated in Figure 9 showing the oscillator output voltage, *vOUT*, waveform. Two phases of startup can be clearly observed in this plot. The first one, covering the time interval up to about 1.4 ms, is mainly related to operation of the transistor M1. The second phase begins when the voltage amplitude exceeds the threshold voltage of M1a. During this time interval, additional current pulses are generated to further increase the amplitude of *vOUT*. The plot also illustrates the shutdown moment, which occurs at 2 ms.

The voltage waveform at the output of the starter, *vST*, is shown in Figure 10. It can be seen that obtaining *vST* above 1 V became possible only after boosting the oscillator by the transistor M1a. The effectiveness of the shutdown circuit can be determined based on the waveform of the current *iSUP* sourced from the supply *VDD*. In shutdown state, *iSUP* decreases to a few tens of nA.

**Figure 9.** The output voltage, *vOUT*, waveform in HSCO illustrating the startup process.

**Figure 10.** Waveforms of the output voltage (*vST*) and current (*iSUP*) sourced from supply in the starter.

The effect of temperature changes and variations of technology parameters, represented by corners, on the startup voltage is shown in Figure 11. The worst case startup voltage is 29 mV at 50 ◦C under worst-speed (WS—slow NMOS, slow PMOS) and worstzero (WZ—slow PMOS, fast PMOS) corners. Therefore, the proposed starter enables reliable start at supply voltages greater than 29 mV.

**Figure 11.** Minimal startup voltage, *VDD,min*, as a function of temperature and variations of technology parameters, represented by corners.

A comparison of the main features of the developed starter with solutions reported in the literature is given in Table 3. The developed starter has a startup voltage which is within the lower range of voltages generated by TEGs. It should be emphasized that the startup voltage can be further reduced for CMOS technologies where zero threshold voltage transistors are available. The developed starter needs two external inductors (*L*1, *L*2), where *L*<sup>2</sup> can be of low quality, and two external capacitors (*C*1, *C*2). In the presented solution, the oscillation frequency is about 1 MHz, but can be increased to more than 10 MHz, allowing further reduction of external inductors and capacitors leading to a higher degree of miniaturization. The power efficiency of the proposed starter is approximately 1.5%. However, it should be emphasized that such low efficiency is not important since the starter operates only in the initial phase of the converter start-up and then is immediately turned off.


**Table 3.** Comparison of starters.

<sup>1</sup> Results of simulations.

#### **5. Conclusions**

A comparison of ULV oscillators, suitable for on-chip implementation, in terms of critical features for their use as starters in boost converters was presented. Based on the analysis, the improved oscillator configuration featuring a small startup voltage and a large output voltage swing was proposed. These features allow for simplification of the starter design. With the developed oscillator, a starter for on-chip implementation was designed that meets the requirements for using TEG as a power source. Compared to known solutions, the proposed starter offers greater miniaturization owing to the possibility of using smaller inductors with lower quality.

**Author Contributions:** Conceptualization, G.B.; methodology, G.B.; formal analysis, G.B.; investigation, G.B., J.J. and W.J.; writing—original draft preparation, G.B., J.J. and W.J.; writing—review and editing, G.B., J.J. and W.J. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded in part by National Science Centre of Poland under the grant 2016/23/B/ST7/03733.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** This study did not report any data.

**Conflicts of Interest:** The authors declare no conflict of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, or in the decision to publish the results.

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## *Article* **Do Perceived Risk, Perception of Self-Efficacy, and Openness to Technology Matter for Solar PV Adoption? An Application of the Extended Theory of Planned Behavior**

**Arifa Tanveer 1, Shihong Zeng 1,2,3,\*, Muhammad Irfan 4,5,\* and Rui Peng 1,2,\***


**Abstract:** Solar PV (photovoltaic) technology has gained considerable attention worldwide, as it can help reduce the adverse effects of CO2 emissions. Though the government of Pakistan is adopting solar PV technology due to its environmental friendliness nature, studies focusing on consumer's acceptance of solar PV are limited in the country. This research aims to close this knowledge gap by looking into the various considerations that may influence consumers' willingness to adopt (WTA) solar PV for household purposes. The study further contributes by expanding the conceptual framework of the theory of planned behavior by including three novel factors (perceived risk, perception of self-efficacy, and openness to technology). The analysis is based on questionnaire data collected from 683 households in Pakistan's provincial capitals, including Lahore, Peshawar, Quetta, Gilgit, and Karachi. The proposed hypotheses are investigated using the state-of-the-art structural equation modeling approach. The empirical results reveal that social norms, perception of self-efficacy, and belief about solar PV benefits positively influence consumers' WTA solar PV. On the contrary, the perceived risk and solar PV cost have negative effects. Notably, the openness to technology has an insignificant effect. This study can help government officials and policymakers explore cost-effective, risk-free technologies to lessen the environmental burden and make the country more sustainable. Based on research results, study limitations, as well as prospective research directions, are also addressed.

**Keywords:** solar PV technology; consumers; willingness to adopt; theory of planned behavior; structural equation modeling; Pakistan

#### **1. Introduction**

Climate change is a global environmental challenge, and to minimize its negative impacts, governments are implementing environmentally friendly technologies worldwide [1]. The persistent advancement in the population and globalization development has increased the energy demand [2,3]. Although being more technologically evolved than ever before, most countries still depend purely on crude oil to generate electricity [4]. About two-thirds of the world's increasing energy demand is owing to fossil fuels [5]. The continuous use of traditional sources in electricity generation is the primary cause of global climate change [6]. As a result, to combat global warming, the world must transition to clean energy sources [7,8]. Solar PV, a form of clean energy, has become more common in recent times and reached a global installed capacity of 303 GW, with a healthy annual

**Citation:** Tanveer, A.; Zeng, S.; Irfan, M.; Peng, R. Do Perceived Risk, Perception of Self-Efficacy, and Openness to Technology Matter for Solar PV Adoption? An Application of the Extended Theory of Planned Behavior. *Energies* **2021**, *14*, 5008. https://doi.org/10.3390/en14165008

Academic Editor: Carlos Henggeler Antunes

Received: 16 July 2021 Accepted: 11 August 2021 Published: 15 August 2021

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

33-percent growth rate [9]. By 2025, solar PV is projected to meet 4% of the global electricity demand [10].

Similarly to other developing countries, Pakistan is facing environmental degradation and the worst energy crisis [11]. Due to Pakistan's massive population and economic growth, the energy demand has increased over the last two decades [12]. Pakistan's existing energy structure is heavily dependent on costly imported fuels such as oil and gas. Fuel imports from other countries are the only choice because Pakistan's domestic fuel supplies are inadequate to meet the country's energy demands. The country spends nearly 60% of its foreign exchange on fossil fuel imports [13]. An enormous dependence on traditional electricity generation methods is the main cause of environmental problems and a burden on economic development [14]. Solar PV is being introduced in Pakistan to address climate change issues and provide a long-term strategy for resolving the country's energy crisis [15].

Solar PV, a novel energy green technology, effectively decreases the cost of imported oil and minimizes CO2 emissions [16]. Different countries have taken steps to raise the proportion of solar energy in their portfolio structure [17,18]. According to the sustainable global progress report 2020, solar PV rose 12% and generated electricity of 115 GW in 2019. Until 2019, the estimated worldwide solar PV output reached 627 GW [19].

Solar PV projects are believed to boost the quality of life for residents in numerous ways, such as providing job opportunities for people [15], they can help to reduce CO2 emission [20], and it is the cheapest source of renewable energy and would be helpful to sustain the prices of electricity [21]. Electricity is considered a vital component in economic growth [22]. Solar PV technology helps to generate electricity at the household level and minimize carbon emissions [23]. The value of solar PV is highlighted by the fact that home appliances are one of the largest sources of CO2, accounting for 70% of global emissions [24]. Fossil fuels (coal, oil, and gas) are the major energy sources of Pakistan [25]. The country spends USD 7 M annually on importing such costly energy sources [26]. According to the Pakistan Economic Survey, households are one of the largest energy consumers in Pakistan, with a share of 49.1% [27]. Other industries and sectors, including construction, transportation, and agriculture, also have a major share in energy consumption and carbon emission. As the country's energy structure is primarily based on fossil fuels, environmentally and economically friendly technologies are needed to minimize carbon emissions, on the one hand, and reduce the import of costly fossil fuels, on the other hand [28].

Solar PV is the most sustainable energy alternative for meeting the rising energy demand while also preserving the climate. Furthermore, the importance of solar PV adoption in Pakistan is demonstrated by [29], who claim that if 20% of the land in Baluchistan were covered in solar panels, then Pakistan's total electricity demand could be met. This demonstrates the considerable capability of solar PV technology to meet Pakistan's electricity needs. However, persistent electricity shortages can be addressed at the household level by using solar PV. Despite its enormous potential, solar PV has a low acceptance rate in Pakistan.

Several researchers have examined the dwellers' willingness to adopt solar PV in developed countries. Previous studies were conducted in economies where the governments already have defined strategic policies to achieve zero carbon emissions. Polo Lopez, Lucchi, and Franco [30] examined the potential, barriers, assessment criteria, and acceptance of building integrated photovoltaic in heritage buildings and landscapes. The authors concluded that it is necessary to protect the compatibility requirements for architecture and landscape. The possibilities of emerging solar products, which are currently not wellintroduced in the market, are endless, thanks to advanced customization capabilities that enable a better integration into contexts of special heritage-protected buildings, thereby preserving their cultural and essential values. In another study, [31] established a conceptual framework for integrating solar energy systems into heritage sites and buildings to preserve their cultural and natural values, while lowering primary energy consumption, increasing comfort levels, mitigating environmental impacts, and enhancing the technical quality and economic outlays. The authors of [32] found that Australia attains 6% of its necessities from renewable resources. The authors concluded that Australia has diligently used renewable resources in recent years, which has had a positive environmental impact. According to the report of [33], the share of solar PV to generate electricity globally has increased by 28.3%. Irfan et al. [22] examined consumers' acceptance of solar energy by employing the theory of planned behavior from a Chinese perspective and discovered that consumers are positively influenced by awareness, self-efficacy, and the belief in the benefits of solar energy. Consumers' willingness to adopt solar PV is considered as the crucial factor to determine social acceptance [34]. Subsequent studies also identify the factors that may affect consumer's acceptance. Likewise, [35] investigated that acceptance is high when consumers believe that solar PV could mitigate carbon mission, benefit society, and increase job opportunities for people. Their study further revealed that descriptive factors such as age, income, education, and location also affect social acceptance [36].

A few scholars have conducted studies in developing countries as well to analyze the consumers' willingness to adopt solar PV. Alrashoud and Tokimatsu [37] examined considerations that may either empower or dissuade Saudi Arabian people from purchasing solar photovoltaic (PV) systems. The research found that education had the greatest positive effect, while the installation cost was the greatest barrier to adoption. Another study conducted by [38] in Ethiopia found that consumers have a high willingness to pay for solar energy to generate electricity, and the tendency to pay is positively influenced by economic variables such as age, income, and education. Likewise, [39] examined the solar PV social acceptation in six major states of India. They found that villagers show concern about the cost of solar PV, and they consider that solar PV is the best alternative, but it is more expensive in villages than in urban cities.

Along these lines, former researchers considered solar PV adoption from the following standpoints: (i) economic sustainability [40], (ii) social and environmental factors [41–43], (iii) barriers and drivers [29], (iv) the moderating role of policy and propaganda [24], (v) and financial incentives and subsidies [44]. Despite former researchers' long-standing interest, the inclination to find consumers' risk perceptions, self-efficacy, and openness to technology regarding solar PV adoption has been largely ignored. This research gap prompted us to add to the existing literature by evaluating the influence of these novel factors that could shape households' willingness to adopt solar PV. The study makes three major contributions in this regard. First, we considered all possible factors that may affect consumers' willingness to adopt (WTA) solar PV. Second, we added three new factors to the theory of planned behavior (TPB), including the perceived risk, perception of self-efficacy, and openness to technology. Previous studies have never taken these considerations into account in any context before, which is another contribution of this study. Third, unlike previous studies, the current research findings went beyond the previous research findings. For instance, the perceived risk appeared to be a significant factor in the acceptance of solar PV. Similarly, self-efficacy perception remains a vital component of TPB's theoretical structure. On the other hand, openness to technology plays a minor role in solar PV acceptance.

This study examines the willingness of Pakistani consumers to adopt solar PV using both existing and proposed novel factors. Pakistan has plenty of solar power resources, and if they are used properly, they can meet all of the country's current and potential energy needs [45]. However, as a developing country, Pakistan faces significant challenges in developing solar energy, including technological constraints, developers' reluctance to invest in solar PV generation, policies, and economic woes [46]. In addition, our research provides a robust conceptual framework by extending the TPB model and adding novel factors to better understand consumers' acceptance of solar PV.

The rest of the research is organized as follows: The theoretical framework is explained in Section 2. The formulation of hypotheses is shown in Section 3. Research methods are depicted in Section 4. The study's findings and implications are mentioned in Section 5. A discussion of research results is included in Section 6. Section 7 concludes the study, offers valuable policy guidance and discusses study limitations.

#### **2. Theoretical Framework**

To investigate the buying behavior of consumers, various theoretical models have been used in the literature, such as TPB, the theory of reasoned action (TRA), and theory of self-efficacy (TSE) [47,48]. However, TPB is a commonly used model that predicts and identifies consumer behavior [49]. Professor Ajzen was the first one to study behavioral intention, notably with Fishbein. The TPB model suggests that a person's behavioral intentions control his or her actions [50]. TPB explains that individuals' behavior is shaped by their notable beliefs and the subsequent evaluations of a particular action. Several researchers have employed this theory to evaluate consumer behavior in different fields and contexts (see Table 1).


**Table 1.** Usage of TPB in different fields and contexts.

As previously stated, TPB's model can identify and forecast consumer behavior adoption. Several researchers have added additional variables to the model to enhance behavior prediction and clarify why certain people find it hard to put their good intentions into effect [61–63]. The TPB model can incorporate other critical variables that specifically affect behavior and intention, in addition to the factors that make up the theory itself. Based on the justification from the literature, we added three additional factors (perceived risk, perception of self-efficacy, and openness to technology) with existing factors (belief about solar PV benefits, solar PV cost, and social norms) to the TPB model to investigate consumers' WTA solar PV. The study's framework is portrayed in Figure 1. Consumers' adoption was negatively influenced by perceived risk. Perceived risk was the customers' assessment of the probability of safety and security incidents and the corresponding consequences. Reasonably, perceived risk may negatively influence the dwellers' willingness. Perception of self-efficacy indicated "a person's assessment of how easy or difficult it is to conduct a specific action". Individuals believed that they had the requisite expertise, resources, or opportunities to adopt new technology successfully. The perception of self-efficacy plays a crucial role and positively influenced consumers' adoption. The third factor was openness to technology that was defined as "whether consumers try new technologies or stick with existing ones". We examined households' opinions by determining their willingness to adopt solar PV (see Figure 1).

**Figure 1.** Study framework depicting the adoption of solar PV. Notes—BPVB: belief about solar PV benefits; SPVC: solar PV cost; PRSK: perceived risk; OTEC: openness to technology; SOCN: social norms; PRSE: perception of self-efficacy; WTAPV: willingness to adopt solar PV.

#### **3. Development of Research Hypotheses**

#### *3.1. Belief about Solar PV Benefits (BPVB)*

Belief about solar PV benefits (BPVB) was defined as consumers' perceptions about solar PV that it has various benefits such as energy protection measures, combating climate change, and energy-saving [64]. The study found that farmers' assumptions about perceived benefits had a major impact on their adoption in India [65]. People distinguished between traditional and renewable energy sources, making purchasing decisions based on their socio-economic status [66]. As a result, initiatives are required to increase residents' understanding of the advantages of solar power use, such as improved air quality and lower carbon emissions, as well as to educate them about the negative consequences of dependence on energy that is based on fossil fuel [67]. Further research carried out by [68] in Sweden found that folks who are constantly aware of the benefits of solar PV and how it helps to alleviate the burden of electricity are highly motivated to adopt solar PV. In light of these considerations, we formulated the following hypothesis:

**Hypothesis 1 (H1).** *Consumers' willingness to adopt solar PV is positively influenced by BSPVB.*

#### *3.2. Solar PV Cost (SPVC)*

As per the results of previous studies, there is a negative correlation between the cost of solar energy and its public acceptance. For instance, [69] concluded that solar PV was still more costly than traditional electricity. During purchasing circumstances, consumers also think about cost details to address monetary deficits [70]. Solar energy is relatively expensive since solar PV projects necessitate a large initial investment [15]. According to [38], rising prices are discouraging customers from adopting solar PV. Rising prices are the major deterrent to solar PV deployment [71]. Another study was conducted to determine consumers' desire to adopt solar home systems and solar PVs. The research results indicate that respondents are discouraged by high costs [72]. As a result of these findings, we came up with the following hypothesis:

#### **Hypothesis 2 (H2).** *Consumers' willingness to adopt solar PV is negatively impacted by SPVC.*

#### *3.3. Perceived Risk (PRSK)*

In this context, perceived risk refers to a customer's belief that solar PV technology is risk-oriented. Consumers utilizing a new service or product were concerned about safety risks. This has a significant effect on consumers' interest in that particular product or service and, thus, on the acceptance of that technology [73]. A study by [74] reported that consumers should feel comfortable when interacting with technologies to increase adoption. Furthermore, results revealed that customers were hesitant to implement internet of things (IoT) services due to a lack of protection. Lee [75] discovered that security risk negatively affects consumers' attitudes toward online banking. In terms of customer confidence in adoption, the security risk is frequently cited as a major concern. Similarly, [76] also found that attitudes toward smart meter adoption were negatively influenced by perceived danger, to which privacy and safety issues are important antecedents. The study suggests the following hypotheses based on the preceding literature review:

#### **Hypothesis 3 (H3).** *Consumers' willingness to adopt solar PV is negatively influenced by PRSK.*

#### *3.4. Openness to Technology (OTEC)*

Individual judgments about the usefulness of technology would be influenced by their willingness to try new things [77]. In recent years, research has increasingly focused on the impact of transparency on people's interactions with technology. Openness to technology has been linked to an inquiring mind, intelligence, and intellectual interests because it reflects the responsiveness of an individual to new perspectives [78]. High openness to technology is described as a desire to learn and understand things that are new to them, and embrace innovative ways to solve problems and adopt new technology [79]. Individuals vary in their level of openness towards technology due to their diverse backgrounds and life experiences [80]. Watjatrakul [81] found that students eager to learn new things want to do so in a constantly changing world. The practical importance of online learning is positively influenced by openness to technology. Students who can take risks and try new things are more concerned about the content of online learning. Based on these study findings, we formulated the hypothesis as follows:

**Hypothesis 4 (H4).** *Consumers' willingness to adopt solar PV is positively impacted by OTEC.*

#### *3.5. Social Norms (SOCN)*

Social norms refer to the social influence on consumers' WTA solar PV [82]. Every country has its specific economic characteristics and individual culture [83]. Researchers observed that farmers inspired other farmers to engage in conservation initiatives by recommending them to attend agro-environmental programs [84]. It means that social pressure is often present during the execution of a specific action [85]. Another study conducted by [86] in three villages of South Korea's Geumsan county examined how residents who engage in the rural landscape development program have a substantial effect and motivation on other residents' perceptions. The majority of participants demonstrated an interest in and involvement in group activities. Lopes et al. [87] found a significant link between SOCN and residents' energy conservation behavior. According to [88], the actions of society have a huge influence on residents' intentions to purchase solar PV. Subsequently, it is essential to look at the impact of this crucial factor on WTA solar PV in Pakistan. Thus, we formulated the hypothesis as follows:

**Hypothesis 5 (H5).** *Consumers' willingness to adopt solar PV is positively impacted by SOCN.*

#### *3.6. Perception of Self-Efficacy (PRSE)*

In the context of solar PV, understanding regarding self-efficacy refers to how convenient or difficult it is for consumers to adopt solar PV [89]. PRSE has been shown in many studies to have a substantial impact on consumers' decisions. According to a study, PRSE has a favorable impact on customer perceptions of solar PV adoption [90]. Talpur et al. [91] revealed that PRSE was discovered to be a significant factor in the acceptance of solar PV. Another study conducted by [92] provides support for applying the theory of planned behavior in the United States on adolescents' perceptions of competence to protect themselves in their future occupational workforce. Similarly, PRSE influences customers' decision making, as per [93]. According to the analysis, PRSE plays a significant role in buyers' decisions to support solar PV. Thus, we formulated the hypothesis as follows:

**Hypothesis 6 (H6).** *The willingness of consumers to adopt solar PV is positively influenced by PRSE.*

#### **4. Research Methods**

#### *4.1. Target Population: Provincial Capitals of Pakistan*

The study's target population included residents of all five provincial capitals (Lahore, Peshawar, Quetta, Gilgit, and Karachi). As the Pakistani government intends to develop provincial capitals and make them the mainstream regions of the country, the urbanization trend has been steadily growing. The majority of the population is migrating from rural areas to the country's capital centers, searching for better jobs, education, and healthcare opportunities. In view of the economic, energy, and resource structure, these provincial capitals represent the country's unique characteristics, and the energy demand is increasing day by day in these capitals [94]. For instance, Lahore, the provincial capital of Punjab, is usually recognized as the cultural capital of Pakistan. This is Pakistan's second-largest city, with a population of 12,642,000 in 2020 [95]. Due to the rapid increase in population, the city faces a huge electricity shortage. Peshawar is the provincial capital of KPK. It is located next to the eastern terminus of the historic Khyber Pass near to the Afghan border. The city covers an area of 1257 km2 and has a population of about 2 M [96].

On the other hand, Baluchistan is Pakistan's largest province by area, with Quetta as the provincial capital and the province's most urbanized city, hosting 29% of the province's total urban population. Provincial capital Karachi is the largest city in Sindh province and is known as the business center of Pakistan and the world's second-largest Islamic city with a population of about 24 M [97]. Gilgit is the fifth provincial capital of Pakistan. It possesses an enormous economic potential through tourism, tremendous renewable energy resources, minerals, and precious stones, and its strategic location that facilitates Pakistan's only road-to-road trade link with China: the CPEC's linchpin [98].

The survey description is provided in Table 2. The following three criteria were considered while conducting the questionnaire survey. (i) Due to COVID-19's second wave, Pakistan's government imposed a smart lockdown in all of the country's cities at the end of December 2020. Therefore, the authors used an online survey to collect data. (ii) We chose 800 participants using a convenient random sampling methodology [99], and a total of 683 responses were received. (iii) We followed the Comfrey and Lee's scale to determine the adequacy of sample size. For instance, [100] recommended the following scale: (very poor—50), (poor—100), (fair—300), (very good—500), (excellent—1000 or more). According to this scale, our study sample size (683 respondents) falls under the "excellent" category, ensuring that the sample size represents this research and supports its findings.



#### *4.2. Questionnaire Development*

The questionnaire's items were mainly adopted from past studies that had been checked through a thorough review. The sources of data used to calculate each item and the development of the questionnaire are mentioned in Table 3. The self-administered questionnaire consisted of two parts: one for profiling and another for the elements that were used to assess each construct. In Section A, there were six questions about gender, age, marital status, as well as education, household income, and occupation. Section B had 39 questions, including seven questions for belief about solar PV benefits, social norm, and perception of self-efficacy—five questions were about solar PV cost and perceived risk. Four questions were asked about openness to technology and willingness to adopt solar PV. Section B items were rated on a seven-point Likert scale ranging from 1 (strongly disagree) to 7 (strongly agree). The detailed questionnaire is reported in Appendix A.

**Table 3.** Measurement source.


#### **5. Data Analysis and Empirical Results**

To investigate the research hypotheses and model that were considered, SEM was used by employing SPSS and AMOS version 26. SEM is a realistic method that provides reliable and concrete results when determining the relationship between various variables [106]. The method has several advantages over conventional techniques. A precise estimation of measurement errors and observed variables is used to estimate latent factors and validate the model for pattern evaluation and execution [107]. Furthermore, the majority of multivariate methods implicitly ignore the measurement error. On the other hand, the SEM measures all dependent and independent variables by taking the measurement error into account [108]. The technique produces reliable and eloquent results due to its robustness and reliability [109]. Considering the benefits of SEM, we used it in our research because it was the most efficient way to evaluate the relationship between all of the variables under consideration. The descriptive statistics of the data are presented in Table 4. The descriptive statistics were scrutinized by means and standard deviations.


**Table 4.** Descriptive statistics of the data.

Notes: Dependent variable—WTAPV.

#### *5.1. Respondents' Profile*

The survey peculiarities of the 683 respondents are summarized in Table 5. Male respondents outnumbered female respondents, with 398 male respondents accounting for 58.27% of the overall sample and 285 female respondents accounting for 41.72% of the total sample. In addition, the vast majority (459, 67.20%) were married, followed by unmarried respondents (224, 32.79 percent). Nearly 42.75 percent of respondents were between the ages of 26 and 35, followed by 36 to 45-year-olds (19.91 percent), 46 to 55 (11.71 percent), up to age 25 (16.39 percent), and those aged 56 and more (9.2 percent). The majority of respondents (45%) had an MS/MPhil degree, followed by a Ph.D. (16%), master's (29%), bachelor's degree (8%), and people with intermediate or below qualifications (4 percent). Furthermore, 287 (42.02 percent) respondents had a monthly household income of PKR 26,000–45,000, and 326 (47.73 percent) had their own business. See Table 5.


**Table 5.** Respondents profile N = 683.

#### *5.2. Measurement Model Testing*

The measurement model was evaluated using a validity and reliability test. There were two types of validity tests, one was convergent validity, as determined by average variance extracted (AVE), and discriminant validity calculated by Heterotrait–Monotrait ratios (HTMT) [110]. Outer loadings were used to calculate reliability, which included items reliability.

Table 6 presents the discriminant and convergent validity test. Discriminant validity determined that construct measures should not be highly correlated with one another theoretically and were not found to be highly correlated. HTMT is the most robust approach for determining discriminant validity. As a result, HTMT criteria were used to assess the discriminant validity [111] assert that if the values of (HTMT) were greater than 0.90, there were some validity problems. Kline [112] argues that there is discriminant validity if values are greater than 0.85. Table 6 indicates that all values were within the recommended criteria, measuring constructs were not overlapping each other and justified the discriminant validity test. Convergent validity refers to the degree to which two measures of constructs that should be related theoretically are actually related. The convergent validity test acceptability criteria are that AVE's value is well above the suggested value of 0.5 [113]. In Table 6, all measuring constructs had values greater than 0.5, indicating that they were highly related.

**Table 6.** Correlation, discriminant validity, and convergent validity analysis.


Notes: Diagonal values in parentheses represent the root square of AVEs.

Furthermore, the factor loadings and composite reliability (CR) test was performed to assess the consistency and stability of all variable elements. Table 7 presents the analysis of outer loadings and composite reliability. The recommended value of 0.5 was met by all outer loadings [114]. Composite reliability was used to ensure that the scale item was internally consistent. The criteria to check the reliability analysis were acceptable and have been used in numerous research [115]. Furthermore, Table 7 demonstrates that CR and Cronbach α values were far above the acceptable limit of 0.7, indicating that all scale items were internally consistent [113]. The outcomes of the measurement model demonstrated that the data were reliable and valid.

An Exploratory Factor Analysis (EFA) was used to find the detrimental conceptual model. Before performing EFA, the Kaiser–Meyer–Olkin (KMO) and Bartlett's sphericity tests (BTS) were used to assess the data fit [116]. The KMO test was used to determine the proportion of variance shared by variables. If the proportion was lower, more data were suitable for the factor analysis. The value should have been as close to 1.0 as possible. If the value was less than 0.50, it indicated that data were unsuitable for factor analysis. Table 8 evidences that the KMO value was 0.918, suggesting that a factor analysis could be performed [117]. Similarly, BTS generated a significant value of 9985.49 [118], satisfying the EFA requirement (see Table 8). The data were then scrutinized using the confirmatory factor analysis (CFA) to ensure that it was suitable for the proposed research context. The measurement model's content validity was verified since all items were substantially loaded on their respective constructs (see Figure 2).


**Table 7.** Factor loadings and results of reliability analysis.

Notes: extraction method–maximum likelihood; rotation method–Promax with Kaiser normalization.

**Table 8.** KMO and Bartlett's test.


**Figure 2.** Confirmatory factor analysis, representing that all items substantially loaded on the respective constructs.

#### *5.3. Structural Model Testing*

Upon reviewing the measurement model, we determined the structural model and evaluated the hypotheses. The collinearity diagnostic is shown in Table 9. Collinearity is a predictor–criterion concept that can be used to determine whether or not proposed variables calculated the same constructs. The collinearity test was recommended as a viable alternative for detecting common method bias. If the variance inflation factors (VIFs) are less than 10, the model is stated to be free of common method bias [119]. As a result, every latent variable had its VIFs generated. The results showed that the VIFs of all latent variables were less than 10. Our model was found to be free of common method bias. Table 10 illustrates the communalities finding. Osborne, Costello, and Kellow [120] define that communalities greater than 0.4 are acceptable. To determine the number of variables, only those with an eigenvalue greater than one were considered (see Table 11).


**Table 9.** Collinearity diagnostic test.

Notes: Dependent variable—WTAPV.

**Table 10.** Communalities findings.


Notes: extraction method–maximum likelihood.



Notes: rotation method—Promax with Kaiser normalization; cumulative variance—63.399%.

The Path diagram of the structural model is shown in Figure 3. There were three different levels of significance considered: (\*\*\*) indicates significance at the 0.1% (*p* = 0.001), (\*\*) signifies significance at the 1% level (*p* = 0.01), whereas (\*) signifies significance at the 5% level (*p* = 0.05). Insignificant paths are denoted by dotted lines, while constant lines denote significant paths. The belief about solar PV benefits H1 (*β* = 0.09, *p* = 0.01) and perception of self-efficacy H6 (*β* = 0.10, *p* = 0.01) were statistically significant at 5% and had a positive influence on dwellers' adoption of solar PV, according to the path diagram. Thus, we accepted the *H1* and *H6* hypotheses. Consumers' willingness to adopt solar PV was negatively influenced by perceived risk H3 (*β* = −0.4, *p* = 0.05) and positively influenced by social norms H5 (*β* = 0.12, *p* = 0.05). On the other hand, solar PV cost H2 (*β* = −0.01, *p* = 0.001) substantially influenced customer willingness at the 1% significance level. The path coefficient did not validate the hypothesis H4 (β = 0.80) because the variable "openness to technology" did not substantially impact dwellers' willingness to adopt, and it was refuted. The path of structural models and hypothesis significance are depicted in Table 12. The *R2* value was determined to be 0.73, indicating a significant interpretation because it exceeded the 0.35 value suggested by (Cohen, 2013). Various fitness measurements were also used to see whether the data were well-fitting for the proposed model. All fit

index values were in line with the prescribed requirements [121], according to the findings reported in Table 13. The Heckman test was used to analyze endogeneity to preserve that the findings were reliable [122]. Our findings showed that there was no endogeneity bias in our findings (see Table 14).

**Figure 3.** Diagram of structural model's path. Notes: \*\*\* *p* < 0.00, \*\* *p* < 0.01, \* *p* < 0.05.



Notes: \*\*\* *p* < 0.00, \*\* *p* < 0.01, \* *p* < 0.05.

**Table 13.** Goodness-of-fit indices values of the measurement and structural model.



**Table 14.** Endogeneity test.

Notes: \*\*\* *p* < 0.00, \*\* *p* < 0.01, \* *p* < 0.0.

#### **6. Discussion and Implications**

#### *6.1. Belief about Solar PV Benefits and Willingness to Adopt Solar PV*

The analysis results validated that consumers' WTA solar PV the is significantly influenced by their beliefs about its benefits. The findings of [66] also demonstrated that buyers' buying decisions were established on a solid faith in the advantages of the specific thing they needed to buy. Likewise, another recent study in Zambia factors influencing households' intention to adopt solar energy solutions revealed that due to its numerous advantages and the region's vast solar energy generation potential, solar energy solutions have become an attractive alternative to grid-based electricity, and many households are influencing their adoption [123]. Consumers can adopt solar PV if they can see the real advantages of using it over non-renewable resources. Similarly, a study conducted in India found that consumers are more receptive to adopting new technologies if they believe in the innovative benefits of technology [124]. Thus, in the early stages of its implementation, the Pakistani government must emphasize the advantages of solar PV, and consumers' confidence in solar PV will grow over time.

#### *6.2. Solar PV Cost and Willingness to Adopt Solar PV*

The study's findings added to the body of knowledge by indicating that SPVC negatively influenced dwellers' acceptance. Users' intentions to install a solar PV system were mostly influenced by price, and previous studies back up these findings [125,126]. Due to the higher cost of rooftop solar PV, a recent study in the United States discovered that lowand moderate-income (LMI) households are less likely to install it. The findings indicate that when financial incentives, PV leasing, and property-assessed financing are used, PV adoption among LMI households in established markets increases and solar installation expansion is facilitated [127]. As a response, policymakers should consider price value when developing and implementing energy policies in Pakistan. Household tax relief and other incentive programs are needed. In addition, solar PV companies should spend more on technology and research to tackle the technology's perceived price issue.

#### *6.3. Perceived Risk and Willingness to Adopt Solar PV*

The results confirmed that consumers' perceptions of risk had an adverse influence on their adoption of solar PV. Past research also supports this result [73,74]. Physical and health protection has indeed become a global regulatory concern. As a result, Pakistan's government should empower solar PV companies to manufacture risk-free technology and employ personnel with experience and a willingness to assist and support their clients, even after they have purchased their products. Simultaneously, marketers can provide consumers with sufficient knowledge and advice on operating a solar PV system. The removal of these risk beliefs gives people more interest in adopting new technologies, which can be a key factor in the future.

#### *6.4. Openness to Technology and Willingness to Adopt Solar PV*

Openness is a personality trait that indicates that individuals with a high openness level are intellectually curious and receptive to unique ideas and pro-environmental practices. These individuals are more apt to take risks. Additionally, they are more susceptible

to adopting new technologies quickly and easily. As per results, hypothesis four had no substantial effect on willingness to adopt solar PV. This result differed from previous research findings, which showed that customers with a high degree of openness were enthusiastic about emerging technology, and their acceptability was high [128,129]. Previous studies conducted in developed countries show that the adoption of new emerging technologies is common there. However, in Pakistan, literacy rates are relatively low, and people are more comfortable using technology. Thus, in Pakistan, purchasing decisions are not affected directly by the openness to technology.

#### *6.5. Social Norms and Willingness to Adopt Solar PV*

As per findings, SOCN had an important influence on dwellers' willingness to adopt solar PV. Research findings supported previous research by those who found that SOCN has a major influence on dwellers' intentions. Another study by [130] found that dwellers' behavior is directly affected by social norms. According to [131], the result of a consumer's product intake is predetermined by social norms. When people have a negative perception of a product, their intake of that product drops dramatically [132]. Nevertheless, the results showed that promoting conditions were determined by the outcome of social norms. Individuals who portray solar energy as having a positive environmental effect would be more likely to accept it [133]. Pakistan has a socially constructed structure, and the behavior of society and neighbors has a huge effect on people's minds. The previous impression of peers to the use of solar PV may influence dwellers' actions in such a way that a positive experience allows for solar PV acceptance. On the contrary, negative experiences have a different effect. Each country has its distinct social characteristics. As a result, companies use corporate governance as a social tool. If community members believe that the norms are fair or in everyone's best interest, they will share and adhere to them, as well as adopt those technologies. Similarly, researcher explore the corporate governance in the Romanian economy using the Bucharest Stock Exchange's corporate governance code. Corporate governance refers to the procedures and policies that a business uses to accomplish its stated goals. In conclusion, implementing a corporate governance code in the Romanian energy system has increased companies' overall liquidity, which contributes to an increase in the overall performance [134]. As a result, SOCN plays a key role in the decision-making framework.

#### *6.6. Perception of Self-Efficacy and Willingness to Adopt Solar PV*

The findings revealed that consumers' perceptions of self-efficacy had a positive impact on their willingness. This conclusion is backed up by previous research [135–137]. Another study conducted in Telangana revealed that ease of use plays a vital role in customers' attitude towards solar energy [138]. The energy efficiency, energy savings, and environmentally friendly solar PVs inherent characteristics are all factors that may encourage residents to use it. PVs for domestic use are also handy and simple to install, with such a long lifespan. Dwellers' assessments of technology and understanding about how to use it would boost dweller's interest in solar PV as vital developments in the near future.

#### **7. Conclusions and Policy Recommendations**

Being an environmentally friendly technology, solar PV has the potential of reducing carbon emissions; however, studies examining consumers' WTA solar PV technology are limited. This study focused on this research gap by incorporating novel factors (perceived risk, self-efficacy, and openness to technology) with existing factors (social norm, solar PV cost, and belief of solar PV benefits) in the conceptual framework of TPB to comprehensively investigate the consumer's adoption mechanism. Data were gathered from Pakistan's provincial capitals and analyzed using SEM. The research findings revealed that social norms, perception of self-efficacy, and belief about solar PV benefits positively affected consumer willingness to adopt solar PV. On the other hand, perceived risk and solar PV cost negatively affected consumers' willingness. Interestingly, openness to technology had an insignificant impact.

Pakistan, such as other developing countries, is facing environmental degradation issues. Global recognition has been accorded to sustainable energy technologies. Additionally, a number of countries are putting in significant amounts of investment in these technologies. This study's conclusions have significant ramifications for the government and solar PV vendors' efforts to promote solar PV deployment in Pakistan. An alternative energy board and the Ministry of climate change should create awareness programs for the public and promote the benefits of solar PV. They should reassure the public that solar PV provides sustainable solutions for combating climate change and the planet's ongoing degradation. As a consequence, dwellers will consider solar PV more beneficial and will feel more confident installing and using it.

The study's findings are instructive for policymakers and developers. Cost was a significant concern for many users; therefore, the Pakistani government should provide subsidies and sufficient financial assistance in collaboration with solar PV companies. Make sure the availability of financial incentives, such as grants, assist people install home solar PV systems. Solar PV companies must develop risk-free technologies and recruit a knowledgeable workforce which could provide sufficient technical support to their customers. Furthermore, in order to attract multinational businesses, the government should provide tax relief; this would increase market pressure, causing companies to boost product quality. When consumers are weighing the pros and cons of different solar PV options, such initiatives will help them decide to adopt solar PV. The importance of perceived risk, self-efficacy, and the price were highlighted in the conceptual context for this analysis, and the results were robust for Pakistan, indicating that the findings may be transferable to other countries.

There were a few limitations to this study that should be considered in future works. First, the analysis only considered provincial capitals, where the infrastructure and quality of living are much superior to other cities. This flaw can be addressed in future research by incorporating consumer input from other cities. Second, we approached the analysis from the consumer's perspective; future research can explore the supply side. Third, due to the country-wide lockdown situation during COVID-19, conducting a large-scale questionnaire survey was impossible. In this respect, a sample of 683 respondents was insufficient for a country with a 37 M population. Subsequent researchers should extend the sample size to overcome this constraint. Finally, it would be interesting to perform a cost–benefit analysis and determine the Levelized cost of electricity. This critical feature may be addressed in future investigations in order to add to the existing body of knowledge.

**Author Contributions:** Conceptualization, M.I. and A.T.; methodology, M.I.; software, M.I.; validation, M.I.; formal analysis, M.I.; investigation, M.I.; resources, S.Z.; data curation, M.I.; writing original draft preparation, A.T.; writing—review and editing, M.I., A.T., S.Z., R.P.; visualization, M.I.; supervision, M.I., S.Z.; project administration, S.Z.; funding acquisition, S.Z. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by Beijing Nova Program of Science & Technology under grant Z191100001119100 for Rui Peng.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Informed consent was obtained from all subjects involved in the study.

**Data Availability Statement:** The data will be made a vailable on reasonable request from the corresponding author.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **Acronyms and Abbreviations**


#### **Appendix A. Questionnaire Survey**


#### **Part B. Factors Influencing Consumers' Willingness to Adopt Solar PV**


I have power over all resources to adopt solar PV I have power over the adoption of solar PV services My home has sufficient space for solar PV Solar PV energy is not difficult to use; therefore, I am capable of adopting it I would not have any difficulty adopting solar PV if I wanted to Social norms The majority of people who are important to me encourage me to use solar PV Those who have my best interests at heart would prefer that I purchase solar PV When it comes to energy-saving behavior, most of the people who matter to me believe that I should buy solar PV People close to me believe that solar PV should play a significant role in reducing greenhouse gas emissions People I care about adopt solar PV Solar PV adoption is increasing among those in my close surroundings Most of the people in my social network advise me to use solar PV. Solar PV benefits Adopting solar PV will help to reduce carbon emission. Adopting solar PV will help to improve the clean environment.. The development of solar PV projects will aid in the reduction in greenhouse gas emissions and the creation of new job opportunities. Solar PV adoption will aid in the improvement of the energy structure. Solar PV is the most efficient source of energy. Generally, solar PV systems do not require much maintenance. Solar PV energy will assist in lowering electricity bills. Willingness to adopt solar PV I am willing to pay more for solar PV because it saves energy. I am willing to adopt solar PV because I can afford it. I strongly encourage others to adopt solar PV because it contributes to a clean environment Solar PV appeals to me because it is eco-friendly

#### Notes: 1—strongly disagree; 2—disagree; 3—slightly disagree 4—neutral; 5—slightly agree; 6—agree, 7—strongly agree.

#### **References**


**Cheng Luo 1, Xikui Ma 1, Lihui Yang 1,\*, Yongming Li 1, Xiaoping Yang 2, Junhui Ren <sup>2</sup> and Yanmei Zhang <sup>2</sup>**


**Abstract:** Under unbalanced grid voltage faults, the output power oscillation of a grid-connected inverter is an urgent problem to be solved. In the traditional topology of inverters, it is impossible to eliminate power oscillation and simultaneously maintain balanced output current waveform. In this paper, considering the solvability of reference current matrix equation, the inherent mechanism of inverter output power oscillation is analyzed, and a modified topology with auxiliary modules inserted in series between the inverter output filter and the point of common coupling (PCC) is proposed. Due to the extra controllable freedoms provided by auxiliary modules, the inverter could generate extra voltage to correct PCC voltage while keeping balance of output current, so as to eliminate the oscillation of output power. Simulation and experimental results verify the effectiveness of the proposed topology.

**Keywords:** modified gird-connected inverter topology; negative-sequence component; power oscillation; unbalanced grid voltage fault

#### **1. Introduction**

The grid-connected inverter is the vital interface module for distributed generation (DG) systems, including wind power generation, photovoltaic power generation, to be connected to the grid. It can directly determine the value and direction of current and power and is crucial for the safe operation of the grid [1,2]. Small and medium-sized DG systems are often connected to the grid through the power distribution network. However, due to the abnormal weather conditions, large load switching on–off, insulation failure, human error and so on, voltage faults often occur in the power distribution network. Most of voltage faults can be attributed to the asymmetric faults of grid voltage, for example, the unbalanced voltage fault caused by single-phase grounding is a representative type [3]. In the case of asymmetric faults, the grid-connected inverter is required to have the low voltage ride through (LVRT) capability so as to avoid the chain reaction of DGs disconnection with the grid [4,5]. When the voltage at the point of common coupling (PCC) drops, grid code requires the inverter to keep connecting with the grid for a certain period of time [3]. At the same time, the grid-connected inverter should have the power transmission capacity under abnormal voltage at PCC [1,6]. Under unbalanced PCC voltage, the traditional current closed-loop control strategy which only controls positive-sequence current in essence will cause output power oscillation so as to enlarge the voltage ripple of DC side bus and damage the output current quality [6–9]. To enhance the performance of inverters, it is necessary to eliminate the output power oscillation of grid-connected inverters under unbalanced PCC voltage.

At present, the main methods to eliminate the output power oscillation of gridconnected inverter under unbalanced grid voltage can be divided into two categories: the

**Citation:** Luo, C.; Ma, X.; Yang, L.; Li, Y.; Yang, X.; Ren, J.; Zhang, Y. A Modified Grid-Connected Inverter Topology for Power Oscillation Suppression under Unbalanced Grid Voltage Faults. *Energies* **2021**, *14*, 5057. https://doi.org/10.3390/en14165057

Academic Editor: Mohamed Benbouzid

Received: 18 July 2021 Accepted: 15 August 2021 Published: 17 August 2021

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

first type is to improve the control strategy; the second one is to change the topology of the inverter. In [6,10,11], different proportions of negative-sequence current is added to the current reference to decrease power oscillation. The main problem is that the output current has difficulty meeting the requirements of grid codes, and there may be risk of current overrun. In [12,13], the power reference is modified by considering the upper current limit value of switch tube to guarantee that the output current will not exceed the maximum allowable value. However, the waveform of the output current is seriously distorted. A positive and negative-sequence conductance and susceptance control scheme is proposed in [14]. By optimizing the value of negative-sequence conductance, the peak value of the output current can be controlled, but the power oscillation is not effectively reduced. The second type of strategy is to eliminate the power oscillation by changing the topology of the inverter. In [15], a three-phase four-wire system with zero-sequence current channel is proposed. The introduction of zero-sequence current increases the controllable quantity of the system, which is conducive to eliminating power oscillation and improving current quality. Nevertheless, the power oscillation still exists when adopting the current closedloop control strategy. In one word, the reference current matrix equation of grid-connected inverter in the topologies mentioned above cannot meet the solvability condition, which is the essential reason that the power oscillation could not be eliminated while the current waveform is balanced.

In this paper, a modified grid-connected inverter topology with auxiliary modules inserted in series between PCC and the output filter of each phase is proposed, which could increase the controllable freedoms of reference current equation of inverter so as to make the reference current equation of the inverter meet the solvability condition. Then, the oscillation of the output power is eliminated, and the negative-sequence current is avoided to be injected into power grid simultaneously. The simulation and experimental results are presented to verify the effectiveness of the modified topology.

#### **2. Relationship between Power Oscillation and Grid Voltage in Traditional Topology**

Typical grid voltage faults can be divided into seven categories [16], most of them are asymmetric faults. Unbalanced voltage fault caused by single-phase grounding is a representative one [3]. The unbalanced voltage at PCC will cause the oscillation of output power and the distortion of output current, which will affect the safe operation of the grid-connected inverters [11].

#### *2.1. Relationship among Output Current, Power Oscillation and Unbalanced Voltage*

The traditional control strategy of grid-connected inverters under unbalanced grid voltage can be summarized as a unified control strategy [10,11,17], which uses different values of adjustment coefficient (−1 ≤ *k* ≤ 1) to reflect different control strategies, as shown in Table 1. No matter what control strategy is used, it is always difficult to achieve the optimal output current and power at the same time. A quantitative numerical analysis is given as follows.


**Table 1.** Output effect under different adjustment coefficient *k*.

#### (1). Numerical analysis of output current

Since there is no zero-sequence current component channel in the three-phase threewire power distribution network, the voltage at PCC and output current can be expressed in Equation (1):

$$
\begin{bmatrix} u\_{a} \\ u\_{b} \\ u\_{c} \end{bmatrix} = \mathcal{U}^{+} \begin{bmatrix} \sin(\omega t + \theta\_{\text{vp}}) \\ \sin(\omega t + \theta\_{\text{vp}} - 120^{\circ}) \\ \sin(\omega t + \theta\_{\text{vp}} + 120^{\circ}) \end{bmatrix} + \mathcal{U}^{-} \begin{bmatrix} \sin(\omega t + \theta\_{\text{v}\text{n}}) \\ \sin(\omega t + \theta\_{\text{v}\text{n}} + 120^{\circ}) \\ \sin(\omega t + \theta\_{\text{v}\text{n}} - 120^{\circ}) \end{bmatrix} + \mathcal{U}^{0} \begin{bmatrix} \sin(\omega t + \theta\_{0}) \\ \sin(\omega t + \theta\_{0}) \\ \sin(\omega t + \theta\_{0}) \end{bmatrix} \tag{1}
$$

$$
\begin{bmatrix} i\_a \\ i\_b \\ i\_c \end{bmatrix} = I^+ \begin{bmatrix} \sin(\omega t + \theta\_{ip}) \\ \sin(\omega t + \theta\_{ip} - 120^\circ) \\ \sin(\omega t + \theta\_{ip} + 120^\circ) \end{bmatrix} + I^- \begin{bmatrix} \sin(\omega t + \theta\_{in}) \\ \sin(\omega t + \theta\_{in} + 120^\circ) \\ \sin(\omega t + \theta\_{in} - 120^\circ) \end{bmatrix} \tag{2}
$$

where *U*+, *U*<sup>−</sup> and *U*<sup>0</sup> are the amplitudes of positive, negative and zero-sequence components of the voltage, *I* <sup>+</sup> and *I*<sup>−</sup> are the amplitudes of positive and negative-sequence components of output current, *θvp*, *θvn* and *θ*<sup>0</sup> are the initial phase angles of positive, negative and zero-seqence components of the voltage, *θip* and *θin* are the initial phase angles of positive, negative-sequence component of output current and *ω* is the angular frequency of the voltage, respectively.

When the three-phase inverter is connected to the grid, the current reference value is shown in Equations (3) and (4) [12].

$$\begin{aligned} I\_a^\* &= \frac{2}{3} \frac{P^\*}{\left(\left(\varprojlim\nolimits\right)^2 + k\left(\varprojlim\nolimits\right)^2\right)} \left[\varprojlim\nolimits \left(\varprojlim\nolimits + \theta\_{vp}\right) + k\left\varprojlim\nolimits \left(\varprojlim\nolimits + \theta\_{vn}\right)\right] \\ &+ \frac{2}{3} \frac{Q^\*}{\left(\varprojlim\nolimits\right)^2 + k\left(\varprojlim\nolimits\right)^2} \left[-\varprojlim\nolimits \left(\varprojlim\nolimits + \theta\_{vp}\right) - k\left(\varprojlim\nolimits + \theta\_{vn}\right)\right] \end{aligned} \tag{3}$$

$$\begin{split} I\_{\beta}^{\*} &= \frac{2}{3} \frac{P^{\*}}{\left(lI^{+}\right)^{2} + k\left(lI^{-}\right)^{2}} \left[ -lI^{+} \cos\left(\omega t + \theta\_{vp}\right) + klI^{-} \cos\left(\omega t + \theta\_{vn}\right) \right] \\ &+ \frac{2}{3} \frac{Q^{\*}}{\left(lI^{+}\right)^{2} - k\left(lI^{-}\right)^{2}} \left[ -lI^{+} \sin\left(\omega t + \theta\_{vp}\right) + klI^{-} \sin\left(\omega t + \theta\_{vn}\right) \right] \end{split} \tag{4}$$

where *P*\* and *Q*\* are the reference values of active power and reactive power, respectively. After transformation to *abc* coordinate system, Equations (5)–(7) are obtained,

$$I\_a^\* = \frac{2}{3}\sqrt{A\_1^2 + (kA\_2)^2 + 2kA\_1A\_2\cos(\theta\_{vp} - \theta\_{vn} - 2\delta)} \cdot \sin(\omega t + \psi\_a) \tag{5}$$

$$I\_b^\* = \frac{2}{3}\sqrt{A\_1^2 + \left(kA\_2\right)^2 + 2kA\_1A\_2\cos\left(\theta\_{\text{vp}} - \theta\_{\text{vn}} - 2\delta - 240^\circ\right)} \cdot \sin\left(\omega t + \psi\_b\right) \tag{6}$$

$$I\_c^\* = \frac{2}{3}\sqrt{A\_1^2 + \left(kA\_2\right)^2 + 2kA\_1A\_2\cos\left(\theta\_{\text{vp}} - \theta\_{\text{vn}} - 2\delta + 240^\circ\right)} \cdot \sin\left(\omega t + \psi\_\mathbb{C}\right) \tag{7}$$

where,

$$A\_{1} = \sqrt{\left[\frac{P^\*\mathcal{U}^+}{\left(\mathcal{U}^+\right)^2 + k(\mathcal{U}^-)^2}\right]^2 + \left[\frac{Q^\*\mathcal{U}^+}{\left(\mathcal{U}^+\right)^2 - k(\mathcal{U}^-)^2}\right]^2}$$

$$\delta = \arctan\frac{Q^\*\left[\left(\mathcal{U}^+\right)^2 + k(\mathcal{U}^-)^2\right]}{P^\*\left[\left(\mathcal{U}^+\right)^2 - k(\mathcal{U}^-)^2\right]}$$

$$A\_2 = \sqrt{\left[\frac{P^\*\mathcal{U}^-}{\left(\mathcal{U}^+\right)^2 + k(\mathcal{U}^-)^2}\right]^2 + \left[\frac{Q^\*\mathcal{U}^-}{\left(\mathcal{U}^+\right)^2 - k(\mathcal{U}^-)^2}\right]^2}$$

$$\psi\_d = \arctan\frac{A\_1\sin(\theta\_{vp}-\delta) + kA\_2\sin(\theta\_{vn}-\delta)}{A\_1\cos(\theta\_{vp}-\delta) + kA\_2\cos(\theta\_{vn}-\delta)}$$

$$\psi\_{\theta\text{-}} = \arctan\frac{A\_1\sin(\theta\_{vp}-\delta-120^\circ) + kA\_2\sin(\theta\_{vn}-\delta+120^\circ)}{A\_1\cos(\theta\_{vp}-\delta-120^\circ) + kA\_2\cos(\theta\_{vn}-\delta+120^\circ)}$$

$$\psi\_{\varepsilon} = \arctan \frac{A\_1 \sin(\theta\_{vp} - \delta + 120^{\circ}) + k A\_2 \sin(\theta\_{vn} - \delta - 120^{\circ})}{A\_1 \cos(\theta\_{vp} - \delta + 120^{\circ}) + k A\_2 \cos(\theta\_{vn} - \delta - 120^{\circ})}.$$

When three-phase inverter is in grid-connected operation state, the current closed-loop control strategy is often used [8], so the output current could accurately track the reference value. The maximum value of output current is given as Equation (8):

$$\begin{split} I\_{\text{max}} &= \quad \max \left\{ \frac{2}{3} \sqrt{A\_1^2 + (kA\_2)^2 + 2kA\_1A\_2 \cos(\theta\_p - \theta\_n - 2\delta)}, \\ &\frac{2}{3} \sqrt{A\_1^2 + (kA\_2)^2 + 2kA\_1A\_2 \cos(\theta\_p - \theta\_n - 2\delta - 240^\circ)}, \\ &\frac{2}{3} \sqrt{A\_1^2 + (kA\_2)^2 + 2kA\_1A\_2 \cos(\theta\_p - \theta\_n - 2\delta + 240^\circ)} \right\}. \end{split} \tag{8}$$

It can be seen from Equations (5)–(7) that the amplitudes and phase angles of threephase currents are related to the amplitudes of positive and negative-sequence voltages, initial phase angles of positive and negative-sequence voltages, power reference value and adjustment coefficient *k*. To ensure that the output current of grid-connected inverters meets the grid codes [18,19], the only way is to set the adjustment coefficient *k* as 0, which means to use the balanced positive sequence control (BPSC) strategy [20].

According to Equation (8), when the parameters of Table 2 are adopted, the relationship between the maximum value of output current amplitude and the adjustment coefficient *k* is shown in Figure 1. When *k* changes from −1 to 1, the maximum value of output current amplitude decreases firstly and then increases, and the BPSC control method, which means *k* as 0, can ensure that the current stress of the inverter is minimum under the same power.

#### (2). Analysis of power oscillation

According to the instantaneous power theory, the active power and reactive power can be expressed as Equations (9) and (10):

$$\begin{aligned} p &= \frac{3}{2} u\_a \left[ A\_1 \sin(\omega t + \theta\_{vp} - \delta) + k A\_2 \sin(\omega t + \theta\_{vu} - \delta) \right] \\ &+ \frac{3}{2} u\_\beta \left[ -A\_1 \cos(\omega t + \theta\_{vp} - \delta) + k A\_2 \cos(\omega t + \theta\_{vu} - \delta) \right] \end{aligned} \tag{9}$$

$$\begin{array}{lcl}q&=&-\frac{3}{2}\boldsymbol{\mu\_{a}}\left[-A\_{1}\cos(\omega t + \theta\_{\upsilon\eta}-\delta)+kA\_{2}\cos(\omega t + \theta\_{\upsilon\eta}-\delta)\right] \\ &+\frac{3}{2}\boldsymbol{\mu\_{\beta}}\left[A\_{1}\sin(\omega t + \theta\_{\upsilon\eta}-\delta)+kA\_{2}\sin(\omega t + \theta\_{\upsilon\eta}-\delta)\right] \end{array} \tag{10}$$

where *u<sup>α</sup>* and *u<sup>β</sup>* are the *αβ* axis components of the PCC voltage, respectively.

When expanding Equations (9) and (10), the quadratic term is the fluctuating power, as shown in Equations (11) and (12):

$$\begin{aligned} \Delta p &= -(1+k) \frac{P^\*}{\left(\mathcal{U}^+\right)^2 + k\left(\mathcal{U}^-\right)^2} \mathcal{U}^+ \mathcal{U}^- \cos(2\omega t + \theta\_{\text{vp}} + \theta\_{\text{vn}})\\ &- (1+k) \frac{\mathcal{Q}^\*}{\left(\mathcal{U}^+\right)^2 - k\left(\mathcal{U}^-\right)^2} \mathcal{U}^+ \mathcal{U}^- \sin(2\omega t + \theta\_{\text{vp}} + \theta\_{\text{vn}}) \end{aligned} \tag{11}$$

$$\begin{split} \Delta q &= (1-k) \frac{P^\*}{\left(lI^+\right)^2 + k\left(lI^-\right)^2} lI^+ lI^- \sin\left(2\omega t + \theta\_{\text{vp}} + \theta\_{\text{vn}}\right) \\ &- (1-k) \frac{Q^\*}{\left(lI^+\right)^2 - k\left(lI^-\right)^2} lI^+ lI^- \cos\left(2\omega t + \theta\_{\text{vp}} + \theta\_{\text{vn}}\right). \end{split} \tag{12}$$

When the parameters shown in Table 2 are adopted, the relationship between the power oscillation value and the adjustment coefficient *k* is shown in Figure 2. When *k* changes from −1 to 1, the oscillation value of output power can reach 0.4 p.u. at most. The change trend of active power oscillation value is just opposite to that of reactive power oscillation value. It is impossible to make active power oscillation value and reactive power oscillation value minimal at the same time by changing *k*. When BPSC is used, the oscillation value of active power and reactive power can reach 0.2 p.u., which means that the oscillation of output power is not eliminated.


**Table 2.** Operating parameters of main circuit used in simulations.

**Figure 1.** Maximum value of output current amplitude varying with the adjustment coefficient.

**Figure 2.** Oscillation value of output power varying with the adjustment coefficient.

The variation of *k* represents different control strategies. The power oscillation cannot be eliminated by just changing the control strategy when the topology is not optimized. The next section will give a strict theoretical proof.

#### *2.2. Deficiency of Traditional Inverter Topology*

After Clark transformation, Equation (1) can be written as Equation (13):

$$
\begin{bmatrix} u\_{\mathfrak{a}} \\ u\_{\mathfrak{f}} \end{bmatrix} = \frac{2}{3} \begin{bmatrix} 1 & -\frac{1}{2} & -\frac{1}{2} \\ 0 & \frac{\sqrt{3}}{2} & -\frac{\sqrt{3}}{2} \end{bmatrix} \begin{bmatrix} u\_{\mathfrak{a}} \\ u\_{\mathfrak{b}} \\ u\_{\mathfrak{c}} \end{bmatrix} = \begin{bmatrix} u\_{\mathfrak{a}}^{+} + u\_{\mathfrak{a}}^{-} \\ u\_{\mathfrak{f}}^{+} + u\_{\mathfrak{f}}^{-} \end{bmatrix} \tag{13}
$$

where

$$
\begin{bmatrix} u\_a^+ \\ u\_\beta^+ \end{bmatrix} = \begin{bmatrix} \mathcal{U}^+ \sin(\omega t + \theta\_{vp}) \\ -\mathcal{U}^+ \cos(\omega t + \theta\_{vp}) \end{bmatrix} \begin{bmatrix} u\_a^- \\ u\_\beta^- \end{bmatrix} = \begin{bmatrix} \mathcal{U}^- \sin(\omega t + \theta\_{vn}) \\ \mathcal{U}^- \cos(\omega t + \theta\_{vn}) \end{bmatrix}.$$

Three-phase output currents can be written as Equation (14):

$$
\begin{bmatrix} i\_a \\ i\_\beta \end{bmatrix} = \frac{2}{3} \begin{bmatrix} 1 & -\frac{1}{2} & -\frac{1}{2} \\ 0 & \frac{\sqrt{3}}{2} & -\frac{\sqrt{3}}{2} \end{bmatrix} \begin{bmatrix} i\_a \\ i\_b \\ i\_c \end{bmatrix} = \begin{bmatrix} i\_a^+ + i\_a^- \\ i\_\beta^+ + i\_\beta^- \\ \beta^+ + i\_\beta^- \end{bmatrix} \tag{14}$$

where

$$
\begin{bmatrix} i\_a^+ \\ i\_\beta^+ \end{bmatrix} = \begin{bmatrix} I^+ \sin(\omega t + \theta\_{ip}) \\ -I^+ \cos(\omega t + \theta\_{ip}) \end{bmatrix} \begin{bmatrix} i\_a^- \\ i\_\beta^- \end{bmatrix} = \begin{bmatrix} I^- \sin(\omega t + \theta\_{in}) \\ I^- \cos(\omega t + \theta\_{in}) \end{bmatrix}.
$$

The instantaneous output power is given as Equation (15):

$$
\begin{bmatrix} p \\ q \end{bmatrix} = \begin{bmatrix} v\_{a}i\_{a} + v\_{\beta}i\_{\beta} \\ v\_{a}i\_{\beta} - v\_{\beta}i\_{a} \end{bmatrix} = \begin{bmatrix} P\_{0} + P\_{c2}\cos(2\omega t) + P\_{s2}\sin(2\omega t) \\ Q\_{0} + Q\_{c2}\cos(2\omega t) + Q\_{s2}\sin(2\omega t) \end{bmatrix} \tag{15}
$$

where *P*<sup>0</sup> is the DC component value of active power, *P*c2 and *P*s2 are the coefficients of cosine and sinusoidal terms for the second oscillation value of active power, *Q*<sup>0</sup> is the DC component value of reactive power, *Q*c2 and *Q*s2 are the coefficients of cosine and sinusoidal terms for the second oscillation value of reactive power.

*P*0, *Pc*2, *Ps*2, *Q*0, *Qc*<sup>2</sup> and *Qs*<sup>2</sup> can be expressed by matrix as Equation (16):

$$
\begin{bmatrix} P\_0 \\ Q\_0 \\ P\_{c2} \\ P\_{s2} \\ Q\_{c2} \\ Q\_{s2} \end{bmatrix} = \begin{bmatrix} \upsilon\_d^+ & \upsilon\_q^+ & \upsilon\_d^- & \upsilon\_q^- \\ \upsilon\_q^+ & -\upsilon\_d^+ & \upsilon\_q^- & -\upsilon\_d^- \\ -\upsilon\_d^- & -\upsilon\_q^- & -\upsilon\_d^+ & -\upsilon\_q^+ \\ -\upsilon\_q^- & \upsilon\_d^- & \upsilon\_q^+ & -\upsilon\_d^+ \\ -\upsilon\_q^- & \upsilon\_d^- & -\upsilon\_q^+ & \upsilon\_d^+ \\ \upsilon\_d^- & \upsilon\_q^- & -\upsilon\_d^+ & -\upsilon\_q^+ \end{bmatrix} \begin{bmatrix} i\_d^+ \\ i\_q^+ \\ i\_d^- \\ i\_q^- \end{bmatrix} \tag{16}
$$

where *v*<sup>+</sup> *<sup>d</sup>* , *<sup>v</sup>*<sup>+</sup> *<sup>q</sup>* are the *dq* axis components of *u*<sup>+</sup> *<sup>α</sup>* , *<sup>u</sup>*<sup>+</sup> *<sup>β</sup>* ; *v*<sup>−</sup> *<sup>d</sup>* , *v*<sup>−</sup> *<sup>q</sup>* are the *dq* axis components of *u*− *<sup>α</sup>* , *u*<sup>−</sup> *<sup>β</sup>* ; *i* + *<sup>d</sup>* , *i* + *<sup>q</sup>* are the *dq* axis components of *i* + *<sup>α</sup>* , *i* + *<sup>β</sup>* ; *i* − *<sup>d</sup>* , *i* − *<sup>q</sup>* are the *dq* axis components of *i* − *α* , *i* − *<sup>β</sup>* after Park transformation, respectively.

When the output current meets the grid codes [18,19], the negative-sequence current should be set as zero, then Equation (16) will be changed into Equation (17):

$$
\begin{bmatrix} P\_0 \\ Q\_0 \\ P\_{c2} \\ P\_{s2} \\ Q\_{c2} \\ Q\_{s2} \end{bmatrix} = \begin{bmatrix} \upsilon\_d^+ & \upsilon\_q^+ \\ \upsilon\_q^+ & -\upsilon\_d^+ \\ -\upsilon\_d^- & -\upsilon\_q^- \\ -\upsilon\_q^- & \upsilon\_d^- \\ -\upsilon\_q^- & \upsilon\_d^- \\ \upsilon\_d^- & \upsilon\_q^- \end{bmatrix} \begin{bmatrix} \dot{i}\_d^+ \\ \dot{i}\_q^+ \end{bmatrix}. \tag{17}
$$

In Equation (16), the rank of the coefficient matrix is 4, the rank of the augmented matrix is 5. The rank of the coefficient matrix is not equal to the rank of the augmented matrix, so Equation (16) has no solution. This is the reason why the control strategy in [10–14] has difficulty eliminating the power oscillation.

In Equation (17), the rank of the coefficient matrix is 2, the rank of the augmented matrix is 3. The rank of the coefficient matrix is not equal to the rank of the augmented matrix, so Equation (17) has no solution. This is the reason why the BPSC control strategy has difficulty eliminating power oscillation for the traditional topology.

In the same way, it can be found that after adding a zero-sequence component in [15], Equation (17) becomes:

$$
\begin{bmatrix} P\_0 \\ Q\_0 \\ P\_{\mathcal{C}2} \\ P\_{\mathcal{S}2} \\ Q\_{\mathcal{C}2} \\ Q\_{\mathcal{S}2} \end{bmatrix} = \begin{bmatrix} \upsilon\_d^+ & \upsilon\_q^+ & \upsilon\_{\text{Re}}^0 & \upsilon\_{\text{Im}}^0 \\ \upsilon\_q^+ & -\upsilon\_d^+ & 0 & 0 \\ -\upsilon\_d^- & -\upsilon\_q^- & \upsilon\_{\text{Re}}^0 & -\upsilon\_{\text{Im}}^0 \\ -\upsilon\_q^- & \upsilon\_d^- & -\upsilon\_{\text{Im}}^0 & -\upsilon\_{\text{Re}}^0 \\ -\upsilon\_q^- & \upsilon\_d^- & 0 & 0 \\ \upsilon\_d^- & \upsilon\_q^- & 0 & 0 \end{bmatrix} \begin{bmatrix} i\_d^+ \\ i\_q^+ \\ i\_{\text{Re}}^0 \\ i\_{\text{Im}}^0 \end{bmatrix} \tag{18}
$$

where *v*<sup>0</sup> Re, *<sup>v</sup>*<sup>0</sup> Im are the real and imaginary components of zero-sequence voltage at PCC, *i* 0 Re, *i* 0 Im are the real and imaginary components of zero-sequence output current, the detailed definition refers to [15].

In (18), the rank of the coefficient matrix is 4, the rank of the augmented matrix is 5. The rank of the coefficient matrix is not equal to the rank of the augmented matrix, so Equation (18) has no solution. This is the reason why the BPSC control strategy has difficulty eliminating power oscillation for three-phase four-wire inverter in [15].

#### **3. Principle and Advantages of Modified Topology for Grid-Connected Inverter**

According to the discussion in Section 2, the reason why the traditional topology is incapable of eliminating the power oscillation is that the number of controllable free variables is small, which leads to the mismatch between the order of the current reference coefficient matrix and the order of the augmented matrix. From the point of view on hardware, the number of controllable variables in the current reference equation can be increased by changing the topology structure, so that the equation can meet the solvability conditions.

#### *3.1. Modified Topology of Grid-Connected Inverters*

The proposed topology of grid-connected inverter is shown in Figure 3. The auxiliary modules are inserted in series between the output filter of inverter (the points *a*1, *b*<sup>1</sup> and *c*<sup>1</sup> in Figure 3a) and PCC (the points *a*2, *b*<sup>2</sup> and *c*<sup>2</sup> in Figure 3a).

**Figure 3.** Structure block diagram of the modified topology of grid-connected inverter: (**a**) general system diagram. (**b**) Auxiliary module block diagram.

The three-phase auxiliary modules are independent of each other and can be separately controlled. Figure 3b shows the detailed internal block diagram of the auxiliary module which is essentially a single-phase inverter. *L*add and *C*add constitute the output filter circuit of the auxiliary module to filter the switching subharmonics in the circuit. *R*add is the damping resistance of the output filter circuit to prevent the possible oscillation of the LC filter circuit. For the voltages at PCC1, Equation (19) could be obtained as:

$$
\upsilon\_{a1} = \upsilon\_a + \Delta \upsilon\_a \\
\upsilon\_{b1} = \upsilon\_b + \Delta \upsilon\_b \\
\upsilon\_{c1} = \upsilon\_c + \Delta \upsilon\_c \tag{19}
$$

where Δ*va*, Δ*vb* and Δ*vc* are the output voltages of auxiliary modules in phases A, B and C, respectively.

Accordingly, Equation (17) can be changed into Equation (20):

⎡ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎣

$$
\begin{bmatrix} P\_0 \\ Q\_0 \\ P\_{c2} \\ P\_{s2} \\ Q\_{c2} \\ Q\_{s2} \end{bmatrix} = \begin{bmatrix} v\_d^+ + \Delta v\_d^+ & v\_q^+ + \Delta v\_q^+ \\ v\_q^+ + \Delta v\_q^+ & -v\_d^+ - \Delta v\_d^+ \\ -v\_d^- - \Delta v\_d^- & -v\_q^- - \Delta v\_q^- \\ -v\_q^- - \Delta v\_q^- & v\_d^- + \Delta v\_d^- \\ -v\_q^- - \Delta v\_q^- & v\_d^- + \Delta v\_d^- \\ v\_d^- + \Delta v\_d^- & v\_q^- + \Delta v\_q^- \end{bmatrix} \begin{bmatrix} i\_d^+ \\ i\_q^+ \end{bmatrix} \tag{20}
$$

where Δ*v*<sup>+</sup> *<sup>d</sup>* , <sup>Δ</sup>*v*<sup>+</sup> *<sup>q</sup>* are the positive-sequence *dq* axis components of Δ*va*, Δ*vb* and Δ*vc*; Δ*v*<sup>−</sup> *d* , Δ*v*− *<sup>q</sup>* are the negative sequence *dq* axis components of Δ*va*, Δ*vb* and Δ*vc* after positive and negative-sequence separation and Park transformation.

When the output of the auxiliary module is set to satisfy Equation (21):

$$\begin{array}{l} \Delta v\_d^- = -v\_d^-\\ \Delta v\_q^- = -v\_q^-\\ \Delta v\_d^+ = 0\\ \Delta v\_q^+ = 0 \end{array} \tag{21}$$

a new equation, Equation (22) can be obtained from Equation (20):

$$
\begin{bmatrix} P\_0 \\ Q\_0 \\ P\_{c2} \\ P\_{s2} \\ Q\_{c2} \\ Q\_{s2} \end{bmatrix} = \begin{bmatrix} \upsilon\_d^+ & \upsilon\_q^+ \\ \upsilon\_q^+ & -\upsilon\_d^+ \\ 0 & 0 \\ 0 & 0 \\ 0 & 0 \\ 0 & 0 \end{bmatrix} \begin{bmatrix} i\_d^+ \\ i\_q^+ \\ i\_q^+ \end{bmatrix}. \tag{22}
$$

It can be further simplified as Equation (23):

$$
\begin{bmatrix} v\_d^+ & v\_q^+ \\ v\_q^+ & -v\_d^+ \end{bmatrix} \begin{bmatrix} i\_d^+ \\ i\_q^+ \end{bmatrix} = \begin{bmatrix} P^\* \\ Q^\* \end{bmatrix}. \tag{23}
$$

The coefficient matrix rank of Equation (23) is 2, the rank of the augmented matrix is 2. The number of equations is equal to the number of variables, so that Equation (23) has a unique solution. The corresponding current reference value can be solved as Equation (24):

$$
\begin{bmatrix} \dot{i}\_d^\* \\ \dot{i}\_q^\* \end{bmatrix} = \begin{bmatrix} \dot{i}\_d^+ \\ \dot{i}\_q^+ \end{bmatrix} = \begin{bmatrix} \upsilon\_d^+ & \upsilon\_q^+ \\ \upsilon\_q^+ & -\upsilon\_d^+ \end{bmatrix}^{-1} \begin{bmatrix} P^\* \\ Q^\* \end{bmatrix}. \tag{24}
$$

When it is needed to limit the current, the upper limit of the reference current can be adjusted by changing the value of Δ*v*<sup>+</sup> *<sup>d</sup>* and <sup>Δ</sup>*v*<sup>+</sup> *<sup>q</sup>* in Equation (21).

The overall control structure of the system is shown in Figure 4. After positive and negative sequence separation module, positive-sequence components *v*<sup>+</sup> *<sup>a</sup>* , *<sup>v</sup>*<sup>+</sup> *<sup>b</sup>* and *<sup>v</sup>*<sup>+</sup> *c* , negative-sequence components *v*− *<sup>a</sup>* , *v*<sup>−</sup> *<sup>b</sup>* and *v*<sup>−</sup> *<sup>c</sup>* , and zero-sequence components *v*<sup>0</sup> *<sup>a</sup>*, *v*<sup>0</sup> *<sup>b</sup>* and *v*0 *<sup>c</sup>* are derived from PCC voltages *va*, *vb* and *vc*. Following that, *<sup>v</sup>*<sup>+</sup> *<sup>d</sup>* and *<sup>v</sup>*<sup>+</sup> *<sup>q</sup>* are generated from *v*<sup>+</sup> *<sup>a</sup>* , *<sup>v</sup>*<sup>+</sup> *<sup>b</sup>* , *<sup>v</sup>*<sup>+</sup> *<sup>c</sup>* through *abc*/*dq* transformation. Then, the current reference values *i* ∗ *<sup>d</sup>* and *i* ∗ *<sup>q</sup>* are given from current reference generator module according to Equation (24). After that, the current reference values *i* ∗ *<sup>d</sup>* and *i* ∗ *<sup>q</sup>* generate the PWM waves that control the main circuit through the PI module as well as processing the decoupling components *ω*0*Lf id* and *ω*0*Lf iq*. The negative-sequence voltage components *v*<sup>−</sup> *<sup>a</sup>* , *v*<sup>−</sup> *<sup>b</sup>* , *v*<sup>−</sup> *<sup>c</sup>* and the zero-sequence voltage components *v*<sup>0</sup> *<sup>a</sup>*, *v*<sup>0</sup> *<sup>b</sup>*, *<sup>v</sup>*<sup>0</sup> *<sup>c</sup>* are added and then create reference values Δ*v*<sup>∗</sup> *<sup>a</sup>* , Δ*v*<sup>∗</sup> *<sup>b</sup>* , Δ*v*<sup>∗</sup> *<sup>c</sup>* of the auxiliary module output voltage by multiplying by minus one. The three reference

values Δ*v*∗ *<sup>a</sup>* , Δ*v*<sup>∗</sup> *<sup>b</sup>* and Δ*v*<sup>∗</sup> *<sup>c</sup>* , respectively, generate PWM waves for three auxiliary module circuits through the PR controller.

**Figure 4.** Overall control structure diagram.

The Decoupled Double Synchronous Reference Frame Phase-Locked Loop (DDSRF-PLL), which has better performance under unbalanced voltage, is adopted to achieve phase detection [21]. The structure of DDSRF-PLL is shown in Figure 5. After positive and negative sequence abc/dq transformation, *v*<sup>+</sup> *<sup>d</sup>* , *<sup>v</sup>*<sup>+</sup> *<sup>q</sup>* , *v*<sup>−</sup> *<sup>d</sup>* and *v*<sup>−</sup> *<sup>q</sup>* are derived from the grid voltage *va*, *vb* and *vc*. Then, *v*+<sup>∗</sup> *<sup>d</sup>* , *<sup>v</sup>*+<sup>∗</sup> *<sup>q</sup>* are generated from *<sup>v</sup>*<sup>+</sup> *<sup>d</sup>* , *<sup>v</sup>*<sup>+</sup> *<sup>q</sup>* after a decoupling network. Similar to the phase detection principle of the Synchronous Reference Frame Phase-Locked Loop (SRF-PLL) [21], the phase of the system ˆ *θ* could be obtained by making *v*+<sup>∗</sup> *<sup>q</sup>* approach zero through the PI controller. The detailed structure of decoupling network is expressed as in [21].

**Figure 5.** The structure of DDSRF-PLL.

#### *3.2. Advantages of Modified Topology*

The voltage and current vector trajectories of the traditional topology and the modified topology are shown in Figure 6 [9], respectively. When single-phase voltage fault occurs, the trajectory of voltage vector will be distorted. When the voltage vector trajectory shows a spindle-shaped variation, as the trajectory of *Utra* in Figure 6, in order to keep the output power constant, the trajectory of the current amplitude becomes an ellipse, as the trajectory of *Itra* in Figure 6. Where, *Imax* is the maximum value of the allowable current amplitude of the system. It can be seen that the amplitude of *Itra* has exceeded the value of *Imax* near the long axis of the actual current track, as shown in the shaded area, which may give rise to over-current fault. When the auxiliary modules are inserted into the system, the

unbalanced voltage is corrected to a standard circle, as the trajectory of *Umod* in Figure 6, and the corresponding current amplitude trajectory is also a standard circle, as the trajectory of *Imod* in Figure 6. Since the amplitude of *Umod* can be adjusted by changing the value of Δ*v*<sup>+</sup> *<sup>d</sup>* and <sup>Δ</sup>*v*<sup>+</sup> *<sup>q</sup>* , so that the radius of the trajectory of *Umod* can be ensured not to be too small, then the corresponding trajectory of *Imod* can be guaranteed to be included in the circular trajectory of *Imax*, so as to avoid the risk of overcurrent fault.

**Figure 6.** Change of voltage and current amplitude trajectories of the traditional and the modified topologies.

#### *3.3. Capacity Design of Auxiliary Modules*

Supposing that the fault occurs in phase B, and the voltage amplitude of phase B is *β* times of its original normal value, then the vector format of three-phase voltage is described as Equation (25):

$$\mathbf{V\_{a}} = V \angle \varphi \quad \mathbf{V\_{b}} = \beta V \angle (\varphi - 120^{\circ}) \quad \mathbf{V\_{c}} = V \angle (\varphi + 120^{\circ}) \tag{25}$$

The positive, negative and zero-sequence voltage components of phase A are obtained as Equation (26), [21].

$$
\begin{bmatrix} V\_{a(1)} \\ V\_{a(2)} \\ V\_{a(0)} \end{bmatrix} = \frac{1}{3} \begin{bmatrix} 1 & h & h^2 \\ 1 & h^2 & h \\ 1 & 1 & 1 \end{bmatrix} \begin{bmatrix} V\_a \\ V\_b \\ V\_c \end{bmatrix} = \begin{bmatrix} \frac{2+\beta}{3} V \angle \varphi \\\ \frac{1-\beta}{3} V \angle (\varphi - 60^\circ) \\\ \frac{1-\beta}{3} V \angle (\varphi + 60^\circ) \end{bmatrix} \tag{26}
$$

where

$$h = e^{j120^\circ} = -\frac{1}{2} + j\frac{\sqrt{3}}{2}h^2 = e^{j240^\circ} = -\frac{1}{2} - j\frac{\sqrt{3}}{2}$$

The positive, negative and zero-sequence voltage components of phase B and phase C are obtained as Equations (27) and (28):

$$
\begin{bmatrix} V\_{b(1)} \\ V\_{b(2)} \\ V\_{b(0)} \end{bmatrix} = \begin{bmatrix} \frac{2+\beta}{3} V \angle(\varphi - 120^{\circ}) \\ \frac{1-\beta}{3} V \angle(\varphi + 60^{\circ}) \\ \frac{1-\beta}{3} V \angle(\varphi + 60^{\circ}) \end{bmatrix} \tag{27}
$$

$$
\begin{bmatrix} V\_{c(1)} \\ V\_{c(2)} \\ V\_{c(0)} \end{bmatrix} = \begin{bmatrix} \frac{2+\beta}{3} V \angle(\varphi + 120^{\circ}) \\ \frac{1-\beta}{3} V \angle(\varphi + 180^{\circ}) \\ \frac{1-\beta}{3} V \angle(\varphi + 60^{\circ}) \end{bmatrix} . \tag{28}
$$

In the modified topology, the average powers of the three auxiliary modules are shown in Equation (29):

$$P\_a = \frac{1-\beta}{6} V I \\ P\_b = -\frac{1-\beta}{3} V I \\ P\_c = \frac{1-\beta}{6} V I. \tag{29}$$

When *β* changes between [0, 1], the power curve of the auxiliary module is shown in Figure 7. Auxiliary module of the fault phase-phase B essentially injects power into the circuit. When the output power of the grid-connected inverter is used as the power base value, which is *Pbase* = (3/2)*V I*, the maximum value of the injected power is 0.22 p.u. (*β* = 0). Phases A and C are non-fault phases. Their auxiliary modules absorb power from the circuit, and the maximum absorbed power is 0.11 p.u. (*β* = 0). Therefore, for the single-phase voltage fault, the power capacity of the auxiliary module designed above 0.22 p.u. can meet the requirements no matter what the drop depth is and no matter which phase the fault occurs in.

**Figure 7.** Output power of the auxiliary module.

According to the clearing time of inverters under voltage faults shown in Figure 8, in case of voltage drop, the grid-connected inverter only needs to maintain the connection time of 2 s at most. Therefore, the energy needed to be absorbed or released by the auxiliary module will not be too large, and the operation of the inverter during the LVRT period will not cause damage to the energy storage devices in the auxiliary module.

**Figure 8.** Clearing time of inverters under different voltage faults.

#### *3.4. Stability Analysis of the Modified Topology*

Since the parameters of the three branches of the inverter are identical, according to [7,22], the whole system can be simplified shown in Figure 9.

In Figure 9, *v*<sup>∗</sup> is the output voltage reference of the auxiliary module, *Gadd*(*s*) is the transfer function of the auxiliary module voltage in open mode. *Ladd*, *Cadd* and *Radd* are inductance, capacitor and resistor of the auxiliary module, respectively. *Gcli*,*m*(*s*) denotes the current reference to output transfer function of grid-connected inverter, *Yoi*,*m*(*s*) represents the equivalent output admittance of the system, *i* ∗ *gm*(*s*) and *igm*(*s*) are the reference current and output current of system, respectively, and their detailed form are expressed as [22].

When we adopt the parameters in Tables 3–5, the pole-zero maps of the current closed transfer functions for the traditional topology and the modified topology are shown in Figure 10, respectively. In Figure 10, p1 and p2 are the dominant closed-loop poles of the current transfer function for the traditional topology and the modified topology, respectively. Although p2 is closer to the imaginary axis than p1, they are still very close to each other and far away from the imaginary axis. Therefore, compared with the traditional topology, the output stability of the modified topology is reduced, but all poles of the modified topology system are still in the left half plane and the whole system is still stable.

**Figure 9.** Equivalent structure diagram of the modified topology.

**Figure 10.** Pole-zero maps of current closed transfer functions for the traditional topology and the modified topology.


**Table 3.** Operating parameters of main circuit used in experiments.

**Table 4.** Operating parameters of auxiliary module used in experiments.



**Table 5.** Parameters of auxiliary module used in simulations.

#### **4. Simulation Results**

With the detailed discussion of the modified topology, the MATLAB/Simulink was performed to achieve the verification. In the simulation, the fault type is that the voltage of phase B drops to 0.5 p.u. The parameters of other main circuits are shown in Table 2, and the parameters of the auxiliary modules are shown in Table 5. The results of the traditional topology and the modified topology are shown in Figures 11 and 12, respectively.

Comparing the results in Figures 11 and 12, when the modified topology is adopted, the unbalanced voltage at PCC1 can be corrected, and the inverter output current keeps being balanced. The oscillation value of the output active power is reduced from 0.49 to 0.17 p.u., and the output reactive power oscillation value is reduced from 0.46 to 0.15 p.u. The oscillation value of active power for the modified topology is 33.88% of that of the traditional topology and the reactive power oscillation value is reduced to 32.17% of the value of traditional topology. The simulation results show that the modified topology can correct the unbalanced voltage at the output of the inverter and reduce the oscillation of the output active power and reactive power.

**Figure 11.** Simulation results of the traditional topology, when *Vb* drops to 0.5 p.u. (**a**) Output voltage at PCC1; (**b**) output current; (**c**) output active power and reactive power.

**Figure 12.** Simulation results of the modified topology, when *Vb* drops to 0.5 p.u. (**a**) Output voltage at PCC1; (**b**) output current; (**c**) output active power and reactive power.

#### **5. Experimental Results**

In order to confirm the simulation results, the three-phase converter was verified by downscaling the levels of voltage and power. The overall configuration of the experimental setup is shown in Figure 13. The core control algorithm is implemented on TMS320F28335, while the intelligent power module (IPM) is PM150RLA120. IT6516C DC source is used to generate DC voltage and Chroma 61702 AC source is implemented to generate AC voltage to simulate grid voltage. The auxiliary module consists of three identical single-phase inverters, all of which adopt the filter composed of *Ladd*, *Radd* and *Cadd*. *Lf* is the filter inductance of grid-connected inverter output circuit. In the experiment, the fault type is that the voltage of phase B drops to 0.5 p.u. The parameters of other main circuits are shown in Table 3, and the parameters of auxiliary modules are shown in Table 4. The experimental results of the traditional topology and the modified topology are shown in Figures 14 and 15, respectively.

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**Figure 13.** Configuration of the experimental setup.

**Figure 14.** Experimental results of the traditional topology, when *Vb* drops to 0.5 p.u. (**a**) Output voltage at PCC1; (**b**) output current; (**c**) output active power and reactive power.

**Figure 15.** Experimental results of the modified topology, when *Vb* drops to 0.5 p.u. (**a**) Output voltage at PCC1; (**b**) output current; (**c**) output active power and reactive power.

Comparing the results of the traditional topology and the modified topology in Figures 14 and 15, the unbalanced voltage at PCC1 can be corrected under the modified topology, and the inverter output current keeps balanced. The oscillation value of the output active power is reduced from 43.35 to 13 W, and the output reactive power oscillation value is reduced from 55.06 to 15.08 var. The oscillation value of active power in the modified topology is 29.99% of that in traditional topology and the reactive power oscillation value is reduced to 27.39% of the value of the traditional topology. The experimental results show that the modified topology can correct the unbalanced voltage at the output of the inverter and reduce the oscillation of the output active power and reactive power.

#### **6. Conclusions**

The grid-connected inverter with modified topology could compensate the negativesequence and the zero-sequence components of the output voltage, so that the reference current equation of the inverter meets the solvability condition, thus eliminating the output power oscillation while the output current waveform still meets the requirements of grid codes. The simulation and experimental results show that the modified topology can effectively correct the unbalanced voltage and reduce the output active power oscillation and reactive power oscillation.

When the grid voltage is balanced, grid voltage does not contain negative-sequence components and zero-sequence components. Therefore, the output voltage reference value of the auxiliary module is zero at this time, and the auxiliary module will not output voltage, nor will it absorb power from the circuit or inject power to circuit. The auxiliary module is always connected to the circuit regardless of the unbalanced grid voltage fault or normal grid voltage, but when the grid voltage is balanced, the auxiliary module will not play a role.

The auxiliary voltage source can be a DC voltage source, a large capacitor, a super capacitor, or other energy storage units. This article aims to illustrate the function of the auxiliary module, so in the experiment, only the DC voltage source is used. In the future, the methods of using large capacitors or other energy storage structures to replace the additional DC power source in the auxiliary module and also designing the effective charging and discharging topologies of auxiliary modules as well as reducing the cost of hardware will be explored.

**Author Contributions:** Conceptualization, C.L., X.M. and L.Y.; methodology, C.L., X.M. and L.Y.; software, C.L. and Y.L.; validation, C.L., X.Y. and J.R.; data curation, Y.Z.; writing—original draft preparation, C.L. and X.M.; supervision, X.M.; project administration, X.M. All authors have read and agreed to the published version of the manuscript.

**Funding:** This work was supported by China Scholarship Council under Grant 202006280458.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** Not applicable.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


### *Article* **An Investigation into Conversion of a Fleet of Plug-in-Electric Golf Carts into Solar Powered Vehicles Using Fuzzy Logic Control**

**Wafaa Saleh 1,2,\*,†, Shekaina Justin 1, Ghada Alsawah 1,3, Areej Malibari <sup>4</sup> and Maha M A Lashin 1,5**


**Abstract:** This paper presents an investigation factors that need to be considered in the design and selection of components for the conversion of a fleet of plug-in electric golf carts at Princess Nourah Bint Abdelrahman University, (PNU), Riyadh, Kingdom of Saudi Arabia (KSA), into solar power energy. Currently, the plug-in electric golf carts are powered by a set of deep-cycle lead-acid battery packs consisting of six units. Solar energy systems (photovoltaics and solar thermal) provide significant environmental benefits and opportunities over the traditional and conventional sources. Therefore, they can contribute positively to many aspects of the built environment and societies. There are many factors that affect the energy generated from the solar panel system. These include type and dimension of the solar panels, weight, speed, acceleration, and other characteristics of the used golf carts, and the energy efficiency of the solar energy system, as main factors that affect the green energy generated to operate the carts. The energy values needed to power the electric cart were calculated and optimized using traction energy calculation and optimized using a fuzzy logic analysis. The fuzzy logic system was developed to assess the impacts of varying dimensions of solar panel, vehicle speed, and weight on the energy generation. Initial calculations show that the replacement cost of the batteries can be up to approximately 75 percent of the operating cost. Together with the indirect cost benefits of achieving zero tail-pipe emission and the comfort of silent operation, the cost of operation using solar energy can be significant when compared with the cost of battery replacement. In order to achieve better efficiency, supercapacitors can be investigated to replace the conventional batteries. The use of fuzzy logic successfully facilitated the optimization of system operation conditions for best performance. In this study, fuzzy logic and calculated data were used as an optimization tool. Future work may be able to use fuzzy logic with experimental data to demonstrate feasibility of utilizing fuzzy logic systems to assess energy generation processes. Future investigations could also include investigation of other factors and methodologies, such as various types of batteries, supercapacitors, solar panels, and types of golf carts, together with different techniques of artificial intelligence to assess the optimum system specifications.

**Keywords:** golf carts; electric carts; solar energy; conversion of electric carts

#### **1. Introduction and Literature Review**

Electric vehicles have been recognized as a key technology in the mobility sector that are associated with reducing emissions, greenhouse gases, and fuel consumption. Therefore, electric carts are good candidates to demonstrate and begin the journey for achieving a much more sustainable mobility future. Small electric vehicles seem to be excellent options to achieve adaptation to solar energy initiatives in the transportation

**Citation:** Saleh, W.; Justin, S.; Alsawah, G.; Malibari, A.; Lashin, M.M.A. An Investigation into Conversion of a Fleet of Plug-in-Electric Golf Carts into Solar Powered Vehicles Using Fuzzy Logic Control. *Energies* **2021**, *14*, 5536. https://doi.org/10.3390/en14175536

Academic Editors: K.T. Chau and Tek Tjing Lie

Received: 15 June 2021 Accepted: 25 August 2021 Published: 4 September 2021

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**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

<sup>1</sup> College of Engineering, Princess Nourah Bint Abdulrahman University, Riyadh 84428, Saudi Arabia; SJThambi@pnu.edu.sa (S.J.); gaalsawah@pnu.edu.sa (G.A.); mmlashin@pnu.edu.sa (M.M.A.L.)

sector [1,2]. In order for this technology to achieve its target, it has to be powered by a source of renewable energy such as solar, wind, or natural gas. Solar energy technologies are fundamental components of a sustainable energy future since they provide clean, renewable, and a home energy source. In comparison to traditional energy sources, solar energy systems have significant environmental benefits. The development and operation of solar systems have considerable environmental consequences that have been demonstrated in literature [3].

Electromobility can contribute to more ecologically responsible, climate-friendly mobility. However, in terms of electric vehicles, it has not yet reached its full potential. There are two significant impediments to purchasing an electric automobile from the user's perspective: it is more expensive than a car with an internal combustion engine and it has a shorter range than a normal vehicle. Intermodal concepts based on electric shared vehicles can be a potential option because the total cost of ownership of the electric vehicles may be split among many users, and as part of the public transportation system, it can also serve as a supplement for local and long-distance travel [4].

The golf automobiles, in contrast, are created to be durable, dependable, and safe when used for long periods of time. There are many forms available for such cars (see the PNU golf cart picture, Figure 1). Solar panels, batteries, and electronics that can be used to power these types of golf carts have recently become more affordable, functional, and reliable, allowing for new and inventive uses. Various forms of solar-panel-powered electric carts have been seen in various studies. The solar powered golf cart can be used in many purposes including short distance travel where there is solar incidence, within campuses travel, and outside superstores to transport customers with mobility issues, elderly, and children [5].

**Figure 1.** Princess Nourah Bint Abdelrahman University's golf cart.

In comparison to traditional energy sources, solar energy systems (photovoltaics and solar thermal) also provide significant environmental benefits, contributing to the long-term development of human evolution and well-being [6]. Solar energy is an abundant energy resource and the fastest growing renewable energy source in the world. In photovoltaic (PV) technology, many categories of solar panels have been produced and currently are used. Further development of similar products is also progressing in addition to the optimization techniques that contribute to cost reduction and energy efficiency [7].

The solar cell's efficiency is stated as the ratio of the calculated energy generation, the besieged direct current (DC) yield, and the actual alternating current (AC) yield generated [8]. This efficiency is often affected by factors such as dirt, sand, and snow together with other obstacles such as shade, etc. Electrical efficiency of the PV module (in this case, the higher the temperature of the panel, the lower the performance of the modules), also affects the system's overall efficiency [9].

In recent years, the market for solar energy has greatly expanded and further expansion is expected. This is due to the global interest in more renewable sources and because of the overall goal of achieving more sustainable societies.

The case of light electrical vehicles has been broadly studied by Keshri, Bertoluzzo, and Buja [10]. De Pinto et al. [11] investigated the allowance of the range of the EV via PV panels [11]. Kim et al. [12] investigated issues related to battery savings of the electrical vehicles while utilizing the vehicle's surface areas in order to optimize charging time [12], which is a new area of research [13]. The autonomy of the car showed an increase in both studies. Okedu [14] investigated the use of solar panels in hydrogen cars [14]. Other studies have focused on the PV integration and their applications [15]. Direct applications in buildings [16], PV parks [17] or on renewable-energy-based EV charging stations, specifically wind-based [18] and solar-based [19]. The available research is very scarce in innovative methods of solar integration, such as powering buggies, golf cars, and other options that can be used for sports or local transporting functions. This paper's objective is to explore whether or not such an investment in the PNU University's Golf carts would show potential saving in energy and provision of renewable energy.

Solar golf carts are mostly powered by a photovoltaic (PV) or thin film panel mounted on top of the existing roof, or using a PV panel as the roof itself (see Figure 1). A controller converts the sun's energy to charge the golf cart's supercapacitor bank. In terms of solar energy supply, the solar panels may well increase the distance the cart can travel on a single charge and hence can provide potential increased usage of these golf carts. In this paper, a case study is presented where we investigate the potential benefits of powering a university's fleet of battery-powered golf carts into solar energy power. The aim of the paper also is to briefly investigate the operation cost and its implications of adopting green energy to operate golf carts at Princess Nourah Bint Abdulrahman University (PNU) campus in Riyadh, Kingdom of Saudi Arabia, for transportation within the university, instead of using electric batteries. The paper is structured as follows: Section 1 provides an introduction and literature review of the study. The case study is presented in Section 2. System specification is overviewed in Section 3 with a discussion of the general specifications of the proposed main system and the operating characteristics. The methodology is presented in Section 4 where the calculations of energy needed to power the electric cart are presented. The fuzzy logic control system, which is used to assess optimum energy generation relative to the system specifications, is discussed in Section 5. Section 6 concludes the findings of the study and discusses future work.

#### **2. Case Study**

Princess Nourah Bint Abdelrahman University (PNU) in Riyadh, KSA, is the first all-female university in Riyadh that was established in 2006 with the aim of serving the development and progress of the Kingdom. Riyadh is 587 m above sea level. Riyadh has a desert climate. During the year, there is virtually no rainfall. According to Köppen and Geiger, this climate is classified as BWh. The average annual temperature is 26.2 ◦C|79.2 ◦F in Riyadh. Precipitation averages about 66 mm|2.6 inch per year. The driest month is June, with 0 mm|0.0 inch of rainfall. Most of the precipitation here falls in April, averaging 14 mm|0.6 inch. The university's mission is distinguished by its leadership in education and scientific research. It contributes to establishing a knowledge-based economy with societal and global partnerships. The campus is 13 million square meters in size, with a maximum capacity of 60,000 students. The campus has 600 high-tech smart buildings, large-capacity student residencies, various models of faculty residence units, and three spacious, state-of-the-art recreation centers. In addition, it has preschools, primary schools, intermediate, and secondary schools. It also has an elegant central library, research centers, a university hospital, student support centers, student-accessible sport facilities, a convention center, and an automated metro system. Due to the large size of the campus, efficient means of transporting systems are in operation. These include an

11.5 km automated guideway metro system together with a fleet of 150 golf cars—100 plug-in-electric and 50 petrol engined that are used as a multipurpose utility vehicles.

The plug-in-electrics typically include 6–8 batteries of 8–6 volts/each. The recharging is usually carried out overnight at different centers located inside the university campus. Each car is charged every 2 to 3 days depending on the usage and the condition of its batteries. Batteries are replaced every 2 to 3 years. Therefore, the operating efficiency of the golf cars is rather limited in addition to the high cost associated with the operation of these cars. There are also operating cost implications regarding the golf cars used. In terms of the cost involved in operating the batteries, this is relatively high, as each unit costs about 850 to 900 SAR (226.7 to 240 USD) costing an average of around 4534–4800 USD on an annualized basis for the fleet. Assuming that each cart is operated on an average of about 2000 km annually, the cost of the battery works out to be about 0.12 USD per km of operation. Even after considering the indirect cost benefits accrued on account of the zero tail-pipe emission and the comfort of silent operation, the cost of operation is quite undesirable. Moreover, the cost of operating and maintaining the charging centers are also involved, though they are not as high when compared with the cost of battery replacement.

#### **3. System Specifications**

The annual solar incidence at PNU location is about 2350 kWh, translating into a daily mean solar incidence of 6.44 kWh [20]. There are only a few days in the year when the solar incidence is low due to cloud cover or when the angle of incidence is relatively positive for energy generation.

The PNU golf cart roof has a dimension of 2 m × 1 m. The cart roof is the location where harvesting of solar energy is undertaken. When the surface area is increased, the generated energy is increased. Table 1 shows the estimated energy generated by different dimensions and conversion efficiency ranges as found in the market, which have been based on published findings [20–23].

**Table 1.** The energy generated by different dimensions and conversion efficiency ranges as found in the market.


For example, with a 2.0 m × 1.0 m area of the roof covered with solar panel, the energy generated by a panel with 24% efficiency should work out to be 2.7 kWh per day on an average, which is more than sufficient to meet the daily usage for the golf cart, as illustrated later.

When the area of the roof is increased, thereby increasing the panel area, and when the conversion efficiency of the solar panel used is high, the supercapacitor capacity can be decreased. This will help in reducing the cost and mass of the supercapacitor module. The increase in mass of solar panel is relatively low when compared with increase in mass of the supercapacitor on account of higher capacity.

We need to compare this energy with the energy produced from the battery pack fitted in the golf cart, which consists of either 6 units of 8 V-170 Ah or 8 units of 6 V-170 Ah deep-cycle lead-acid batteries connected in series totaling an energy capacity of 8.16 kWh. The net energy available to be discharged from the battery pack is about 4 kWh. Based on the available data, as 4 kWh energy is utilized over a period of 2 to 3 days, the mean daily distance covered is in the range of about 10 to 15 km. These data indicate the optimum capacity needed for the supercapacitor bank.

As the charging would be done with solar PV panel installed on the roof of the cart, and as the supercapacitor could be fully discharged, a supercapacitor bank with a capacity of 1.5 to 2 kWh is considered optimal to meet the current usage. In any unlikely event of a mismatch between solar incidence and demand for transport, for example, recharging 1 kWh using a 100 kWh charger would take no more than 50 s.

The parameters that can be considered for selecting the solar panels are mean efficiency, efficiency variance with respect to temperature, type of the solar panels and their connections to withstand stress and vibrations, mass per unit area of the panel, cost of the panel per unit area for panels fabricated as per specified dimensions, cost per unit area of readily available panels, and flexibility of the panel [20–23]. Panels designed exclusively for transport applications or panels fabricated with similar design should be considered. The solar panels suitable for this application are thin-film rolled panels, perovskite single junction and multijunction panels, thick-film panels and semiflexible silicon panels [24,25]. It should be noted, however, that the commercial availability of some of these panels may not be fully guaranteed. Since there are many factors involved, the investigation in this paper focuses on the solar panel types (or dimension, in this case), speed of the golf cars, and energy efficiency as main factors that affect the green energy generated to operate the carts. The energy values needed to power the electric cart was calculated and assessed using traction energy calculation and optimized using fuzzy logic analysis. The fuzzy logic system was developed to assess the impacts of varying dimensions of solar panel, speed of vehicle, and weight on the energy generation.

#### **4. Methodology Traction Energy Calculation**

Vehicle acceleration, maximum velocity, and range are the main parameters that affect traction energy calculations. In order to consider these forces, it is therefore required to include the force due to rolling resistance, the aerodynamic force, the acceleration force, and the rotational acceleration force [26]. The impact of driver behavior is represented in the acceleration force while the impact of the passengers should be included in the total weight of the vehicle. For this analysis and for simplification, the energy required for operating the golf cart is assumed to be the sum of two components only, as given below:


Assuming that the mean speed of the golf cart is 25 km/h, mass is 500 kg, air density 1.2 kg/m3, and the energy conversion efficiency of the cart *η* = 0.75, the electricity consumption is calculated as follows (Equation (1)):

$$E\_{25} = \frac{v \left(c \cdot m \cdot g + 0.5 c\_d \cdot p \cdot A \cdot v^2\right)}{\eta} \tag{1}$$

where *c* = 0.06 (rolling resistance coefficient)

*m* = 500 kg (mass of the cart) *g* = 9.81 m s−<sup>2</sup> (gravitational acceleration) *cd* = 0.7 (aerodynamic drag coefficient) *p* = 1.2 kg m−<sup>3</sup> (density of air) *v* = 6.94 m s−<sup>1</sup> (velocity of cart) *η* = 0.75 (energy conversion efficient of the cart) *A* = 1.5 m<sup>2</sup> (frontal area) *E*<sup>25</sup> = 3238.67 Wh

This is equal to 3.238 kWh. On the other hand, the energy generation obtained in Section 3 above is 2.7 kWh. Given that the speed of the golf cart is much lower than 6.94 ms<sup>−</sup>1, the energy generated should be sufficient to run the cart. For comparison, Table 2 shows the level of energy need, energy consumption, and energy generation from solar panels. From the table, it appears that while the theoretical value for energy requirement per day is 3.238 kWh, the actual value needed to run the cart is slightly lower; a value of 2.66 kWh seems sufficient.


**Table 2.** Summary of golf cart energy requirement and energy generation from batteries and solar panels.

Other than that, the factors that can be investigated in this case that impact electricity consumption are vehicle speed, solar panel dimensions, and energy efficiency factors. In the section below, a fuzzy logic control system is developed to investigate impacts of various values of these factors on the energy production. Fuzzy logic controllers (FLCs) have the following advantages over the conventional controllers: they are easily developed and processed using very simple software, they can cover a broader range of operating conditions, and they are more readily adaptable in natural language terms. It should be noted, however, that it is possible to use other conventional methods.

#### **5. Fuzzy Logic Control System**

In managing complicated situations, fuzzy logic systems are effective prediction tools. These models or groups are mathematical representations of the ambiguity and hazy information. They are capable of distinguishing, expressing, explaining, and operating this ambiguous and imprecise information. They can be programmed to calculate a difference between data sets by emulating human thinking processes [27]. Because there is no "standard" mathematical model available or one that can be derived from physical laws for effectively modeling pedestrians' crossing behavior, fuzzy logic is clearly effective in this type of inquiry. Furthermore, because fuzzy systems were first offered to represent human decision-making by weighing rules, it appears sensible to utilize them to simulate human behavior. Fuzzy logic has a wide range of applications, including transportation (for example, [28–31]). In comparison to other industries, however, transportation has a considerable dearth of fuzzy logic system applications. The membership functions are an important aspect of fuzzy logic analysis. The membership functions can take a variety of shapes including triangular, trapezoidal, and Gaussian [32,33] for assessing the efficiency of estimation of various forms. Because of their simplicity and ease of computation, the triangular and trapezoidal membership functions are frequently used in various applications. As a result, adopting a triangle form as a first step in any research is reasonable. Other forms can be utilized if the system's performance is not adequate.

A nonlinear translation of input data sets to scalar output data is a fuzzy logic system [27]. As shown in Figure 2, the fundamental mechanisms of a fuzzy system are a fuzzifier and a defuzzifier, if–then rules, and an inference engine. The use of a fuzzy logic system has the advantage of being able to manage challenges involving imprecise and partial data. They can also simulate arbitrary or sophisticated nonlinear functions.

#### *5.1. Fuzzy Logic Analysis*

The values of electricity required for driving golf cars used as transportation inside PNU are affected by cart speed and solar panel area. The mathematical equation for calculating the electricity needed to power the golf carts and to confirm a fuzzy logic control system was designed and implemented for the car working variables (cart speed and roof area), which enabled a prediction of the electrical power required for driving the car.

The fuzzy logic system was developed using the traction energy calculations presented earlier in the paper. The membership function of fuzzy logic is a fundamental component of a fuzzy logic system and the most crucial stage in fuzzy set construction. The membership function controls the fuzziness feature of a fuzzy set. The only requirement for a membership function is that it must fluctuate between 0 and 1. Because of their simplicity

and ease of calculation, triangle and trapezoidal membership functions are frequently used in various applications, as opposed to other function types such as bell, sigmoidal, asymmetric, LR, and Gaussian, which may need more sophisticated mathematical procedures. In addition, defining a triangular and trapezoidal membership function requires fewer data. In our instance, it might be most appropriate to utilize a triangle shape.

**Figure 2.** Architecture of the fuzzy system.

Table 3 lists the names and input and output variables that correspond to the parameter ranges with the triangular membership functions. Three parameters were included to define the input variables for building and implementing fuzzy logic systems (low, medium, and high).

**Table 3.** Levels and name of inputs (triangular membership function) used and output variables and range values.


*5.2. Detection of Electrical Power Using the Fuzzy System*

The fuzzy system procedure that is used in this study follows Mendel's (1995) methodology, which consists of three steps:


The first step is to fuzzify the data, which can be done by using fuzzy linguistic variables and membership functions to convert the input data to a fuzzy set. The inference procedure is then carried out using if–then rules. Finally, the defuzzification stage is accomplished, and fuzzy outputs are crisped using membership functions (Figure 3). Each of these steps is further illustrated below.

**Figure 3.** Fuzzy logic system for electric power from solar panel.

#### *5.3. Fuzzification Process*

The fuzzy logic system's first stage is the fuzzification process. Fuzzy linguistic variables and membership functions are used to turn the input data into a fuzzy set at this stage. Three to seven language variables are commonly used to muddle the input and output components. It would be inefficient to use less than three values since it would be difficult to discriminate the output after fuzzy inference [29–34]. The number of fuzzy rules employed would become more complicated if there were more than seven.

The membership function in the fuzzification process is built in this case utilizing three parameters a, b, c for each input and output variable, representing low, medium, and high values of each of the inputs, with variable ranges shown in Table 3. The estimating toolkit that comes with MATLAB was used. The z coordinates of the three vertices in a fuzzy set L are represented by the triangle membership function, which is determined by the three parameters a, b, and c. (a and c are the lower and upper boundaries, where membership degree is 0; b is the center, where membership degree is 1).

$$\mu\_A(z) = \begin{cases} \begin{array}{c} 0 \quad \text{if } z \le a \\ \frac{z-a}{b-a} \text{ if } a \le z \le b \\ \frac{c-z}{c-b} \text{ if } b \le z \le c \\\ 0 \text{ if } z \ge c \end{array} \tag{2}$$

The real-time data can then be matched with the fuzzy model established, and a mathematical explanation for selecting a determined value for a rule, such as sum-ofsquared-error minimization or any other applicable rule, can be provided using this toolkit. For operating a golf automobile, a fuzzy system is employed to determine the values of electrical power obtained from a solar panel. Low, medium, or high membership functions are available for all variables. This was done for all input and output variables in the same way (Table 3). The values and structure of inputs, outputs, and critical gap values for the three adopted ranges are shown in Table 1 and Figure 4.

**Figure 4.** Fuzzification process of electric power from the solar panel fuzzy logic system.

Figure 5a–d depicts the fuzzy logic system's three levels of inputs and outputs, along with the membership function ranges for the inputs and outputs, respectively. The membership functions used are of the triangular type, as seen in the fuzzy system's inputs and outputs. As previously stated, triangle membership functions are one of several options for determining the best values for the introduced criteria. While the simplicity of this division is apparent, it does not exclude the construction of additional partitions that are

optimal in terms of the specified requirements for the input and output interface while also performing better in terms of processing block optimization.

**Figure 5.** Low, medium, and high values for inputs (**a**–**c**) and output (**d**).

#### *5.4. Inference Process Based on If–Then Rules*

Inference operations are carried out utilizing linguistic if–then rules to determine the relationships between the input and output variables, which are based on a wide range of if–then rules. The linguistic fuzzy logic control system that is a part of the suggested fuzzy control or fuzzy decision step, generates the if–then rules. Table 4 lists some of the if–then rules that were employed in this inquiry. To cover all possible outcomes, fifteen if–then rules were employed in this research.

**Table 4.** A few examples of if–then rules that were used as part of the proposed fuzzy decision.


#### *5.5. Defuzzification Step*

The process of defuzzification is the final step in the optimization process using a fuzzy control system. The defuzzification procedure is based on each person's membership function and the computation of their decisions. If the performance does not meet the assessment criteria, some fuzzy rules will need to be adjusted and the test performed again. Using the same inputs (Table 3), a graphical illustration of the defuzzification process is shown in Figures 4 and 6 and Table 5, which illustrate the outcomes of the fuzzy system.

**Figure 6.** Results of electric power from the solar panel fuzzy logic system.


**Table 5.** Levels and name of outputs obtained from the fuzzy logic system and input values.

The results from fuzzy analysis (Figure 5 and Table 6) show that the minimum PV electrical energy production is achieved at lower values of cart speed and energy conversion efficiency factors. The maximum PV electricity energy production obtained is 4.17 kWh and this was acquired with maximum input parameter values.


**Table 6.** Output results from the proposed fuzzy system.

#### **6. Conclusions**

The aim of this paper is to investigate an optimum energy generation methodology that can be implemented using a renewable energy source. The energy generation is needed to power a set of golf cars at PNU campus in Riyadh, KSA. It is proposed therefore, to adopt a green energy system rather than using electricity from the grid to charge the batteries that are used to power the golf carts. As Riyadh, KSA, consistently receives very good solar radiation, calculations were carried out to assess the energy requirement to power these vehicles and to determine if the area of the roof is sufficient to meet mean daily energy requirements.

Based on the mean utilization derived from the charging interval, initial investigations show that the replacement cost of the battery is about 75 percent of the operating cost.

Then, based on the theoretical energy production for traction and the charging interval, the mean distance covered daily was calculated. Assuming that each cart is making an average of about 2000 km annually, the cost of the battery is assumed to be 0.12 United States Dollar (USD) per km of operation.

If the proposed adoption of green energy is implemented, the annual expenditure incurred in the replacement of batteries would be totally considered as initial and running cost savings. In addition, the energy consumed in charging the batteries is saved, which results in green-energy environmental benefits leading to sustainability of resources and lower emissions resulting from less conventional electricity production. In addition, there will be savings on consumables such as acid and distilled water. Moreover, there will be savings in labor spent on recharging, maintaining, and replacing vehicles. Using fuzzy logic facilitated the optimization of system operation conditions for best performance, taking into account three variables: cart velocity, solar panel dimensions, and energy conversion efficiency. Other variables are also possible. Future investigations could include investigating various types of batteries, capacitors, solar panels, and types of golf carts, together with using different techniques of analytical and artificial intelligence to assess the optimum system specifications. In this case, fuzzy logic facilitated the optimization of

system operation conditions for best performance based on the three variables identified. These could be changed, and the optimization conditions could also be altered to include different conditions.

It is further suggested that research should examine the reduction of selected pollutant emissions, lower traditional fuel consumption, and extent of decreased operating cost when PV panels are used to power golf carts. Further research into alternative fuels and appropriateness for their use in this case is also recommended.

**Author Contributions:** Conceptualization, W.S. and S.J.; methodology, all; software, M.M.A.L. and A.M.; validation, W.S., S.J. and G.A.; formal analysis, S.J. and M.M.A.L.; investigation, W.S. and G.A. resources, A.M. and W.S.; data curation, M.M.A.L. and S.J. writing—original draft preparation, W.S. and S.J.; writing—review and editing, all; visualization, all; supervision, W.S.; project administration, W.S.; funding acquisition College of Engineering, PNU. All authors have read and agreed to the published version of the manuscript.

**Funding:** The APC was funded by DSR and PNU.

**Institutional Review Board Statement:** Not applicable.

**Acknowledgments:** This research project was funded by the Deanship of Scientific Research, Princess Nourah bint Abdulrahman University, through the Program of Research Project Funding after Publication, grant No (41-PRFA-P-39).

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


### *Article* **Evaluation of Electrical Performance and Life Estimation of PPs for HVDC Power Cable**

**Seung-Won Lee 1, Hae-Jong Kim 1, Ik-Su Kwon <sup>1</sup> and Jang-Seob Lim 2,\***

<sup>1</sup> Superconductivity Research Center, Korea Electrotechnology Research Institute, Seongju-dong,


**\*** Correspondence: Janylim@mmu.ac.kr; Tel.: +82-055-280-2535

**Abstract:** Demand and need for the application of high voltage direct current (HVDC) are increasing because of high capacity and long-distance transmission. Research on polypropylene (PP) that can increase the operation temperature compared to existing insulation is constantly being considered. This study aimed to evaluate the electrical performance and estimate the life of HVDC application of PP. In this study, a DC V-t characteristic tests were conducted on three types of PP sheets at a temperature of 110 ◦C. In addition, a life estimation formula based on the electrical stress was derived and the electrical performances were evaluated. The experimental results show that the life exponent of material mixed with block copolymer, homo polymer and high density polyethylene (HDPE) was 23 and the electrical performance was 17% better than block copolymer, thereby demonstrating the reliability and electrical performance for application of HVDC.

**Keywords:** HVDC; polypropylene; life exponent; V-t characteristic test; long term reliability; life estimation

#### **1. Introduction**

Demand for high voltage direct current (HVDC) is increasing due to higher voltage of power cables and long-distance transmission. Classically, the insulations for HVDC uses mass oil, which has recently been converted to polymers due to environmental, production, and transmission capacity issues [1–3]. Among them, polypropylene (PP) has an operating temperature of 110 ◦C, has a higher transmission capacity than existing mass impregnated (MI), oil filled (OF) and cross linked polyethylene (XLPE), and can be recycled. Currently in terms of cable insulation, PP has a lot of interest [4,5].

In general, the design life of HVDC MI, OF and XLPE power cables is 30 to 40 years. Since HVDC cables are operated underground or on the seabed for a long period of time, the evaluation of life and long-term reliability is considered as an important factor for the development of DC insulating materials [6,7].

This study aimed to evaluate the electrical performance and long-term reliability of PPs for HVDC application.

Several researchers are using the conductivity, space charge, dielectric strength, V-t characteristic test, partial discharge (PD) and dissipation factor to evaluate reliability of materials [8–15]. Among them, the V-t characteristic test is believed to be major factor contributing toward the evaluation of long term reliability using life exponent [13,15,16]. Other researchers used the life exponent that is a simple numerical value to assess the reliability of XLPE, epoxy, polypropylene laminated paper (PPLP) and low density polyethylene (LDPE) materials. The life exponent of materials ranged from 15 to 30 based on additive type and AC and DC application [13–19]. However, as the design life of power cables was not considered when evaluating the long-term reliability, it is impossible to determine the performance of materials during actual operation. Above all, the reliability evaluation and life estimation of PPs for HVDC application has not been considered yet.

**Citation:** Lee, S.-W.; Kim, H.-J.; Kwon, I.-S.; Lim, J.-S. Evaluation of Electrical Performance and Life Estimation of PPs for HVDC Power Cable. *Energies* **2021**, *14*, 5673. https://doi.org/10.3390/en14185673

Academic Editors: Mario Marchesoni, Ching-Ming Lai and Yitao Liu

Received: 6 August 2021 Accepted: 8 September 2021 Published: 9 September 2021

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

In general, the breakdown voltage of an insulating material depends on the temperature and the pressure applied to the test sample [20,21]. However, during the V-t characteristic test, the temperature of the test object could not be known in real time because the dummy sample was not installed, and there was no description of a method that could equalize the measuring force of the samples.

Unlike previous studies, we calculated the life exponent of PPs that can increase the transmission capacity and demonstrated the HVDC applicability by comparing life exponent of other materials. Furthermore, the electrical performance of PPs with a design life of 40 years for power cables was evaluated and priorities were established. In addition, the failure data was analyzed using the Weibull distribution, the value of 63.2% of the Weibull distribution function of the data of time to breakdown was applied to derive the lifetime estimation according to the electrical stress. Temperature sensors were installed in the dummy sample to improve the reliability of the V-t characteristic test of the PPs, the electrodes and micrometer were combined so that the uniform measuring force was applied to the sheets.

As for the test contents, a short-term ascent test and a V-t characteristic test were conducted at 110 ◦C on three types of PP sheets in which block copolymer, homo polymer and high density polyethylene (HDPE) were mixed.

This paper contributes to long-term reliability and life evaluation during research and development of HVDC insulating materials, and the calculated life exponent should be used as a reference for calculating the deterioration coefficient with the type and prequalification (PQ) test of PP cables for application of HVDC [22].

The remainder of this paper is organized as follows. Section 2 presents the discussion of the theory for calculating the life exponent and life estimation formula and Weibull distribution. In addition, we propose a circuit for V-t test. In Section 3, we demonstrate how to conduct the V-t characteristic test at 110 ◦C and Section 4 presents the evaluation of electrical performance.

#### **2. Theory**

#### *2.1. Inverse Power Law*

Insulating materials for power cables are exposed to various stresses. As the operating time of the cable increases, aging progresses and the insulation performance degrade. V-t test is an experimental method based on electrical stress of aging factors. As a result, the life exponent n and the formula of life estimation due to electrical stress can be calculated, and it is mainly used in the long-term reliability evaluation method. The equation of V-t is as follows [23,24].

$$\mathbf{V}^{\mathbf{n}} \times \mathbf{t} = \mathbf{k} \tag{1}$$

The life equation using Equation (1) is as follows.

$$\mathbf{L}(\mathbf{V}) = \mathbf{k} \mathbf{V}^{-\mathbf{n}} \tag{2}$$

where L is the time-to-breakdown in hours, usually it is the Weibull probability of 63.2%, V is the applied voltage to materials, and n, k, are constants to be determined for the specific tested material or device. The inverse power law is considered valid, if the data being plotted on log-log graph fits a straight line [25].

In Equation (2), n is called the life exponent and is used to evaluate the long-term reliability of insulating materials and calculate the aging factor [22]. The output formula of the n is as follows. Figure 1 shows the V-t characteristic curve.

$$\mathbf{V\_1^n \times t\_1 = |V\_2^n \times t\_2|} \tag{3}$$

$$\mathbf{m}^\* = \frac{\log\left(\frac{\mathbf{t}\_2}{\mathbf{t}\_1}\right)}{\log\left(\frac{\mathbf{V}\_1}{\mathbf{V}\_2}\right)}\tag{4}$$

**Figure 1.** The V-t characteristic curve.

#### *2.2. Weibull Distribution*

Statistical methods such as normal distribution, exponential distribution, logarithmic distribution and Weibull distribution are used to analyze and evaluate the failure data of materials. Among them, the Weibull distribution function is widely used for the reliability analysis of products associated with failures because it is possible to determine the failure modes in the early, constant, and wear out failures by using the scale parameter and shape parameter [26,27]. The following is the formula for the two-parameter Weibull distribution function [28].

$$\mathbf{F(t)} = 1 - \exp\left[-\left(\frac{\mathbf{t}}{\alpha}\right)^{\beta}\right] \tag{5}$$

In the equation, t represents the breakdown time, F (t) is the probability of failure, alpha is a scale parameter greater than 0, and means the 63.2% value of the failure probability. In the case of beta, it is a shape parameter, which means the type of data.

#### **3. Experimental**

#### *3.1. Test Sample*

In general, PPs are divided into two types, homo polymer and copolymer, depending on the use of co-monomer. Homo polymer refers to polypropylene obtained by polymerizing only propylene monomer without using co-monomer. Further, as a general copolymer, there is a block copolymer polymerized by adding ethylene to propylene. Homo polymer has the advantages of heat resistance, mechanical properties, chemical resistance, and recycling, but is vulnerable to impact resistance at low temperatures. In the case of block copolymer, the impact resistance was improved.

The materials were blended with different proportions of block copolymer, homo polymer and HDPE. Table 1 shows three types of the test samples. The block polymer was selected because it best suits the properties required for the cable, and when the homo polymer and block polymer are mixed in half, it was selected to confirm the recyclability of the homo polymer. Furthermore, the quantity of ethylene included in the block copolymer of this paper was about 15%, and the reason why HDPE was mixed with the mixture of homo polymer and block copolymer was because of corrosion resistance, and the reason why homo polymer and block polymer had a larger ratio than HDPE was to emphasize the heat resistance of PP. In general, submarine and underground cables are corroded from various sources. HDPE has better corrosion resistance than LDPE, XLPE and other materials and has the advantage of melting.



Prior to sheet production, the hot press was heated to 200 ◦C for 5 min. Then, compound supplied by the cable manufacture was added to the molding flask, and the mixture was pressurized at 10 MPa for 5 min, and rapidly cooled for 2 min using a cooling press of 10 ◦C. Figure 2 shows the equipment for manufacturing the PP sheets and the completed test sample.

**Figure 2.** The equipment for manufacturing test samples.

The outer diameter of the PP sheet was 22 cm, the thickness was 0.2 mm, and the error range of the thickness was within 5%.

With reference to the IEC 62431 standard, the number of specimens for the ramping test was set to 10 [29]. In addition, the V-t characteristic test was performed 20 times, and 5 specimens per test voltage were used.

#### *3.2. Experimental Setup*

HVDC generator, voltage dividers, oven, oil bath, data acquisition system (DAS) and PC for temperature measurement were used as equipment for the breakdown test of PP materials.

The HVDC voltage source has a maximum voltage and current of 120 kV and 30 mA, and is configured as a high-voltage transformer, a clamp circuit and peak detector that combines a capacitor and a diode, a protection resistor and a voltage divider. HVAC is generated from the transformer, DC voltage is superimposed via the clamp circuit, and HVDC is generated through the peak detector. The DC voltage from the power source is connected in series with the protection resistor and then applied in parallel to the voltage divider and the test sample. The applied HVAC transformer is 220 V input and 60 kV output, and the diode is for rectifying the AC voltage. It is combined with a diode and a capacitor to the voltage doubler [30]. Capacitors and diodes were used that could withstand a HVDC voltage of 100 kV or higher, and a limited resistor of 120 kΩ was also configured to protect the circuit from overvoltage and overcurrent when the test sample was breakdown. In addition, the voltage divider that connected 300 MΩ and 30 kΩ in series was used to measure the DC voltage applied to the test sample in real time. Figure 3 shows a circuit diagram for the HVDC generator. In general, in order to perform a DC breakdown test, the ripple factor of the HVDC generator is important, and its value must be 3% or less. Note that if the value is exceeded, DC voltage characteristics are not reflected in the test.

Figure 4 shows the schematic representation of ramping and the V-t characteristic test. An oven was used to maintain a constant temperature of 110 ◦C for the test sample, and a temperature sensor was constructed to the dummy sample, and the temperature of the PPs was measured in real time. The transformer oil was put into an oil bath made of stainless steel to prevent flashover, and the oil bath was grounded. For the supporting structure of the breakdown test a polytetrafluoroethylene (PTFE) that was not deformed even at a temperature of 110 ◦C or higher was applied. A heat-resistant silicon-insulated cable was used to apply DC voltage in the air and oil inside the oven.

**Figure 4.** Schematic representation of the experimental setup for V-t characteristic test.

Commercialized micrometers and electrodes were combined for the constant measuring force applied to the test sample. The test electrodes were designed so that the constant force was applied to PP sheet during the V-t characteristic test. The electrode was made of a stainless steel with an outer diameter of 20 mm referring to the standard of IEC 62431. The temperature and voltage applied to the test sample were saved in real time using RS 485 communication. Figure 5 is a picture of the test electrode and the V-t characteristic test inside the oven.

**Figure 5.** The pictures of V-t test: (**a**) electrode with micrometer and PTFE structure; (**b**) dummy sample inside oil for measuring temperature.

#### *3.3. Test Conditions*

The ramping test was performed under a step-up condition at 2 kV per second in accordance with the IEC standard [29]. The DC V-t characteristic test was performed with voltage until it broke. The test was carried out while maintaining the constant operating temperature of 110 ◦C for the PPs.

#### **4. Results**

#### *4.1. Ramping Test*

In order to determine the approximate test voltage of the V-t characteristic test, a ramping test was performed on three types of PPs, and the Weibull distribution 63.2% of breakdown data was 40 kV or more. Figure 6 shows the breakdown data after the ramping test of the test samples as a Weibull distribution function. Table 2 specifies the scale and shape parameters of three types of PPs after ramping test.

**Figure 6.** The Weibull distribution after ramping test of the test samples.


**Table 2.** Specification of the scale and shape parameters of three types of test samples.

#### *4.2. DC V-t Test*

After the ramping test, a DC V-t characteristic test was performed based on a breakdown voltage of 63.2%. For the test voltage, four voltage levels were applied between a maximum of 47 and 36 kV. The breakdown data according to time was plotted using the Weibull distribution function, and a V-t characteristic curve was made using the value of the breakdown time according to the applied voltage. The life exponent was calculated through the slope of the graph, and the life estimation equation of the PPs was derived through the relationship between voltage and time.

In Figures 7a, 8a and 9a the analyses are shown of the breakdown data using the Weibull distribution function, and Figures 7b, 8b and 9b display the figure for calculating the life exponent and life estimation equation. In Figures 7b, 8b and 9b, the red data is the Weibull 63.2% of the breakdown time according to the applied voltage, and the life estimation was derived from the four red data. In the figure, the fastest breakdown data in Figure 9 was 23 s when 47 kV was applied, and the longest lasting data in Figure 8 was 87,138 s when the voltage 36 kV was applied.

**Figure 7.** Breakdown data analysis on block copolymer: (**a**) Weibull distribution according to time to breakdown; (**b**) V-t graph to obtain life exponent and life estimation formula.

#### *4.3. Life Exponent and Estimation*

The V-t characteristic test was carried out on three types of PPs, and the V-t characteristic curve was drawn according to electrical stress. Using Equations (2) and (4), the life exponent n was calculated, and the life estimation formula was also derived.

In general, the life exponent is used in a way that makes it easy to evaluate the longterm reliability of insulating materials. It is judged that the larger the life exponent of the insulating materials, the better the life characteristics. Each life exponent is as follows: the block copolymer was 20.1, when the block copolymer and homo polymer PP were mixed, it was 21.1, and when the block copolymer PP, homo polymer and HDPE were mixed, it was 23.2. It was shown that as the mixture was added to the block copolymer, the long-term reliability properties improved.

**Figure 8.** Breakdown data analysis on block copolymer and homo polymer: (**a**) Weibull distribution according to time to breakdown; (**b**) V-t graph to obtain life exponent and life estimation formula.

**Figure 9.** Breakdown data analysis on block copolymer, homo polymer and HDPE: (**a**) Weibull distribution according to time to breakdown; (**b**) V-t graph to obtain life exponent and life estimation formula.

Since the design life of a power cable is usually 40 years, an equation that can calculate the long-term operating life due to electrical stress was needed. Table 3 shows the life exponent and life estimation formula of other PPs with the mixing ratio of additives.

**Table 3.** The life exponent and life estimation formula according to PPs.


#### *4.4. Evaluation of Electrical Performance*

The use of life exponent in assessing long-term reliability and performance is very relative. So, we required a way to express the electrical performance as a percentage. Figure 10 shows the electrical stress of 100 years of PP insulating material using the lifetime equation and when comparing the three materials, the larger breakdown voltage value according to life is more economical because it can reduce the insulation thickness applied to the cable. Electrical performance was evaluated by electrical stress tolerance based on a block copolymer with a design life of 40 years as a standard. The PP with HDPE was 17%, and the electrical performance was excellent. Table 4 shows the performance evaluation of dielectric strength of PPs in 40 years.

**Figure 10.** V-t curve considering the long term operation of power cables.


**Table 4.** Performance evaluation of dielectric strength of PPs in 40 years.

#### **5. Discussion**

Many researchers have used the life exponent as a method for assessing long-term reliability, but some have not considered it in experiments and analyses.

Initially, the experimental part did not use a dummy sample during the V-t test and did not present a method that could provide a uniform pressure on the test samples.

Second, the long-term reliability of the materials was evaluated only by the life exponent, which is a relative numerical value in the analysis. Based on the life equation, the evaluation of electrical performance at the design life of the cable should be performed.

In this study, dummy samples were used to measure temperature in real time, and a commercially available micrometer was used to present a method for a constant measuring force of samples. The V-t characteristics test of the test samples was conducted at 110 ◦C. As shown in Figures 7–9, the life exponent according to the breakdown voltage and time to breakdown is quantitatively calculated. The block copolymer had a value of 20.1, the case block copolymer and homo polymer were mixed, with a value of 21.1, and the block copolymer, homo polymer and HDPE were mixed, with a value of 23.2. We compared the electrical performance between the materials mixed block copolymer, homo polymer and HDPE to prove the long-term reliability and applicability of HVDC. In addition, we evaluated the electrical performance which is the cable design life of 40 years. The electrical performance of the insulation mixed block copolymer, homo polymer and HDPE is up

to 17% higher than block copolymer. Additionally, it was found that the mixed material without HDPE was also about 16% higher than the block copolymer, and the influence of HDPE seems to be inadequate. However, HDPE has a corrosion resistance to water, which will prevent the aging and failure due to moisture penetration of the submarine and underground cable and will ensure long-term reliability. Based on this study, evaluation of electrical performance with PPs when exposed to water is also essential, and further research on the long-term reliability of the block copolymer and HDPE mixed materials are not mentioned in this paper.

There are some points and limitations that need to be improved in this study. Since the content of this study is related to the life due to electrical stress, additional studies according to the thermal and mechanical properties are also required. In addition, the reliability of this model depends on the number of breakdown data. Because the Weibull distribution function is a statistic, the reliability of the analysis increases with more data. Conversely, this model is vulnerable and can fail if the amount of data is small. We test to meet the minimum number provided by the IEC and require additional testing to obtain more reliable results. Further study of the related attributes of conductivity and space charge for a DC application is also required. It is also necessary to evaluate the long-term reliability of cables to which PP insulating materials are applied. In this paper, we can contribute as a reference for HVDC application of PP and insulation, and contribute to the life and long-term reliability evaluation of insulating materials through the DC V-t.

In addition, as described in this paper, Figures 1 and 6, Figures 7–10 use a software program called Origin.

#### **6. Conclusions**

In this study, electrical performance was evaluated for HVDC application of PP. DC V-t characteristics tests were performed on three types of s, the life exponent was calculated, and the life estimation equation of the PP insulating material due to electrical stress was derived.

The implications of this study can be summarized as follows. First, the life exponent of PPs is 20 or more, which is equivalent to or higher than that of conventional materials, demonstrating the applicability of HVDC. Second, the long-term reliability was evaluated by deriving the life estimation equation of PP insulating material due to electrical stress. Third, based on the third life estimation equation, the PP with HDPE had a 17% better electrical performance than the block polymer based on the design life of the cable of 40 years.

**Author Contributions:** This paper is a result of the collaboration of all co-authors. S.-W.L. and I.-S.K. conceived and designed the study. H.-J.K. and S.-W.L. established the model and drafted the manuscript. J.-S.L. refined the language and provided statistical information. H.-J.K. helped with the corrections. S.-W.L. designed and performed the experiments. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by the Ministry of Science and ICT (MSIT) (No. 21A01058).

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** Not applicable.

**Acknowledgments:** This research was supported by Korea Electrotechnology Research Institute (KERI) Primary research program through the National Research Council of Science &Technology (NST) funded by the Ministry of Science and ICT (MSIT) (No. 21A01058).

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


**Zhengwang He 1, Zhiyong Li 1,\*, Ruoyue Wang 1, Ying Fan <sup>2</sup> and Minqian Xu <sup>1</sup>**


**Abstract:** This paper presents the design and optimization of a wireless power transfer (WPT) charging system based on magnetically coupled resonant technology, applied to an Unmanned Aerial Vehicle (UAV). In this paper, a charging system, including dual active transmitter coils and a single receiver coil, is proposed. The dual transmitting coils adopt a coaxial structure with different radii. This structure simplifies the calculation of the complex mutual inductance between the coils to a function of mutual inductance only related to the value of the radial misalignment. Aiming toward a constant charging power, the optimal transmission efficiency of electric energy is achieved by controlling the input voltages of the active coils, which are solved via a set of equations defined as Lagrange multipliers. The simulation results of the 570 V and 85,000 Hz system verified the validity of the proposed wireless UAV charging scheme.

**Keywords:** Lagrange multiplier; magnetically coupled resonant technology; power compensation; radial misalignment

#### **1. Introduction**

UAVs undoubtedly have high research potential and application value, but the flight time of UAVs restricts their development. This is because a high-energy density lithium battery, which is adopted to the UAV, only permits a flight time of about 20–40 min [1].

Thus, researchers began to research the application of magnetically coupled resonant technology to charge UAVs for solving this limitation [2–5]. This method creates a base station where the batteries can be automatically charged after landing [3]. The proposed magnetically coupled resonant system in [2] is mainly composed of two coils, namely, a single transmitting coil and a single receiving coil. The power transmission efficiency between the two coils is a function of the vertical distance between the two coils and the power supply. When the two coils are coaxial, the power transmission efficiency of the coil is the highest, and when the distance between the two coils is increased, the power transmission efficiency decreases. In the practical charging process of UAVs, the coaxial position of the receiving coil and the transmitting coil cannot be guaranteed, namely, radial misalignment, which will lead to a reduction in output power and charging time delay [6]. Therefore, it is necessary to research the power compensation problem of misaligned charging.

Scholars have adopted various methods to solve this problem [7–18]. In [7–11], a reconfigurable resonator and numerous transmission coil arrays with different structures have been used to improve transmission efficiency. A relatively complete mutual inductance model for analyzing magnetically coupled resonant technology was established. A planar transmitting resonator with an array of 2 × 2 using a single feeding loop was presented in [12]. This structure could maintain high transfer efficiency in a plane. However, the power transfer efficiency function determined by this structure is still two-dimensional

**Citation:** He, Z.; Li, Z.; Wang, R.; Fan, Y.; Xu, M. A New Arrangement of Active Coils for Wireless Charging of UAV. *Energies* **2021**, *14*, 5754. https://doi.org/10.3390/en14185754

Academic Editor: José Gabriel Oliveira Pinto

Received: 21 July 2021 Accepted: 9 September 2021 Published: 13 September 2021

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

in essence. This leads to the need for complex control strategies to achieve the goal of constant output power, which is not worth it in practical application. In [13], two circular planar spiral coils were applied to both receive and transmit circuits of a WPT system. The main disadvantage of this configuration is that it reduces the load capacity of the UAV. In [14], an automatic landing procedure for UAV was proposed, which fundamentally reduces the possibility of radial misalignment. A WPT charging system with a movable transmitting coil was introduced in [15]. When the UAV lands, the mobile transmitting coil can automatically align with the receiving coil. Of course, it requires a high-precision positioning system. A lightweight wireless charging system was presented in [17]. This design can improve the load capacity of UAVs without affecting the operation of various equipment carried by UAVs. In [18], Noriaki Oodachi et al. have proposed a wireless power transmission system to solve this problem by using phase weights of transmission coil arrays. When the receiving coil is not coaxial with the transmitting coil, according to the direction between the transmission coil and the receiving coil, the transmission coil of the coil array is excited by the transmission circuit and the corresponding phase weight to achieve the purpose of power compensation. However, this method also requires a large number of coils, and the control algorithm and implementation are complex, which increase the costs.

The system proposed in this paper is simple and effective. In order to compensate the power reduction caused by radial misalignment, two coaxial active coils with different radii are used as the transmitting coils, and the compensation is realized by controlling the different input power of the two coils. When the output power of one transmitting coil decreases due to radial misalignment, the other transmitting coil with different radii that are still coaxial is applied to compensate the output power, so as to maximize the transmission efficiency of the system, which satisfies the Lagrange multiplier. In addition, by controlling the input voltage of the two active coils of the system, a power supply with arbitrary output power can be designed. This design simplifies the efficiency function from a function with two-dimensional variables to a function with only a radial variable, so there is no need for a complex control algorithm, which makes it more practical.

#### **2. Proposed Wireless Charging of UAV System**

This paper presents the design of a UAV charging system with magnetically coupled resonant technology, as shown in Figure 1. The transmitting coil uses double coaxial active coils, with the receiving coil and transmitting coils coupled by air. The vertical distance between the UAV and the charging pile is 10 cm. Both the double transmitting circuit and the single receiving circuit adopt the topology of inductance and capacitor in series. The whole system realizes power transmission through the full resonance of coil and capacitor.

**Figure 1.** Proposed system for UAV charging.

In order to research the specific internal strategy of the new charging pile, two mathematical models, including the power model and mutual inductance model of the system, are established according to the actual charging situation of the UAV, and the theoretical analysis is carried out. The power model analyzes the relationship between the output power of the system and the input voltage of the two active coils; the transmission efficiency is found when the mutual inductance and output power are constant. The mutual inductance model analyzes the relationship between the mutual inductance of the system and the radial misalignment caused by the landing error when the UAV is charging, and provides a scheme to compensate for the system's output power reduction that is simple and effective. A 570 V, 85,000 Hz system is built in MATLAB/Simulink, and the output power of the system is obtained. The transmission efficiency of the system can reach 82%. At the same time, it is confirmed that the double transmitting coils have a good compensation effect on the power reduction caused by the radial misalignment of the system; the correctness of the control strategy is also verified.

#### *2.1. Model of System Mutual Inductance and Radial Misalignment Distance*

In most of the experimental studies, the transmitting coil and receiving coil are placed in parallel, and their central axis position is the same. However, when the UAV actually stops, it cannot be guaranteed that it will stop in the axial direction of the transmitting coil. When the position of the coil deviates, the mutual inductance M will change. When the system frequency is fixed and the coil resistance is constant, the change in mutual inductance M is the most important factor affecting system performance. Therefore, when the receiving coil has radial misalignment, the mutual inductance between the receiving coil and the transmitting coil changes, which leads to a change in system power and efficiency.

Only the mutual inductance mode of the single transmitting and single receiving coils is considered, as shown in Figure 2. The center of the transmitting coil is placed in the coordinate system (0, 0, 0), and the center of the receiving coil is placed in the coordinate system (0, t, h).

**Figure 2.** One active to receiver charging mode.

The parameter equations of the transmitting and receiving coils are listed as follows:

$$\begin{cases} \begin{aligned} \mathbf{x}\_1 &= r\_1 \times \cos \theta \\ y\_1 &= r\_1 \times \sin \theta + r \\ \mathbf{z}\_1 &= h \\ \mathbf{x}\_2 &= r\_2 \times \cos \alpha \\ y\_2 &= r\_2 \times \sin \alpha \end{aligned} \end{cases} \tag{1}$$

Therefore:

$$\begin{cases} \text{d}l\_1 = (r\_1 \times \cos\theta - r\_1 \times \sin\theta)\text{d}\theta\\ \text{d}l\_2 = (r\_2 \times \cos\alpha - r\_2 \times \sin\alpha)\text{d}\alpha\\ \text{d}l\_1 \times \text{d}l\_2 = r\_1 \times r\_2 \cos(\theta - \alpha)\text{d}\theta\text{d}\alpha \end{cases} \tag{2}$$

According to the Neumann formula, when the number of turns of the receiving coil is *N*<sup>1</sup> and the number of turns of the transmitting coil is *N*2, the mutual inductance formula between them is as follows:

$$M = \frac{N\_1 \times N\_2}{4\pi} \times \frac{\text{d}l\_1 \times \text{d}l\_2}{R} = \frac{N\_1 \times N\_2}{4\pi} \int\int\limits\_0^{2\pi} \frac{r\_1 \times r\_2 \cos(\theta - \alpha)\text{d}\theta \,\text{d}\alpha}{D} \tag{3}$$

In the above formula:

$$\mathbf{D} = \sqrt{\left(r\_1 \times \cos \theta - r\_2 \times \cos \alpha\right)^2 + \left(r\_1 \times \sin \theta + r - r\_2 \times \sin \alpha\right)^2 + h^2}$$

Analysis of Equation (3) shows that the mutual inductance of the system decreases with the increase in radial misalignment, and the output power decreases with the decrease in mutual inductance. Therefore, it is necessary to compensate for the mutual inductance reduction caused by the radial misalignment of the single transmitter and single receiver system.

Considering double transmitting and single receiving coils, the two transmitting coils are coaxial with different radii. With the increase in radial misalignment, the mutual inductance between the two transmitting coils and the receiving coil changes according to Equation (3). However, for the receiving coil, the total mutual inductance is the sum of mutual inductance between the two transmitting coils and the receiving coil, which compensates for the reduction in mutual inductance; Maxwell simulation verifies this conclusion.

#### *2.2. Model of Output Power and Input Voltage*

We define the mutual inductance between coil 1 and coil 2 as *M*12, and define *M*<sup>13</sup> and *M*<sup>23</sup> in the same way. When the UAV lands on the charging pile, the relative position between the receiving coil and the two transmitting coils is fixed, so the mutual inductance between the two coils is fixed, i.e., *M*13, *M*<sup>23</sup> and *M*<sup>12</sup> are constant. The output power of the system is only related to the input voltage of the active coil, as shown in Figure 3. The detailed model analysis is as follows:

**Figure 3.** Two active to receiver charging modes.

In order to simplify the model, the parameters of the circuit model are symmetrical, namely, R1 = R2 = R3 = R. The transmitter and receiver of the system will work at the same frequency, which is defined as:

$$
\omega = 2\pi \mathbf{f} = \frac{1}{\sqrt{\mathbf{C}\_1 \mathbf{L}\_1}} = \frac{1}{\sqrt{\mathbf{C}\_2 \mathbf{L}\_2}} = \frac{1}{\sqrt{\mathbf{C}\_3 \mathbf{L}\_3}} \tag{4}
$$

where f is the fundamental frequency of the power supply.

By listing the voltage equation of each circuit, the following voltage and current (Equation (5)) can be obtained:

$$
\begin{pmatrix} V\_1 \\ V\_2 \\ 0 \end{pmatrix} = \begin{pmatrix} \mathbf{R}\_1 + j\omega \mathbf{L}\_1 + \frac{1}{j\omega \mathbf{C}\_1} & -j\omega M\_{12} & -j\omega M\_{13} \\ -j\omega M\_{12} & \mathbf{R}\_2 + j\omega \mathbf{L}\_2 + \frac{1}{j\omega \mathbf{C}\_2} & -j\omega M\_{23} \\ -j\omega M\_{13} & -j\omega M\_{23} & \mathbf{R}\_3 + \mathbf{R}\_1 + j\omega \mathbf{L}\_3 + \frac{1}{j\omega \mathbf{C}\_3} \end{pmatrix} \begin{pmatrix} I\_1 \\ I\_2 \\ I3 \end{pmatrix} \tag{5}
$$

The input impedance of the system is solved. According to the defined system operating frequency, order *V*<sup>2</sup> = 0, the following equation (Equation (6)) can be obtained:

$$Z\_{\rm sent1} = \mathbf{R}\_1 + \frac{\left(\omega M\_{12}\right)^2 \left(\mathbf{R}\_3 + \mathbf{R}\_1\right) - \mathbf{j}\omega^3 M\_{12} M\_{13} M\_{23}}{\mathbf{R}\_2 \left(\mathbf{R}\_3 + \mathbf{R}\_1\right) + \left(\omega M\_{23}\right)^2} + \frac{\left(\omega M\_{13}\right)^2 \mathbf{R}\_2 + \mathbf{j}\omega^3 M\_{12} M\_{13} M\_{23}}{\mathbf{R}\_2 \left(\mathbf{R}\_3 + \mathbf{R}\_1\right) + \left(\omega M\_{23}\right)^2} = \mathbf{R}\_1 + \mathbf{Y}\_2 + \mathbf{Y}\_3 \tag{6}$$

*Y*<sup>2</sup> and *Y*<sup>3</sup> in Equation (6), respectively, indicate the mutual inductance influence of loop 2 and loop 3 on loop 1:

$$\begin{cases} \begin{array}{c} \mathcal{Y}\_{2} = \frac{\left(\omega \nu M\_{12}\right)^{2} \left(\mathcal{R}\_{3} + \mathcal{R}\_{l}\right) - \left[\omega \nu^{3} M\_{12} M\_{13} M\_{23}\right]}{\mathcal{R}\_{2} \left(\mathcal{R}\_{3} + \mathcal{R}\_{l}\right) + \left(\omega \nu M\_{23}\right)^{2}}\\ \mathcal{Y}\_{3} = \frac{\left(\omega \nu M\_{13}\right)^{2} \mathcal{R}\_{2} + \left[\omega \nu^{3} M\_{12} M\_{13} M\_{23}\right]}{\mathcal{R}\_{2} \left(\mathcal{R}\_{3} + \mathcal{R}\_{l}\right) + \left(\omega \nu M\_{23}\right)^{2}} \end{array} \tag{7}$$

Therefore, the input current *I*<sup>1</sup> of active coil 1 can be expressed as:

$$I\_1 = \frac{V\_1}{Z\_{\text{sent1}}} = \frac{V\_1}{R\_1 + Y\_2 + Y\_3} \tag{8}$$

Aligned, the input current *I*<sup>2</sup> of active coil 2 can be expressed as:

$$I\_2 = \frac{V\_2}{Z\_{\text{sent2}}} = \frac{V\_2}{R\_2 + Y\_2^{'} + Y\_3^{'}}\tag{9}$$

Among:

$$\begin{cases} \begin{array}{c} Y\_2' = \frac{\left(\omega M\_{12}\right)^2 \left(\mathbf{R}\_3 + \mathbf{R}\_1\right) - \left(\omega \nu^3 M\_{12} M\_{13} M\_{23}\right)}{\mathbf{R}\_1 \left(\mathbf{R}\_3 + \mathbf{R}\_1\right) + \left(\omega \nu M\_{13}\right)^2} \\\ Y\_3' = \frac{\left(\omega \nu M\_{23}\right)^2 \mathbf{R}\_1 + \mathbf{j} \omega^3 M\_{12} M\_{13} M\_{23}}{\mathbf{R}\_1 \left(\mathbf{R}\_3 + \mathbf{R}\_1\right) + \left(\omega \nu M\_{13}\right)^2} \end{array} \tag{10}$$

Considering two active coils, the output current *I*<sup>3</sup> of the receiver can be expressed as:

$$I\_3 = \frac{\text{j}\omega M\_{13} \times I\_1 + \text{j}\omega M\_{23} \times I\_2}{\text{R}\_3 + \text{R}\_l} = \frac{\text{j}\omega M\_{13}}{\text{R}\_3 + \text{R}\_l} \times \frac{V\_1}{\text{R}\_1 + Y\_2 + Y\_3} + \frac{\text{j}\omega M\_{23}}{\text{R}\_3 + \text{R}\_l} \times \frac{V\_2}{\text{R}\_2 + Y\_2 + Y\_3} \tag{11}$$

Among *Zsent*<sup>2</sup> = *R*<sup>1</sup> + *Y*<sup>2</sup> + *Y*<sup>3</sup> . Therefore, the input power *P*in and output power *P*out of the system can be expressed as:

$$P\_{\rm in} = \text{Re}(V\_1 \times I\_1^\*) + \text{Re}(V\_2 \times I\_2^\*) = \frac{\left(V\_1\right)^2}{\text{R}\_1 + \text{Y}\_2 + \text{Y}\_3} + \frac{\left(V\_2\right)^2}{\text{R}\_2 + \text{Y}\_2^\* + \text{Y}\_3^\*} \tag{12}$$

$$P\_{\rm out} = I\_3^2 \times \mathcal{R}\_{\rm l} = \left(\frac{\rm j\omega}{(\rm R\_3 + \rm R\_l)}\right)^2 \times \left(\frac{M\_{13}V\_1}{\rm R\_1 + Y\_2 + Y\_3} + \frac{M\_{23}V\_2}{\rm R\_2 + Y\_2 + Y\_3}\right)^2 \times \mathcal{R}\_{\rm l} \tag{13}$$

Therefore, the efficiency of the system *η* can be calculated as follows:

$$\eta = \frac{P\_{\text{out}}}{P\_{\text{in}}} = \left(\frac{\text{j}\omega}{R\_{\text{\textdegree}} + \text{R}\_{\text{l}}}\right)^2 \times \frac{Z\_{\text{sent1}} \times Z\_{\text{sent2}} \times \left(\frac{M\_{\text{13}}V\_{\text{l}}}{Z\_{\text{sent1}}} + \frac{M\_{\text{23}}V\_{\text{2}}}{Z\_{\text{sent2}}}\right)^2}{\left(V\_{\text{l}}\right)^2 \times Z\_{\text{sent2}} + \left(V\_{\text{2}}\right)^2 \times Z\_{\text{sent1}}} \times R\_{\text{l}}\tag{14}$$

Thus, the value of *η* is related to the two input voltages of the system and the mutual inductance between the two coils. Additionally, the observation Equations (13) and (14) show that when the output power and radial misalignment are fixed, there must be the maximum transmission efficiency.

The output power *Pout* is set as constant at 640 W. The goal is to maximize transmission efficiency. The optimal problem formulation is Equation (15):

⎧ ⎪⎨ ⎪⎩ *Max* : \* η*η* = *<sup>P</sup>*out *<sup>P</sup>*in = jω R3+Rl 2 <sup>×</sup> *<sup>Z</sup>*sent1×*Z*sent2<sup>×</sup> *<sup>M</sup>*13*V*<sup>1</sup> *<sup>Z</sup>*sent1 <sup>+</sup> *<sup>M</sup>*23*V*<sup>2</sup> *<sup>Z</sup>*sent2 <sup>2</sup> (*V*1) <sup>2</sup>×*Z*sent2+(*V*2) <sup>2</sup>×*Z*sent1 × Rl + *Pout* − 640 = 0 ⎫ ⎪⎬ ⎪⎭ (15)

Lagrange multiplier *λ* is introduced and a Lagrangian function is constructed:

$$L = \eta - \lambda \times (P\_{\text{out}} - 640) \tag{16}$$

When the partial derivative of Equation (16) is found, they can be set to zero:

$$\begin{cases} \frac{\partial L}{\partial V\_1} = \frac{\partial \eta}{\partial V\_1} - \lambda \times \frac{\partial P\_{\text{out}}}{\partial V\_1} = 0\\ \frac{\partial L}{\partial V\_2} = \frac{\partial \eta}{\partial V\_2} - \lambda \times \frac{\partial P\_{\text{out}}}{\partial V\_2} = 0\\ P\_{\text{out}} = 640 \end{cases} \tag{17}$$

The corresponding *V*<sup>1</sup> and *V*<sup>2</sup> are obtained when the efficiency is maximum, as long as *V*<sup>1</sup> and *V*<sup>2</sup> are satisfied (Equation (17)).

The flowchart of the methodology mentioned is introduced in Figure 4.

**Figure 4.** The flowchart of the methodology.

#### **3. Simulation**

The proposed 570 V and 85,000 Hz power model is simulated in MATLAB/Simulink, and the rationality of the model is verified. The parameters of the system are listed in Table 1. The mutual inductance parameters of the coil are simulated by the finite element method in Maxwell.


**Table 1.** Parameters of the system.

#### *3.1. Simulation of Mutual Inductance Parameters*

When the coil has radial misalignment, double transmitting and single receiving coils are considered. The radii of the two transmitting coils are 26 cm and 36 cm, respectively, and the radius of the receiving coil is 26 cm. The vertical distance between the transmitting coil and the receiving coil is kept at 10 cm, and the medium is air. The finite element simulation, as shown in Figure 5a, is carried out in Maxwell. The relationship between mutual inductance and radial distance in the two transmitting coils and receiving coils can be obtained, as shown in Figure 5b,c. It is found that the mutual inductance between the two transmitting coils and the radial distance decreases with the increase in radial misalignment. Combined with the power model, the power of the system also decreased. For the receiving coil, mutual inductance is the sum of the two, which compensates for the reduction in mutual inductance and power of the single transmitting coil. At the same time, the self-inductance of the 36 cm coil is twice that of the other two 26 cm coils, and the self-inductance is only related to the material and radius of the coil.

**Figure 5.** Maxwell simulation. (**a**) Snapshot of Maxwell simulation diagram (**b**) Simulation result of 26 cm transmitting coil. (**c**) Simulation result of 36 cm transmitting coi.l.

#### *3.2. Power*

According to the coil parameters calculated in model A, the simulation output waveform of the system simulated by Simulink is shown in Figure 6. A snapshot of the simulation file is shown in Figure 6a. We use a transformer to replace the resonant coils and their mutual inductance. As for the high-frequency AC power required by the system, we directly use AC power to generate it. Both the double transmitting circuit and single receiving circuit adopt the topology of inductance and capacitor in series. In other figures, *Uout* is the output voltage waveform. *Uin* is the input voltage of the active coil. *Iin* is the input current waveform of the active coil. *Iout* is the output current waveform. Output power is the output active power of the system and input power1 and input power2 are the input active power of the system. According to the simulated voltage and current, the transmission efficiency of the system can be calculated, which reaches 94%. Comparing the simulation results with the theoretical results, the output power error is less than 5%.

At the same time, the simulation results show that the output current and voltage waveform is sine wave, but there are phase differences, which is caused by mutual inductance resonance not being complete, and therefore, there is phase lag.

**Figure 6.** Waveforms of the transmitter currents and the load voltage. (**a**) Snapshot of Matlab simulation (**b**) Voltage (**c**) Current (**d**) Output power and input power 1 (**e**) input power 2.

By changing the value of the input voltage, an arbitrary power output can be achieved. Table 2 shows the simulated output power under different voltage peaks, which is close to the theoretically derived value.

In addition, different radial misalignment will cause a decrease in the mutual inductance between the receiving coil and the transmitting coil, resulting in a decrease in power. As shown in Figure 7, when the peak input voltages of the two active coils are both 570 V, the output power is negatively correlated with the radial misalignment.

Finally, when the radial misalignment is constant with the input voltage of one active coil, the simulation between the output power and the input voltage of the other active coil verifies the correctness of the control strategy.

The verification result is shown in Figure 8. At this time, the radial misalignment of the system is 5 cm, and the input voltage of an active coil is 570 V. The output power of the system increases as the input voltage of the active coil increases.

**Table 2.** Comparison of simulation and theoretical values of output power.


**Figure 7.** The output power and the radial misalignment.

**Figure 8.** The output power and the input voltage.

#### **4. Discussion**

This paper presents a new wireless power transmission charging system for UAVs, and establishes two mathematical models to perfect the theoretical basis of the system. We also determine the control strategy between output power and input voltage when there is radial misalignment. The structure of a double transmitting coil and single receiving coil can better compensate for the mutual inductance and output power drop caused by radial misalignment. At the same time, the output power of the system can be changed by controlling the input voltage of the system to realize a power supply of any output power, which is simple and easy to operate. When the output power is constant, maximum power transfer efficiency is obtained by controlling the input voltage of the two coils. Numerical and simulation results have been presented in terms of electrical performance to demonstrate the validity of the proposed structure.

**Author Contributions:** Conceptualization, Z.H. and Z.L.; methodology, Z.H.; software, Z.H.; validation, M.X., Y.F. and R.W.; formal analysis, Z.H.; investigation, M.X.; resources, Z.L.; data curation, R.W.; writing—original draft preparation, Z.H.; writing—review and editing, Z.H.; visualization, R.W.; supervision, Z.L.; project administration, Z.H.; funding acquisition, Z.L. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research received no external funding.

**Data Availability Statement:** The data presented in this study are available on request from the corresponding author.

**Acknowledgments:** Thanks are due to Wenjing Xiong and Zixi Liu, of Central South University, for their help in the testing.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


## *Review* **Multilevel Inverter: A Survey on Classical and Advanced Topologies, Control Schemes, Applications to Power System and Future Prospects**

**Subhashree Choudhury 1, Mohit Bajaj 2, Taraprasanna Dash 3, Salah Kamel <sup>4</sup> and Francisco Jurado 5,\***


**Abstract:** In recent years, multilevel inverters (MLIs) have emerged to be the most empowered power transformation technology for numerous operations such as renewable energy resources (RERs), flexible AC transmission systems (FACTS), electric motor drives, etc. MLI has gained popularity in medium- to high-power operations because of numerous merits such as minimum harmonic contents, less dissipation of power from power electronic switches, and less electromagnetic interference (EMI) at the receiving end. The MLI possesses many essential advantages in comparison to a conventional two-level inverter, such as voltage profile enhancement, increased efficiency of the overall system, the capability of high-quality output generation with the reduced switching frequency, decreased total harmonic distortions (THD) without reducing the power of the inverter and use of very low ratings of the device. Although classical MLIs find their use in various vital key areas, newer MLI configurations have an expanding concern to the limited count of power electronic devices, gate drivers, and isolated DC sources. In this review article, an attempt has been made to focus on various aspects of MLIs such as different configurations, modulation techniques, the concept of new reduced switch count MLI topologies, applications regarding interface with renewable energy, motor drives, and FACTS controller. Further, deep insights for future prospective towards hassle-free addition of MLI technology towards more enhanced application for various fields of the power system have also been discussed. This article is believed to be extremely helpful for academics, researchers, and industrialists working in the direction of MLI technology.

**Keywords:** flexible AC transmission systems (FACTS); multilevel inverter (MLI); renewable energy resource (RER); selective harmonic elimination (SHE); space vector control (SVC); total harmonic distortions (THD)

#### **1. Introduction**

Recently, the MLI has been regarded as state of the art technology for power conversion from DC to AC in the fields of generation, transmission, distribution, and employment of electrical energy. They have been innovated as an competent solution for wide range of power applications such as RER [1–6], FACTS [7–10], high-voltage direct current (HVDC) [11–14], static compensators (STATCOMs) [15–18], unified power flow controllers (UPFCs) [19–21], dynamic voltage restorers (DVRs) [22,23], active filters (AFs) [24,25], motor drives used for traction/transportation [26–33], marine propulsion [34–38], conveyors [39,40], mine hoists [41], magnetic resonance imaging system (MRI) [42] and induction heating power supply [43]. The conventional two-level inverters fail to operate in the

**Citation:** Choudhury, S.; Bajaj, M.; Dash, T.; Kamel, S.; Jurado, F. Multilevel Inverter: A Survey on Classical and Advanced Topologies, Control Schemes, Applications to Power System and Future Prospects. *Energies* **2021**, *14*, 5773. https:// doi.org/10.3390/en14185773

Academic Editor: Ching-Ming Lai

Received: 19 July 2021 Accepted: 7 September 2021 Published: 13 September 2021

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

medium voltage range due to the semiconductor's blockage voltage limitation. However, MLIs play a key role in medium-voltage and high-power operations.

Further, for the same power ratings, MLIs have merit over a two-level inverter in terms of reduced harmonic contents of line-to-line voltage that are fed to load with respect to its level of switching frequencies [44]. The primary reasons behind the MLI serving as a vital revolution in the era of industrialization for potent performance are as follows: (i) compatible in design; (ii) capability of operating at higher current and voltage due to its modular structure; (iii) lesser voltage derivatives on power electronic switches as the voltage stress gets divided across the switches at various levels; (iv) easy interface with RER and motor drives where the load sharing is brought about by DC link; (v) enhanced power quality performance with low harmonic content and better electromagnetic compatibility; (vi) produces lower common-mode voltage; (vii) ability of transformer-less operation; (viii) enhanced efficiency level due to switching at fundamental frequency thus decreasing losses due to conduction and switching; (ix) draws input current with fewer distortions and (x) uses various control approaches and reduced switching states for achieving fault-tolerant operation. Table 1 highlights the primary differences between a traditional two-level inverter and the MLI.

**Properties Two-Level Inverter MLI** Structure Complicated Modular Operation at high voltage and current Can operate (for parallelized structures) Can operate stress on power electronic switches More Less Application Low voltage High voltage Power quality performance Low High Harmonic content Low High Electromagnetic interference (EMI) Immunity/susceptibility Less More Production of common-mode voltage Higher Lower Ability of transformer-less operation No Yes Efficiency Low High Switching losses High Low Operation at the fundamental frequency Fails Can operate Input current distortions High Low Fault tolerant operation Impossible Possible Rate of change of voltage High Low Ability to operate at low/high/ fundamental frequency More Less Production of multiple voltage level Not possible Possible Electromagnetic interference (EMI) generation High Low

**Table 1.** Comparison between traditional two-level inverter and MLI.

The basic principle behind MLI is that it consists of one or more DC sources and an array of low-rated power semiconductor switches for generating an output voltage with a stepped voltage waveform to achieve higher power levels [45,46]. The main objective of MLI is to synthesize an approximately sine wave of voltage with various steps by using the appropriate switching signal of the power electronic switches with the help of different direct current voltage sources such as batteries, supercapacitors, fuel cells, solar panels, etc. [47]. The number of levels of the output waveform can be increased for attaining pure sinusoidal voltage without the use of heavy transformers and passive filters [47,48]. The most traditional MLI topologies, according to their structure, are classified into three types (i) neutral point clamped (NPC); (ii) flying capacitor (FC), and (iii) cascaded H-bridge (CHB) [49]. The three-level NPC type of MLI is widely used in the application of motor drive. The FC type of MLI uses balancing capacitors on phase buses to generate multilevel output voltage waves clamped by capacitors instead of diodes. The CHB is extensively

used as it's more flexible due to its modular configuration and uses the least number of semiconductor switches for a particular level of operation. It generally comprises an array of H-bridge cells for synthesizing a required voltage from numerous isolated DC sources [50]. However, the classical MLIs undergo a crucial shortcoming: the increase in the count of driving circuits and devices in proportion to the number of levels makes the control circuit very complicated. The increased number of device components, in turn, reduces the overall stability of the system. Consequently, many authors have investigated new configurations intending to optimize the utilization of components and enhance the output voltage waveform [51].

Amongst the different topologies developed are the cascaded H-bridge, hybrid series and parallel sources (HSPSs), criss-cross, packed-U cells, and cascaded-bipolar switched cells have been reported by many researchers and have acquired worldwide consideration. Authors in [49] have researched the classical Voltage Source Inverter (VSI) development for the MLI application. Consequently, the research has been expanded to investigate the performance of numerous control approaches to improve the operation of MLIs and optimize their performance with various topologies. The modulation methods in MLIs have been endorsed by their range of switching frequencies. Nevertheless, the highfrequency modulation methods are restricted in the medium voltage range because the losses incurred during switching reduce the inverter component values and the system's overall efficiency.

The SPWM approach is implemented in industrial applications to lower the harmonic content on the output voltage waveform. Space vector modulation (SVM) technique possesses remarkable performance in 3-level MLI topologies. Other techniques involving modulation methods at a low switching frequency that have attained more demand in a broader field of function are Staircase modulation, space vector control (SVC), and selective harmonic elimination (SHE) [39]. A detailed study of these techniques has been discussed further in this article. Figure 1 illustrates the summary of the review methodology adopted in the present research work.

The significant contributions of this research paper include:


The entire research article is structured into seven major sections. Section 2 addresses the development of MLI Topologies. A thorough classification of MLI topologies in terms of classical versus new reduced switch count topology and single versus multiple DC sources is projected in Section 3. Section 4 represents the detailed categorization of various modulation schemes depending upon the switching frequency. The novel applications of MLI after a rigorous survey of literature on MLI are highlighted in Section 5. The key points to be dealt with seriously for further enhancement in MLI technology in the future have been meticulously discussed in the Section 6. Finally, the conclusion from the entire study is presented in Section 7.

**Figure 1.** A summary of the review methodology adopted in the present research work.

#### **2. Development of MLI Topologies**

An outlook on the development of various topologies of MLI is depicted in Figure 2. A thorough study of this evolution has been discussed in this section. CHB was first developed by Baker and Bannister [52] in the 1970s, which possessed the capability of generating multilevel voltage using different DC source voltage [53–55]. The next advancement in MLI topology was the NPC inverter, first evolved by Nabae et al. [56] in the 1980s [57–59]. In the 1990s, Meynard and Foch [60] and Lavieville et al. [61] developed the FC type of MLI. These three classical types of MLI-based topologies were regarded as the foundation of most MLI inverters presented in the modern era. The next invention was the modular multilevel converter (MMC), primarily applied in industrialization [62,63]. In 2000 [64], a generalized MLI named P2 was introduced. Authors in [65] have proposed active neutral point clamped (ANPC) topology. Many other new MLI configurations with application-based approaches have been proposed and conferred in the recent past. Authors have also focused on developing a new reduced switch count topology of MLI [66,67]. The new topology of

MLI can be categorized as (i) symmetric type based on the use of equal DC sources [68–80]; (ii) asymmetric type based on the use of unequal DC sources [69,70,81–85]; (iii) having inherent negative level [68–70,81–85]; (iv) without inherent negative level [72–80]; (v) use of capacitors links with single sources [81–86]; (vi) regenerative configuration for operation as both an inverter and a rectifier [73–75] and (vii) hybrid approach of NPC, FC and CHB [84–87].

**Figure 2.** An outlook on the development of various MLI topologies.

#### **3. Classical and New Reduced Switch Count MLI Topologies**

The concept of MLIs was first introduced in 1975 [52] and then pursued by combative work to develop numerous topologies based on modifying the configuration regarding arrangements of power electronic semiconductor switches and DC sources. Research was also conducted to achieve greater power by the series combination of switches using DC sources with a small voltage range to convert power and synthesize voltage. The most frequently used voltage sources which could be configured in one (single) and more (multiple) units are RER, batteries, and capacitors. The broad categorization of MLI on several DC sources used and their structure is given in Figure 3. In addition, a comprehensive survey of the literature yields various classifications of MLI based on different strategies as suggested by many researchers.

Nevertheless, this research article is an attempt to broadly classify all possible types of MLIs depending upon the structure of DC source (either single or multiple units) used. The multiple uses of capacitors can produce multiple voltage levels. Table 2 summarizes the significant advantages and disadvantages of various MLI configurations.

#### *3.1. Single DC Source*

This type of topology is extensively endorsed in the industrial field, considering its simple structure, high efficiency, and power rendering [88]. The different categories of MLIs using a single DC source are discussed below [89].

#### 3.1.1. Neutral Point Clamped Multilevel Inverter (NPC-MLI)

Nabae, Takashi, and Akagi in 1981 proposed the diode clamped multilevel inverter (DC-MLI), also termed NPC-MLI [56]. These inverters have been broadly adopted on account of their immense proficiency in high-power and medium-voltage operations with comparatively high efficiency. It is a three-level structure with two diodes that clamp the switching voltage to half the supply voltage magnitude. Further, it guarantees equal sharing of the supply voltage among the two halves of the switches being held at these points consisting of a neutral point between them. The middle voltage level is termed the neutral point. This topology employs multiple capacitor banks in series for providing multiple DC voltage levels, as illustrated in Figure 4.

**Figure 3.** Overall classification of MLI.

**Figure 4.** Topology of neutral point clamped multilevel inverter.

The major benefits of this topology are: (i) the capacity demand of the converter is minimized as all of the phases share a common DC bus; (ii) enhanced capability of reducing the THD; (iii) the capability of the capacitors to be pre-charged as a group; (iv) provides higher efficiency and (v) the number of switches, clamping diodes and capacitors can be enhanced to obtain higher voltage levels. However, this topology faces some demerits such as: (i) implementation cost can be increased as additional reactors are needed for mitigation of elevated voltage levels and THD of current as this topology uses fundamental frequency for switching; (ii) although voltage level can be increased by enhancing the number of capacitors and clamping diodes it increases the complexity of the overall configuration; (iii) due to deviation in the switching characteristics, the voltage at the neutral point fluctuates which creates difficulty in the static and dynamic sharing of the voltage across the switching units and (iv) due to imbalance in capacitor voltage and over-voltage issues, the actual application of this topology are confined to three-level only. NPC-MLI finds its application in the following ways: static VAR compensation (SVC), variable-speed motor drives, high voltage system interconnections, and be assimilated with high voltage AC/DC transmission system [90–95].

#### 3.1.2. Flying Capacitor Multilevel Inverter (FC-MLI)

In 1992, Meynard and Foch [60] and Lavieville et al. [61] proposed the FC-MLI topology to mitigate the issue of static and dynamic sharing of the voltage across semiconductor switches as built in the NPC-MLI topology. The main architecture of FC-MLI is identical to NPC-MLI. Nevertheless, here the clamping diodes are replaced by capacitors, as illustrated in Figure 5. This topology is termed FC. In FC, capacitors that replaced the diodes of the DC-MLI are autonomous (flying) as compared to the other capacitors present in the total configuration. The voltage on every capacitor varies from that of the adjacent capacitor. This MLI topology possesses numerous advantages as compared to NPC-MLI, such as: (i) improved stability of the FC is attained by the redundancy of switching within the phase; (ii) capability in controlling both the active and reactive power; (iii) it has transformerless working and (iv) more flexible in synthesizing voltage by using capacitors instead of clamping diodes.

**Figure 5.** Topology of flying capacitor multilevel inverter.

Although this topology marks the issues of the NPC, it also has some disadvantages such as: (i) the proper charging and discharging control of capacitors is restricted due to an increase in the voltage levels; (ii) the increment in the number of the capacitor leads to increased cost, reduced lifetime and system becomes bulky; (iii) increase in the number of levels leads to increase the number of capacitors thus limiting its operation to maximum 3–5 level; (iv) complexity in start-up and same level pre-charging of all the capacitors; (v) high switching losses due to operation at high frequency and (vi) large numbers of levels creates packaging issues. The major attractive applications of FC-MLI includes [39,60,94]: (i) static var generation; (ii) AC motor drives; (iii) active filter operations; (iv) switched converters; (v) sinusoidal current rectifier and (vi) converters with THDreducing capacities.

#### 3.1.3. Active Neutral Point Clamped Multilevel Inverter (ANPC-MLI)

Bruckner et al. [68,96] have proposed the ANPC-MLI topology. This inverter helps to overcome the insufficient and uneven losses which are shared between the outer and inner switches. It was possible by placing power switches rather than normal diodes [97]. Figure 6 demonstrates the nine-level ANPC inverter with the combination of NPC and FC-based MLI topologies [97]. In this configuration, the number of the two-level inverter can be found out by (n − 1)/2, where 'n' is the number of output levels of the inverter. So, four number of two-level inverters were cascaded to obtain a nine-level inverter. In Figure 6, switches 'Sw1' to 'Sw8' and capacitors 'C1' to 'C3' belong to the first part, whereas the switches 'Sw17' to 'Sw24' and capacitors 'C7' to 'C9' belong to the second part of the MLI. Switches 'Sw9' to 'Sw16' and capacitors 'C4' to 'C6' belong to part three, used for connecting the inverter to the load.

**Figure 6.** Topology of active neutral point clamped multilevel inverter.

#### 3.1.4. Modular Multilevel Converter (MMC)

The MMC was first proposed in 2001 by Lesnicar and Marquardt in a German patent [62], and later in 2002, it was employed for a wide-scale power range [98]. MMC offers numerous merits in comparison to other available topologies such as [99,100]: (1) large range of voltage operation by cascading cells; (2) independent PQ control; (3) negligible losses; (4) high modularity; (5) low switching frequency; (6) output almost sinusoidal so does not need AC filters; (7) mechanical structure is simple; (8) voltage and current quality generated is high and (9) high reliability, availability, and efficiency. Therefore, they are often preferred for medium to high voltage applications because of their high-quality output and modular structure.

Over recent years, MMC has been successfully operated as an efficient power converter in numerous power system applications such as HVDC system [101–104], FACTS devices [105–107], energy storage devices [108–110], electric vehicles [111,112], motor

drives [113–115], active power filters [116,117] and renewable energy [118–121]. Presently, the primary vital concerns of MMC include capacitor voltage balancing (CVB) and circulating current suppression (CCS). Authors in [122] have reported an efficient CVB method for MMC using the carrier-based phase shift pulse width modulation method for designing a flexible mission profile emulator for the test of MMC under various working conditions. In [123], a step up non-isolated DC-DC MMC having self-voltage balancing and soft-switching has been discussed. Researchers in [124] and [125] have proposed a sensorless switch clamp MMC for voltage balancing and inter-cluster voltage balancing control for MMC during unbalanced grid voltage. CVB control strategy for MMC has been reported in [126,127]. A novel voltage balancing control with dv/dt reduction for 10-kV SiC MOSFET-based medium voltage MMC has been proposed in [128]. Authors have also carried out hardware implementation based on the peak current mode switching cycle control for CVB of MMCs [129]. Numerous techniques have been designed and implemented for the voltage balancing of MMCs, as reported in the literature [130–134]. The CCS in MMC has been carried out efficiently through various techniques as proposed by several researchers [135–137]. In [138], authors have analyzed effective ways of CVB and CCS for a three-phase four-wire split capacitor DSTATCOM. Authors have applied various methods such as fuzzy logic controller [139,140], predictive control method [141], dead beat control [142], sliding mode approach [143], and frequency adaptive spatial repetitive [144] for suppressing the circulating current harmonics in an MMC. Many other methods have been studied and incorporated for efficient CCS of MMC [145–149].

The basic circuit of the three-phase MMC is illustrated in Figure 7, which consists of a DC voltage source, three phases (legs) with two arms per leg (upper and lower arm), each arm consisting of series connections of several (N) sub modules (SM) producing a multilevel voltage signal at its output terminal and a series inductor for smoothening and filtering the circuits. Different types of SM topologies are reported in the literature [99,100]. Recently, authors have proposed MMC basing on interleaved half-bridge submodules [150]. Some of the basic configurations are illustrated in Figure 8. Half-bridge SM, full-bridge SM, single clamped, and double clamped and shown in Figure 8A, Figure 8B, Figure 8C, and Figure 8D, respectively.

**Figure 7.** Topology of modular multilevel inverter.

**Figure 8.** Topologies of sub modules (**A**) half-bridge, (**B**) full-bridge, (**C**) single clamped, and (**D**) double clamped.

#### *3.2. Multiple DC Source*

Authors in [33,90,93] have proposed MLI topologies with multiple sources (DC) as the use of a single source (DC) is limited for achieving greater voltage levels. In this section, various topologies of MLI with multiple DC sources are discussed in detail.

#### 3.2.1. Basic Multiple DC Source Topology

Cascaded H-bridge Multilevel Inverter (CHB-MLI)

Baker and Bannister [52] proposed the first patent on this topology which was considered to be a viable substitute to previously described topologies as it requires a significantly fewer number of power devices. This topology was termed CHB-MLI, which constitutes the series connection of H-bridges with separate DC sources. Numerous series-connected H-bridge structures generate the multilevel stepped waveform. By cascading the general H-bridge cell, the resultant CHB-MLI can form an unlimited number of levels theoretically. This property of CHB-MLI allows modulation. The advancement of the technique for eminence follows the trade-off for high power medium voltage operations, which have now reached the level of megawatt by industries. It is an effective solution to voltage imbalance found in the NPC and FC configurations due to its modular structure. CHB generally comprises power conversion cells, each of which is supplied by an isolated DC source on the DC side, obtained from batteries, ultracapacitors, fuel cells, and series connected on the AC side [151]. A schematic diagram of the CHB topology has been shown in Figure 9.

**Figure 9.** Topology of cascaded H-bridge multilevel inverter.

The advantages of CHB-MLI topology are as follows: (i) easy modulation, control, protection, and maintenance during failure due to compatible structure; (ii) capable of handling higher voltages and absence of voltage imbalance; (iii) ability to eliminate common-mode voltages by proper selection of modulation scheme; (iv) generates almost sinusoidal output and hence almost requires no output filter; (v) less component requirement being equated to other topologies; (vi) no requirement of flying capacitors or clamping diodes and (vii) uniform distribution of load power amidst all switching devices [152]. However, despite several merits, this topology faces some serious drawbacks such as: (i) requirement of numerous separate DC sources and ii) need of many DC link voltage controllers. Various fields of application of this topology include RER interface, motor drives, electric vehicle drives, laminators, blowers, fans, conveyors, DC power source utilization, frequency link systems, and power factor compensators [39,56,153–155].

#### Hybridized Cascaded H-bridge Multilevel Inverter (HCHB-MLI)

HCHB-MLI was first introduced by Odeh and Nnadi [156], as illustrated in Figure 10. HCHB-MLI signifies that the inverter is employed with: (i) various semiconductor device technology; (ii) various amplitude and characteristics of DC sources; and (iii) combination of many modulation strategies [157]. Figure 10 depicts a nine-level HCHB-MLI, which consists of two DC sources. Two five-level hybrid inverters are interconnected for providing nine-level of voltages per cycle. This topology is quite identical to the earlier discussed CHB-MLI topology. However, the significant difference between HCHB and CHB topology are: (i) in HCHB, each H-bridge cell is added with an auxiliary switch for the harmonic profile improvement of output waveforms; (ii) the number of devices required in this HCHB topology is comparatively significantly less in comparison to the CHB topology for the same level of output voltage waveform [158] and (iii) with the operational and switching activities, HCHB topology possesses double RMS output voltage, voltage steps quantity and reduced number of DC sources. However, the major demerit is that it cannot be employed for high voltage applications.

**Figure 10.** Topology of hybridized cascaded H-bridge multilevel inverter.

3.2.2. New Reduced Switch Count Topology

Topologies with H-bridge broadly consist of asymmetric and symmetric types.

H-bridge Topologies

(i) Asymmetric H-bridge Topology

Asymmetric MLI is usually CHB-MLI type in which the value of the voltage of any one DC source varies dynamically [159,160]. The main merits include: (i) generation of output voltage waveform with minimum THDs [39,161,162]; (ii) requires reduced number of semiconductor devices in comparison to symmetric topology [163]; (iii) needs only 12 switching units to attain seven, nine, fifteen and twenty-one levels [164]; (iv) operates with reduced dimension and cost of the inverter [165] and (v) enhanced reliability due to operation with fewer semiconductor switches and capacitors [166]. Asymmetric topologies with H-bridge have been further classified into two types, and the details are highlighted below [167].

A. Cascaded H-bridge based Multiple Level DC Links Inverter

Gui Jia Su et al. [72] proposed this topology which comprises the CHB with multiple level DC links (MLDCL). Figure 11 represents an MLDCL inverter consisting of 2 input DC sources. The circuit comprises of 'n' number of half-bridge units in cascade, and each unit has one DC source with two switches connected in series. A stepped DC voltage waveform is produced with the help of these cascaded units, which are also known as level-generation parts. A full multilevel AC waveform is generated using the H-bridge by changing the polarity of the output voltage. MLDCL topology utilizes only fewer semiconductor switches to generate the same output voltage level [39]. Major applications of this configuration include: (i) permanent magnet (PM) motor drives with low range of power (<100 kW); (ii) metal oxide semiconductor field effect transistors (MOSFETs); (iii) insulated gate bipolar transistors (IGBTs) and (iv) solar and fuel cell integration [168,169].


**Table 2.** A

comprehensive

 summary of merits and demerits of various MLI

configurations.


**Table 2.** *Cont.*


**Table 2.** *Cont.*


**Table 2.** *Cont.*

#### B. Switched Series/Parallel Sources based Multilevel Inverter (SSPS-MLI)

Hinago and Koizumi [170] proposed the SSPS-MLI topology. It is comprised of two major units; the "level-generation" unit, where a staircase voltage waveform with positive polarity is generated, and the "polarity-generation" unit, where the staircase DC voltage waveform gets converted to AC voltage as depicted in Figure 12. This configuration possesses the primary merit of generating more output voltage levels using very few numbers of switches in contrast to other conventional MLI topologies. Therefore, SSPS-MLI can be applied in the areas of: (i) electric vehicle where a single unit of the battery can be composed of several series-connected battery cells [171]; (ii) vehicle drive system to meet voltage or power need by a possible combination of two or more sources either in series or in parallel and (iii) traction purposes by possible joining of multiple sources in various flexible configuration [168,172].

**Figure 11.** Topology of multiple level dc links inverter.

**Figure 12.** Topology of switched series/parallel sources based multilevel inverter.

(ii) Symmetric H-bridge Topology

This family of MLI usually consists of inverters where the magnitude of all the isolated supply DC sources to each of the H-bridge cells is identical. The symmetric H-bridge topology is further classified into different types. This section throws light on each of the Symmetric H-bridge topologies in specific.

A. T-type Multilevel Inverter

A novel T-type configuration with a five-level single phase inverter was first proposed by Gerardo Ceglia et al. [80–82]. The primary benefit of it is that the designed configuration reduces the use of more switches. A T-type inverter topology is depicted in Figure 13 below. Compared with other traditional topologies, T-type topology delivers an extraordinary improvement regarding the lower count of switches used and lower layout complexity. Further, almost 40–50% reduction in power switch count is achieved without diodes or capacitors [173]. This configuration has an H-bridge and an auxiliary bidirectional switch for controlling the connection of the supply from the DC sources to generate the staircase output voltage. However, this topology fails to render switching states to have all essential levels, as in the asymmetric H-bridge topologies [80].

B. Nilkar Multilevel Inverter (N-MLI)

**Figure 13.** Topology of T-type symmetric H-bridge topology.

Nilkar et al. proposed the Nilkar inverter topology [174]. The basic module of N-MLI is comprised of two identical DC voltage sources with four semiconductors switching units for generating a staircase DC voltage waveform with positive polarity, which is further connected to an H-bridge consisting of 4 switching devices as demonstrated in Figure 14. The H-bridge helps in alternating the polarity of voltage for producing a complete sinusoidal alternating output signal. This topology renders many advantages, such as: (i) operates with significantly less number of switches; (ii) THD is effectively lessened in comparison to other available classical MLI topologies, and (iii) batteries and capacitors can be used as the DC voltage source. This topology can be used for various RER's (such as solar and fuel cell) interface and medium to high voltage applications in industries.

#### C. Crisscross Cascaded Multilevel Inverter (CCHB-MLI)

In [175], Khosroshahi proposed a CCHB-MLI topology consisting of the basic units in cascade. Figure 15 shows a CCHB inverter configuration comprising of two sources of DC voltage and a combination of one-way and two-way switches. It has two units; the first is the level generation unit, and the second is the polarity generation unit. The levelgeneration unit has two power switches, namely Sw2 and Sw3, which are unidirectional. The other switches Sw1 and Sw4, are bidirectional conducting and blocking switches, respectively. The four power switches P1, P2, P3, and P4 constitute the polarity-generation part. The benefits of this topology are: (i) usage of the reduced number of semiconductor switches; (ii) limited use of isolated DC voltage sources as compared to other classical topologies; and (iii) low cost and volume as compared to CHB-MLI [51].

**Figure 14.** Topology of Nilkar multilevel inverter.

#### D. Reversing Voltage Multilevel Inverter (RV-MLI)

Reversing voltage MLI topology was first suggested by Najafi et al. in [78,176]. In this topology, the sinusoidal output voltage is produced in both level generation and polarity generation stages. The positive and negative polarity of voltages is generated in the level generation and polarity generation stage, respectively, as shown in Figure 16. By duplicating the centre stage operation with any number of levels can be possible, so application to three phases can also be extended. It has flexibility in the switching sequence and needs very few components for its work. Therefore, it can be useful in the areas of applications such as FACTS and HVDC. However, operation using different DC sources is not possible in this topology, as it is practically impossible to combine additive and subtractive DC sources.

**Figure 15.** Topology of crisscross cascaded multilevel inverter.

E. Series Connected Switched Sources Multilevel Inverter (SCSS-MLI)

In this topology, the basic concept lies in the series connection of sources by the switches [76,77]. Figure 17 shows SCSS based MLI configuration. Here the poles of the voltage sources with lower magnitude are being associated with semiconductors. They are also in contact with the voltage poles with a higher magnitude of the upstream source. The link can synthesize a DC voltage with multiple levels, which take into account both the polarities with the help of the H-bridge. This structure also helps in reducing the number of switches for the symmetrical structure of the inverter. Nevertheless, the main shortcomings of this topology are: (i) power semiconductor used must be of the same rating; (ii) load sharing is impossible as input stage requires various configurations and (iii) high rated switches need to be switched with the minimum possible frequency.

**Figure 16.** Topology of reversing voltage multilevel inverter.

**Figure 17.** Topology of series connected switched sources multilevel inverter.

F. Multilevel Module Based Multilevel Inverter (MLM-MLI)

Babaei in [79] suggested the MLM-MLI topology, which comprises the level generation part and the polarity generation part. Figure 18 illustrates an MLM-MLI with four DC input sources. With the increase in output voltage level, this configuration can operate with the reduced number of DC voltage sources, semiconductor switches, transistors, and power diodes. The major demerit is that it fails for application in an asymmetric configuration. However, it can be used for high power quality applications that use an ample number of DC voltage sources [79].

G. Two Switch Enabled Level Generation Based Multilevel Inverter (2SELG-MLI)

Babaei in [83] discovered the level-generation based MLI Topology with two switches and seven input levels, as shown in Figure 19. This topology has two different stages, a levelgeneration stage and a polarity-generation stage. The name 'Two Switch' justifies that this configuration needs only two number of conducting switches in the level generation stage for synthesizing any level of voltage. However, this inverter fails to work in asymmetric topology. The major disadvantage is that as the level generation stage fails to realize the zero level of its own, the operation with a fundamental switching frequency becomes impossible [168].

**Figure 18.** Topology of multilevel module based multilevel inverter.

H. H-bridge and two-level Power Modules Based Multilevel Inverter (HBTPM-MLI)

In [177], Suroso and Noguchi presented HBTPM-MLI. An HBTPM based inverter configuration has been illustrated in Figure 20, which consists of 4 input DC sources (VDC1 to VDC4). Semiconductor switches are used to interconnect the terminals with a source of low potential. Further, the proceeding source is attached to a high potential terminal using power switches. Switches P1 to P4 are for the polarity generation stage, and switches 'Sw1' to 'Sw6' form the level generation unit. The structure is simple, but it fails to synthesize

various levels of the voltage waveform at the bus end. However, this topology fails to operate in asymmetric configuration for further reducing the count of the switch.

**Figure 19.** Topology of two switch enabled level generation based multilevel inverter.

Topologies without H-bridge

Topologies without H-bridge can be either asymmetric or symmetric type. However, mostly they are of a symmetric type.

(i) Asymmetric Topology without H-bridge

This category of MLI consists of numerous DC voltage sources, among which at least one differs dynamically. They do not consist of H-bridge cells or units.

(ii) Symmetric Topology without H-bridge

In this topology, the magnitude of all the isolated supply DC sources are identical, but they do not form an H-bridge configuration. In this section, different types of symmetric topology without H-bridge structure have been reviewed.

A. Cross Connected Sources Based Multilevel Inverter (CCS-MLI)

Authors in [69] have introduced the CCS-MLI topology comprising input DC sources isolated for every cell, as depicted in Figure 21. In this topology, a switch connects the two different terminals of two different sources and vice-versa. It requires a minimum number of switches for its operation and is usually active where isolated DC sources are present [51].

B. Packed U Cell Multilevel Inverter (PUC-MLI)

A novel MLI topology was offered by Youssef Ounejjar et al. and was named "PUC" [178–182]. The circuit of PUC-MLI is represented in Figure 22, which constitutes ten power semiconductor switches and four DC sources. Every individual U-cell has a single DC input level and two switching units [168]. The main advantage of this technology is that the maximum voltage-producing switch can be operated at the minimum frequency. Further, it allows easy change in the voltage level number, reduces stress on the switch, and enhances the overall converter operation.

**Figure 20.** Topology of H-bridge and two-level power modules-based multilevel inverter.

**Figure 21.** Topology of cross connected sources based multilevel inverter.

C. Cascaded Bipolar Switched Cells Multilevel Inverter (CBSC-MLI)

Babaei et al. in [71] have introduced this topology, as shown in Figure 23. The circuit comprises 4 DC sources and 10 bidirectional power semiconductor switches capable of generating voltage levels in both positive and negative polarities. Every bidirectional switch needs two IGBTs and is equal to the number of gate drive circuits. This concept helps in decreasing the operational cost and overall complexity of the circuit. The major shortcoming is that this topology is that it cannot work with an asymmetric configuration.

**Figure 22.** Topology of packed U-cell multilevel inverter.

#### D. Mokhberdoran Multilevel Inverter (M-MLI)

This topology is named after Mokhberdoran as in [183]. The basic circuit of M-MLI is illustrated in Figure 24, which comprises of two symmetric DC voltage sources, six switches, and eight diodes. Here to obtain a higher level of voltage, the basic units are cascaded in series [51]. The topology is such designed that it utilises a significantly fewer number of switching devices. The entire operation is divided into two parts depending upon frequency, such as low and high. This enhances the efficacy of the configuration. The structure is modular, and the cost of this unit is also minimum. Mokhberdoran technology usually finds its application in high power operations [183].

**Figure 23.** Topology of cascaded bipolar switched cells multilevel inverter.

E. Babaei Multilevel Inverter (B-MLI)

Figure 25 illustrates the B-MLI topology as proposed in [70,184]. The key elements are composed of six unidirectional switches and two symmetrical DC voltage sources. For increasing the output voltage level, the circuit developed can be reproduced by connecting in series [51].

**Figure 24.** Topology of Mokhberdoran multilevel inverter.

**Figure 25.** Topology of Babaei multilevel inverter.

#### **4. MLI Control and Modulation Schemes**

Modulation techniques play a principal role in governing the overall efficiency parameters such as harmonic reduction and switching losses used to control the inverter and turn the entire system [185]. They also have the responsibility to synthesize reference control signals to maintain all voltage sources balanced. The major purpose of modulation is to generate a staircase DC voltage signal, nearest a reference signal that is generally sinusoidal in a steady state [186]. The modulation process usually involves a variety of single or multiple attributes of a carrier signal waveform with a modulating waveform. Modulation is also referred to as a strategy to control the switching action by changing the characteristics of a particular signal (carrier signal) using another signal (reference signal). Every family of MLI has a selected appropriate modulation scheme for optimizing the circuit working and achieving the target criteria. Following are the major important factors basing on which a particular modulation technique is chosen for a particular MLI family: (i) total generated harmonics; (ii) level of distortion; (iii) frequency of switching; (iv) amount of losses and (v) response speed. The MLI modulation methods have the following needs to be fulfilled before operation: (i) quality of voltage should be high; (ii) should have modular structure; (iii) switching of multiple voltage levels simultaneously is not permitted; (iv) power devices should operate with minimum frequency; (v) load sharing should be uniform among the power modules; (vi) algorithm used for control should be easy and simple and (vii) cost of implementation must be minimum [51].

The modulation index also has a vital role in all control schemes. Modulation also depends upon modulation ratio (either over or under modulation), and the THD varies accordingly. Multiple techniques are proposed by authors in the literature depending upon the switching frequency, either fundamental or high frequency [187,188]. However, low losses are found when switched at fundamental or low frequency. A thorough survey of various modulation methods is highlighted in this section below. Figure 26 illustrates the various control and modulation schemes for MLI. Table 3 lists the merits and demerits of different modulation schemes discussed in this review article.

**Figure 26.** Categorization of modulation schemes for multilevel inverter.

#### *4.1. Fundamental Switching Frequency Pulse Width Modulation (FSF-PWM) Techniques*

These techniques generate a staircase waveform performing single or multiple commutations of the power electronic switches [189,190]. Here, an increased number of levels is obtained by adding extra units without creating any complexity in the generation of the switching signals. Moreover, due to switching at low frequency, the losses incurred are very less. Various FSF-PWM methods have been discussed below.

#### 4.1.1. Sine Property

It is a modern method for calculating the firing angle that is to be provided to the switching units [191–193]. Calculation of firing angle is easy on adopting this technique. The firing angle is generally obtained in degrees and has the provision of appropriate conversion to any other unit of time such as 'seconds' for the easy performance of simulations.

#### 4.1.2. Selective Harmonic Elimination

Researchers in 1973 suggested a voltage control and harmonic elimination theory known as SHE. This technique is utilized for eliminating the most dominant selected lower order harmonics [194–197]. In SHE, there is a possibility of lowering the THD and the size of the output filter. As the switching angles are pre-determined off-line, it is assumed to be an open-loop modulation method [198,199]. Authors have also reported that many Fourier equations are utilized for calculating the firing angle for the switching purpose [195]. Selection of correct values of the firing angle for the Fourier series equation, the odd harmonics can be limited for any level of MLI. A microcontroller device is then used to supply these firing angles to the switches. Thus, it does not require a closed-loop controller for its implementation.

The vital functions of the SHE are: (i) maintaining the fundamental component of the waveform; (ii) harmonic reduction individually; (iii) decrease in THD, and (iv) lower switching losses. However, a major drawback of the SHE technique is that it requires the design of massive passive filters to limit the lower-order harmonics [196]. To counteract the above-cited issue of the SHE method, a novel technique known as selective harmonic mitigation (SHM) has been proposed in the literature by researchers [200]. In the SHM method, switching angles are calculated to reduce the individual harmonic distortion without the grid code limits. SHM is also an open-loop control technique and an offline procedure for calculating the switching angles and cost function that can be minimized using a search algorithm [201]. Numerous solutions can be utilized to solve the non-linear equation of MLI, such as: (i) iterative numerical methods [202]; (ii) artificial intelligencebased methods [203], and (iii) resultant theory [204]. A new technique for the SHE method named Groebner Bases Theory Method has been developed [205,206]. This method has been carried out with a three-level inverter. This method has the advantage of finding the most accurate switching angles as no initial value for iteration is required.

Recently numerous evolutionary algorithms based on SHE techniques for MLI are reported in the literature [207–218]. Authors in [185,207] have implemented a genetic algorithm (GA) to minimize low-count switch MLI distortions. In [208,209], the output voltage regulation and improvement of the harmonic profile are carried out by particle swarm optimization (PSO) technique. Additionally, PSO is used in [210,211] for the control of THD. The ant colony system (ACS) algorithm was incorporated in [212] for removing the harmonic content of a 3-phase inverter with a unipolar output voltage waveform. Researchers have used bee algorithm (BA) for ninety-seven-level CHB-MLI [213]. THD reduction is brought about by bacterial foraging algorithm (BFA) in CHB-MLI. In [215], a clonal search algorithm (CSA) has been reported for a three-phase inverter. The harmonics in the line voltage of an inductor motor are eliminated using the evolutionary programming algorithm (EPA) as in [216]. Authors in [217,218] have suggested using the differential evolution (DE) algorithm for a 3-phase inverter to enhance the level of output voltage, improve the harmonic profile for rapid convergence and better efficiency.

#### 4.1.3. Space Vector/Nearest Vector Control (SVC/NVC)

The space vector control (SVC) is also known as nearest vector control (NVC). It is reported as an alternative to SHE and can operate at a low switching frequency. Like SHE, it does not generate the average value of the required load voltage for every switching time interval. The major function of the SVC technique is to select a vector closest to the reference vector for minimizing the distance between them or the space error [187]. However, in SVC, the lower distortions produced due to switching at low frequency are usually not eliminated like in the SHE technique. The NVC technique is very simple and applicable for higher output voltage levels as the higher density of vectors can generate only small errors about the reference vector. Authors in [219] have discussed the principle of an eleven-level inverter with SVC control. Recently the SVC finds its implementation in numerous MLIs, including both classical as well as newly proposed reduced switch count technology. In [220], a five-level MLI configuration with quasi Z-source has been designed in which the NVC has been utilized as the control scheme.

#### 4.1.4. Staircase with a Fixed Time Step Control Scheme

Staircase with a fixed time step control scheme generates the output voltage signal is generated from uniform time steps within each level. The main merit is that the structure is simple and hence makes the inverter control very easy. The major drawback is that the output voltage profile consists of lower order harmonics and thus increases the THD. The waveform is divided into equal time intervals similar to the number of levels to find equal switching instants. In this control scheme, the inverter input voltage can be controlled, but the output voltage is not controllable.

#### *4.2. High Switching Frequency Pulse Width Modulation (HSF-PWM) Techniques*

The HSF-PWM techniques are usually employed for high switching frequency applications in the order of kHz and consist of many commutations per cycle [39]. A detailed classification of each type of this technique has been deliberated in this section.

#### 4.2.1. Multi-Carrier Pulse Width Modulation (MC-PWM) Techniques

In this technique, only a single modulating sinusoidal signal is produced using multiple triangular carriers. Usually, the number of employed carriers is '(n-1)', where 'n' is the level of the inverter [39]. The MC-PWM techniques are further categorized into two types: (i) carrier disposition PWM and (ii) phase shifted PWM. The basic diagrams containing modulating and carrier signals for carrier disposition and phase shifted PWM methods have been reported by numerous authors in the literature [221,222].

#### Carrier Disposition Pulse Width Modulation (CD-PWM) Techniques

In this scheme, the reference waveform is produced by comparing the amplitude of the carrier waveform to a reference waveform amplitude. It is further classified into three various types [223]. The details of each are highlighted in this section.

#### (i) Phase Disposition (PD) Method

The important feature of the phase voltage spectrum of a PD Method is the initial distortion of the carrier. Therefore, this method generates a very good performance of the line voltage. Generally, all the carrier signals have equal amplitude and frequency and lie in one phase. PD method is usually used for asymmetric MLI, and with the increase in the number of voltage levels, the harmonic contents are decreased [224].

#### (ii) Phase Opposition Disposition (POD) Method

In this modulation scheme, the in-phase components are the positive carrier signals, whereas the carrier signals with negative polarity are 180◦ out of phase.

#### (iii) Alternative Phase Opposition Disposition (APOD) Method

This method involves all the carriers to be in phase opposition by 180◦ to the nearest carriers [224].

#### Phase-Shifted Pulse Width Modulation (PS-PWM) Technique

In the PS-PWM method, the multiple carriers are phase-shifted accordingly. It requires '(m−1)' triangular carriers for an 'm'-level inverter. This triangular carrier possesses identical frequency and amplitude; however, adjacent carriers have a definite phase shift between them [225]. The gate signals of the MLI switches are produced with the help of the on/off state of some logic circuit switches [224].

#### 4.2.2. Hybrid Pulse Width Modulation (H-PWM) Technique

The low-frequency and high-frequency modulation techniques are combined to form H-PWM. This control scheme is applied for CHB-MLI having a varying magnitude of DC sources. This method majorly aims to lower the inverter's losses by reducing the switching frequency of the higher power units. The lower power unit is controlled by using the unipolar pulse width modulation method [224].


#### 4.2.3. High and Low Carrier Cells and Alternative Phase Opposition Pulse Width Modulation (HLCCAPO-PWM) Technique

HLCCAPO-PWM is a modification of the PD method. Here two different carrier groups are introduced by dividing them as per each carrier period. The method renders the use of higher modulation frequency by reducing the switching losses effectively. Further, this technique also reduces the dissipation of energy as the energy shifts from the lower to higher-order harmonics. It mostly finds its application in hybrid clamped MLI.

#### 4.2.4. Space Vector Pulse Width Modulation (SV-PWM) Technique

The SV-PWM technique consists of many vector states that are utilized for modulation of the reference waveform. This method is usually based on the digital modulation method for generating PWM voltages under a known voltage [226]. Here the values of the control algorithm are directly taken from the control system [227]. However, this scheme fails to operate with a large number of levels as identifying sectors and selecting switching sequences are very crucial. Generally, for an 'n'-level inverter, '(n − 1)2' vector combination per sector, six sectors, and 'n3' switching sequences are required [228]. Reduction in the commonmode voltage, losses due to switching, and the control of the DC link voltages can be brought about by appropriate selection of modulation vector and switching combinations. Generation of a particular voltage level takes place by redundancy switching states.

Various authors have reported in the literature the application of this technique in numerous areas. In [229], a space vector hysteresis current control (SVHCC) scheme has been implemented. The SVHCC has been used with a recent MLI configuration, as suggested in [230]. The use of SVC is also projected in [231] for a T-type MLI system that implements a fault-tolerant control scheme. Amit Kumar Gupta et al. in [232] addressed a simple SV-PWM method for MLI operation in the over-modulation range. In [233], Mohan M. Renge suggested a technique for reducing common-mode voltage at the output of MLI that used the 3-D SV-PWM technique.

Better values of fundamental voltage ratio and harmonic elimination are achieved in this technique as compared to the sinusoidal PWM method. In addition, the maximum peak value of the output voltage is almost 15% more in SV-PWM than in the triangular carrier-based modulation method. Although the requirement of a look up table and identification of sectors for determining the switching intervals for all sectors make the SV-PWM technique complex, the microprocessor and digital signal processing units serve as a better solution for preparing the preparation of the process the algorithm.

#### **5. Applications of MLI Topologies and Control Schemes**

This section throws light on the detailed application of various MLI topologies and control schemes in different fields of power system networks, such as (i) integration of RERs to grid; (ii) FACTS devices, and (iii) electric motor drives. Table 4 provides a brief idea of the application of various MLI topologies in numerous power system domains.


**Table 4.** Application of various MLI topologies in numerous power system domains.


**Table 4.** *Cont.*

#### *5.1. Grid Integration of RERs*

The control schemes for RERs integration are categorized as (1) time and (2) frequency domain schemes. Fast Fourier Transformation is usually not employed because of more computational time and delay in computing reference signals [234]. On the other hand, p-q theory and d-q theory based on time-domain control algorithms are highly adopted due to lesser computation time in deriving the instantaneous compensating current or voltage signals. The DC quantities are assumed to be the fundamental components in the d-q algorithm. Furthermore, authors in [80] have studied the sensorless control of voltage waveform in packed U-cell topology to reduce control complexity and redundancy switching state. This operation keeps the capacitor voltage constant at half the magnitude of the DC source. Figure 27 depicts the controller for adjusting the amplitude and the phase shift of the current injected from the inverter to the grid.

**Figure 27.** Block diagram of a single phase grid connected packed U-cell based MLI.

In [235–237], researchers have addressed the use of a solar-based MLI for enhancement in the waveform quality and reduction in issues on power quality. For a three-level NPC-MLI, instantaneous power theory control is studied for generating the perfect reference signal. Here, two control loops are defined, one for controlling the DC bus voltage and the other for controlling the current. Source active power and load reactive power are computed using the fuzzy logic controller (FLC), and in the α-β reference frame, the p-q theory was used to find the reference current [238]. Authors in [239] have proposed a digital proportional integral (PI) Controller to inject the current from the photovoltaic source to the utility grid to achieve maximum dynamic operation with minimum harmonics. Figure 28 describes the block diagram of the control part of the above study, which comprises maximum power point tracking (MPPT) control and inverter control.

**Figure 28.** Block diagram of grid tied PV system with digital proportional integral control and fuzzy logic control.

The authors have introduced the dual-loop control method for a three-level inverter, as demonstrated in Figure 29. Here, two loops are present, the outside loop controlling the DC bus voltage and the current being controlled by the inner loop [240]. In NPC-MLI, the predictive control method is utilized to balance the DC link voltage. As suggested by authors in [241], a dual loop d-q controller is used to control the active and reactive power distribution. Different topologies of MLI in various combinations are interfaced with RERs for grid-tied applications [242–248]. In the recent past, the MLI topologies are also applied for application in the areas of marine [245] and microgrid [246,249].

**Figure 29.** Block diagram of the dual loop control method for a three-level inverter.

#### *5.2. FACTS Device*

STATCOM is considered to be a vital controller among all other types of available FACTS devices. The most appropriate topology for STATCOMs operation is the CHB-MLI for direct connection to medium voltage networks [250]. It does not need injecting active power for a normal range of operation [251]. In [17,252], authors have reported that CHB-MLI can be placed in series to achieve the operational voltage without using a transformer. A reactive current reference control scheme is proposed to enhance the transient operation of STATCOM, as depicted in Figure 30. In Figure 30, the phase locked loop (PLL) block is utilized to determine the reference phase angle of the grid voltage. The STATCOM output voltage and current are transformed into d-q reference frame vectors by adopting Park's Transformation. The feedback operation is preferred by the controller and produces the switching pulses with a proper modulation index.

**Figure 30.** Block diagram for control technique for STATCOM application.

Researchers have suggested a novel hybrid control method for STATCOM application for delta CHB-MLI subjected to an unbalanced condition [253]. A current control method is proposed for every phase individually to control every link's active and reactive power independently. The hybrid control approach consists of four different parts as follows: (i) PLL; (ii) active current reference; (iii) reactive current reference; and (iv) instantaneous current tracking. The PLL determines the phase angle of the system. However, the compensation model is used to calculate the amplitude of the voltage, which lags the phase of reactive current by 90◦. The overall value of phase current can be obtained by summing up the active and reactive current reference [254].

DVR plays a vital role in eliminating voltage-related problems like sudden rise or fall of voltage, spikes, swell, etc. It injects a voltage to prevent any disturbance in the load side voltage and is connected in series with the source side voltage [255]. The use of MLI in DVR enhances the capability of voltage injection to the maximum that can be applied for medium voltage application without using a transformer [256]. Here, the grid voltage and reference voltage comparison yield the reference value for the DVR output voltage (voltage sag value). PI controller is utilized to regulate the voltage level of the load and output voltage of the boost converter having a feedback control. The reference signal of MLI can be calculated by dividing the control output by the DC link voltage. The transformation ratio of the boost converter can be computed by its duty cycle. A crucial issue in DVR is the transformer's magnetic saturation, which causes the production of a large inrush current. Authors in [257] have suggested a novel modulation scheme called direct magnetizing flux linkage control for preventing the transformer from getting saturated, as illustrated in Figure 31. The overall modulation approach is divided into three loops depending upon their functions.

**Figure 31.** Block diagram for direct flux linkage control technique in DVR.

Loop 1 is called the flux linkage loop for tracking the flux linkage command. For attenuating the DC flux, linkage loop two, known as the integral feedback loop, is present. Loop 3 is utilized for tracking the compensation voltage command. To limit the linkage of flux, a flux linkage limiter is added between loop two and loop 3. Researchers in [258,259] have discussed the importance of MLI for unified power quality controller (UPQC) operations. A CHB-MLI is applied for DVR operation in [260].

#### *5.3. Motor Drives*

The basic necessity for an extraordinary function of an electric motor drive unit is its accurate torque control. A deep insight into the present literature reveals that control of field and torque for an induction machine serve as the two most remarkable control schemes [261]. In [262], authors have stated that direct control of torque can be directly switched on to an inverter without needing the regulation of stator current. However, the torque and flux generating units are separately controlled for field control. In [263], a recent control scheme is proposed for IM by CHB-MLI prone to a faulted condition. The block diagram of rotor flux linkage-oriented control as used in [263] is demonstrated in Figure 32. In [264–266], artificial neural network control [267] is used in IM to improve performance parameters. In addition to that, a reduced switch count MLI topology was executed with IM control for enhancing the quality of power, thereby lowering the THD of the output voltage.

**Figure 32.** Block diagram for rotor flux linkage oriented control method of motor drive system.

#### **6. Future Work**

MLIs undoubtedly have been the state of art and technology for power conversion from DC to AC, electrical energy employment, and a wide range of power applications in the present era. However, some of the major shortcomings in the implementation of MLI technology can be listed: (i) cost of manufacturing enhances as the number of switching devices used is more and (ii) addition of power electronic units may lead to the incorporation of more gate driving circuits, voltage and frequency control methods and complicated switching techniques making the control unit more complicated.

In order to cope up with the above issues, researchers are opting out ways for a tradeoff among the increased levels and complications in the design and working. Intending to assist the hassle-free integration of MLI technology in the present era, this comprehensive review has suggested some vital points that can be adopted in the future for further possible enhanced application of MLI technology in the various field of power systems.


#### **7. Conclusions**

The upgradation and advancement of different industries and academic research globally have led to an increased demand for high energy-based efficient converters. The MLIs have attained tremendous demand due to their inherent merits and play a significant role in DC/AC conversion operations for both high/medium voltage and high power applications. In this regard, this review article attempts to critically survey the evolution of MLIs, which would serve as a prominent guideline for the researchers working in this area. This comprehensive paper throws light on the traditional MLI topologies, new reduced switch count topologies, various control approaches, applications of MLI to renewable energy interface, FACTS devices, and motor drives in detail. A thorough review of the literature reveals that the recently developed reduced switch count MLI topologies possesses many merits over the classical techniques in terms of better clarity of output waveform, low modularity, reduced number of switches, occupies minimum space, ease of control, and cost effectiveness.

Further, for easy analysis, a precise comparison among all the categories of MLI about advantages and shortcomings has been tabulated. This research article also projects a thorough idea about all conventional and newly adopted modulation techniques for different MLI topologies. This review also serves as a major objective to understand the vital role played by MLI in the areas of application for renewable energy, FACTS devices, and electric motor drives. The article's primary focus is the suggested key points to be incorporated in future research work to integrate the MLI technology more efficiently. The article is promising for obtaining maximum useful knowledge to the academicians, pursuing research in MLI field, in the fact of the suitable configuration selection for definite operation, proper schemes of switching and control, parameter selection and manifests real-time application to other sectors of the power system.

**Author Contributions:** Conceptualization, S.C and T.D; methodology, S.C.; validation, M.B., S.K. and F.J.; formal analysis, S.C and F.Z; investigation, S.C and M.B.; resources, S.K. and F.J.; writing original draft preparation, S.C.; writing—review and editing, S.C, and T.D.; supervision, F.J.; All authors have read and agreed to the published version of the manuscript.

**Funding:** This research received no external funding.

**Institutional Review Board Statement:** NA.

**Informed Consent Statement:** NA.

**Data Availability Statement:** Authors may provide data on due request.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


### *Article* **An Integrated Device of a Lithium-Ion Battery Combined with Silicon Solar Cells**

**Hyeonsu Lim 1, Dan Na 1, Cheul-Ro Lee 1, Hyung-Kee Seo 2, O-Hyeon Kwon <sup>3</sup> , Jae-Kwang Kim 3,\* and Inseok Seo 1,\***


**Abstract:** This study reports an integrated device of a lithium-ion battery (LIB) connected with Si solar cells. A Li(Ni0.65Co0.15Mn0.20)O2 (NCM) cathode and a graphite (G) anode were used to fabricate the lithium-ion battery (LIB). The surface and shape morphologies of NCM and graphite powder were characterized by field emission scanning electron microscopy (FE-SEM). The structural properties of NCM and graphite powder were determined by X-ray diffraction (XRD) analysis. XRD patterns of powders were well matched with those of JCPDS data. To investigate the electrochemical characteristics of NCM and graphite, cycling tests were performed after assembling the NCM-Li, the G-Li half-cell, and the NCM-G full-cell. The discharge capacity of the NCM cathode at 0.1C was 189.82 mAh/g<sup>−</sup>1. The NCM-graphite full-cell showed 98.25% cycle retention at 1C after 50 cycles. To obtain enough charging voltage for the LIB connected with solar cells in an integrated device, eight single Si solar cells were connected in a series. The short-circuit photocurrent density for Si solar cells was 4.124 mA/cm2. The fill factor and the open circuit voltage were 0.78 and 4.5 V, respectively. These Si solar cells showed a power conversion efficiency of 14.45%. The power conversion andstorage efficiency of the integrated device of the NCM battery and Si solar cells was 7.74%. Charging of the integrated device could be as effective as charging with a battery cycler.

**Keywords:** Li(NixCoyMnz)O2; graphite; lithium-ion battery; silicon solar cell; integrated device

#### **1. Introduction**

As the industry develops and the population grows, the world's energy demand has been increasing every year. Fossil fuels supply most of the global energy needs. In recent years, problems of depletion of fossil fuels and environmental pollution such as SOx and NOx emission problems caused by wastes of fossil fuels have emerged around the world [1]. To solve these problems, interest in renewable energy has increased. Among renewable energy sources, sunlight is the most abundant one. It is more widely used than other renewable energies such as geothermal, wind, and tidal power [2]. However, sunlight is highly dependent on weather conditions. In addition, it cannot be used at night. To use sunlight effectively, it is necessary to store solar energy in a battery or a grid [3,4].

Many research studies have reported that a converter is necessary to charge from solar energy to a battery system. However, the system that uses a converter could be more complex and expensive than a direct connection between a solar cell and a battery system [5–9]. In addition, it can be less efficient than direct charging a battery with solar energy [10]. Therefore, a direct DC current storing is in the spotlight as a promising technology using an integrated method [11].

**Citation:** Lim, H.; Na, D.; Lee, C.-R.; Seo, H.-K.; Kwon, O.-H.; Kim, J.-K.; Seo, I. An Integrated Device of a Lithium-Ion Battery Combined with Silicon Solar Cells. *Energies* **2021**, *14*, 6010. https://doi.org/10.3390/ en14196010

Academic Editor: Pablo García Triviño

Received: 19 August 2021 Accepted: 18 September 2021 Published: 22 September 2021

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

Lithium-ion batteries (LIBs) have been applied to portable devices and electric vehicles (EV). Conventionally, LIBs are manufactured using lithium metal oxide cathode electrode materials such as LiCoO2(LCO), LiFePO4 (LFP), Li(NixCoyAlz)O2 (NCA), and Li(NixCoyMnz)O2 (NCM) with anode electrode materials [12,13].

Among various cathode materials, LFP has the advantages of a low price and high safety. Therefore, LFP is generally widely used in energy storage systems (ESSs). However, LFP has the disadvantages of low electronic conductivity and capacity [14,15]. NCA has a high energy density and high power. Thus, it has a higher capacity than LFP. However, NCA has a disadvantage in that its capacity retention rate is low, and its performance is degraded when stored at high temperatures [16]. Although NCM has similar properties to NCA, NCM has a higher cycle performance and C rates than those of NCA [17].

In this study, an integrated device of LIB connected Si solar cells was developed. The shape and structures of the powder of the NCM622 cathode and the graphite anode material were evaluated by field-emission scanning electron microscopy (FE-SEM) and X-ray diffraction (XRD) analysis, respectively. Electrochemical characteristics were evaluated after assembling NCM, the graphite half-cell, and the NCM-G full-cell. To obtain enough charging voltage for the battery, eight single Si solar cells in a series were connected. Electrical properties such as the fill factor (FF), the short circuit photocurrent density (ISC), and the open circuit voltage (VOC) were analyzed with a solar simulator. To develop an integrated device, Si solar cells and NCM-graphite LIB were combined. Photo-charging from solar cells to the NCM battery and galvanostatic charging from a cycler to the NCM battery were compared.

#### **2. Materials and Methods**

#### *2.1. Preparation of LIB and Solar Cell*

A cathode electrode slurry was prepared by adding NCM powder, polyvinylidene difluoride (PVDF), and carbon black (super P) to N-Methyl-2-pyrrolidone (NMP) solvent at a weight percent ratio of 8:1:1. The anode electrode slurry was made using graphite powder in the same way. Cathode and anode slurries were coated on Al foil and Cu foil, respectively. The coated slurry was dried and pressed to make a sheet electrode. The half-cell and the full-cell were assembled in a glove box. As an electrolyte, 1.2 M LiPF6 in a 1:1 (*v/v*, %) solution of ethylene carbonate (EC) and dimethyl carbonate (DMC) was used. The half-cell was in the form of a CR 2032 coin cell. The full-cell was assembled in the form of a pouch. The pouch-type cell was 4.5 cm × 4.5 cm in size. Al and Ni were used as anode and cathode lead tabs. To obtain enough charging voltage from Si solar cells for LIB charging, a polycrystalline Si solar cell with eight single Si solar cells in a series was purchased from SAVE SOLAR Co. Ltd.

#### *2.2. Characterizations*

Large and small particles of NCM622 precursor were prepared using a co-precipitation method. First, large and small particles of NCM cathode were mixed at a 7:3 ratio. Graphite powder was purchased from Sigma Aldrich Co. Ltd. Surface and shape morphologies of NCM as a cathode and graphite as an anode powder were characterized by FE-SEM (model SU-70, Hitachi High-Tech Corporation, Fukuoka, Japan). The acceleration voltage for the FE-SEM measurement was 10 kV. Structures of NCM and graphite powder were analyzed with an XRD (MAX-2500, RIGAKU in Japan) with Cu-kα radiation. XRD patterns of the powder were obtained in a 2θ range of 10–80◦ with a scan rate of 2.0◦/min and a step size of 0.05◦. Diffraction intensity data for a Rietveld refinement analysis were collected in a step-scan mode with a scanning step of 0.02◦ and a sampling time of 2 s. Rietveld refinement was performed using a FullProf program to obtain the crystal structure parameters of NCM622. Electrochemical characteristics of NCM and the graphite halfcell and the NCM-graphite full-cell were analyzed using a battery cycler (WBCS3000S, WONATECH Co., Ltd., Seoul, Korea). Galvanostatic charge and discharge tests of the NCM-graphite full-cell were carried out over a voltage range of 2.6–4.4 V. Charge and

discharge analyses were performed according to various C-rates of the NCM-graphite full-cell. Cycle retention of the NCM-graphite full-cell was examined after 50 cycles. The fill factor, the open circuit voltage, and te short circuit photocurrent density were measured by irradiating 100 mW/cm2 of light on silicon solar cells with a solar simulator (PEC-L01, Peccell Technologies, Yokohama, Japan).

#### *2.3. Integrated Si Solar Cells-LIB Device*

Si solar cells and LIB were directly connected to fabricate an integrated device. The integrated sample was examined in the glovebox (WGB2200S, Woosung Hivac, Daejeon, Korea) installed in the Future Energy Convergence Core Center (FECC). The LIB was charged by irradiating light on Si solar cells with a solar simulator (PEC-L01, Peccell Technologies, Japan). Before the test, the light intensity was calibrated to 100 mW/cm2. Photo-charging for the Li-ion battery using the Si solar cells was performed using a solar simulator. Discharge was then performed with a battery cycler.

#### **3. Results and Discussion**

Figure 1 shows FE-SEM images of NCM and graphite powder. The particle size and the shape of NCM powder are shown in Figure 1a,b. The NCM powder consisted of large and small particles with diameters of about 10 μm and 3 μm, respectively. Large particles and small particles were mixed as a bimodal. By mixing large and small particles with optimized ratios, a better energy density could be realized [18]. Park et al. [19] have reported that optimized bimodal-sized active materials can minimize voids and maximize the packing density. A bimodal structure could also improve electrochemical performance due to a large contact area between large particles and small particles [19]. The particle size and the shape of the graphite powder are shown in Figure 1c,d. FE-SEM magnitudes of Figure 1c,d were 1000 and 3000, respectively. The average size of the graphite powder was about 20 μm. As shown in Figure 1, the size of the graphite powder was greater than that of the NCM powder. Surface morphologies of the graphite powder were smoother than those of the NCM powder.

**Figure 1.** FE-SEM images of (**a**,**b**) NCM powder and (**c**,**d**) graphite powder.

XRD patterns of NCM and graphite powders are shown in Figure 2a,b. As shown in Figure 2a,b, XRD patterns of NCM and graphite powders and their joint committee on powder diffraction standard (JCPDS) data were compared. It could be noted that XRD patterns of NCM and graphite powders were very close to those of PDF data. Other XRD patterns related to impurities were not found. Results of XRD patterns confirmed that the NCM cathode powder and the graphite anode powder were successfully synthesized. For detailed structural analysis, Rietveld refinement of the NCM cathode was performed. The results are shown in Figure 2c. The structural parameters of NCM622 obtained from the Rietveld refinement are listed in Table 1. The NCM622 sample presented a hexagonal α-NaFeO2 structure with an R3m space group. Structural lattice parameters of the NCM 622 cathode are also shown in Table 1. These parameters indicated that the NCM 622 cathode material was well-ordered with a layer structure. The values of *c*/*a* and *I*003/*I*<sup>104</sup> are important factors because these values indicate the degree of structural orderliness for layered structural materials. As shown in Table 1, the values of *c*/*a* and *I*003/*I*<sup>104</sup> were larger than 4.9 and 1.2, respectively. Thus, the sample had a well-ordered layered structure and a lower amount of Li+/Ni2+ mixing [20]. The refined atomic parameters of Ni, Co, and Mn were 0.65, 0.15, and 0.20, respectively, as shown in Table 2. While the Li1 was located in the interslab layer, the Ni1, Co1, and Mn1 were in the NCM interlayer. A slight cation mixing between Li and Ni atoms was allowed by constraining the total amount of each element to 1.00 and 0.65, respectively.

**Figure 2.** XRD patterns of (**a**) NCM (JCPDS, 74-0919) powder, (**b**) graphite (JCPDS, 03-065-6212) powder, and (**c**) Rietveld refinement of NCM622 powder.


**Table 1.** Structural parameters obtained from Rietveld refinement of XRD pattern of NCM622.

**Table 2.** Atomic parameters of the pristine NMC622 material obtained from Rietveld refinement.


The electrochemical results of the half-cell and the full-cell batteries are shown in Figure 3. As shown in Figure 3a, charge and discharge capacities were obtained at 0.1 C, 0.2 C, 0.5 C, and 1 C of the NCM half-cell. The NCM half-cell had a discharge capacity of 187.36 mAhg−<sup>1</sup> at 0.1 C. The discharge capacity was similar to that reported previously [21]. Figure 3b shows the charge and discharge capacities at 0.1 C, 0.2 C, 0.5 C, and 1 C of the graphite half-cell. The graphite half-cell had a discharge capacity of 336.82 mAhg−<sup>1</sup> at 0.1 C. Figure 3c shows the charge and discharge capacities at 0.1 C, 0.2 C, 0.5 C, and 1 C of the NCM-graphite full-cell. The NCM-graphite full-cell had a discharge capacity of 183.39 mAhg−<sup>1</sup> at 0.1 C. The discharge capacity of the full-cell was very similar to that of the NCM half-cell. Figure 3d shows the discharge capacities of the NCM-graphite battery at various C-rates. As shown in Figure 3d, the discharge capacity was almost the same at each C-rate. Thus, the NCM-graphite full-cell had a good electrochemical stability.

**Figure 3.** Electrochemical properties of (**a**) NCM-Li, (**b**) graphite-Li, (**c**) NCM-graphite full cell, and (**d**) rate capability of NCM-graphite full cell analyzed at various C-rates.

Charge and discharge data of the NCM-graphite full-cell until 50 cycles at the 1 C rate are shown in Figure 4a. The discharge capacity was 160.22 mAhg−<sup>1</sup> at the 1st cycle, 158.33 mAhg−<sup>1</sup> at the 5th cycle, 157.98 mAhg−<sup>1</sup> at the 25th cycle, and 157.41 mAhg−<sup>1</sup> at the 50th cycle. The NCM-graphite full-cell had a cycle retention of 98.25% after 50 cycles. This suggests that the NCM-graphite full-cell has an excellent lifecycle performance. The NCM-graphite full-cell might exhibit good performance during operation of the integrated device with Si solar cells. The discharge capacity and the Coulombic efficiency for each cycle are shown in Figure 4b. The Coulombic efficiency was 99.68% at the 1st cycle, 99.66% at the 5th cycle, 99.52% at the 25th cycle, and 99.25% at the 50th cycle. Coulombic efficiency was almost constant over 50 cycles.

**Figure 4.** (**a**) Cycle performance of the NCM-graphite full cell over 50 cycles; (**b**) discharge capacity and Coulombic efficiency of the NCM-graphite full cell over 50 cycles.

Figure 5 shows a schematic of the integrated device using Si solar cells and the NCMgraphite battery. The voltage range of the NCM-graphite full-cell was 2.6–4.4 V. Therefore, Si solar cells were designed to obtain enough charging voltage for the battery that eight single Si solar cells (0.58 V per each single solar cell) were connected in series. Si solar cells and the NCM-graphite full-cell were directly connected without a power converter. As shown in Figure 5, the integrated Si solar cells and the battery device could be operated by self-photo-charging to the battery. The simple structure without any power converter could be an advantage.

**Figure 5.** Schematic diagram of NCM-graphite integrated device with Si solar cells.

To examine the electrical property of Si solar cells, current density–voltage (J–V) curves of Si solar cells were characterized. The results are shown in Figure 6. These Si solar cells had a short-circuit photocurrent density of 4.124 mA/cm<sup>2</sup> and an open-circuit voltage of 4.5 V. These Si solar cells had enough voltage to charge the NCM-graphite battery. They had revealed a fill factor of 0.78 and a power conversion efficiency of 14.45%. Generally, efficiencies of commercialized Si solar cells are about 12–14% [22]. Thus, Si solar cells used in this study had a moderate efficiency of 14.45% based on the literature.

**Figure 6.** J–V curve of Si solar cells.

Figure 7 shows the results of charging and discharging tests by directly connecting Si solar cells with the NCM-graphite full-cell. The charge–discharge test was performed at a voltage range of 2.6–4.4 V. The LIB of the integrated device was charged by Si solar cells using a solar simulator. The battery was then discharged using a galvanostatic method over 10 cycles. During charge–discharge over 10 cycles, the charge–discharge behavior was almost the same. This means that the integrated device can be operated stably. The power conversion and storage efficiency of the integrated Si solar cells-NCM-graphite full-cell device was 7.74%. The integrated device showed excellent power conversion and storage efficiency at a high photo-charging voltage [23].

**Figure 7.** Photo-charging and discharging diagrams of the NCM-graphite full cell using Si-solar cells and charging and discharging with a battery cycler.

In general, LiFePO4(LFP) cathode-based batteries (LFP-graphite, LFP-LTO, etc.) are widely used in ESS due to their advantages such as superior thermal stability and chemical stability [24]. These features provide better safety properties than other types of Li-ion batteries. LFP batteries have a low charging voltage. Thus, small amounts of single silicon solar cells were connected to match their charging voltage. LFP batteries are widely used in ESS. However, LFP batteries have lower capacities than NCM batteries [25,26]. NCM batteries have higher charging voltages than LFP batteries. The NCM-graphite full-cell in this study revealed a good cycle life of 98.25% after 50 cycles. Its capacity was higher than the capacity of LFP (~170 mAh/g). Therefore, the NCM-graphite full-cell could be a promising candidate for an integrated device. The energy storage efficiency from Si solar cells to LIB was 53.56%. After that, the integrated device was charged and discharged for 11–20 cycles with a battery cycler using a galvanostatic power supply in the voltage range of 2.6–4.4 V, similar to the charge–discharge voltage profile of the NCM-graphite battery. Photo-charging of integrated devices is an efficient way of charging using a battery cycler. Therefore, an integrated device of a LIB and a Si solar cell is a promising power system for portable devices, wearable devices, ESS, and EVs.

Figure 8a shows J–V curves of Si solar cells connected to an NCM-graphite full-cell before and after various cycle tests. The current density of Si solar cells connected to the NCM-graphite full-cell was 4.124 mA/cm2 before the cycle test. As the number of cycles increased, the current density of Si solar cells connected to the NCM-graphite fullcell decreased slightly. After 1, 5, and 10 cycles, current densities were 4.122 mA/cm2, 4.114 mA/cm2, and 4.099 mA/cm2, respectively. These Si solar cells integrated to the NCM-graphite battery revealed an open circuit voltage of 4.49 V after 10 cycles. This open circuit voltage did not change significantly over 10 cycles. Figure 8b shows the fill factor and the energy efficiency of Si solar cells integrated to the NCM-graphite full-cell before and after various cycle tests. The energy efficiency of Si solar cells connected to the NCM-graphite full-cell was 14.45% before the cycle test. As the number of cycles increased, the energy efficiency of Si solar cells connected to the NCM-graphite full-cell decreased slightly. Energy efficiencies of Si solar cells connected to the NCM-graphite full-cell after 1, 5, and 10 cycles were 14.41%, 14.32%, and 14.26%, respectively. The fill factor of the Si solar cells connected to the NCM-graphite full-cell was 0.78 before the cycle test. As the number of cycles increased, the fill factor slightly decreased. The fill factor values of the Si solar cells connected to the NCM-graphite battery after 1, 5, and 10 cycles were 0.78, 0.78, and 0.77, respectively. After 10 cycles, the energy-conversion efficiency of solar cells connected to the NCM-graphite full-cell was 98.68% of the efficiency before the cycling test. Therefore, Si solar cells were suitable devices to supply power to the NCM-graphite full-cell.

**Figure 8.** (**a**) Current density and voltage (J–V) curve; (**b**) fill factor (FF) and energy efficiency of Si-solar cells integrated to an NCM-graphite battery before and after 10 cycles.

#### **4. Conclusions**

In summary, we fabricated a LIB using NCM as the cathode and graphite as the anode. To obtain enough photo-charging voltage, eight single Si solar cells were connected in a series. LIB and Si solar cells were directly connected without any converter. The results of photo-charging with Si solar cells at galvanostatic discharge were very close to charging/discharging with a galvanostatic system. The power conversion efficiency of the NCM-graphite full-cell and Si solar-cells was 7.74%. The energy conversion efficiency of Si solar-cells to LIB was 53.56%, which showed a high energy conversion efficiency.

The cycle retention of the NCM-graphite battery was stable at 98.68% over 50 cycles. In addition, the NCM-graphite full-cell showed a higher capacity than reported LFP-based batteries. Charging of the integrated device could be as effective as charging with a battery cycler. Therefore, an integrated system using an NCM-graphite full-cell is a promising approach to replace an LFP-based integrated system.

**Author Contributions:** Methodology, C.-R.L.; formal analysis, D.N.; investigation, H.-K.S.; resources, O.-H.K.; data curation, H.L.; writing—original draft preparation, H.L.; writing—review and editing, I.S.; project administration, J.-K.K., I.S.; funding acquisition, I.S. All authors have read and agreed to the published version of the manuscript.

**Funding:** This work was supported by grants (2018R1A4A1025528 and 2020R1A2C2009057) of the National Research Foundation of Korea (NRF). This research was also partially supported by Cheongju University Research Scholarship Grants in 2021.

**Acknowledgments:** The authors thank Baeksang Yoon for providing technical support. The aurthors also thank anonymous reviewers for fruitful discussion and useful comments.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


### *Technical Note* **Design and Comparison of the Performance of 12-Pulse Rectifiers for Aerospace Applications**

**Fabio Corti 1,2,\*, Abdelazeem Hassan Shehata 1, Antonino Laudani <sup>3</sup> and Ermanno Cardelli <sup>2</sup>**


**Abstract:** In this paper, a conventional 12-pulse transformer unit (CTU) and an autotransformer 12-pulse transformer unit (ATU) are compared in the view of the RTCA DO-160 standard for aircraft applications. The design of the magnetic components is proposed via a coupled FEM-circuital analysis in the time domain for an 800 Hz/2 kW system. Input AC distortion, power factor, and output DC ripple are evaluated through simulations. An accurate power loss analysis is carried out, taking into account copper losses, magnetic losses, and power losses due to power switches. The reduction in the size and weight of the ATU with respect to the CTU solution is discussed, including the need for filtering systems and the standard requirements.

**Keywords:** aerospace 12-pulse rectifier; autotransformer rectifier; magnetic component design; performance; standard requirements

#### **1. Introduction**

Aircraft with advanced electric drives represent a green solution that can reduce fuel consumption and greenhouse gas emissions, thanks to lower weight, low maintenance, and higher conversion efficiency than mechanical, hydraulic, and pneumatic systems. This transition is possible thanks to reliable and high-efficiency power converters, which allow power loss reduction, leading to higher power density, lower weight, and lower volumes. Compliance with existing international standards guarantees the adoption of power converters with acceptable values of total harmonic distortion (THD), power factor (PF), and DC output ripple, leading to increasingly reliable systems. High-harmonic components in currents and voltages and a high ripple rate in DC output voltages may result in resonances overvoltages and other problems of electromagnetic compatibility inside the onboard electrical systems [1].

The application of a CTU as an AC–DC converter represents the most used solution, even if it may not always meet the quality standard requirements in terms of input current THD and output voltage ripple [2]. Lower current harmonic content and higher power factor are achieved by using interphase transformers and impedance-matching inductors, which, in contrast, result in increased complexity, volume, weight, and cost [3]. Moreover, these components may suffer from detuning [3–9]. To improve the quality standards and reduce the overall size, AC–DC converters having a higher pulse number have been proposed [1–3]. Recently, several authors have investigated solutions based on the use of autotransformers, indicating their possible advantages and suggesting these solutions as alternatives to the use of CTUs [10–14]. In the proposed autotransformer-based solution, the windings are interconnected such that the apparent power transmitted by the actual magnetic coupling is only a portion of the total apparent power [14]. The reduced apparent

**Citation:** Corti, F.; Hassan Shehata, A.; Laudani, A.; Cardelli, E. Design and Comparison of the Performance of 12-Pulse Rectifiers for Aerospace Applications. *Energies* **2021**, *14*, 6312. https://doi.org/10.3390/en14196312

Academic Editor: Javier Contreras

Received: 17 August 2021 Accepted: 28 September 2021 Published: 2 October 2021

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

power rating makes the autotransformer-based solution smaller and less costly and lets it operate at a higher efficiency than the conventional transformer-based solution [15]. This reduces the system weight and volume and seems to increase the overall reliability, capability, and maintainability; finally, it seems to provide higher durability for aircraft operations [16,17].

In this paper, an 800 Hz/2 kW 12-pulse ATU is investigated and designed, and its performance is compared with that of a CTU of the same frequency and power rate. The CTU solution is based on a Δ–ΔY transformer and two diode bridges connected in series. The ATU solution has two diode bridges in parallel.

The standards of reference used in the regulation of aircraft power supplies are CEN-EN 2282 [18], ISO 1540 [19], IEEE-1531-2020 [20], and RTCA DO-160 [21]. In this paper, the RTCA DO-160 standard has been considered, since it is the most referenced standard.

The IEEE-1531 standard recommends a limit of 8% on the THD of AC current and 5% on the THD of voltage at input AC mains [20]. The RTCA DO-160 standard indicates different maximum THD rates, depending on the device category [21].

The two configurations examined in the paper are designed for the typical avionic 115 RMS AC input voltage and 270 V output voltage. The design is made via a coupled FEMcircuital analysis. The resulting nominal parameters of the designed solutions, including their size and weight, are obtained and indicated.

As indicated by RTCA DO-160, several tests are simulated on both the CTU and the ATU to assess their compliance with this standard. In particular, four tests are simulated: (1) AC input current distortion test, (2) AC power factor test, (3) DC output voltage ripple test, and (4) phase unbalance test.

In addition to compliance with the standards, an accurate analysis of AC–DC conversion efficiency and power losses is carried out. Finally, a comparison of the CTU and ATU in terms of size, weight, and converter performance is illustrated.

The paper is organized as follows. In Section 2, the architecture and design of the CTU and ATU 12-pulse rectifier solutions are presented and discussed, including the FEM-circuital approach. In Section 3, the main features of the RTCA DO-160 standard are described. The AC current distortion, power factor, DC output voltage, and phase unbalance are evaluated through the simulation of the tests indicated by the standard in Sections 4–7, respectively. Starting from the obtained results, a comparison between the two topologies is discussed in Section 8. Finally, some concluding remarks are provided in Section 9.

#### **2. Twelve-Pulse AC/DC Configurations**

#### *2.1. Conventional 12-Pulse Unit Design*

As shown in Figure 1a, the CTU was fed from a three-phase transformer with a Δconnected primary winding and two secondary windings (one is Δ connected, and the other is Y connected). The magnetic core with the primary and secondary winding arrangement is shown in Figure 1b. Each secondary winding was connected to a three-phase, six-pulse diode bridge. The two bridges were connected in series to form a 12-pulse rectifier. The output voltage was usually connected to a DC load, such as batteries or a supercapacitor, which allowed increasing the power density, reducing weight [22]. As shown in Figure 1c, this configuration produced a 30◦ phase shift between the voltage phasors of the two bridges, and this resulted in a 12-pulse per cycle output voltage [23].

**Figure 1.** Schematic of CTU 12-pulse rectifier. (**a**) Electrical circuit. (**b**) Magnetic structure representation. (**c**) Phasor diagram representation.

The 12-pulse AC–DC converter must be suitable to operate with the design constraints shown in Table 1.

**Table 1.** Converter operating conditions.


It was designed according to the following steps:


The design procedure was recursively run, considering at that stage a linear behavior of the magnetic material.

This first stage resulted in the output characteristics shown in Table 2.

**Table 2.** Conventional 12-pulse unit parameters.


The magnetic core material used in the design was a stacking iron-based Metglas® amorphous alloy [24]. To check the previous approximated computation of the magnetic induction and that of the magnetic inductances in the magnetic coupling coefficients between the windings, a finite element analysis (FEA) was performed by using a code developed by the authors [25–28]. In particular, a 2D analysis was performed by assuming a linear behavior of the material (constant value of the magnetic permittivity, equal to the value measured at the working magnetic induction) and a current-driven formulation of the problem. A full three-phase current system was used for the excitations, and the coupling coefficient was computed by considering the effective winding geometry. The aim of this simulation was to compute both the coupling coefficient and the maximum value of the magnetic induction in real operating conditions. The mesh discretization of the magnetic core and a close-up of the air gap region are shown in Figure 2. To compute the coupling coefficient, a postprocessing of the FEA solution was performed by evaluating the linked flux in different parts of the section surrounded by the windings. The coupling coefficient estimated was about *k* = 0.98, while the maximum value of magnetic induction (RMS value) was about *BRMS* = 0.85 T. The field vectors are shown in Figure 3 at the maximum value of magnetic induction.

**Figure 2.** Mesh of the half section of the magnetic core used in finite element analysis.

**Figure 3.** Magnetic induction field vector distribution computed by FEA in the air gap region.

#### *2.2. Autotransformer 12-Pulse Unit Design*

Figure 4a shows the ATU electrical circuit. It consists of a Δ-connected autotransformer with secondary windings connected to two three-phase diode bridge rectifiers; these two bridges were connected in parallel with the load. The winding representation and the voltage phasor diagram of the proposed Δ-type autotransformer are shown in Figure 4b,c, respectively.

The transformer phase-shifting angle was equal to 30◦, the winding configuration of the ATU resulted in the lowest apparent power rating [3], and the size of the magnetic component reduced [10] under this condition. As described in [12,29], the proposed autotransformer achieved the simplest winding configuration when the angle was 30◦ (±15◦). To produce a 30◦ phase shift between the two sets of secondary windings, the winding turn ratio should be

$$\frac{N\_1}{N\_2} = \frac{\sqrt{3}}{2 - \sqrt{3}}\tag{1}$$

**Figure 4.** Schematic of an ATU. (**a**) Electrical circuit. (**b**) Structure representation. (**c**) Voltage phasor representation.

The phasors of the voltages produced by the autotransformer *VA*1, *VB*1, and *VC*<sup>1</sup> were at +15◦ with respect to the supply voltages *VR*, *VS*, and *VT*, while the other set of the phasors of the voltages *VA2*, *VB2*, and *VC2* were at −15◦ with respect to supply voltages, resulting in a 12-pulse rectification [9,30,31]. The magnitudes of the secondary line voltages (*VA*1, *VB*1, and *VC*<sup>1</sup> and (*VA2*, *VB2*, and *VC2*) should be equal to each other to result in a symmetrical system and to reduce the ripple in output DC voltage [11–32].

A two-step design of the ATU, requiring the same procedure described in the previous section for the CTU, was carried out. The final parameters of the designed ATU device are reported in Table 3.



According to the previous FEA, a coupling coefficient of *kps* = 0.98 between the primary and the secondary and a coupling coefficient *kss* = 0.96 between the two secondaries were estimated.

An additional filter constituted by Δ-connected capacitors was added to the system to reduce the input current THD. The IEEE 1531-2003 standard [20] was used to size the capacitors. To determine the value of each capacitor, the required reactive power for the system *Q* was first determined through the simulation and then the capacitance was calculated according to [33]

$$C\_f = \frac{Q}{2\pi f V\_i^2} \tag{2}$$

where *f* is the fundamental frequency of the current, *Vi* is the RMS value of the line voltage, and *Q* is the required reactive power. By using the power measurements Matlab's block, a reactive power *Q* of about 1700 VAR was estimated, leading to a filtering capacitor *Cf* = 13 μF. To reduce the THD, three filtering capacitors Δ-connected with a value C*<sup>f</sup>* =25 μF were finally chosen.

#### **3. Application of RTCA DO-160G Standard Tests**

From RTCA DO-160G, the equipment intended for use on aircraft electrical systems where the primary power is supplied through an AC system with a frequency in the range of 360–800 Hz was designated as A(WF). Regarding the DC side, if the output was 270 V, the systems were designated with the letter D. Therefore, the systems studied in this paper were classified as A(WF)-D. This information is required to properly select tests that must be performed on the rectifiers to check the required compliance of the system. In addition to the tests required from RTCA DO-160G, an accurate evaluation of the conversion efficiency of the system was carried out, properly analyzing the power losses.

During the analysis, a line inductance *Ls* = 0.1 mH was assumed to be connected in series to the three-phase voltage sources to take into account the electrical power supply system upstream of the device.

The same diode was used in the CTU and ATU rectifiers, with a forward voltage *VF* = 0.6 V and a conduction resistance *rON* = 0.1 Ω. The performance of each rectifier was evaluated for three different load resistances, *RL*<sup>1</sup> = 37 Ω, *RL*<sup>2</sup> = 74 Ω, and *RL*<sup>3</sup> = 148 Ω, called here heavy load, intermediate load, and light load resistances, respectively, which represent, approximatively, a working condition at 100%, 50%, and 20% of the nominal power, respectively. These working conditions are summarized in Table 4.


**Table 4.** Converters' operating conditions.

As requested from the RTCA DO-160G standard, the following parameters must be evaluated.

The output voltage ripple Δ*Vo* was evaluated under the three different operating conditions and calculated as

$$V\_{o,ripple}(\%) = \frac{V\_o^{max} - V\_o^{min}}{V\_o^{avg}} \cdot 100\tag{3}$$

The total harmonic distortion (THD) of the input current was calculated as

$$THD(\%) = \frac{\sqrt{I\_2^2 + I\_3^2 + \dots + I\_N^2}}{I\_1} \cdot 100\tag{4}$$

where *I*<sup>1</sup> is the amplitude of the fundamental current harmonic and *I*2, *I*3, ... , *IN* are the amplitudes of the second, third, . . . , *N*-th current harmonic, respectively.

The power factor (PF) was also evaluated by using

$$PF = \frac{1}{\sqrt{1 + \left(\frac{THD(\%)}{100}\right)^2}} \cos(\varphi\_1) \tag{5}$$

where *ϕ*<sup>1</sup> is the displacement angle between the fundamental components of the input current and voltage.

Another parameter of primary importance is the AC–DC conversion efficiency. As known, it can be calculated as *η* = *Po*/*Pi* with *Po* = *Vo*·*Io* and *Pi* = *Po* + *Ploss*.

The power losses can be assumed to be constituted by two main contributions as

$$P\_{loss} = P\_{TRF} + P\_D \tag{6}$$

where *PD* is the loss due to the rectifier and it is strictly related to the characteristics of the diodes. It can be calculated as

$$P\_D = r\_{ON} \cdot I\_{D,RMS}^2 + V\_F \cdot I\_{D,AVG} \tag{7}$$

where *ID,RMS* and *ID,AVG* are the RSM and average current flowing through the diode, respectively. The average and RMS value of the current were calculated on Simulink, measuring the current flowing through each diode and then computing the power loss using Equation (7).

*PTRF* is the transformer power loss and can be divided into two contributions

$$P\_{TRF} = P\_{\mathbb{C}u} + P\_{\mathbb{C}ore} \tag{8}$$

where *PCu* is the ohmic loss due to the copper windings and is calculated as

$$P\_{\mathbb{C}u} = \mathbb{R} \cdot I\_{\mathbb{R}}^2 \tag{9}$$

while *PCore* is the magnetic core loss given by

$$P\_{\mathbb{C}ore} = \mathbb{C}\_m \cdot f^a \cdot B\_{rms}^{\beta} \tag{10}$$

From the datasheet of the Metglas® alloy 2605SA1, the values of the parameters for this material were *α* = 1.51, *β* = 1.74, and *Cm* = 6.5 [25].

#### **4. AC Current Distortion Test**

In this section, the AC current distortion for both the CTU and the ATU are evaluated by using the procedure provided by the RTCA DO-160 standard.

This test must be performed for AC equipment with a maximum power consumption larger than 35 VA. The first 40th harmonics are required to satisfy the individual current harmonic limits, as shown in Table 5.


**Table 5.** Harmonic limits according to RTCA DO-160.

\* As above, *I*<sup>1</sup> is the amplitude of the current fundamental harmonic and *Ih* is the amplitude of the harmonic current of *h* order.

From the RTCA DO-160G standard, the current distortion must be evaluated under two operating conditions:


The two waveforms used to perform test A and test B are shown in Figure 5a,b, respectively. In particular, test A was simulated assuming a three-phase voltage with THDV = 0%, while test B was simulated assuming THDV = 10% with equal RMS values of the third, fifth, and seventh harmonics.

Next are summarized the results obtained for the simulated tests on both the CTU and the ATU.

#### *4.1. CTU Current Distortion Evaluation*

The input currents *ia* when the system was supplied with the voltage shown in Figure 5a,b are shown in Figure 6a,b, respectively.

**Figure 6.** CTU input current waveforms. (**a**) Nominal condition. (**b**) Distorted input voltage.

The CTU harmonic current components under tests A and B are summarized in Table 6. The amplitude of the primary harmonic (order *H*<sup>1</sup> in the table) at *f* = 800 Hz was *IH*<sup>1</sup> = 8.4 A. Each harmonic value was expressed as a percentage of the amplitude of the primary harmonic.


**Table 6.** CTU total harmonic distortion.

As can be seen from Table 6, the simulation indicated that the limits of the standards were respected for both tests A and B.

Therefore, it was indicated by the simulation results that the designed CTU complies with the current harmonic limits.

#### *4.2. ATU Current Distortion Evaluation*

The ATU harmonic current components under tests A and B are summarized in Table 7. The amplitude of the primary harmonic (order *H*1) at *f* = 800 Hz was *IH*<sup>1</sup> = 9.6 A.


**Table 7.** ATU total harmonic distortion.

harmonic.

Each higher-order harmonic was expressed as a percentage of the amplitude of the primary

As can be seen from Table 6, the simulations that indicated the limits of the standards were respected for both tests A and B.

The input currents *ia* when the system was supplied with the voltage shown in Figure 5a,b are shown in Figure 7a,b, respectively.

In addition, for the ATU, the test simulations indicated that the input current harmonic content allows satisfying the standard limits.

**Figure 7.** ATU input current waveforms. (**a**) Nominal condition. (**b**) Distorted input voltage.

#### **5. AC Power Factor Test**

Another test required by RTCA DO-160G is the AC power factor test. The power factor, defined as in Equation (5), will be equal to or higher than the values listed in Table 8.


**Table 8.** ATU total harmonic distortion and power factor limits.

Since the proposed 12-pulse rectifiers were characterized by a 2 kW nominal load power and they were seen as ohmic-inductive loads by the source, a lagging power factor *PF* > 0.8 was required to comply with the standard requirement.

#### *5.1. CTU Power Factor Test Results*

The THD of the line currents and the PF computed under different load conditions are summarized in Table 9.

The simulations indicated that the PF was always higher than the limit defined by the standard *PF* > 0.8 for all the load conditions examined. The presence of resistive-inductive loads seemed to not affect the converter behavior.


**Table 9.** CTU total harmonic distortion and power factor.

#### *5.2. ATU Power Factor Test Results*

The THD of the input line current and the PF values, calculated in analogy with the case of the CTU, are summarized in Table 10.


In addition, for the ATU case, the PF computed was always higher than the limits specified by the standard, and it can be concluded that both AC–DC converters comply with the standard requirements.

#### **6. DC Current Ripple Test**

The output voltage of a 12-pulse rectifier is characterized by a DC component plus a fundamental AC component with a frequency 12 times higher than that of the AC line, plus higher-order harmonics. The RTCA DO-160G standard establishes amplitude limits for different frequency contents. Thus, the harmonic content of the output voltage was analyzed to evaluate whether the two converters meet the standard limits.

#### *6.1. CTU Output Voltage Ripple Results*

The waveforms of the output voltage computed under nominal conditions are shown in Figure 8.

To evaluate whether the standard limits are respected, the first 20 voltage harmonics (fundamental frequency *f* <sup>0</sup> = 800 Hz) were evaluated at different load levels, as shown in Table 11.

**Figure 8.** CTU output voltage waveforms.


**Table 11.** The harmonic content of CTU output voltage.

The average output voltage *Vo avg* and the ripple *Vo ripple* are indicated in Table 12. Simulated results indicated that the voltage amplitudes values were only marginally affected by the load, even when it was ohmic-inductive.



#### *6.2. ATU Output Voltage Ripple Results*

In Figure 9, the output voltages for different loads are shown; the average output voltage *Vo avg* and the ripple *Vo ripple* are summarized in Table 13.

**Figure 9.** ATU output voltage waveforms.


**Table 13.** ATU with input capacitor filter—simulation results.

The first 20 harmonics of the output voltage are reported in Table 14.


**Table 14.** Ripple voltage for ATU total harmonic distortion.

The output voltage harmonic contents computed for the CTU and ATU are shown in Figure 10. Both solutions maintained the harmonic content inside the allowable standard limits.

**Figure 10.** ATU input current amplitude.

#### **7. Phase Unbalance Test**

The RTCA DO-160G standard requires the evaluation of the effects of phase unbalances. The unbalance includes unequal voltage magnitudes at the fundamental system frequency, fundamental phase angle deviation, and unequal levels of harmonic distortion between the phases. A major cause of voltage unbalance is the asymmetry of the loads, if the loads are not uniformly shared among the three phases. The input voltage waveforms shown in Figure 11 has been used to reproduce the unbalanced operating condition.

**Figure 11.** Typical input voltage waveforms under unbalanced operating conditions.

#### *7.1. CTU under Unbalanced Input Voltage*

In Figure 12a, the output voltages *vo* computed under unbalanced voltage conditions for different loads are shown. The related output voltage ripples are indicated in Table 15.


**Table 15.** CTU output voltage simulation results under unbalanced input voltage.

The input current computed is shown in Figure 12b. The THD of the line currents and the PF for different loads are indicated in Table 16.

**Table 16.** CTU total harmonic distortion and power factor under unbalanced input voltage.


Simulations indicated that there is an inversely proportional relationship between the THD of the input line current and the output load power, while the power factor changed from 0.86% at 10% of the load to 0.65 at full load. Finally, Figure 12c shows that independent from the load conditions, the magnetic flux density *B*(t) was sinusoidal, as expected, with an RMS value *BRMS* = 0.58 T.

**Figure 12. CTU** Simulink/FEM simulation of a conventional 12-pulse rectifier. (**a**) Output voltage. (**b**) Input current. (**c**) Magnetic flux density.

#### *7.2. ATU under Unbalanced Input Voltage*

Figure 13a shows the output voltages *vo* of the ATU computed for different loads. The average output voltage *Vo avg* and the ripple *Vo ripple* are summarized in Table 17.

**Figure 13. ATU** Simulink/FEM simulation of a conventional 12-pulse rectifier. (**a**) Output voltage. (**b**) Input current. (**c**) Magnetic flux density.

**Table 17.** ATU output voltage simulation results under unbalanced input voltage.


The input current is plotted in Figure 13b. The THD of the line currents and the PF for different loads are indicated in Table 18.


**Table 18.** ATU total harmonic distortion and power factor under unbalanced input voltage.

As in the case of the CTU, Figure 13c indicates that independent from the load conditions, the magnetic flux density *B*(*t*) was sinusoidal, as expected, with an RMS value *BRMS* = 0.58 T.

#### **8. Final CTU and ATU Comparison**

Figure 14 shows the comparison between the estimated CTU and ATU conversion efficiency under different load conditions. The AC–DC conversion efficiency evaluated as in Section 3 was always higher than 95% under all the considered operating conditions and for both the analyzed solutions. Simulations indicated that the ATU has higher efficiency than the CTU under heavy load conditions (i.e., *RL* = 37 Ω and *RL* =74 Ω), while the ATU efficiency is comparable with the CTU's under lighter load conditions (*RL*<sup>3</sup> = 148 Ω).

**Figure 14.** Comparison of AC–DC conversion efficiency computed under different load conditions.

The power loss contributions at different loads were analyzed for each converter, and results are summarized in Figure 15. The copper losses *PCu*, the core loss P*Cor*e, and the diode rectifier losses *PD* were separately computed. The three power loss contributions for the CTU are shown in Figure 15a. The core loss was the higher contribution, independent from the operating conditions. As expected, the diode loss and the winding loss decreased under a lighter load condition. The copper loss always represents the lowest contribution.

In Figure 15b, in analogy, the different ATU-related power loss contributions are shown. In this case, the simulations indicated that the diode losses were higher than in the case of the CTU, independent from the load condition, as expected, in consideration that the two diode bridges were in series for the ATU and in parallel for the CTU. The diode losses and winding losses decreased according to the load current. The core losses, as expected, were almost constant and independent from the different load conditions.

In Figure 16, the comparison of the input current THDs predicted by the simulations by using the CTU and ATU is shown. Both the CTU and the ATU allowed meeting the standard requirements under the whole operating conditions, ensuring a THD lower than the threshold value THDmax = 8%. Thanks to the input capacitive filter, the THD of the ATU was always lower than in the case of the CTU and <2%.

**Figure 15.** Power losses at different loads: The blue line is the winding loss, the red line is the core loss, and the green line is the diode rectifier loss. (**a**) CTU. (**b**) ATU.

**Figure 16.** Comparison of input current THD at different loads.

The obtained results for the two topologies are summarized in Table 19.


**Table 19.** Summary of CTU and ATU characteristics.

#### **9. Conclusions**

This paper describes the design and modeling of two different AC–DC 12-pulse rectifiers, here named CTU and ATU. These devices are suitable for both terrestrial and aircraft applications. The parameters considered for the comparison of the performance of the CTU and the ATU are the conversion efficiency, output voltage, and input current THD in view of the RTCA DO-160 standard requirements. The comparison was performed by suitable numerical simulations made by a coupled FEM-circuital approach and considering variable load conditions up to the nominal power. Both pure resistive and inductiveresistive loads were considered.

Based on the simulation results, either the CTU or the ATU solutions comply with the standard requirements and limits and have a high conversion efficiency (more than 96%).

Results of the simulations indicate also that the ATU solution allows for a significant reduction in weight (more than 50% in the case study) and for an appreciable increase in efficiency (2% at nominal current) with respect to the CTU solution. However, the ATU solution needs an additional input capacitive filter, which, anyway, does not change substantially the gain in weight and size obtained and, in addition, greatly reduces the THD with respect to the case of the CTU solution and is under 2%.

Another important difference between the two topologies is that the CTU, differently from the ATU solution, allows for galvanic isolation between primary and secondary.

As future development, other 12-pulse topologies will be compared with ATU and CTU systems. The effect of the non-linearities on the magnetic core will be analyzed and techniques able to reduce copper and diode losses will be studied. Experimental validation of the obtained results will be performed.

**Author Contributions:** Conceptualization, E.C. and F.C.; methodology, E.C., F.C., and A.L.; software, F.C. and A.H.S.; validation, F.C., A.H.S., and A.L.; formal analysis, E.C., A.L., and F.C.; investigation, E.C., F.C., and A.L.; data curation, A.H.S.; writing—original draft preparation, F.C. and A.H.S.; writing—review and editing, F.C. and A.H.S.; supervision, E.C. and A.L. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research received no external funding.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


## *Article* **Design, Analysis and Experimental Verification of the Self-Resonant Inverter for Induction Heating Crucible Melting Furnace Based on IGBTs Connected in Parallel**

**Borislav Dimitrov 1,\*, Khaled Hayatleh 2, Steve Barker <sup>2</sup> and Gordana Collier <sup>2</sup>**


**Abstract:** The object of this research was a self-resonated inverter, based on paralleled Insulated-Gate Bipolar Transistors (IGBTs), for high-frequency induction heating equipment, operating in a wide range of output powers, applicable for research and industrial purposes. For the nominal installed capacity for these types of invertors to be improved, the presented inverter with a modified circuit comprising IGBT transistors connected in parallel was explored. The suggested topology required several engineering problems to be solved: minimisation of the current mismatch amongst the paralleled transistors; a precise analysis of the dynamic and static transistors' parameters; determination of the derating and mismatch factors necessary for a reliable design; experimental verification confirming the applicability of the suggested topology in the investigated inverter. This paper presents the design and analysis of IGBT transistors based on datasheet parameters and mathematical apparatus application. The expected current mismatch and the necessary derating factor, based on the expected mismatch in transistor parameters in a production lot, were determined. The suggested design was experimentally tested and investigated using a self-resonant inverter model in a melting crucible induction laboratory furnace.

**Keywords:** induction heating; self-resonant inverter; IGBTs; IGBTs in parallel

#### **1. Introduction**

This paper aimed to design, analyse, prototype, and experimentally test a self-resonant inverter for crucible inductance furnaces to verify the suggested circuit based on IGBTs connected in parallel. For this purpose, a methodology for analysing the transistors' characteristics and the expected mismatch in a production lot was suggested and implied as part of the design procedure. It was based on trend analysis of the transistors' datasheets, digitalising the graphical data and deriving precise polynomial equations. Such a study aimed to compensate for the lack of data on the mismatch of IGBT parameters. In this sense, the presented research's novelty consisted of modifying a well-known circuit, which was analysed with a novel methodology focused on paralleled transistors, giving the expected current mismatch and the necessary derating factor.

As a highly efficient and fast method, induction heating is applicable for numerous technological processes of heating, melting, hardening, etc. The investigated crucible furnaces are used for metal melting, such as gold, steel and copper, applied in different industries—jewellery, steel production, etc. The theoretical basis of induction systems has been described in multiple well-established literature sources [1–6], giving fundamental knowledge for the system inductor-workpiece.

A popular method for induction heating analysis is modelling and simulation with the Finite Element Method (FEM), which depicts the system's electromagnetic field inductorworkpiece. The system's thermal and electrical parameters can be analysed, as well as

**Citation:** Dimitrov, B.; Hayatleh, K.; Barker, S.; Collier, G. Design, Analysis and Experimental Verification of the Self-Resonant Inverter for Induction Heating Crucible Melting Furnace Based on IGBTs Connected in Parallel. *Electricity* **2021**, *2*, 439–458. https:// doi.org/10.3390/electricity2040026

Academic Editors: Oriol Gomis-Bellmunt and Andreas Sumper

Received: 13 July 2021 Accepted: 28 September 2021 Published: 11 October 2021

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

the required parameters of the high-frequency electronic converter to be predicted on the simulation level. Using FEM, in [7,8], an induction heating process with a moving inductor or workpiece was presented. Such systems require considerable power to be transferred for a short time for the necessary temperature to be reached at the required time. For this purpose, significant currents through the inductor, for example, 450–890 A at 36 kHz [8], must be supplied from the induction heating inverter. The optimisation of the inductor-workpiece system gave positive results [9] for the magnetic coupling but did not minimise the current provided, presented in most FEM models in the range of 106–108 A/m2.

According to the research published in [10], the induction heating process with spray cooling, realised by the presented experimental equipment, can continue for a relatively long time at about 30 min. The required inductor current exceeded 400 A. The provided experiments were used for FEM model calibration. A similar study [11], based on the induction heating and FEM modelling analysis, showed a process established at a relatively low frequency of 3 kHz and 544.5 A current through the inductor. Higher frequencies, up to 20 kHz, can be applied for magnetic and nonmagnetic workpieces [12]. The presented experimental verification in [12] was completed with a low-voltage inductor, rated at 47.1 V, which gave a maximum current of 1063 A. In addition, the used capacitor tank at the resonant tank was rated at 15.41 μF or 55.7 μF, which gave a resonant frequency of between 10 kHz and 20 kHz.

Studies focused on the influence of the workpiece characteristics over the heating process [13–15] have shown that the inductor geometry characteristics have a critical impact on the electromagnetic field shape and must be considered with the specific workpiece. This phenomenon has the potential to influence the inverter characteristics influenced by the inductor length and its inductivity and, hence, the resonance frequency with the necessary capacitance tank, as well as the inverter's output current at a given power, which requires additional study.

Another group of recently published papers [16–18], focusing on the development and application of new materials, showed the induction heating application for materials' laboratory production and further investigation. The technological parameters required variations in broad ranges in output power of 10–200 kW, inductor currents up to thousands of amps, low or high inductor voltages and resonant frequencies up to 300 kHz. The exact requirements can be stated for flat-inductor systems [19] and melting induction furnaces [20]. They clearly show that with respect to the industrial equipment with specific parameters, the laboratory induction heating must be much more flexible, which would ensure its application for different laboratory tests and studies. According to these requirements, self-oscillating inverters for induction heating are good candidates for laboratory equipment as a simple structure that is highly reliability and naturally operating with inherent Zero Voltage Switching (ZVS) modulation, which gives low switching losses. In [21–23], a self-oscillating inverter with a parallel resonant tank operating at a relatively low power of 300 W was proposed. The research showed the advantages of implementing a Current Source Parallel Resonant Push-Pull Inverter (CSPRPI) and the possibilities of achieving ZVS with low switching losses. A similar topology based on a half-bridge but a series resonant tank was also proven to have a stable operation at ZVS [24]. Furthermore, the same source proved that these classes of converters can be controlled with a simple phase-locked loop based on a variable duty cycle.

A converter structure with proven application in induction heating, giving high power density and the ability to operate with soft-switching, is the full-bridge circuit with a parallel or series resonant tank, based on different modulation techniques, such as Phase-Shift Modulation (PSM), Pulse-Frequency Modulation (PFM), Pulse-Density Modulation (PDM) and Asymmetrical Duty-Cycle (ADC) [25–31]. These types of modulation offer flexible control over the wide range of output powers [25]. These inverters applied for induction heating can have a good match with a Power Factor Correction (PFC) stage [26]. An additional characteristic of the PSM is the ability of the ZVS to be achieved for the required power range under regulation with variable switching frequency [27]. It has been shown that the use of variable switching has a better efficiency than a fixed switching frequency. Despite the modulation technique, the problem with the transient overvoltages and electromagnetic interference (EMI) due to the transistor switching is mitigated with snubbers.

In contrast to the self-oscillating inverters [21–23], one of their advantages is usually based on snubber-less power stage circuits for the full-bridge PSM topology, and different types of passive snubbers such as C, RC, and RCD can be used. Their selection and design depend on the modulation technique and the match between the used IGBTs and the resonant tank parameters [28,29]. In the same class, transformer-based converters are the LLC resonant inverters. A powerful inverter of this type, rated at 25 kW with a fixed frequency of 25 kHz, is presented in [30]. Transformer-less topologies based on a full-bridge can be realised as matrix converters, whose topology requires bi-directional switches [31]. Although these converters have significant advantages, a comparative analysis shows that the self-resonant converters are based on a more straightforward structure, giving a budget-friendly induction heating system, with low EMI, without snubber circuits and low losses.

Another group of papers focused on induction heating devices for cooking [32–36], which usually have flat inductors and an installed power in the range of 1.5–2.8 kW. According to their shapes and materials, an important issue is the magnetic coupling between the inductor and the loads, i.e., pan, pot and wok [32,33]. The other parts of the control system: sensors, feedbacks, filters, etc., are also well investigated from the cooking-intended induction heaters [34–36]. The reported efficiency for cooking induction heating converters is over 95%, which can be expected as a parameter for a powerful induction heating crucible system.

The provided literature review concludes that the self-oscillating resonant converters have the simplest circuit, offering a robust and budget-friendly solution. Currently, they are applied for relatively low power in the range of 300–800 W as laboratory equipment, using cylindrical inductors for heating magnetic elements [37,38]. It can be suggested that their application can be extended to more considerable powers, over 30 kW, and a frequency range of 25–35 kHz, giving an application for fast-melting crucible inductance furnaces [39]. Such a power would require a power stage based on IGBT transistors connected in parallel to be designed and implemented. Numerous papers [40–47] present research mainly focused on IGBTs. Current equalisation with improved gate drive control implemented with Digital Signal Processors (DSPs) and precise current measurements is given in [40,41]. Strategies based on active driver circuits and current cross-reference control techniques were proposed in [42], including for Silicon Carbide (SiC) MOSFETs [43,44].

Nowadays, Revers Conducting IGBTs (RC-IGBTs), specialised for resonant inverters, i.e., applicable for induction heating systems, are offered by manufacturers [45–48]. According to the presented applications [45], the analysis of the transistors' technology and their implementation in the induction inverters [47] justifies the suggestion that paralleled RC-IGBT can operate with a good current sharing and, hence, low current mismatch. The experimental data presented with oscillograms showed inverters' soft-switching operation [45,47–50] in the induction heating resonant inverters. Furthermore, the assembling procedure applied for half-bridge resonant inverters [46] implies that current equalisation for the self-resonant induction converters based on paralleled IGBTs can be easily achievable. All of the stated suggestions require additional analytical and experimental research as such has not been found in the literature. Some statistical information about the parameters' dispersion of IGBT modules is given in [50], but no analysis or experimental data have been found for discrete transistors.

As a conclusion from the presented literature review: the self-resonant converters for induction heating [21–24] are an applicable technology giving reliable and budget-friendly solutions; induction heating inverters, with an installed power higher than 10–15 kW for industrial and laboratory research purposes [29–31], can be constructed by IGBT transistors connected in parallel, but the literature presenting such applications specifically

for self-resonated inverters is insufficient; although the paralleling of transistors is an object of significant research [40–44], the application of this topology in the self-resonance architectures requires additional investigation. In general, from the literature, it is clear that the topology of self-resonant inverters for induction crucible melting furnaces has the potential to reach higher powers with paralleled transistors. However, the undesirable phenomena caused by transistors' parameters mismatches are not well described in the literature specifically for this application. Furthermore, the parallel operation in the resonant inverters can cause problems such as uneven current allocation, operation outside the ZVS region and major malfunction.

Based on the presented literature findings, the primary purpose of the suggested research was to experimentally show the possibility of resonant inverters with paralleled IGBTs operating with improved characteristics. For this purpose, a methodology for the analysis of transistors' characteristics was developed, giving a precise estimation of the paralleling IGBTs abilities. The presented approach estimated the derating factors and the expected current share through digitalising the graphical data and conducting a thorough analysis.

The paper is organised as follows: Section 2 shows an analysis of the modified selfresonated inverter based on the suggested methodology for analysis of the transistors connected in parallel; Section 3 shows an experimental verification; the conclusions are presented in Section 4.

#### **2. Analysis of the Investigated Inverter, Based on RC-IGBTs in Parallel**

The self-resonated converter is shown in Figure 1. The object of this research was the power stage of the inverter, which is part of the entire system presented with a block diagram. The further analysis and the experimental model presented in Section 3 were completed with discrete RC-IGBTs. In this circuit, it is necessary for the transistors' emitters to be connected at a common point (GND); off-the-shelf half-bridge IGBT modules would not be suitable. Analysing the IGBTs currently available on the market, the targeted power for the designed crucible melting induction system in a range of 20–30 kW, with a potential to reach 50 kW, could be achieved with 3 to 8 high and low side transistors connected in parallel. Such a circuit applies the necessity of a precise analysis of the IGBTs parameters to be undertaken due to the specific parasitic elements that the discrete packages, usually TO-247, TO263, etc., and their modification typically have. The gate drive circuits are based on optical drivers to supply the necessary gate drive current. An additional obstacle is the lack of information about the expected mismatch of transistors' parameters in a production lot, usually not published by the manufacturers.

The block diagram presented in Figure 1 is arranged as follows: (1) the three-phase rectifier and power factor correction (PFC) module are based on a full-bridge circuit, followed by a Boost PFC converter controlled by an ASIC (Application Special Integrated Circuit); (2) the Buck converter is a transformer-less PWM converter, but for safety purposes, a transformer-based full-bridge converter can be considered; (3) the resonant inverter was the object of this research, depicted in the power circuit. As the circuit is self-resonated, the control module operates as overcurrent and overvoltage protection, with the functionality to shut down the inverter; (4) the feedback from the inductor is performed by isolated current and voltage sensors; (5) the control and protection system is based on an STM microcontroller, including feedback networks from each module.

**Figure 1.** The electronic circuit of the proposed inverter for induction heating crucible melting furnace. Q1-Q8 IGBT transistors; GD1-GD8 gate drivers; C1, L1, L2 resonance tank; L3 induction heating inductor. A block diagram of the entire system for induction heating.

The steady-state and transient conditions caused, respectively, by the saturation collector-emitter voltage *VCE*(*sat*) and the variations in the gate-emitter threshold voltage *VGE*(*th*) of the IGBTs connected in parallel and, associated with them, thermal dependencies, are the most critical parameters, which must be analysed. The suggested methodology was focused on in the analysis of the variations in the transistors' parameters and the estimation of the probable current mismatch, which was designed in several steps as follows [51–55]: Step 1. Estimating the necessary derating factor and total current.

Calculation of the derating factor Δ:

$$\Delta = 1 - \frac{I\_{\text{max}}}{N\_{\text{paralle}} \times I\_{IGBTmax}} \tag{1}$$

where *Imax* is the maximum current through all transistors connected in parallel, *Nparallel* is the number of IGBT transistors in parallel, connected in the high or low side of the circuit given in Figure 1, *IIGBTmax* is the maximum current per IGBT transistor. The result from this equation under the satisfactory deration requires the number of transistors or *IIGBTmax* to be increased.

At a given derating factor, the total current in a parallel *ITotal* is:

$$I\_{Total} = (1 - \Delta) \times N\_{parallel} \times I\_{IGBTmax} \tag{2}$$

For the designed and experimentally tested inverter for induction heating, the maximum current of *Imax* = 160 *A* is assumed. Equation (1) is calculated for 2 to 6 transistors in parallel, and the derating factor is in the range Δ = 0.1 − 0.5; the result is depicted in Figure 2A. Following the recommendations given by IGBT manufacturers and the industrial research on induction heating [45–47], as a first assumption, a derating factor of

Δ = 0.2 is accepted. A suitable transistor technology for a resonant inverter can be chosen (Trenchstop, Trench gate field-stop, etc., RC-IGBT [48,49]) with Positive Thermal Coefficient (PTC). Considering the current ranges for the discrete IGBT transistors, assembled in TO-247, TO-3PN, TO-264, etc. packages, the feasible current capacity would be 50–160 A, as shown in Figure 1. With this assumption, four transistors are accepted for this design. The analysis shows that the datasheet transistor current must be selected at *IC* = 50 A (Figure 2A), the expected current through each transistor is 40 A (Figure 2B) calculated from Equation (2), and the specific derating factor is Δ = 0.2 (Figure 2C). Several IGBTs, which have been used for the analysis and experimental verification, are presented in Table A1, Appendix A.

**Figure 2.** Analysis of the number of IGBTs in parallel. (**A**) Number of transistors in parallel calculated in a derating range Δ = 0.1 − 0.5, giving the necessary nominal current per transistor; (**B**) expected current through each transistor at the assumed maximum current of *Imax* = 160 A; (**C**) the targeted derating of Δ = 0.2, i.e., 20%, is feasible with *ICEnom* = 50 A, 4 IGBTs in parallel.

Step 2. Selecting the IGBT, digitalising the necessary datasheet graphics and analysing the obtained data.

The critical parameters for this analysis, given in the datasheets as diagrams, are shown as examples in Figure 3 as the transconductance characteristic (Figure 3A) and the output characteristic (Figure 3B).

**Figure 3.** (**A**) IGBT transconductance characteristic and its dependence on the temperature; NTC— Negative Thermal Coefficient; PTC—Positive Thermal Coefficient; ITP—Isothermal Point; (**B**) IGBT output characteristics and its dependence on the temperature.

Using the IGBTs datasheet in the design procedure shows several problems that prevent a precise analysis of the paralleled transistors from being completed:


The suggested methodology offers a solution to the stated problems as follows:


**Figure 4.** (**A**) Transconductance (dynamic) characteristics at nominal 25 ◦C (graphic 1 maximum and 2 minimum) and maximum 150 ◦C (graphic 3 maximum and 4 minimum) temperatures. (**B**) Output (static) characteristics at nominal 25 ◦C (graphic 1 maximum and 2 minimum) and maximum 150 ◦C (graphic 3 maximum and 4 minimum) temperatures.

The equations, products of the trend analysis obtained from the IGBTs datasheet (Figure 3), would be a polynomial of 4–6 degrees in order for the parameters to be described with greater precision.

Nominal transconductance characteristic, at nominal temperature 25 ◦ C (Figure 3):

$$I\_C = \left(0.0091 \times V\_{GE}^5\right) + \left(-0.1009 \times V\_{GE}^4\right) + \left(-3.6877 \times V\_{GE}^3\right) + \left(82.845 \times V\_{GE}^2\right) + \left(-571.73 \times V\_{GE}\right) + 1300.2 \tag{3}$$

Maximum transconductance characteristic (Figure 4, graphic 1), i.e., +5% from Equation (3):

$$I\_{\mathbb{C}} = \left(0.0096 \times V\_{\text{GE}}^5\right) + \left(-0.106 \times V\_{\text{GE}}^4\right) + \left(-3.8721 \times V\_{\text{GE}}^3\right) + \left(86.988 \times V\_{\text{GE}}^2\right) + \left(-600.32 \times V\_{\text{GE}}\right) + 1365.2 \quad \text{(4)}$$

Minimum transconductance characteristic (Figure 4, graphic 2), i.e., −5% from Equation (3):

$$I\_C = \left(0.0087 \times V\_{GE}^5\right) + \left(-0.0959 \times V\_{GE}^4\right) + \left(-3.5033 \times V\_{GE}^3\right) + \left(78.703 \times V\_{GE}^2\right) + \left(-543.15 \times V\_{GE}\right) + 1235.2 \quad \text{(5)}$$

Nominal transconductance characteristic, at high temperature 150 ◦ C (Figure 3):

$$I\_C = \left(-0.0278 \times V\_{GE}^5\right) + \left(1.2169 \times V\_{GE}^4\right) + \left(-21.274 \times V\_{GE}^3\right) + \left(186.96 \times V\_{GE}^2\right) + \left(-812.84 \times V\_{GE}\right) + 1381.6 \quad \text{(6)}$$

Maximum transconductance characteristic (Figure 4, graphic 3), i.e., +5% from Equation (6):

*IC* = <sup>−</sup>0.0292 <sup>×</sup> *<sup>V</sup>*<sup>5</sup> *GE* + 1.2777 <sup>×</sup> *<sup>V</sup>*<sup>4</sup> *GE* + <sup>−</sup>22.338 <sup>×</sup> *<sup>V</sup>*<sup>3</sup> *GE* + 196.31 <sup>×</sup> *<sup>V</sup>*<sup>2</sup> *GE* +(−853.48 × *VGE*) + 1450.6 (7)

Maximum transconductance characteristic (Figure 4, graphic 4), i.e., −5% from Equation (6):

$$I\_{\mathbb{C}} = \left(-0.0264 \times V\_{\text{GE}}^5\right) + \left(1.156 \times V\_{\text{GE}}^4\right) + \left(-20.211 \times V\_{\text{GE}}^3\right) + \left(177.61 \times V\_{\text{GE}}^2\right) + \left(-772.2 \times V\_{\text{GE}}\right) + 1312.5 \tag{8}$$

The derived equations are presented as matrices in Table 1. Such a format is suitable for calculation with a simple Matlab script, shown in Listing A1 the Appendix A. The designed converter is depicted in Figure 4 as *Vge* = 9 V, and the expected maximum collector current due to the temperature and parameters variation would be *ICmax*(150◦ C,*min*) = 40.91 A, *ICmax*(150◦ C, *max*) = 44.75 A, *ICmax*(25◦ C,*min*) = 52.41 A, and *ICmax*(25◦ C,*max*) = 56.99 A. This analysis shows that the current can vary by 16 A under the worst-case conditions, i.e., if the paralleled transistors operate at the minimum and maximum temperature, assembled on different heatsinks and operating under specific cooling conditions, etc. Although such a thermal condition is less probable to be established, the correct design must consider it. If the paralleled transistors shared the same thermal conditions at the maximum temperature, the maximum current mismatch would be 4.58 A, i.e., under 20% of the maximum current. It can be expected that the accepted Δ = 0.2 would be a correct assumption.



Following the same data presentation format, the necessary equations for the static transistor's characteristics are given in Table 2. At the calculated points, the selected transistor would operate with PTC, considering the variations in the ITP under the worstcase conditions shown in Figure 4A. The voltage collector-emitter at the nominal expected current through each transistor of *IC* = 40 A (Figure 4B) is *VCE*(*sat* <sup>25</sup>◦ <sup>C</sup> *max*) = 2.22 V, *VCE*(*sat* <sup>25</sup>◦ <sup>C</sup> *min*) = 2.29 V, *VCE*(*sat* <sup>150</sup>◦ <sup>C</sup> *max*) = 2.71 V, and *VCE*(*sat* <sup>150</sup>◦ <sup>C</sup> *max*) = 2.83 V. The result shows that the expected conductive losses, which are the primary losses for the analysed ZVS inverter, are feasible for the TO-273 transistor package and its modifications, as shown in Table A1, Appendix A.


**Table 2.** Digitalisation of the output characteristics shown in Figure 4B.

Step 3. Analysing the mismatch and the derating factor for the stationary and dynamic transistors' characteristics.

The mismatch factor M can be estimated from the maximum and minimum current at the given conditions from the equation:

$$M = \frac{I\_{\mathbb{C}\\_\max} - I\_{\mathbb{C}\\_\min}}{I\_{\mathbb{C}\\_\max}} \tag{9}$$

where *IC max* and *IC min* are the maximum and minimum current per IGBT transistor in parallel, respectively, calculated in Step 2.

Having the mismatch factor M and the accepted IGBTs in parallel, Equation (1) about the derating factor Δ can be presented as:

$$\Delta = 1 - \frac{\left(N\_{parallel} - 1\right)(1 - \mathcal{M}) + 1}{N\_{parallel}} \tag{10}$$

The result from Equations (9) and (10) is depicted in Figure 5. In the range *Vge* = 9–10 V, the derating factor varies in the range Δ = 0.12–0.21 under the worst-case conditions, which would occur at nonthermal equivalence amongst the transistors (Figure 5A, graphic 1). The result shows that the accepted Δ = 0.20 at Step 1, Equation (1), is a correct assumption. If the paralleled transistors share the same thermal equilibrium, the necessary derating factor would be in the range Δ = 0.034–0.053, i.e., 3.4%–5.3%. Under these conditions, the system based on a 20% derating factor, matching the probable worst-case condition, would be oversized under thermal equalisation. This result is supported by an expression of the

current difference in Figure 5B—graphic 1 shows the maximum current difference under the worst-case conditions and graphic 2 at thermal equalisation.

**Figure 5.** (**A**) Expected variation in the derating factor; (**B**) expected variation in the maximum current through the paralleled transistors. Graphics 1 and 2 at maximum and minimum thermal difference.

Step 4. Analysis of the single IGBT transistor parameters and the relevant selection requirements.

After the expected current through each transistor in parallel is found from the presented equations above with the necessary safety margin, the transistors can be selected according to several considerations about their basic parameters.

The continuous collector current through a single transistor must be considered according to the expected junction temperature as:

$$I\_{\mathbb{C}} = \frac{\left(T\_{\circ \max} - T\_{\mathbb{C}}\right)}{V\_{\mathbb{C}E} \times R\_{th(J-\mathbb{C})}}\tag{11}$$

where *Tj max* is the maximum junction temperature; *TC* is the case temperature; *VCE* is the collector-emitter saturation voltage at *IC*; *Rth*(*J*−*C*) is the junction-case thermal resistance of the transistor.

The peak collector current should be selected to be at least two times the nominal collector current for 1 ms at the maximum temperature.

$$I\_{PK} = 2 \times I\_{\mathbb{C}} \tag{12}$$

The maximum dissipated power from a single IGBT transistor can be calculated from:

$$P\_{\text{max}\,IGBT} = \frac{\left(T\_{j\,max} - T\_{\text{C}}\right)}{R\_{th(J-\text{C})}}\tag{13}$$

As the analysed inverter naturally operates with ZVS and, hence, low switching losses, the selected transistors according to the necessary collector current and collector-emitter voltage usually cause an overrating in the power dissipation. This explains the relatively small-size heatsinks combined with forced convection, shown in the next part.

The switching losses during the transistors ON and OFF time depend on the amount of energy, respectively, *Eon* and *Eoff* . The analysis can be conducted according to the following equations:

$$E\_{\rm ou} = \int\_{T\_{\rm ou1}}^{T\_{\rm ou2}} V\_{\rm CE}(t) \times I\_{\rm C}(t) \, dt \tag{14}$$

$$E\_{off} = \int\_{T\_{off1}}^{T\_{off2}} V\_{\rm CE}(t) \times I\_{\rm C}(t) \, dt \tag{15}$$

where the times *Ton*1, *Ton*2, *Toff* 1, *Toff* <sup>2</sup> are, respectively, the beginning and the end of the ON and OFF periods.

As the converter operates with ZVS, the *VCE* voltages during the ON and OFF switching will be comparable with the threshold *VGE*, and the times *Ton*<sup>2</sup> − *Ton*<sup>1</sup> and *Toff* <sup>2</sup> − *Toff* <sup>1</sup> are under 100 ns, confirmed experimentally in the next part. With this, the expected switching losses can be neglected, and the conduction losses can be accepted as dominant. Their calculation is according to the equation:

$$P\_{\rm cond} = V\_{\rm CE} \times I\_{\rm C} = R\_{\rm CE} \times I\_{\rm C}^2(\mathcal{W}) \tag{16}$$

For the considered packages above, TO-247, TO-3PN, and TO-264, transistors with several tens of milliohms *RCE* can be selected.

#### **3. Experimental Setup**

The experimental setup aimed to verify the designed inverter for induction heating based on paralleled IGBTs and the suggested methodology and to depict the current mismatch amongst the transistors experimentally. The experimental study was conducted as follows: converters were designed with 3, 4 and 5 transistors in parallel per side (Figure 1) following the presented step-by-step methodology in point 2; converters were manufactured using IGBTs listed in Table 1 Applications, using transistors from the same and different production lots; the derating factors and expected current mismatch were analysed according to the nominal current per inverter; the currents were measured through each transistor in parallel at full load during the entire melting cycle; the thermal differences were measured with an infrared camera on the heatsink surface. In addition, the layout and inductor construction improvements were implemented, leading to the minimisation of the oscillations.

Figure 6 shows an experimental model of the self-resonant converter for induction heating with its main components: 8 GIBT transistors, connected according to Figure 1; forced air cooling system with fans; resonant capacitor tank, inductor; and graphene crucible. The 4 selected transistors per side were considered according to previously presented Equations (1)–(16) with a current derating factor of 20%.

**Figure 6.** A model of self-resonant converter for induction heating: 1—IGBT transistors; 2—resonant capacitor tank; 3—inductor; 4—graphene crucible. The used measurement equipment is as follows: oscilloscope RS PRO RSDS1204CFL; current probe ELDITEST CP6220; voltage differential probe Pico.

The experimental study was conducted at the maximum converter power to depict the current mismatch under worst-case conditions. The results are illustrated with oscillograms, as follows:


number equal to the number of paralleled transistors sections. With this, the inductors L1, L3, L5 and L7 from the high side and L2, L4, L6 and L8 from the low side correspond to inductors L1 and L2 from Figure 1. Capacitors C1-C4, in summary, represent capacitor C1 from the resonant tangent in Figure 1. Although the effect of parasitics minimisation was experimentally observed, giving the inverter's stable operation, this part requires future research and improvements.

**Figure 7.** Current mismatch amongst four paralleled IGBT transistors. (**A**,**B**) switched-on with a delay of transistor 4; (**C**) switched-on prematurely of transistor 4; 1, 2—transistors with the same production lot; 3, 4—two different production lots.

**Figure 8.** Minimum current mismatch amongst four IGBT transistors from the same production lot.

**Figure 9.** Operation of the inverter for induction heating. (**A**,**B**) 1, 2—voltages, respectively, over the paralleled high side (Q1, Q3, Q5, Q7—Figure 1) and low side (Q2, Q4, Q6, Q8—Figure 1) transistors; 3—current through the inductor; (**B**): 4—voltage crossing the zero switching point.

**Figure 10.** Improving the converter construction, given in Figure 6.

**Figure 11.** Infrared temperature measurements on the surface of the heatsink. (**A**,**C**) Appropriately selected transistors from the same production lot (Figure 7, graphics 1, 2); (**B**,**D**) transistors from different production lots (Figure 7 graphics 1, 4). The thermal measurements were performed with the infrared camera FLIR.

**Figure 12.** Transistors thermal difference for one melting cycle of 10 min. (**A**) Between transistors Q1 and Q4; (**B**) between transistors Q1 and Q2, both selected according to Figure 7A.

**Figure 13.** Infrared image of the graphene crucible, given in Figure 6.

**Figure 14.** Oscillations due to PCB layout issues.

**Figure 15.** A suggested structure of connection.

#### **4. Discussion**

The provided experimental verification was performed with a resonant inverter for induction heating (Figure 6). As the main contribution in this research, the result showed that such a topology (Figure 1) can be completed with paralleled IGBTs, operating with low mismatch current and acceptable current difference amongst the transistors, which is supported by the presented oscillograms (Figures 7–9). The achieved current sharing amongst the paralleled IGBTs makes the ZVS mode of operation possible for a resonant inverter with paralleled transistors, which is the main advantage of the investigated topology. The presented results showed the feasibility of the investigated topology for improving the installed power of the self-resonant inverters for induction heating. As it was experimentally shown that the installed capacity can reach more than 30 kW with four IGBTs in parallel per side of the topology, it can be concluded that such a modification is applicable for small laboratory or industrial induction crucible furnaces.

The suggested methodology for analysing the paralleled IGBT transistors is based on stipulated conditions in which the transistors' static and dynamic parameters (Figure 3) are digitalised into polynomial Equations (3)–(8). The calculating procedure shows the expected parameters dispersion in a production lot (Figure 4). As a result, the necessary derating factor, the current mismatch, and the current difference amongst the paralleled transistors can be suggested (Figure 5). With this, the number of the necessary transistors in parallel can be calculated on the design level for the given application.

The temperature difference between the paralleled IGBTs, which results from the current mismatch, was in an acceptable range of several degrees Celsius. This final experiment verified the applicability of the suggested topology.

#### **5. Conclusions**

In this study, a methodology of the IGBTs' parallel work estimation and its application in the design procedure of a self-resonant inverter for a crucible induction system was demonstrated. The presented step-by-step approach showed satisfactory results, giving the required derating factors and current mismatch between the transistors.

The investigated self-resonant converter based on paralleled transistors was applied to an induction crucible melting system. It was shown that the presented circuit has a stable operation mode in ZVS with paralleled transistors. The conducted experiments showed a satisfactory current share and temperature equalisation. It can be concluded that the circuit has the magnitude to reach an installed power of 50–80 kW with several powerful modules in parallel, giving budget-friendly induction melting systems with inverters with high power density.

The suggested methodology was based on stipulated data, i.e., Equations (3)–(6) were derived only for the concrete transistor, and it did not have diverse characteristics. Despite that, such an approach for analysis is highly applicable for practical design and experimental verification.

**Author Contributions:** Conceptualization, B.D.; methodology, B.D., K.H., S.B., G.C.; software, B.D.; validation, B.D.; formal analysis, B.D.; investigation, B.D.; resources, G.C.; data curation, B.D., K.H., S.B.; writing—original draft preparation, B.D.; writing—review and editing, K.H., S.B.; visualization, B.D.; supervision, G.C., K.H.; project administration, G.C.; funding acquisition, N/A. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research received no external funding.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** Not applicable.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **Appendix A**

**Table A1.** IGBT transistors, suitable for experimental verification with resonant inverters for induction heating, operating with PTC.


Listing A1. Calculating the collector-emitter current (Ic) with polyval function in MATLAB:


#### **References**


**Fabio Corti 1,2,\*, Alberto Reatti 2, Gabriele Maria Lozito 2, Ermanno Cardelli <sup>1</sup> and Antonino Laudani <sup>3</sup>**


**Abstract:** In this paper, the problem of estimating the core losses for inductive components is addressed. A novel methodology is applied to estimate the core losses of an inductor in a DC-DC converter in the time-domain. The methodology addresses both the non-linearity and dynamic behavior of the core magnetic material and the non-uniformity of the field distribution for the device geometry. The methodology is natively implemented using the LTSpice simulation environment and can be used to include an accurate behavioral model of the magnetic devices in a more complex lumped circuit. The methodology is compared against classic estimation techniques such as Steinmetz Equation and the improved Generalized Steinmetz Equation. The validation is performed on a practical DC-DC Buck converter, which was utilized to experimentally verify the results derived by a model suitable to estimate the inductor losses. Both simulation and experimental test confirm the accuracy of the proposed methodology. Thus, the proposed technique can be flexibly used both for direct core loss estimation and the realization of a subsystem able to simulate the realistic behavior of an inductor within a more complex lumped circuit.

**Keywords:** dynamic magnetic losses; ferrite core; core losses measurement; spice equivalent circuit

#### **1. Introduction**

DC-DC power converters are widely used in many electrical and electronic applications. The diffusion of wide-bandgap semiconductors, characterized by fast switching transients is increasing the operating frequency of DC-DC converters allowing for higher power densities [1–3].

Magnetic components are the bulkiest components of power converters, and their design must be accurate to avoid excessive weights and volumes [4]. Much effort has been spent in investigating the inductor losses generated in its winding and on its core [5]. The latter can result in both non-linear and dynamic behavior, because of the saturation and magnetic hysteresis phenomena [6]. This behavior is, in general, due to the material [7]. Considering the device geometry (i.e., the magnetic core shape), additional complexity arises due to the non-uniform distribution of the magnetic induction field across the core section, and this issue has only been partially investigated [8]. Considering these factors during the design of power converters is very difficult. For this reason, some manufacturers aim at constructive solutions that make the behavior of the magnetic component as simple as possible. In addition, they are looking for solutions with uniform distribution of magnetic field [9].

By neglecting the non-uniform magnetic induction distribution and only referring to the component data sheets, the designers are guided to choose a non-optimal magnetic

**Citation:** Corti, F.; Reatti, A.; Lozito, G.M.; Cardelli, E.; Laudani, A. Influence of Non-Linearity in Losses Estimation of Magnetic Components for DC-DC Converters. *Energies* **2021**, *14*, 6498. https://doi.org/10.3390/ en14206498

Academic Editor: Hongwen He

Received: 12 August 2021 Accepted: 8 October 2021 Published: 11 October 2021

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**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

component, which, under practical operating conditions, results in a worse performance than expected. Moreover, it results in oversized and overweight designs [10–13].

An optimal sizing can be achieved through calculation tools able to consider nonlinearity, magnetic hysteresis, and the real non-uniform distribution of the magnetic induction in the component core, with acceptable accuracy [14–16].

The modeling of non-linearity and hysteresis in magnetic materials is achieved with different deterministic approaches, both at the micromagnetic and macromagnetic levels, but also with stochastic approaches based on specific applications of artificial intelligence [17]. The determination of distribution of magnetic field inside an inductor core is also possible by using numerical tools based on finite element methods [18,19].

Many difficulties need to be overcome when both the non-linearity, the magnetic hysteresis, and the distribution of the magnetic induction in the core must be considered in a time-domain simulation [20].

The dominant problem is that the magnetic component analysis must be set in the time-domain, and due to the non-linear nature of the equations regulating its behavior, the numerical solution (i.e., the response of the material/device) must be obtained with iterative methods. If the core geometry is considered, the discretization through the meshes of the magnetic core must be sufficiently dense [21]. Assuming this magnetic component is part of a larger time-domain simulation (e.g., a power converter), this computational process is repeated for every time-step of the simulation, resulting in a very computationally demanding scenario [22]. The computational burden of the simulation is often further increased by the very short time steps chosen to avoid numerical instability.

An interesting approach to estimate the dynamic power losses is given in [23], where the losses are calculated by a specifically designed Spice circuit, which considers the dynamic power losses. This approach is based on a model which is useful for the simulation of the behavior of DC-DC converters and allows the magnetic non-linearity to be considered along with the hysteresis and the non-uniformity of the magnetic induction. In [23], the operation of the core close to the saturation point is not considered, and this yields inaccuracies in the determination of the inductor current waveforms, which are strongly distorted in DC-DC converters. This problem has been faced in an improved model where the capability of reproducing magnetic hysteresis cycles has been introduced by referring to the non-linear behavior of the material when operated near the magnetic saturation point [24].

This paper aims to apply the approach utilized in [24], for the investigation of a DC-DC Buck converter. The proposed work focuses on the proposed model consistency when embedded in a larger design simulation. To validate this methodology, an experimental Buck converter circuit was built, and current measurements were acquired in the choke inductor. Core losses were estimated through three different techniques: the first one is based on the classic Steinmetz Equation (SE), which considers the frequency behavior of the material, yet lacks the capability of time-domain simulation under arbitrarily distorted waveforms. The second is the improved Generalized Steinmetz Equation (iGSE) technique, which introduces a methodology to apply the SE to a time-domain simulation under distorted waveform but lacks the geometric account for non-uniform field distribution in the device. The last one is the Time-Domain Core Loss with Non-Uniform Field (TDNU) technique based in the model as given in [24,25]. This technique seems also to be promising to be included in high component number circuit designs and can benefit from the optimized integration engines coupled with circuit simulation software. The paper is structured as follows. First, the two state-of-the-art methodologies used for the comparison are discussed. Then, the proposed methodology is presented, underlying the improvements introduced with respect to the classic literature approaches. In the following section, the DC-DC Buck converter design and the experimental workbench implementation are described, with particular attention to the inductor characteristics and the algorithmic approach used to estimate the losses using the three techniques. Measurements and estimated losses are then presented, along with the reconstructed hysteresis profiles, for a DC-DC Buck

converter operated under different operating conditions. Conclusion and final remarks close the manuscript.

#### **2. Steinmetz Equations and Improved Generalized Steinmetz Approach**

Core loss estimation can be achieved through the direct application of the Steinmetz equation. This equation relates the losses to the frequency of the excitation and the intensity of the magnetic induction, and thanks to its simplicity, represents a good method to predict the core losses under sinusoidal excitation. The average power loss is given by

$$P = \mathbb{C}\_m f^n B\_m^\beta \tag{1}$$

where *Cm*, α and *β* are the Steinmetz coefficients, *f* is the frequency of the excitation and *Bm* is the RMS value of the core magnetic flux density [26–28]. The main limit of this formula is that it results in an accurate estimation only under sinusoidal induction [26,27]. This limitation makes this formula difficult to use in time-domain simulations of non-linear devices operated at distorted currents (and, thus, H-B fields). To solve this limitation, several models were proposed. One of the most promising one is that based on the improved Generalized Steinmetz Equation (iGSE) [29,30].

Here, the average core loss is computed as

$$P = \frac{1}{T} \int\_0^T |k\_i| \left| \frac{dB}{dt} \right|^\alpha |B\_m|^{\beta - \alpha} dt \tag{2}$$

where *Bm* is the peak-to-peak flux density and

$$k\_i = \frac{\mathbb{C}\_m}{(2\pi)^{a-1} \int\_0^{2\pi} |\cos(\theta)|^a 2^{\beta-a} d\theta} \tag{3}$$

This methodology accounts for an arbitrarily time-varying magnetic field, and for this reason, it is suitable for inclusion in time-domain simulation of magnetic materials. However, iGSE assumes a uniform distribution of the magnetic induction inside the core. It can be noted that the iGSE technique, differently from the SE approach, allows for a time-domain estimation of the core losses and can be therefore implemented in Spice environment.

#### **3. Time-Domain Core Loss with Non-Uniform Field (TDNU)**

A more recent method utilized to obtain a Time-Domain Core Loss estimation under non-sinusoidal excitation was presented in [23,24]. This approach allows to estimate the core power losses by using a time-domain approach rather than one based on a frequency-domain analysis. As a result, non-linearities can be considered, and estimations can be performed even with non-sinusoidal waveforms. In addition, by estimating the instantaneous power loss *p*(*t*), it is possible to predict the core losses during both the transient and steady-state operation. In addition, this approach takes into account the non-uniform magnetic field distribution inside the magnetic core. The instantaneous core loss is derived as

$$p(t) = \frac{C\_m}{C\_{a\mathcal{G}}} |B\_m \cos \theta|^{(\beta - a)} \left| \frac{dB\_{eff}}{dt} \right|,\tag{4}$$

where

$$\mathbb{C}\_{\mathfrak{a}\mathfrak{f}} = (2\pi)^{a} \frac{2}{\pi} \int\_{0}^{\pi/2} (\cos \theta)^{a} d\theta \,\,\tag{5}$$

and *Beff* represents an equivalent flux density which considers the shape and the geometry of the core and approximates the effects of the non-uniformity of the magnetic field inside the core. This method consists of matching the area formed by an equivalent elliptical loop with the original hysteresis loop starting from the standard core loss coefficients. In (5), the parameter *cos ϑ* is computed as

$$\cos\theta(t) = \sqrt{1 - \left(\frac{B\_{eff}(t) - B\_{DC}}{B\_m}\right)}\tag{6}$$

where *BDC* represents the DC induction bias. To compute the effective magnetic flux density *Beff*, a parameter Δ, called "field factor", is defined. This parameter depends on the magnetic core geometry and material, and relates the effective flux density with the current through the inductor according to

$$B\_{eff}(t) = \Delta \cdot I(t). \tag{7}$$

For a toroidal core, the field factor can be calculated as in [24]

$$
\Delta = \left(\frac{(\mu N)^{\beta} (2\pi)^{(1-\beta)} \frac{1}{2-\beta} \left(R\_o^{(2-\beta)} - R\_i^{(2-\beta)}\right)}{\pi \left(R\_O^2 - R\_i^2\right)}\right)^{\frac{1}{\beta}} \tag{8}
$$

where *μ= μ<sup>0</sup> μ<sup>r</sup>* is the magnetic material permeability, *N* is the number of turns, and *Ro* and *Ri* are the outer and inner radius of the toroidal core.

Note that if *β* = 1, the field factor simplifies as

$$
\Delta = \frac{\mu N}{\pi \left(R\_O^2 - R\_i^2\right)}\tag{9}
$$

Under this condition, (7) becomes

$$B\_{eff}(t) = \frac{\mu N}{\pi \left(R\_O^2 - R\_i^2\right)} \cdot I(t) . \tag{10}$$

which fully describes the case with a uniform magnetic field distribution. To properly compute the power loss *p*(t) given by (4), the actual values of *Bm* and *BDC* must be cyclically updated. Since the proposed method works in the time-domain, the wipe out rule method is used: when the derivate of the magnetic flux density *dBeff*/*dt* is zero, a maximum *B*max or a minimum *B*min value of the actual hysteresis loop is reached and, therefore, the values of *BDC* and *Bm* are updated for a correct estimation of the power loss.

This technique has an important improvement which is of fundamental importance to perform time-domain simulations: in iGSE technique the estimation of the core loss is based on the knowledge of the mean average value of the magnetic flux *B*(*t*), while the method described in this section uses the effective magnetic flux *Beff* which is estimated by using (7). Moreover, this approach can be used in a lumped elements circuit and, also, it allows the SPICE subsystem modeling the inductor to be integrated in a more complex circuit, as shown in Figure 1. A detailed description of the LTSpice circuit used to compute the time-domain core power loss can be found in [24].

In the next sections, starting from the measurements of a DC-DC Buck converter prototype, a comparison between the power core losses on the inductor using the Steinmetz Equation, the iGSE and the proposed approach is presented.

**Figure 1.** LTSpice circuit for Time-Domain Core Loss estimation based on wipe out rule [24]. The red dotted box includes the equivalent lumped circuit of the DC-DC converter. The blocks used for the real time core loss estimation are shown inside the blue box.

#### **4. The Case Study: A DC-DC Buck Converter**

To practically evaluate the accuracy of the three different techniques, the core loss on the inductor of a DC-DC Buck converter was analyzed. The electrical circuit of the buck converter is shown in Figure 2.

**Figure 2.** Buck converter unidirectional topology.

The KIT-CRD-3DD065P, Buck-Boost Evaluation Kit [31] was used to realize the experimental converter. The components are summarized in Table 1.



Different operating frequencies and duty cycles were used to understand the performance of each core loss estimation technique and perform a comparison of their results. Indeed, the proposed topology works with unidirectional behavior. This turns out in a simpler driving system but excludes the possibility to evaluate the magnetic losses of typical bidirectional topologies. However, from the point of view of the core losses, the resulting waveforms will still include both the CCM and DCM condition, resulting in a complete behavioral analysis of the phenomenon.

#### *4.1. Inductor Characteristics*

The inductor of Cree's KIT-CRD-3DD065P Buck-Boost Evaluation Kit [31] is based on a toroidal high temperature rated powdered core, which results in a CWS-1SN-12877 inductor; the core material is KoolMu [32]. The geometric characteristics of the core are summarized in Table 2 along with the winding number of turns.

**Table 2.** Inductor characteristics.


The anhysteretic curve of the magnetic core and the magnetic permeability are shown in Figure 3a,b, respectively.

**Figure 3.** Magnetic characteristics of the toroidal core. (**a**) BH curve and permeability. (**b**) Magnetic permeability curve.

The core Steinmetz coefficient are summarized in Table 3.

**Table 3.** Steinmetz parameters from manufacturer.


By using in (5) the parameter values shown in Table 2, a coefficient *Cαβ* = 8.51 is obtained. The curve giving the magnetic core permeability *μ* shown in Figure 3 can be interpolated and expressed as a function of the magnetic field as follows

$$\mu = \frac{N(H)}{D(H)} = \frac{n\_1 H^3 + n\_2 H^2 + n\_3 H + n\_4}{d\_1 H^3 + d\_2 H^2 + d\_3 H + d\_4} \tag{11}$$

where, *<sup>n</sup>*<sup>1</sup> = 1.7650 × <sup>10</sup>−17, *<sup>n</sup>*<sup>2</sup> <sup>=</sup> −1.8125 × <sup>10</sup>−12, *<sup>n</sup>*<sup>3</sup> = 2.551 × <sup>10</sup>−7, *<sup>n</sup>*<sup>4</sup> = 6.379 × <sup>10</sup>−5, *<sup>d</sup>*<sup>1</sup> = 1.4782 × <sup>10</sup>−11, *<sup>d</sup>*<sup>2</sup> = 5.520 × <sup>10</sup>−7, *<sup>d</sup>*<sup>3</sup> = 0.0017, and *<sup>d</sup>*<sup>4</sup> = 1. As shown in Figure 3b, where the black dotted trace represents the plot of (11) and the red trace shows the real

magnetic permeability the interpolation given by (7) perfectly matches the data sheet plot of the permeability.

#### *4.2. Core Loss Estimation Algorithms*

The Steinmetz procedure used to compute the core loss is summarized in the block diagram shown in Figure 4. The magnetic field *H* is deduced from the number of turns and the average axis of the toroidal core. Then, the magnetic field density *B(t)* is computed from the BH curve, and its RMS value is used in (1) to estimate the power core loss.

**Figure 4.** Core loss estimation using classical Steinmetz Equations.

The core loss procedure used by the iGSE technique is shown in Figure 5. The magnetic flux density and its derivative are calculated starting from the current *iL* and the BH curve. The Steinmetz coefficients are used to calculate the coefficient *ki* according to (3) and, finally, the core loss density is computed [29].

**Figure 5.** Core loss estimation using iGSE.

The procedure for the Time-Domain Core Loss density computed using the approach proposed in [23,24] is shown in Figure 6. As already discussed, the field factor is calculated from the Steinmetz coefficients and the core geometry. Then, the effective magnetic flux density is calculated from the current. Finally, the core loss density is computed by using (4).

**Figure 6.** Core loss estimation using non-uniform magnetic field density.

#### *4.3. Lossy Magnetic Hysteresis Cycle Reconstruction*

The induction *B(t)* computed by iGSE and TDNU is in phase with the inductor current *I (t)*. According to Lenz law, the inductor voltage *vL*(*t*) is in quadrature with the current, resulting in a null average power loss. This means that the B-H trajectory would present no hysteresis. This is in conflict with the actual losses that are estimated by the two methodologies. To resolve this conflict, an additional artificial current term *iLOSS*, in phase with the inductor voltage, must be considered. This term can be determined assuming an equivalent *R*-*L* parallel circuit model such as the one shown in Figure 7.

**Figure 7.** Equivalent lossy circuit model for H-B reconstruction.

In this circuit, the inductor is ideal, and the instantaneous power related to the core losses is absorbed by the resistive element. Expressing the quantities in a time-discrete domain, a loss current *iLOSS*[*k*] can be computed by the ratio between the computed losses *p*[*k*] and the instantaneous voltage across the inductor *vL*[*k*]. The latter can be computed from the numerical expression of the Lentz law. Although the magnetic field *H* is not measured in this setup, it is possible to assume that, together with the induction *B*, it should accommodate the instantaneous value of the losses.

$$w\_L[k] = NS\_t \frac{B[k] - B[k-1]}{t[k] - t[k-1]} \tag{12}$$

$$i\_{LOSS}[k] = \frac{p[k]}{v\_L[k]} \tag{13}$$

where *St* is the cross-section of the toroid. From the loss current, the loss-affected *H* field can is derived as

$$H[k] = \left( i\_{LOSS}[k] + i[k] \right) \frac{N}{\lambda} \tag{14}$$

where *λ* is the magnetic path length of the toroid core.

#### **5. Measurements and Simulation Results**

The proposed methodology is validated, both in experimental and simulated environment, through a series of different tests, aimed at assessing the consistency of the three techniques. In the first test, the inductor current used for the different loss estimation methodologies is acquired from an LTSpice simulation. In the second test, the inductor current is measured on the real DC-DC Buck converter. For both tests, the four operating conditions described in Table 4 are considered to explore different current waveforms of the inductor. These operating conditions allow to compare the core loss estimation under significative different operating conditions, considering both the CCM and DCM case. For each operating condition:



**Table 4.** Case studies operating conditions.

The DC-DC converter circuit model simulated by using LTSpice is shown in Figure 7. Simulations were performed as transient analysis with a minimum timestep of 10 ns to capture the high frequency non-linear dynamics of the switching components. For the same reason, parasitic inductances were added on the MOSFET, diode and output capacitor. The small timestep allowed a detailed reconstruction of the inductor current waveform, which is a critical aspect, because the current is directly related to *B* as shown in Figure 8, and the *B* is numerically differentiated, as shown in Figure 4, to compute the instantaneous power loss.

**Figure 8.** LTSpice simulation for the acquisition of the inductor current waveforms in different operating conditions of the power converter.

In Figures 9–12, the waveforms related to the Buck DC-DC converter operating in Case I, II, III and IV are shown, respectively. Each figure represents the inductor current, the instantaneous magnetic induction and the instantaneous losses.

**Figure 9.** Simulated DC-DC waveforms for Case I (*f* = 10 kHz *D* = 0.5): Inductor current, instantaneous magnetic induction *B*, instantaneous losses *p*. Red and blue traces are the waveforms relative to the TDNU and iGSE estimation methods, respectively.

**Figure 10.** Simulated DC-DC waveforms for Case II (*f* = 1 kHz *D* = 0.3): Inductor current, instantaneous magnetic induction *B*, instantaneous losses *p*. Red and blue traces are the waveforms relative to the TDNU and iGSE estimation methods, respectively.

**Figure 11.** Simulated DC-DC waveforms for Case III (*f* = 1 kHz *D* = 0.5): Inductor current, instantaneous magnetic induction *B*, instantaneous losses *p*. Red and blue traces are the waveforms relative to the TDNU and iGSE estimation methods, respectively.

**Figure 12.** Simulated DC-DC waveforms for Case IV (*f* = 1 kHz *D* = 0.8): Inductor current, instantaneous magnetic induction *B*, instantaneous losses *p*. Red and blue traces are the waveforms relative to the TDNU and iGSE estimation methods, respectively.

Different measurements at different operating frequencies and duty cycles were performed and the test parameters are shown in Table 4. The converter input voltage was fixed to *Vi* = 30 V, to reproduce conditions analogous to those used in the simulation test. Figure 13 shows the experimental setup used to measure the inductor current.

**Figure 13.** Experimental setup.

In Figures 14–17, the waveforms relative to the Buck DC-DC converter operating in Case I, II, III and IV are shown, respectively. Each figure represents the inductor current, the instantaneous magnetic induction field, the instantaneous losses, and the reconstructed lossy B-H profiles. In Table 5, the average losses for the four cases are compared between the methodologies. All the measured current waveforms are very close to the results predicted by the numerical simulations. The greatest difference between the simulated and measured data is for the Case I. This is mainly due to the highest operating frequency which increases the effect of the parasitic components. However, as shown in Table 5, the estimated core losses are consistent with those derived from the simulations. This leads to the conclusion that, even if the current waveforms might exhibit some differences, the computed core losses are not very sensible to these variations.

**Figure 14.** DC-DC waveforms for Case I (*f* = 10 kHz *D* = 0.5): Inductor current, instantaneous magnetic induction *B*, instantaneous losses *p*, reconstructed hysteresis loop. Red and blue traces are the waveforms relative to the TDNU and iGSE estimation methods, respectively.

**Figure 15.** DC-DC waveforms for Case II (*f* = 1 kHz *D* = 0.3): Inductor current, instantaneous magnetic induction *B*, instantaneous losses *p*, reconstructed hysteresis loop. Red and blue traces are the waveforms relative to the TDNU and iGSE estimation methods, respectively.

**Figure 16.** DC-DC waveforms for Case III (*f* = 1 kHz *D* = 0.5): Inductor current, instantaneous magnetic induction *B*, instantaneous losses *p*, reconstructed hysteresis loop. Red and blue traces are the waveforms relative to the TDNU and iGSE estimation methods, respectively.

**Figure 17.** DC-DC waveforms for Case IV (*f* = 1 kHz *D* = 0.8): Inductor current, instantaneous magnetic induction *B*, instantaneous losses *p*, reconstructed hysteresis loop. Red and blue traces are the waveforms relative to the TDNU and iGSE estimation methods, respectively.


**Table 5.** Core losses in the four operating conditions for experimental inductor currents.

Table 6 shows the average losses determined by using the current computed through simulation for the considered cases and methodologies. Table 6 shows the core losses derived by using the experimentally measured currents. The comparison is discussed in the conclusion section.

**Table 6.** Core losses in the four operating conditions for simulated inductor currents.


#### **6. Conclusions**

In this paper, a novel methodology for core losses estimation was compared against two state-of-the-art approaches in the study of a DC-DC power converter. Core loss estimation in time-domain is difficult due to non-linear, dynamic and geometrical phenomena involving the magnetic material. Moreover, practical applications such as power converters

usually involve non-sinusoidal excitations which further complicates the study. A unidirectional topology has been considered. The proposed methodology and the two comparison methodologies allowed the estimation of the core losses in the inductor of a DC-DC Buck converter by considering detailed magnetic behavior of the core. The obtained results showed that the TDNU methodology results in a core losses estimation comparable with the other methods, yet the estimations are usually slightly higher than others resulting from the compared methods, thanks to the ability of the TDNU to consider the field non-uniform distribution inside the core.

The proposed accurate core loss model leads to the possibility of including a real induction model inside the SPICE environment. This model is able to exhibit a consistent behavior considering core non-linearities. In fact, since the TDNU method is inherently a time-domain approach and is natively implemented in the form of a Spice circuit, it is a promising candidate to be included in larger circuit designs and can benefit from the optimized integration engines coupled with circuit simulation software.

**Author Contributions:** Conceptualization, E.C. and A.R.; methodology, F.C., A.L. and G.M.L.; software, F.C.; validation, A.R. and A.L.; investigation, F.C. and G.M.L.; data curation, F.C. and G.M.L.; writing—original draft preparation, F.C. and G.M.L.; writing—review and editing, E.C., A.L. and A.R.; supervision, E.C. and A.R. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research received no external funding.

**Acknowledgments:** We would like to thank Arrow Europe for providing us the Cree CRD-3DD065P Evaluation board.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


**Michael Chrysostomou 1,\*, Nicholas Christofides 1, Stelios Ioannou <sup>2</sup> and Alexis Polycarpou <sup>1</sup>**


**Abstract:** The rapid growth of the Information and Communications Technology (ICT) sector requires additional infrastructure, such as more micro-datacenters and telecom stations, to support the higher internet speeds and low latency requirements of 5G networks. The increased power requirements of the new ICT technologies necessitate the proposal of new power supplies, in an attempt to support the increase in energy demand and running costs. This work provides an in-depth theoretical analysis on the losses of the individual stages of commercially available PSU and proposes a new multicell PSU, the buck PFC converter, which offers a higher overall efficiency at varying load levels. The theoretical results are verified using simulation results, via a PSIM Thermal Module, and using experimental data. The results indicate that multicell structures can improve the overall PSU efficiency by 1.2% at 50% rated power and more than 2.1% at full power. Finally, taking into consideration the economic implications of this study, it is shown that the proposed multicell structure may increase the PSU costs by 10.78%, but the payback period is in the order of just 3.3 years.

**Keywords:** micro-datacenters; Information and Communications Technology (ICT); efficiency; multicell; power supply unit

#### **1. Introduction**

The 5G network requirements for the Information and Communication Technology (ICT) sector has caused a continuous demand for growth in micro-datacenter and Telecommunication Stations (TS) [1,2]. Datacenters accommodate the ICT data storage and processing equipment such as servers, hubs, hard discs, and ICT racks, etc. A micro-datacenter (μDC) is a datacenter of size smaller or equal to one rack. The growth of datacenters and micro-datacenters is huge nowadays and they have a great impact on global electricity consumption. In 2016, more than 1.8% of the global electrical energy was consumed by datacenters and this will keep increasing [3]. The higher speeds of radio frequency bands (such as 4G and 5G) tend to have a shorter area coverage and as a result more TS are needed. Furthermore, 5G networks have increased energy requirements compared to previous generations, and therefore several researchers have concentrated on improving the energy efficiency of communication links [4–6]. The increased number of TS and μDC will unavoidably lead to an increased energy consumption.

The impact of the power supply system to the overall energy efficiency of datacenters and TS has pushed several energy agencies to develop strict efficiency requirements, such as Energy Star and EPRI [7,8]. In the last two decades, the telecommunications industry has adopted equipment supplied by 48 V DC. In the Information Technology (IT) and Datacenter industries though, the preferred voltage system over the last few decades was 230 V AC, using though integral secondary power supplies for converting the AC 230 V to 12 V DC. With the IT and Telecom industry convergence of the last few years, both AC 230 V and DC 48 V systems were used, causing a debate as to which system would dominate

**Citation:** Chrysostomou, M.; Christofides, N.; Ioannou, S.; Polycarpou, A. Multicell Power Supplies for Improved Energy Efficiency in the Information and Communications Technology Infrastructures. *Energies* **2021**, *14*, 7038. https://doi.org/10.3390/ en14217038

Academic Editors: Ching-Ming Lai and Yitao Liu

Received: 5 October 2021 Accepted: 23 October 2021 Published: 27 October 2021

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

the market. Over the last few years, Facebook initiated the "open compute project" (and other organizations have joined, such as Google and Microsoft), for promoting the 48 V DC distribution topology for the IT industry, because of its improved performance [9,10].

Multicell structures have been utilized in the last two decades for several applications, but the main objectives were the improvement of the voltage gain in the input or the output of a circuit and the component stress decrease. There are four different topologies of multicell structures which are:


Aiming for higher efficiency, Kasper et al. [11] suggested a 6-cell converter system, which showed the highest efficiency conversion above 1 kW, however, the suggested converter [11] has great efficiency only in specific loading conditions. Furthermore, the 6-Cell ISOP converter creates additional complexity to the system and reduced reliability, since failure of one of the cells could lead to overall system failure, especially as cells are connected in series at the input. Multicell structures have been used in various studies but not primarily for energy efficiency improvement. Arezki Fekik et al. [12] proposes a three-cell DC to DC structure for Off-Grid PV systems for improved robustness using an ISOS structure but the study does not include an experimental verification and although simulation results are promising in terms of the maximum power point tracking (MPPT) function, the efficiency is not validated. Furthermore, the reliability of the three-cell DC to DC structure is reduced since failure of one of the three cells leads to overall system failure. ISOS structures in both AC to DC and DC to DC conversion stages do not significantly improve the efficiency and have much more complicated load sharing control [13,14]. The IPOS structure which is proposed in [15] in order to improve efficiency and output voltage, reduces the overall system efficiency (maximum efficiency of 91%) and increases the complexity of the system.

The paper analyzes and compares multicell topology structures (ISOS, IPOS IPOP or ISOP) and the way that these can lead to energy efficiency improvements by investigating each stage of conversion (rectification, power factor correction and DC to DC stage through LLC and PSFB converters). The work verifies through simulations and experimental measurements that IPOP structures can lead to an improved energy efficiency conversion and proposes a new multicell buck PFC structure to increase the energy conversion efficiency. Furthermore, the work presents a technoeconomic evaluation of multicell structures compared to single structure power supply units.

The Introduction Section of the work is followed by Section 2, which presents the structure of AC/DC 48 V power supplies. The section identifies and analyzes the three individual conversion stages and specifies single-stage and two-stage conversion alternative topologies. In Section 3, the multicell structure topologies are introduced and analyzed. This analysis is subsequently followed by Section 4, the experimental setup and verification. The proposed multicell buck PFC converter is presented in Section 5 and a technoeconomic analysis follows in Section 6. The last section of the paper, Section 7, is the conclusion.

#### **2. Structure of AC to DC 48 V Power Supplies**

Power supply (PS) systems tend to have low efficiency under low loading conditions. It is for this reason that modular PS systems are commonly used within TS and datacenters to overcome the problem of oversized PS systems. A DC PS system may be composed of a number of power supply units (PSU), frequently called "modules", that work in parallel to feed a DC bus, creating in this way a scalable PS system. A PSU consists of three main stages: (a) The AC to DC rectification, (b) the power factor correction (PFC) stage, and (c) the DC to DC stage to step-down the voltage to the desired 48 V DC, Figure 1. A μDC should have a capacity of up to 20 kW and thus a modular μDC should have PSU modules of less than 10 kW (at least 2 modules) Pmodule ≤ (Prack-max/2). The rectifier stage of the

PSU consists of a bridge rectifier with switches (MOSFETs, IGBT, Thyristors, etc.) or diodes. The power factor correction system is used to ensure conformity with EN61000 and that there are no excessive harmonics in the AC supply from the UPS system. The third stage of a PSU is needed to step-down the voltage from the rectification stage to the desired 48 V DC. The rectification is common in all systems but there are two options used to produce the desired 48 V DC and to satisfy the input power quality requirements. The first option is to use a two-stage process with boost PFC and DC to DC step-down converter. The second option is to use the buck PFC single-stage circuit solution (PFC and DC to DC step-down circuits combined). In a single-stage conversion circuit it is very difficult to control both the input current quality and the output voltage level at different loads, and at the same time achieve high conversion efficiency. The two-stage conversion is therefore preferred as a solution for loads above 1 kW [16–18].

$$P\_{total\text{\textdegree}} = P\_{\text{rec}} + P\_{pfc\text{\textdegree}} + P\_{dc\text{\textdegree}} \,\text{loss} \tag{1}$$

$$P\_{\text{rec}} = 2 \cdot V \cdot f \cdot I\_{in} \tag{2}$$

$$P\_{pfc-loss} = I\_{sw}^2 \cdot R\_{ds-On\ pfc} + I\_{in-rms}^2 \cdot R\_{ind} + P\_{c.pfc\ loss} \tag{3}$$

$$P\_{dc-dc\ loss} = P\_{\text{sur}-loss} + P\_{\text{trans}-loss} + P\_{\text{ind}-loss} + P\_{\text{cap}} \tag{4}$$

$$P\_{trans-loss} = P\_{tr-con-loss} + P\_{no\ load\ loss} \tag{5}$$

where:

*Prec*: power losses from the rectification stage; *Ppfc*−*loss*: losses of the power factor correction stage; *Pdc*−*dc loss*: losses of the DC-DC converter circuit; *Psw loss*: MOSFET switch losses of the DC converter circuit (conduction and switching losses); *Ptrans*−*loss*: transformer losses; *Pind loss*: inductor losses;

*Pcap*−*loss*: capacitor losses in DC-DC converter circuit;

*Ptr*−*con*−*loss*: transformer load and frequency dependent losses;

*Pno load loss*: transformer no load loss.

**Figure 1.** Block diagram of PSU.

#### *2.1. Single-Stage PSU*

The single-stage PSU is a buck PFC system with a bridge rectifier. Buck PFCs are used in low power applications since their structure creates dead angles at the input current waveform. Dead angles are generated from the switching of the input rectified waveform. Boost PFC circuits have the switching device in the output of the circuit and thus have higher THD, and are therefore preferred for high power applications [16,17]. On the contrary, since buck PFCs are only single-stage conversion systems, they present higher efficiency than boost converters at low power applications. Is not easy to remove dead angles in buck PFCs. Several re-searchers aimed to minimize their impact such as Saeed

Sharifi et al. [19], who introduced a new buck PFC circuit with a Z-source network that smooths out the switching effect on the input power quality, Figure 2 The Z-Source circuit was initially proposed by B. Axelrod et al. [20] with its main target to increase the voltage gain in buck converters. Fortunately, the new circuit introduces a new input inductor that not only increases the gain but also minimizes the stress on the switch and smooths out the input current dead zones.

**Figure 2.** The Z source buck PFC.

#### *2.2. Two-Stage PSU Solution*

The two-stage solution includes the AC to DC boost PFC which converts the AC input voltage to 380–400 V DC and maintains input power quality, and a DC to DC stepdown converter to step-down the voltage to the desired level. Due to imperfect switching (especially for high power applications), high switching losses occur in the converters. To step-down the voltage from 380–400 V to 48 V DC as previously described, a DC to DC stepdown converter is needed. Since high energy efficiency and power density is required for such converter systems, the most commonly used low power (under 1 kW) converter circuit is the LLC half- or full-bridge converter [21–23]. These converters are resonant converters that adopt zero-voltage switching (ZVS) techniques in order to minimize switching losses, something that improves the efficiency of conversion. LLC half- or full-bridge converters, however, incorporate transformers in their structure, which creates no-load losses and therefore has low efficiency on low loads.

#### **3. Multicell Structures**

A multicell structure is a structure made of multiple converter systems (cells) which are put together and work in parallel or in series to form a new, larger converter system, as shown in Figure 3.

This work aims to prove that combining multiple converters (multicells) in series or in parallel can lead to overall energy efficiency improvements. Since conversion from AC 230 to DC 48 V includes more than one conversion step, multicell efficiency improvements need to be analyzed per stage (AC to DC, PFC stage and DC to DC step-down stage).

**Figure 3.** Block diagram of a multicell structure.

#### *3.1. The Multicell AC to DC Rectification Stage*

A multicell rectification can be constructed either with diodes or switches (MOSFETs or IGBTs, etc.), as previously mentioned. A strategy to minimize the losses in the rectification stage is to use parallel diode bridge rectifier systems [24]. Considering that each bridge circuit is a cell using multiple bridges, a multicell structure is formed. According to [24], parallel diode bridge rectifiers lead to lower losses because diodes with lower maximum current carrying capacity have less forward voltage drop, although this stands only for specific applications. The power losses are mainly generated as a result of the conduction and the switching of the diodes or the switches. Due to the low switching frequency (50 Hz or 60 Hz), the switching losses are almost negligible and the resultant losses of each of the two bridge rectifier legs arise mainly due to conduction. The use of IGBT switches would not benefit such systems since IGBT losses are similar and higher than diodes for similar power applications. GaN MOSFETs tend to have lower switching losses than silicon MOSFETs despite their higher conduction resistance (on-resistance RDS−On). For the diode case, the conduction losses are given by:

$$P\_{Dloss} = I\_{rms}.V\_d \tag{6}$$

where *Vd* is the diode voltage drop and *Irms* is the average current passing through the bridge leg. For the MOSFET switch case, conduction losses are given by:

$$P\_{Loss} = I\_{rms}^2 R\_{DS-On} \tag{7}$$

where *RDS*−*On* is the on-resistance of the MOSFET switch.

Connecting bridge rectifier cells in ISOS or IPOS would imply that the output voltage is a multiple of 325 V (Vpeak of AC input). This would require a very high gain to reduce it to 48 V and there would thus be higher power losses in the secondary circuits to step down the voltage. Additionally, a high voltage at the output of the bridge rectification stage would need switches that could withstand a higher voltage. Since RDS−On is proportional to the voltage, this would result in higher power losses. Therefore, the multicell bridge would not have better efficiency if connected in ISOS or IPOS. The ISOP structure with MOSFET switches would not improve the efficiency either, since the series switches would increase the conduction losses. Considering however that the breaking voltage is proportional to RDS−On, switches that can withstand a lower voltage would have lower conduction losses. Replacing, therefore, one MOSFET switch with two switches of smaller RDS−On, could in theory result in better efficiency. Examining however the characteristics of available MOSFET switches, those with breaking voltage of 50 V have an RDS−On as low as 3.3 mΩ (IFR3805), while switches with a breaking voltage of 200 V have an RDS−On as low as 4 mΩ (IXFK300N20X 3). Therefore, energy efficiency improvement could not be achieved with ISOP and MOSFETs for this type of power supply. Analyzing the circuit further, it can be seen that the ISOP structure of the bridge rectification part would not provide any energy efficiency improvement with diodes either, since in each cycle of the AC source only two switches/diodes conduct, as seen in Figure 4, as in the single cell structure, namely D1a and D2b in the positive cycle and D3b and D4a in the negative cycle. In the IPOP structure with diodes, the voltage drop increases as the number of cells increases. Efficiency is therefore slightly improved as a result of lower heat dissipation. For the case of the IPOP structure with MOSFETs, the voltage stress on the switches remains the same and the current passing through the system is divided in the parallel cell bridges, something that may lead to significant energy efficiency improvements.

**Figure 4.** Multicell bridge ISOP circuit.

For instance, in a two-cell rectifier bridge system, the current in the two legs is halved (assuming MOSFETs with the same RDS−On) and since 2 (I/2)<sup>2</sup> < I2, it can be easily proven that parallel bridge structures lead to overall energy savings. For N cells, it can be shown that:

$$\text{N}\left[\frac{\text{I}}{\text{N}}\right]^2.R\_{DS-On} < I^2.R\_{DS-On}\tag{8}$$

#### *3.2. The Multicell PFC Stage*

There are different PFC structures. For single-stage converters, buck PFC can be used. For dual-stage converters, the boost PFC is widely used as well as some modified boost PFC circuits. All PFC circuits always follow the AC to DC rectification, or are incorporated into it.

#### 3.2.1. Multicell Buck PFC

As discussed in the previous sections, to improve the power factor of the buck PFC circuits, the Z-source buck PFC circuit is proposed in [14] by adding a Z-source network in front of the buck converter. As seen in Figure 2, the circuit has two switches, SW1 and SW2. The losses arising in such a circuit are mainly as a result of conduction and switching, as well as due to the inductor at the input. Conduction losses are given by Equation (8) and the switching losses are given by Equation (9).

$$P\_{sw} = V\_{in} \cdot I\_{out} \cdot f\_{sw} \left(t\_r + t\_f\right) \tag{9}$$

where *fsw* is the switching frequency, *tr* is the rising time the transistor needs to switch on and *tf* is the falling time needed to switch off.

In a multicell parallel input configuration such as IPOP and IPOS, the input peak voltage would be 325 V DC (with ripple). For parallel cell circuits, the current in each of the parallel circuits would be split equally and the conduction losses would therefore decrease. The switching losses on the other hand cannot decrease. Considering the use of switches with a lower drain current, faster response, and thus lower tr and tf, they could potentially lead to better efficiency. However, using switches with lower tr and tf and at the same lower maximum drain current capability may negatively affect the RDS−On (i.e., conduction losses).

Connecting the multiple cells in series would require higher gain at the output. As a result, bigger inductor and capacitor at the output would be required, which would lead to higher losses, especially on low loads. Therefore, the IPOP is the only parallel input configuration that should be examined. In a parallel configuration, the inductor winding losses are also less since the current passing through them is divided by the number of cells and, despite the fact that core losses of inductors can increase, they are negligible compared to winding losses. The inductor size in the split cells would not be affected, since the output and input voltages as well as the switching frequency remain the same. The equation for calculating the inductor size is given by:

$$L = V\_{out} \cdot \frac{(V\_{in} - V\_{out})}{\Delta I\_L} f\_{\text{sw}} \cdot V\_{in} \tag{10}$$

where Δ*IL* is the ripple current and is proportional to the output current of each cell.

Connecting multiple buck PFC cells in series at the input (ISOP or ISOS) causes higher overall RDS−On resistance during the ON state. The switching losses, on the other hand, are multiplied by the number of cells but the voltage input is divided by the number of cells (assuming the case of exactly the same RDS−On). The rising and falling times of the switches in the multicell ISOP and ISOS structures can be minimized since switches with lower voltage breaking capacity tend to have lower falling and rising times. Silicon MOSFETs can have RDS−On as low as 3.5 mΩ, with rising and falling times of about 170 nS (IXFN300N20X3), while GaN MOSFETs can have 12.4 ns rising and 24 ns falling time with RDS−On of 25mΩ (GS66516). On the other hand, inductor losses increase if the inductor size is not reduced from the single cell design. Since voltage gain is reduced in the ISOP and ISOS structures, the inductor size can also be significantly reduced. Therefore, ISOP or ISOS structures lead to reduced inductor losses but with insignificant switching loss improvement. The overall improvements are minor in relation to the complexity and increase in cost.

#### 3.2.2. Multicell Boost PFC

The losses in the boost PFC circuit (as in the buck PFC) are mainly due to switching and conduction loss of the MOSFETs, the input inductor and the output capacitor. However, because of the higher voltage stress applied on the switches of the boost PFC compared with that applied on the buck PFC, higher conduction losses occur. An ISOS and ISOP structured boost PFC would lead to increased losses in MOSFET devices since they would be connected in series, even if lower RDS−On MOSFET switches are used. Since the inductors are in series in ISOP and ISOS structures, the overall DC resistance and hence inductor losses will increase. Considering the inductor size needed to form a multicell ISOP

or ISOS structure compared to a single cell, it can be concluded that the ISOP case would lead to reduced losses compared to ISOS, but both cases would not lead to a significant reduction in the inductor's overall size and power losses (6), (7) and (8). The single cell boost PFC inductor value is given by [24]:

$$L = \frac{T}{\%Ripple} \cdot \frac{V\_{ac-min}^2}{P\_o} \cdot \left[1 - \frac{\sqrt{2} \cdot V\_{ac-min}}{V\_o}\right] \tag{11}$$

In a multicell ISOP boost PFC, the inductor value per cell is calculated by:

$$L = \frac{T}{\%Ripple} \cdot \frac{V\_{ac-min}^2}{P\_o \cdot N} \cdot \left[1 - \frac{\sqrt{2} \cdot V\_{ac-min}}{V\_o \cdot N}\right] \tag{12}$$

In a multicell ISOS boost PFC, the inductor value per cell is:

$$L = \frac{T}{\%Ripple} \cdot \frac{V\_{ac-min}^2}{P\_o \cdot N} \cdot \left[1 - \frac{\sqrt{2} \cdot V\_{ac-min}}{V\_o}\right] \tag{13}$$

For IPOS and IPOP structures as in the buck PFC case, the current is split between cells and, as previously mentioned, reduces both inductor and MOSFET losses.

#### *3.3. The Multicell DC to DC Voltage Step-Down in Two-Stage Conversions*

The PSUs used in the ICT industry are converting AC 230 V to DC 48 V, and therefore high gain DC to DC step-down conversion stage is needed. The most common type of circuit for high efficiency DC to DC step-down conversion is the resonant converter such as LLC [21,22] and phase shift full bridge converters (PSFB). The presence of the transformer in these circuits provides magnetic isolation to the connected load. The losses for these types of converter circuits are again down to the switches, the inductors, the capacitors and the transformers. These circuits use zero-voltage switching (ZVS) techniques to minimize the switching losses. However, these techniques do not influence the conduction losses. The losses because of the inductors and the transformers are a result of the core and I2 R of windings. The core losses are given by:

$$P\_{\text{corr}} = P\_{\text{hysternis}} + P\_{\text{cdf}y} \tag{14}$$

$$P\_{\text{hysteris}} = K\_h f B'' V\_c \tag{15}$$

$$P\_{\rm eddy} = K\_{\rm ef} f^2 B^2 V\_{\rm ef} t^2 \tag{16}$$

where *Ke* and *Kh* are the eddy and hysteresis loss constants, *Peddy* is the eddy current power loss (W), *B* is the flux density (Wb/m2), *f* is the frequency of magnetic reversals per second (Hz), *t* is the core material thickness (m), *V* is the volume of core (m3) and *n* is the Steinmetz exponent (ranging from 1.5 to 2.5 depending on the material).

Core losses are not proportional to the current passing through the coils. In inductors, the core losses are proven to be negligible compared to winding losses. In transformers, however, the larger the core size, the higher the core losses, even without any load. Paralleling transformers would reduce winding losses but would increase core losses and the overall losses would therefore also increase.

#### **4. Experimental Verification of Multicell Structures**

This experimental verification work validates the use of parallel converter cells within a PSU system for improved overall energy efficiency. To experimentally validate this proposal, a small-scale experimental setup was implemented with 3 buck conversion cells of a maximum power output of 18 W, input voltage of 24 V DC and output 5 V DC, connected in an IPOP structure.

Initially the setup was simulated in PSIM thermal module (version 12.0.3.) for comparison of theoretical and experimental results. The setup consists of 3 buck converter cells, a 3-pole switch for switching of the 3 parallel cells, variable loads, and two power meters measuring input and output voltage, and current and power. The buck cells used are commercially available and they employ the LM2596 controller. A photo of the experimental setup is shown in Figures 5 and 6, showing the respective schematic diagram. The input power meter used is a Lucas-Nuelle analog/digital multimeter, which is the wattmeter and power-factor meter model SO5127-1Z, which has a measurement accuracy of 2%, and a capability to work with voltages of up to 600 V and a current range of 0–20 A. The meter used in the output of the multicell conversion system is a Fluke 345 PQ meter with an accuracy in current measurements of ±0.2 A or ±1.5% and an accuracy of voltage measurements of ±1%. It is worth mentioning here that since the measurements with 3 cells, 2 cells and 1 cell are comparative, the efficiency improvement could easily be verified. As it can be seen in Figure 5, for 17 W load output, the power input with 3 buck cells is 22.8 W. For instance, at the same load (of 17 W) with 2 cells, the input power was 23.1 W. The voltage input to the 3 cells was 23.56 V and current input 0.97 A.

The efficiency of the single buck cell at different load conditions was measured, graphically analyzed and used as a baseline for energy efficiency. Following the experimental measurements with one buck converter cell, two and then subsequently three similar buck converter cells were used. Repeating the same methodology and measurement strategy, the load-efficiency curve was constructed, as seen in Figure 7. It is worth mentioning that the no-load consumption of one, two and three PFC circuits have an effect on the load-efficiency curves. As it can be seen in Figure 7, for loads corresponding to 10–20% of the full load (i.e., 1.8–3.6 W), the efficiency of one buck converter cell is higher than in the case with two and three buck converter cells. For instance, on 2 W load, the efficiency of 1 cell was 72.76% and with 3 cells it was 70.63%. Additionally, on 3.6 W load, the efficiency with 1 cell was 72.5%, with 2 cells 72.32% and with 3 cells 72.07%. This is due to the no-load losses of the PSU modules arising mainly from the inductors and the control circuitry. The no-load loss of a single buck converter cell is found to be 0.1904 W, that of two cells was equal to 0.238 W and for three cells 0.3094 W.

**Figure 5.** Experimental setup with parallel buck converter cells.

**Figure 6.** Circuit diagram of experimental setup.

**Figure 7.** Efficiency comparison of 1-cell and 3-cell multicell buck converters.

It can be theoretically and experimentally shown that when using parallel cells of the same converter type, size and brand, the load is equally shared between the number of parallel cells. Power converters or PSUs are voltage-controlled systems in which the controller must maintain the output voltage level within certain values for different loading conditions. Either in continuous conduction mode (CCM) or discontinuous conduction mode (DCM), the small signal model of the buck converter in the secondary (output) side of the converter consists of DC sources and a series impedance/resistance. The voltage and resistance of CCM and DCM modes is of course different when analyzing the small signal model. The equivalent simplified circuit for DC power supplies proposed from this work is shown in Figure 8.

**Figure 8.** Equivalent simplified circuit of parallel DC cells connected to a common variable load.

Using the circuit proposed, the equation of output power as a function of output voltage, load and internal resistance can be derived for different cells and is given by:

$$P\_{\rm out-m} = \frac{V\_{\rm oc-m} - V\_{\rm out}}{r\_{\rm m}} \tag{17}$$

For cells which are multiple and dissimilar in size and type, it can be shown that connecting "w" number of cells of type A and "q" number of cells of type B in parallel supplying a common load, the voltage at the output is given by:

$$V\_{out} = \frac{\left[w\frac{V\_{\alpha1}}{r\_1} + q\frac{V\_{\alpha2}}{r\_2} - P\_{out}\right]}{\frac{w}{r\_1} + \frac{q}{r\_2}}\tag{18}$$

where: *Voc*<sup>1</sup> and *Voc*<sup>2</sup> are the cell type A and cell type B, open circuit voltage, *Vout* is the output voltage of the system, *r*<sup>1</sup> is the internal resistance of type A buck-cell and *w* & *q* are the number of buck-cells of type A and B connected to the system, respectively. The power output of the system consisting of "w" cells of type A and "q" cells of type B is given by:

$$P\_{out} = w.P\_{out1} + q.P\_{out2} \tag{19}$$

It is obvious from (12), (13), and (14), that each cell shares a portion of the output load based on the internal resistance, the open circuit voltage and the total load. For IPOP structures with the same type of converter cells, (in ideal conditions) it can be realized from equation (12) that the output power of each cell is equal. Measurements results for load sharing between cells are shown in Table 1. The current was measured using three clamp-on ammeters, which were the brand and type CEM, DT-362. The input power is measured through a Lucas-Nuelle analog/digital multimeter called SO5127-1Z. The experimental set-up is shown in Figure 9.

**Table 1.** Load sharing between three buck cells.


**Figure 9.** Experimental set-up of load sharing between parallel buck cells.

The no-load losses could not be measured by PSIM and this is why, in Figure 7, the simulation results show higher efficiency in all load levels compared with the respective experimental ones. Under full load, an impressive 11.18% higher efficiency was measured with three cells compared to one cell. In addition to no-load losses, PSIM is unable to measure the capacitor losses, control system consumption and other losses arising from cabling or connections, etc. Most industrial power supply units require high frequency transformers for isolation purposes that generate, however excessive, no-load losses. A single centralized transformer should be used in PSUs adopting the multicell circuitry structure. If each cell uses its own transformer, this would result in increased losses and lower overall conversion efficiency. This can be proven experimentally by combining in parallel three complete PSUs, including their individual transformer, and measuring the efficiency for the different loads. Three Eltek Valere Micro pack 250 W, 230 V AC input/48 V DC output PSUs are used to perform this experiment. The input to the three PSUs was measured using a Lucas-Nuelle analog/digital multimeter measuring the input current, applied voltage and consumed power of the system. Each of the three PSU outputs was connected to "dummy loads" of different load values whilst measuring the output current and voltage. For every different load case, input and output parameters were measured so that the efficiency could be subsequently evaluated. The plot of efficiency versus load output is shown in Figure 10, from which is it seen that the efficiency decreases as the number of PSUs connected in parallel increases. The no-load consumption of the PSUs (mainly as a result of the transformers) was measured and found to be 5 W per PSU (i.e., 2% of efficiency at full load).

**Figure 10.** Efficiency against power output of 1, 2 and 3 PSUs working in parallel (with transformer).

#### **5. Proposed Multicell Buck PFC Converter**

#### *5.1. Justification of AC to DC Multicell Selection*

In order to justify the selection and advantages of multicell structures, a high efficiency Z-source buck PFC with a power output of 1000 W was initially simulated. The proposed converter is an AC to DC step-down conversion circuit with improved efficiency. Despite its single-stage conversion structure, due to the Z-source filtering, it satisfies power supply regulation EN 61000-6-3. As a result, it is a transformer-less, single-stage conversion system that can be used with IPOP structures and produces an improved energy conversion efficiency.

The results with the losses at different power output levels are shown in Table 2. It should be noted that the input inductor was 3 mH and the one at the output was 92.4 μH. The output inductor design was optimized to minimize losses based on [25,26]. Table 1 shows that the total converter losses for the 200 W load output are 8.38 W and the efficiency is therefore 95.81%. For the 1000 W load case, the total losses are 55.15 W and the efficiency is 94.485%. It is interesting to note that the losses for switch 1 are lower than those of switch 2 for small loads, however, as the load increases, the losses of switch 2 become greater. Furthermore, the losses of the PFC stage are more than 40% of the total circuit loss and the output inductor losses are negligible.



Initially, the AC to DC part of the multicell rectifier was simulated with the remaining parts of the PSU in a single-cell structure. The results are shown in Table 3. The results are very promising, since the load losses at 1000 W are considerably minimized. As expected, since, for both inductors and MOSFET switches, the main losses are due to the internal resistance (Rindutor and RDS−On, respectively), the three-cell buck PFC has significantly lower losses (since N(I/N)2 × R<I2 × R).


**Table 3.** Comparison of 1-cell and 3-cell rectifier system.

The significant savings affect the overall PSU energy efficiency by up to 0.79%, as demonstrated in Table 3. In the proposed multicell bridge simulation that consists of a threecell system, it is shown that, when increasing the number of cells, the efficiency improves. The efficiency improvement is significant, especially under bigger load conditions, but as the load decreases, the efficiency gains are relatively reduced.

#### *5.2. Multicell Buck PFC*

Simulating a two-cell buck PFC in PSIM's thermal module, it is revealed that inductor losses were minimized by about 50%, as shown in Table 4. The switching losses remained about the same in the case of those of a single cell system; conduction losses, however, were minimized by 52–57% for different loads, and inductor losses were improved by 50%.The overall results of the new system are shown in Figure 11. The results indicate that when increasing the number of parallel cells, the conduction and inductor losses decrease proportionally. Switching losses, on the other hand, are not affected. Therefore, using GaN switches that have low switching losses compared to silicon MOSFETs, and also minimizing conduction losses through multicells, leads to considerable efficiency improvement. The simulated system diagram is shown in Figure 12.



The references "Jameco.com" and "Alibaba.com" shown in Table 4, are all accessed on 1 September 2021.

**Figure 11.** Efficiency comparison of single-cell and multicell PSU.

**Figure 12.** Multicell PSU circuit proposed.

In order to simulate the thermal losses of the individual components of the circuit using PSIM's thermal module, each component was modeled with its equivalent circuit, as shown in Figure 13. In the simulation, the ambient temperature and the thermal resistance of each of the components is also taken into account. The flowchart in Figure 12 illustrates the procedure used for selecting the number of cells in the multicell structure, ensuring no excessive cells are used. The first step is to identify the MOSFET switches with the lowest on-resistance (RDS−On).

**Figure 13.** Equivalent circuits in PSIM thermal module for (**a**) diode, (**b**). inductor, (**c**). MOSFET.

All switches should have a reverse voltage breaking capacity higher than the input voltage of the source. Since the price of the switches tends to be proportional to the output current, the flowchart in Figure 14 compares the system cost with the lowest cost switch and the system cost of a multicell structure with the lowest RDS−On switches. The solution with the lowest system cost is selected from the product of the number of cells and the cost of the switches.

**Figure 14.** Procedure for cell/switch selection.

#### **6. Discussion**

The results of the research have shown that parallel cells in multicell PSU structures can lead to significant overall energy efficiency improvements in PSUs. According to [27], currently, 1.8% of global energy is supplied to the ICT industry, such as datacenters and micro-datacenters. More than 50% of this energy is supplied to the power supply units of the ICT equipment. Therefore, the impact of PSUs with improved energy efficiency could lead to significant energy savings in the ICT industry globally, and could contribute to the efforts and targets set for global energy decrease, through more efficient systems. Of course, the improvement in efficiency comes at an extra cost, as a result of the additional components used. The total manufacturing cost of a PSU system consists of the electronic components, the controller, the mounting, the enclosure, and labor costs. A PSU consisting of multicell parts would have an increased cost on components (cells) and labor costs but would not have an increased cost on the controller, the mounting and the enclosure systems. Additionally, as mentioned earlier, the transformer systems which lead to a significant cost in PSU systems should be single (centralized) and thus no additional cost should arise.

Analyzing the industry's readymade PSU prices, it can be observed that when using smaller units (as in those in multicell structures) for a 20 kW PSU (1 full rack), the cost is slightly higher. Table 4 compares the cost per watt using smaller PSUs for the same type and brand PSUs for different capacities.

The cost variation is in the order of 1–11%. For example, constructing a 20 kW power supply system with 20 pieces of RCP-1000-48 would cost 10.78% more than using 10 pieces of RCP-2000-48. Using 4 Mean Well RST-5000-48 instead of 2 RST-10000-48, would cost 0.8% more, but using Jetpower SP60-48/CR4830 instead of SPS200-48/SR4850 systems would cost less per installed Watt.

Finally, the proposed multicell IPOP structures have limited applicability for circuits that incorporate transformers. As stated in previous sections, transformers have noload losses that do not favor decentralization (multicell structure). Centralization via the transformer part only of a multicell structure could overcome such limitations.

Further research will focus on multicell structures with planar transformers in matrix forms. Studies have shown that such transformers offer reduced no-load losses.

#### **7. Conclusions**

The results presented in this study demonstrate that using low-power modules such as the multicell structure for high-power PSU systems improves the energy efficiency. Using three rectifier cells and two buck PFC cells, a more efficient power supply system can be constructed for the same power output. Efficiency improvements of more than 1.2% can be achieved for 50% of the load and more than 2.1% efficiency improvement under full load. The concept of multicell efficiency improvement is experimentally proven through the testing of a three-cell, a two-cell and a single-cell buck converter system. It is shown that an efficiency improvement of up to 10% can be achieved for particular loads in the DC to DC conversion part. Energy efficiency improvements in PSUs leads directly to energy consumption minimization for the ICT industry.

The initial cost of a power supply system in a datacenter is about 5% of the total capital cost. A 10.78% increase in the power supply unit (i.e., the worst-case scenario) due to a multicell structure compared to a single cell one, corresponds to an additional 0.5% increase in relation to the total capital cost. The respective savings, however, are in the order of 2.1%, as previously mentioned. Looking ahead in the long-term, the cost benefit for this investment is viable, as with simple calculations the payback period is in the order of just 3.3 years.

**Author Contributions:** Conceptualization, M.C. and N.C.; methodology, M.C.; software, M.C.; validation, N.C., S.I. and A.P.; formal analysis, A.P.; investigation, M.C.; resources, A.P.; writing original draft preparation, M.C.; writing—review and editing, N.C. and A.P.; visualization, S.I.; supervision, N.C.; funding acquisition, A.P. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research received no external funding.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** There is no research on humans in this work.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


**Debjani Ghosh , Caroline Willich \*, Christiane Bauer and Josef Kallo**

Institute for Energy Conversion and Storage, Ulm University, Albert-Einstein-Allee 47, 89081 Ulm, Germany; debjani.ghosh@uni-ulm.de (D.G.); christiane.bauer@uni-ulm.de (C.B.); josef.kallo@uni-ulm.de (J.K.) **\*** Correspondence: caroline.willich@uni-ulm.de

**Abstract:** Hybrid electric aircraft offer the potential to decrease emissions from air travel. A new hybrid concept is proposed for a fuel cell-battery hybrid aircraft. In contrast to existing hybrids, the proposed concept puts a battery directly on the AC phases of the motor, which together with a suitable switching circuit superimposes the DC voltage from the battery on the AC voltage of the motor phase providing a voltage boost depending on the battery voltage, which can be used during a high-power demand flight phase. The system is also capable of recharging the battery during flight. The necessary switching architecture was developed and modeled in MATLAB/Simulink to verify the concept and an experimental setup was built for demonstrating the functionality. Simulation and experimental results showed a very good agreement which is very promising for the proposed new hybrid topology.

**Keywords:** hybrid system; battery; fuel cell; electric aircraft; power control

**Citation:** Ghosh, D.; Willich, C.; Bauer, C.; Kallo, J. Demonstration of a Novel Alternating Current Hybrid Concept for a Fuel Cell–Battery Hybrid Electric Aircraft. *Energies* **2021**, *14*, 7350. https://doi.org/ 10.3390/en14217350

Academic Editors: Felix Barreras and Mario Marchesoni

Received: 12 August 2021 Accepted: 1 November 2021 Published: 4 November 2021

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#### **1. Introduction**

The threat of adverse climate change is becoming a prominent issue day by day. Emissions from the burning of fossil fuels in the transportation sector is one of the main contributors to the problem [1]. CO2 is the largest emission component in the aviation sector, comprising 70% of the exhaust [2]. Emissions from the aviation sector also include other pollutants and greenhouse gases, making this sector one of the top 10 global emitters [3]. Although technological advances have made it possible to reduce the amount of fuel burned and emissions produced per passenger, a continued growth in air traffic outweighs the improvement. The International Civil Aviation Organization (ICAO) predicts that the international aircraft emissions can become three times higher by 2050 compared to 2015 [4]. The European Green Deal aims to achieve a 90% decrease of transportation emissions by 2050, which includes emissions from aviation sector as well [5]. Therefore, it is important to develop new technologies for aviation that will be environment friendly and help to transit from fossil fuels to green energy sources. Hybrid electric aircraft based on fuel cells (FCs) as primary energy source and batteries are a promising technology and will help to reduce CO2 emission. Several such systems have already been tested successfully [6–8].

Fuel cells generate electrical power without harmful emissions and the products are only water and waste heat [9]. They also have higher efficiencies (>50%) than an internal combustion engine [10] and, in comparison to batteries, they offer the advantages of high energy densities meaning they are better suited as energy source for medium and long distance flights. Nevertheless, fuel cells have a slow dynamic response and for flight phases with high power demand, combining a fuel cell with a battery can result in an improved performance [11,12]. As determined by Lijun Gao et al., the peak power with a fuel cellbattery hybrid can be four times higher than the power fuel cell can provide alone [13]. Use of the battery as a secondary source provides a power boost when the load demand is higher, such as start or take-off. Like this, the advantage of the high-energy density of fuel cells and the high-power density of batteries are combined. There are several existing

topologies for a fuel cell-battery hybrid system. These conventional hybrid systems usually connect the fuel cell and the battery in parallel connection in the DC side of the inverter.

In an active hybrid system one or more DC/DC converters are used between the fuel cell and the battery as shown in Figure 1a. In this configuration, the DC/DC converter actively controls the fuel cell and the battery to regulate the load sharing [13] and both sources can be operated in such a way that they generate to produce maximum power simultaneously. The peak power supply capability of an active hybrid is much higher than passive topology. However, this active hybrid topology has additional power losses and weight due to the DC/DC converter. According to literature, the DC/DC converter can be 3.2–65 kg for a system of approximately 100 kW range of peak load power demand [14–16].

**Figure 1.** Active (**a**) and passive (**b**) fuel cell battery topology in conventional hybrid systems.

There are also existing hybrids with a passive topology as shown in Figure 1b. Here, the fuel cell and the battery are directly connected to the DC link side without any additional converters [17]. The passive topology has less power loss and cost due to the absence of DC/DC converter. Nevertheless, it needs proper coordination of the voltage-current behavior between the battery and the fuel cell and in this type of hybrid, fuel cell nominal voltage determines the battery pack design. There are also variations on the described topologies. For example, the HY4 aircraft uses a variation of a direct system with additional diodes and a separate path for recharging the battery [18,19].

This paper proposes and describes a novel hybrid concept for a fuel cell–battery drivetrain, which does not connect the fuel cell and battery in parallel on the DC side of the inverter as described above. Instead, it places three batteries directly onto the three phases of the electric motor as shown in Figure 2a. The motor phases are supplied from the inverter with AC voltage, but the batteries can only provide DC voltage. Therefore, a suitable switching circuit was developed and tested to superimpose the battery DC voltage on top of the AC voltage of the motor during each AC phase. This new hybrid configuration, with the newly developed switching circuit, makes it possible to increase the voltage on the electric motor by adding the voltage of the battery on top of the AC voltage provided by the inverter of the electric motor during each AC phase. The resulting power increase can then be used during take-off or climb if the fuel cell alone is not able to achieve the bigger load demand. The new concept excludes the necessity of a DC/DC converter between the fuel cell and the battery as found in the existing active hybrid topology while still allowing a complete control of both the fuel cell and the battery and there are no constraints regarding the voltage matching between fuel cell and battery as in the traditional passive hybrid described above. Another advantage of the newly proposed concept is that between the DC link and the AC side an inverter with a smaller power rating and lower weight can be used compared to the conventional hybrids described

above since only the fuel cell voltage has to be converted by the inverter and not the battery voltage as well. The energy management between the two sources, fuel cell and battery, is crucial for an efficient operation of the hybrid drivetrain. The energy management strategy distributes the power demand of the aircraft between different power sources in such a way that each power source can be utilized optimally. There have been different techniques developed over the years for a good energy management strategy, using for example a fuzzy logic approach [20], battery involved energy managements with Deep Deterministic Policy Gradient Algorithm [21] or Soft Actor-Critic DRL Algorithm [22]. For the aircraft HY4, a Power Management Control and Delivery (PMCD) unit [19] is used to manage the power demand and control the power for different flight phases while additionally providing redundancy and more safety for the aircraft operation. In this paper, it is assumed that an existing energy management system is available on the on-board computer which will send the command to the battery unit of the AC hybrid to turn on and off as required by the mission profile.

**Figure 2.** AC hybrid concept [23]. (**a**) AC hybrid topology. (**b**) Voltage boosting by AC hybrid.

#### **2. Description of the Proposed AC Hybrid Concept**

In the newly proposed AC hybrid concept, batteries are directly connected to the motor on each phase (Figure 2a). This configuration will superimpose the DC voltage from the battery on the AC voltage of the motor, which will provide a voltage increase directly on the motor phases, resulting in a motor voltage boost. A suitable switching circuit is required to correctly superimpose the DC voltage onto the AC voltage as illustrated in Figure 2b. The switches must be controlled in such a way that a positive DC voltage is applied to the positive half wave of the AC voltage and a negative DC voltage is added during the negative half wave of the AC voltage. Consequently, there is an increase in the peak-to-peak motor voltage. The precise control of the switching sequence at the correct phase is very important, otherwise a mismatch of the voltage polarity may cause a voltage decrease instead of increase. In Figure 2b, the output voltage of the inverter is 100 V (in blue). A 50V battery is used to superimpose the DC voltage of the battery on top of the inverter AC voltage. The result is +150 V in the positive half wave and -150V in the negative half wave. This gives an AC voltage of 150 V for the motor input, a total rise of 100 V peak to peak with a 50 V battery. With the proper switching sequence, the resulting voltage can be increased by twice the battery voltage with this new hybrid concept.

#### **3. Design Requirement**

The new AC hybrid concept requires an efficient high-speed circuit for connecting the battery. There are three modes of operation for this circuit:


In order to control the switches, a control circuit is also required. The control circuit receives instructions from the pilot interface (Human Machine Interface—HMI) and based on these inputs, selects the suitable mode of operation and switches accordingly. The current, power, speed, torque, etc., must also be constantly monitored to start switching at the right phase angle.

#### **4. Proposed Architecture of Switching Circuit**

To operate the AC hybrid, a new switching circuit was designed as seen in Figure 3. It consists of four power electronics switches, S1, S2, S3, and S4, forming a bridge architecture. These switches are used in each phase of the motor to connect the battery.

**Figure 3.** Proposed battery bridge model. Red arrows show positive half cycle switching and blue arrows show negative half cycle switching.

Table 1 shows the necessary switching configuration for the different modes. For example, during the voltage boost mode, switches S1 and S3 will be on during the positive AC half cycle in the motor voltage and current; these two switches will be turned off as soon as a negative half wave starts. Switches S2 and S4 will be turned on during the negative AC half cycle, and uninterrupted power is provided to the motor. Due to this switching arrangement, a unidirectional AC current will flow through the battery.


When the power demand from the motor is low, direct mode can be used in which only the fuel cell is providing power. During this mode, all above mentioned switches are off.

The recharging mode is used when the motor power demand is very low, so that the fuel cell can supply both the motor and recharge the battery. It can also be used to recuperate energy from the motor to the battery. In this mode, the switching order is the reverse of the discharge mode.

To assure the switching at the correct phase the logic shown in Table 2 is applied, where Vbattery is the battery voltage and Vmotor and Imotor represent the motor voltage and current, respectively.


**Table 2.** Logic for the switching of the battery bridge.

For the discharging mode, zero voltage and current crossing detection is used to determine the positive and negative half cycle. Due to the inductive nature of the load, there is a phase shift between the motor voltage and current and switching for the positive or negative half cycle may only occur when the voltage and current are both positive or negative, otherwise a decrease of the motor voltage due to the mismatch of the polarity during discharge (voltage boost) mode will occur.

The recharging mode is more complex than discharging. In order to avoid an unwanted result of short discharging pulses on the battery it is necessary to insert a short time in which the battery is not charged in each switching cycle. The battery can only be charged when the motor voltage crosses the battery voltage value as the logic in Table 2 shows. This results in a short time delay between the negative and positive half cycles in which the battery is not charged, the length of which depends on the battery voltage. During this short time delay, the system is in direct mode, so that the power supply is uninterrupted.

#### **5. Simulation Model**

A simulation model was developed in MATLAB Simulink to verify the correct functioning of the AC hybrid concept. Figure 4 shows the simulation model of the drive with a fuel cell, the proposed battery bridge, inverter, and the motor.

**Figure 4.** Simplified block diagram of the simulation model.

#### *5.1. Fuel Cell/DC Source*

The primary power source of the drivetrain is the fuel cell. As the paper focuses on the battery bridge, a 30 V DC source with a small internal resistance in series from the Simulink library is used for this purpose. This way, it is easier to compare the hardware system as well with simulation results, as the hardware includes a motor supplied directly with 30 V DC as discussed later. A diode is connected in series to the source to prevent any current flow from inverter towards the source.

#### *5.2. Inverter and Drive Control*

The drive train has an inverter built with 6 IGBTs. The control for the drive consists of a proportional-integral (PI) controller in the outer control loop. The PI controller is tuned using Ziegler-Nichols method [24], which is a widely used method to tune any proportional (P), proportional-integral (PI), or proportional-integral-derivative (PID) controller. The Ziegler-Nichols method starts by setting the integral and derivative gains to zero and increases the proportional gain until it reaches the point (ultimate gain) when the output of the control loop has stable oscillations. The oscillation period and the ultimate gain value is then used to find out the tuning constant of the controller such as P, PI, or PID values.

The controller compares the setpoint speed with the current speed of the motor and generates a reference torque. The other motor parameters such as hall signals and motor currents are used with this reference torque to generate the switching signal for the gates of the IGBTs in the inverter.

#### *5.3. Battery Bridge*

Figure 5 shows the switching circuit inside the battery bridge block. A battery is connected to each motor phase with the help of the switching circuit. High speed switches are needed for the circuit as switching is done in each half wave of AC voltage. Hence, four MOSFET switches were selected for the purpose. The gate driver circuit of each MOSFET switch gets the gate signals from the battery bridge controller to enable switching at the correct phase and turn on or off the corresponding MOSFET switches.

**Figure 5.** Simulink model of the battery bridge.

The model uses three battery blocks from the MATLAB/Simulink library. This battery block presents a generic dynamic model for various rechargeable batteries such as Lead-Acid, Li-ion, NiCd, and Nickel-Metal-Hydride. It is possible to simulate the temperature effect and ageing effect on the battery.

For the simulation (and for the hardware prototype), two Li-ion rechargeable cells were used in series. There are many types of Li-ion battery models available in literature with different objectives. The electrochemical model contributes to physical cell design and deals with variables such as concentration distribution and galvanostatic charge-discharge. However, this model type is unfit in this context, where only the electrical terminal behavior of the battery is required within a suitable computational time. An electrical equivalent circuit model of a battery is easy to use and suitable for circuit simulations with short computing time. The accuracy of voltage, current characteristics, state of charge, etc., of an electrical model is adequate for this particular application. Therefore, the model used in the simulation is based on an electrical equivalent circuit model of a Li-ion battery with a controlled voltage source and an internal resistance. Table 3 shows the battery parameters for a single Li-ion rechargeable cell from Samsung [25] used in the model and in the hardware.


When the battery current is positive, the battery discharges and when the current is negative, it recharges. In the model it is assumed that both the discharge and recharge characteristics are the same. The model does not consider any self-discharge effect of the battery as this is not relevant for the verification of the concept.

A. Battery bridge controller

The four MOSFET switches in the battery bridge control the power flow through the battery for the different modes. These switches, in turn, are controlled by the battery bridge controller. Figure 6 presents the logical flow chart for the battery bridge controller. It is divided into four types of modes that can be selected by a user or the main computer of the aircraft.

When a particular mode is selected, the logic first checks the SOC of the battery and only then takes the necessary action. For example, if mode 2 (discharge mode) is selected, the controller will first check if the SOC level of the battery is higher or equal to 30%. Only if there is enough energy left in the battery the controller will proceed to zero detection switching according to the logic mentioned in Table 2. If the SOC is between 20% and 30%, the controller will still perform the switching and send a warning signal to the user that the battery has a low energy level. This helps the user or the pilot to determine a corrective course of action for the flight to avoid using the battery any more than necessary. If the battery has 10–20% SOC, the controller sends a critical level warning and still performs the switching. If the battery SOC is lower than 10%, the controller refuses to proceed to switching and enters the direct (FC only) mode. It is possible to override this control if a life-threatening situation occurs and the pilot must use the remaining battery energy at all costs. The different SOC levels for the warnings can of course be changed and the controller can be universally adapted according to the application and its requirements.

**Figure 6.** Logical flow chart for the normal operation in different modes of the battery bridge controller.

Similarly, for the recharging and recuperation modes, the controller checks if the battery is already full. It enables charging according to the logic from Table 2 if the SOC level is less or equal to 95%; otherwise, it goes to direct mode (in case of the hybrid recharging mode) or remains idle (recuperation mode).

The use of state machines for energy management is a well-known approach [26,27] and it is useful for reactive and event driven systems. Therefore, the logic chart from Figure 6 where each mode is considered as a state was programed using the MATLAB/Simulink state flow tool.

The model uses a 3-phase BLDC motor (brushless DC motor) from the Simulink library. BLDC motors are like permanent magnet synchronous motors with a trapezoidal back electromotive force (emf). It uses a closed loop speed control using a Hall sensor as mentioned before. The motor can be operated in either generator or motor mode. Therefore, it is possible to simulate the recharge/recuperation mode during flight.

The hardware prototype has a BLDC motor module from Trinamic Motion Control GmbH & Co which has a QBL5704 motor [28]. Table 4 depicts the parameters used for the simulation of the BLDC motor.


**Table 4.** Parameters of a Trinamic BLDC motor.

#### **6. Results**

*Discharge*

A variable speed drive was simulated and Figure 7 shows the simulation results, where the desired starting speed is higher than the system can supply. It can be seen that in the first 30 s the fuel cell power is not enough to reach the desired speed of 900 RPM. Therefore, the system is switched to hybrid discharge mode at 30 s. Immediately after the battery is turned on, the motor phase voltage increases, and the motor is able to achieve the setpoint speed. The drive is switched back to direct mode once the load requirement is decreased during cruise at 200 s. With the supply of 30 V as fuel cell voltage and 7.2 V nominal battery voltage, the setup is able to provide 80–100 W of mechanical power.

**Figure 7.** Simulation results for the battery discharge mode. (**a**) simulation results; (**b**) battery parameters.

The corresponding battery parameters (voltage, current and state of charge) during hybrid mode are also shown in Figure 7. The battery current acts like a unidirectional alternating current, varying between 0 and 5 A as expected. The battery voltage also has the shape of a unidirectional AC wave. The decrease of the battery state of charge (SOC) shows the proper discharging of the battery over time.

To better understand the battery current, it is necessary to carefully study the MOSFET current. In Figure 8, it can be seen that switches S1 and S3 carry current during the positive half wave and S2 and S4 during the negative half wave of AC. Thus, the battery only supplies a unidirectional current even though an alternating current flows through the battery bridge circuit.

**Figure 8.** Simulated current through switches S1, S2, S3, and S4 of the battery bridge during discharge.

Figure 9 shows the results of the battery parameters during recharging. The battery recharging follows the switching sequences as described in Table 1. A dead time is required between the switching signals to prevent an unwanted short discharging of the battery. The battery has a negative current during recharging, meaning current is entering the battery. During charging the battery current shows again a unidirectional AC behavior. As expected, the SOC of the battery shows an increment over time, confirming that the battery is getting recharged successfully.

**Figure 9.** Simulated battery parameters during recharging.

#### **7. Hardware Verification**

A small test setup was built to demonstrate the functionality of the concept. The test set up uses a Trinamic BLDC motor along with a 3-phase inverter. For the motor control, a controller board (TMC603A) from Trinamic was used as shown in Figure 10. The board is supplied with 30V DC voltage and has six external n-MOSFETs for the inverter function. The output of the converter is usually connected to the motor phases. To test the AC hybrid, the battery bridge was inserted between the phases of the inverter and the motor as shown in Figure 10. The motor is controlled by the external microcontroller depicted in the picture. Based on the position data of the Hall sensor in the motor, the microcontroller sends pulse width modulation (PWM) signals to the inverter.

**Figure 10.** BLDC motor with the controller board and battery bridge.

The control takes place through a cascade regulation of position, speed, and current. The speed controller compares the speed set point with the motor speed measured by the sensors and calculates a set point torque which is converted into a corresponding current in the vector controller and compared with the actual motor phase current. Taking into account the measured position of the motor angle, pulses are then generated for the converter circuit. The microcontroller was programmed using the TMCL-IDE software, provided by Trinamic.

Figure 11 shows the generation concept of the gate signals for the MOSFET switches in the hardware battery bridge. It consists of a logical circuit including sensors, comparators, microcontrollers, optocoupler, resistances, and capacitors. At first, the motor phase voltage and current are measured through sensors. Next, the motor phase current is converted to a voltage signal as the comparator circuit and microcontroller can only use voltage as input for the logical process. A microcontroller (Arduino) is used to synchronously switch the battery bridge for the different operating modes. Depending on the operation modes the microcontroller sends the reference voltage to the comparator for the voltage comparison according to Table 2. In discharging mode, the reference voltage is zero and in recharging or recuperation mode the reference voltage equals the battery voltage. The comparator circuit supplies an input signal to the microcontroller (Arduino) pin every time the voltage of the motor from both positive and negative directions crosses zero voltage or the battery voltage

for discharging and recharging mode, respectively. It also sends another input signal to the microcontroller every time the motor current crosses zero from either direction. Then, the algorithm shown in Figure 6 is executed in the microcontroller, two complementary PWMs are generated and fed to the gate driver circuit. The gate driver circuit provides the signals to the MOSFETs. Optocouplers are used between the microcontroller and the gate driver circuit to provide the necessary galvanic separation between the power and control circuit.

**Figure 11.** Generation concept of gate signals.

The experiment was performed under ambient lab temperature and pressure. The motor module was mounted on a stable surface and the required motor voltage of 30 V was ensured. The battery bridge included the same batteries in series as used for the simulation with a nominal voltage of 3.63 V each. It was ensured that for every motor run, the batteries have the same voltage and SOC.

Figure 12 illustrates the result of switching the battery on and off of the hardware prototype. When the battery bridge is switched on at 37.2 s, the motor speed increases from 800 RPM to about 900 RPM. This matches well with the result obtained from the simulation in Figure 7.

**Figure 12.** Motor speed with battery discharging.

When the battery is turned off at 77.5 s it can be observed that the motor speed also decreases indicating a reduction of motor voltage. The motor speed decreases back to 800 RPM which also corresponds well with the simulation results. It can be seen clearly that adding the battery voltage to the motor voltage boosts the motor speed.

Figure 13 shows the measured phase voltage of the Trinamic motor for the battery discharge mode. At 37.2 s, when the battery is turned on, the motor voltage increases to ±36.08 V and at 77.5 s, it reduces to 29 V as soon as the battery is disconnected. To validate the simulation data, the simulation was repeated with the same time condition as the experiment. The battery was turned on at 37.2 s and off at 77.5 s. The motor phase voltage taken as RMS value was used to compare the data between the simulation and the experiment in Figure 13. The motor waveform closely matches the one from the simulation (Figure 7). The difference between the simulation and experimental data is small, approximately 1–1.2 V for the case of the connected battery as well as the disconnected battery. This voltage drop corresponds to the losses that occur mainly in the power electronics components. Furthermore, it can be observed that the peak to peak phase voltage increases two times the battery voltage with some losses as expected from the simulation and the concept of the AC hybrid. Therefore, the hardware measurements prove the functionality of the concept.

**Figure 13.** Hardware motor phase voltage and difference between simulation and experimental voltage.

Recharging of the battery was also checked with the hardware system. Figure 14 shows the open circuit voltage (OCV) of a single cell during recharging. It was determined during a cumulative motor run, meaning that the motor ran for few minutes, then the battery was taken out to measure the open circuit voltage. After that, the motor ran again for few minutes and the battery was taken again and OCV was measured. The same was performed several times recording the open circuit voltage of a cell. Since a battery OCV depends on its state of charge, it is evident from Figure 14 that the recharging mode also worked, and the battery was recharged. It can also be seen that for a higher charging current the battery is charged faster than with a lower current.

**Figure 14.** Battery open circuit voltage for one cell during recharging with different charging currents.

#### **8. Conclusions**

In the paper, a new AC hybrid topology for a fuel cell battery airplane was developed. In contrast to existing hybrids, the concept places the batteries directly on the phases of the motor. This proposed topology has no need for a DC/DC converter in the drivetrain architecture and at the same time provides the chance to reduce the inverter size. It therefore lowers the total weight of the drivetrain and reduces the power losses. The efficiency of the AC hybrid system is found to be 90% in simulation whereas a passive hybrid of same power range is 93%. Nevertheless, the AC hybrid provides the decoupling between two sources unlike the passive hybrid system. Therefore, it removes the constraint on the voltage-current matching as in the conventional passive hybrid systems. However, in the AC hybrid the switching must be done very precisely to avoid undesirable outcomes. Without proper synchronizing, the voltage can be decreased instead of increased. This will result in the exact opposite of the required voltage boost. Therefore, the switching of the batteries to each AC phase requires a careful synchronizing.

The necessary switching circuit was modeled and build in hardware and the different operating modes of the system (hybrid, primary energy source only, recharging of the battery via primary energy source, or recuperation) were tested to verify the concept. The results of the simulations as well as the hardware measurements confirm the functionality of the concept and there was a good agreement between the simulation and hardware results. The RPM behavior between simulation and hardware matched exactly, whereas the phase voltage of the motor showed an approximate 4% deviation that corresponds to the losses in a real circuit. The concept is therefore very promising, but further research and development is needed to scale up and optimize the hardware and assess the benefit the developed AC hybrid offers in comparison with a conventional hybrid in more detail.

**Author Contributions:** Conceptualization, D.G. and J.K.; Funding acquisition, J.K.; Investigation, D.G.; Methodology, D.G.; Project administration, C.W. and C.B.; Supervision, C.W.; Validation, D.G.; Visualization, D.G.; Writing—original draft, D.G.; Writing—review & editing, C.W. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by the German Federal Ministry of Transport and Digital Infrastructure under the grant 03B10702A and 03B10702A2.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Acknowledgments:** The presented work has received funding from the German Federal Ministry of Transport and Digital Infrastructure under the grant 03B10702A and 03B10702A2.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


### *Article* **A Compensated Peak Current Mode Control PWM for Primary-Side Controlled Flyback Converters**

**Chia-Hsuan Wu 1, Guan-Rong Huang 2, Cheng-Chih Chou 3,4, Ching-Ming Lai <sup>1</sup> and Liang-Rui Chen 3,\***


**Abstract:** In this paper, a feedback compensator (FBC) and a Feedforward compensator (FFC) are proposed to construct a novel compensated peak current mode control pulse width modulation (CPC-PWM) for primary-side controlled flyback converters. Using the proposed FBC, the PWM duty cycle of an abnormal operating flyback converter would be descended to limit the output current for reducing power dissipation. Using the proposed FFC, the effect of delay time would be descended to reduce the over-flow current for increasing the current accuracy. In this paper, the operating principle and mathematical model are described and analyzed. Then, the component values are well designed to satisfy the electrical specifications. Finally, a prototype is designed and realized to access system performance. The experimental results show that the proposed CPC-PWM can validate in a wide input voltage range and output short conditions, which also has good current accuracy and reduces power dissipation by about 68%.

**Keywords:** feedback compensator; feedforward compensator; flyback converter

#### **1. Introduction**

Because the flyback converter has a simple structure and does not require a secondary side output inductor, it has considerable advantages in size and cost. Based on the above advantages, the flyback converter is widely used in low power applications [1–16]—especially in LED lighting [8–10] and battery balancing control [11–16] to show its many advantages. With the advancement of digital technology and the cost of microcontrollers has dropped significantly. The control scheme of flyback is also moving towards digital control to obtain higher performance [17–20]. Since the flyback converter is an isolated converter, the output voltage and current are traditionally regulated by utilizing the secondary-side regulation (SSR). Usually, SSR is mainly constructed by a photocoupler. The photocoupler feedback circuit causes above 10% of the power losses at standby conditions. Recently, primaryside regulation (PSR) flyback converter (i.e., primary-side controlled flyback converter) becomes an important technology due to lower cost and standby power losses [1,17–25]. The primary-side controlled flyback converter stores energy on the transformer when the power switch is ON and releases the energy on the transformer to the load when the power switch is OFF. It is known that this topology is a constant power output. Based on the constant power output characteristics, when the output voltage of the flyback converter drops due to the load, the output current must increase. When the output voltage of the flyback converter keeps dropping, the current keeps increasing until the current is infinite, causing the problem of components burning. At the same output power, the higher input voltage results in a lower input current. On the contrary, the lower input voltage will result

**Citation:** Wu, C.-H.; Huang, G.-R.; Chou, C.-C.; Lai, C.-M.; Chen, L.-R. A Compensated Peak Current Mode Control PWM for Primary-Side Controlled Flyback Converters. *Energies* **2021**, *14*, 7458. https://doi.org/10.3390/en14227458

Academic Editor: Federico Barrero

Received: 12 October 2021 Accepted: 1 November 2021 Published: 9 November 2021

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

in a higher input current. This means that different power losses are caused by different input voltages, so a larger rated component must be selected in the circuit design to meet the range under various conditions.

As shown in Figure 1, the conventional flyback converter has primary side peak current detection overcurrent protection. Because the primary-side peak current detection protection point voltage *VLIMIT* is a fixed value, and the flyback converter working in Discontinuous Conduction Mode (DCM) has a constant power output as shown as [22]

$$P\_{\rm O} = \frac{1}{2} \cdot L\_P \cdot f\_{\rm SW} \cdot I\_P^2 \cdot \eta \tag{1}$$

where *Lp, fsw, Ip* and *η* are the primary side inductance, switching frequency, primary side peak current, and flyback conversion efficiency, respectively.

**Figure 1.** A typical flyback converter with primary side peak current mode control.

When the load on the output terminal becomes larger and larger, the output voltage becomes lower. At this time, the output current will still be larger and larger as shown in Equation (2). Therefore, the current rating of the part needs to be selected with a larger specification, just to meet the protection application.

$$I\_O = \frac{1}{2} \cdot L\_P \cdot f\_{SW} \cdot I\_P^2 \cdot \eta \cdot \frac{1}{V\_O} \tag{2}$$

In order to overcome the above-mentioned problem, two methods were proposed and used in converters. In this first method, a current detection resistor *Rsense* is connected in series with the current loop at the output end to convert the current signal into a voltage signal. Then, use the comparison circuit or the current monitor IC to judge whether the overcurrent condition is reached. If the overcurrent condition is satisfied, turn off the synchronous rectification switch. Another method is to connect a current detection resistor *Rsense* in series with the ground current loop at the output end to convert the current signal into a voltage signal. Then, use the comparison circuit or the current detection IC to determine whether the overcurrent condition is occurring. If the condition is satisfied, the primary switch PWM duty is adjusted through the photocoupler control—to make the entire power supply achieve the functions of stability and overload protection. With these two methods, only a current detection resistor *Rsense* and comparison control circuit or current monitor IC are needed to achieve the purpose of current detection and protection. However, the current detection resistor *Rsense* is connected in series with the output main circuit. Because the current is large, in order to avoid excessive power loss, the current

detection resistor is usually very small. The current detection resistance *Rsense* is generally between several mΩ to tens of mΩ, depending on the output current. Therefore, the converted voltage signal is about tens of mV and hundreds of mV. The accuracy of such a small voltage signal is obviously insufficient for judgment and control. In addition, the power loss caused by the current detection resistor *Rsense* under heavy load is inevitable.

In a typical primary-side controlled flyback converter, a sensing resistor RS is used to convert the current on the primary side into a voltage *VS* and compares it with the reference voltage *VLIMIT* of the controller. When the sensing voltage *VS* is greater than the reference voltage *VLIMIT*, the comparator is activated to turn off the power switch. Unfortunately, in actual applications, due to the stray capacitance inside the semiconductor device, a fixed logic drive delay is caused. When the input voltage is high, the current slope *m* = *Vin LP* on the primary side becomes steeper. Due to the delay in the response time of the comparators, logic gates, and components, the power switch cannot be turned off immediately when the sensing voltage *VS* is greater than *VLIMIT*. As a result, the primary side current still maintains a fixed slope rise, and the overflow current Δ*IP* occurs and can be shown as [22]

$$
\Delta I\_P = \frac{V\_{in}}{L\_P} \cdot t\_{delay} \tag{3}
$$

where *tdelay* is the delay time that is the amount delay times of the comparators, logic gates, and other components.

Figure 2 shows a schematic diagram of overflow current Δ*IP* changes caused by signal delay under traditional peak current mode control. It can be seen that a higher input voltage *Vin* has a larger overflow current Δ*IP* than a lower input voltage. This leads to a significant difference. When the input voltage is higher, the power that can be provided to the load is higher, and vice versa. This is one of the main reasons affecting line regulation of flyback converter.

**Figure 2.** Overflow current with different input voltage.

In order to solve the above problem, many methods and techniques were proposed. The amount of overflow current Δ*IP* can be estimated by using the change of current in the same *tdealy* time. According to this estimated value to modify the PWM, the influence of *tdealy* can be reduced [21]. Furthermore, the CS sample-and-hold circuit is used to measure primary side peak current *Ip*. Then, by calculating the average current, a compensation control method that is theoretically unaffected by *tdealy* can be obtained [22]. Another method is to measure the mid-point current (i.e., average current) and use the average current control method, which can effectively reduce the influence of *tdealy* and increase the accuracy of the output current [23–25]. Recently, digital technology is also used to directly measure *tdealy*. Finally, *tdealy* is compensated to obtain accurate output current [17,20].

Although the above methods can be used to reduce the impact of *tdealy*. However, when an overload occurs and the output voltage is reduced, the output current cannot be suppressed. Therefore, the current rating of the components needs to be selected with a larger specification, just to meet the protection application. In order to solve this

problem, a Compensated Peak Current mode controlled PWM (CPC-PWM) for primaryside controlled flyback converters working in DCM is proposed in this paper. In the proposed CPC-PWM, the input voltage *Vin* is sensed and can be used to compensate for the control signal delay to reduce the overflow current Δ*IP* to improve line regulation. In addition, the current limiting by voltage feedback scheme [26,27] is referenced. The output voltage *Vout* of flyback is sensed and be used to compensate PWM to suppress the overload current.

#### **2. System Description**

In order to suppress the output current *Io* of the flyback converter during overload protection, the feedback compensator (FBC) is proposed in this paper. The inherent characteristics of the flyback converter output voltage *Vout* can be used to detect and adjust the PWM duty. Figure 3 shows the waveforms of a primary-side controlled flyback with FBC control working in DCM. As shown in Figure 3, when the output voltage *Vout* drops, the power switch duty cycle needs to be reduced to suppress the output current *Io*. This means that the PWM duty cycle *Da* during abnormal operation should be much smaller than the PWM duty cycle *Dn* during normal operation. The amount of this output voltage drop Δ*Vout* is the difference between the rated output voltage *V\** and the output voltage *Vout*. Thus, the input voltage of the negative terminal of the comparator *V-* will be compensated by the amount of this output voltage drop and written as:

$$V - = V\_{LIMIT} - k \cdot \Delta V\_{out} = V\_{LIMIT} - k(V^\* - V\_{out}) \tag{4}$$

where *k* is a positive constant. A larger *k* means a smaller duty cycle *Da* is obtained. Equation (4) can be rewritten as:

$$V - = k\_1 \cdot V\_{LIMIT} + k\_2 \cdot V\_{out} - k\_3 \tag{5}$$

where *k*1, *k*2, and *k*<sup>3</sup> are positive constant. It can be seen from (5) that when the output voltage *Vout* drops more, the voltage *V*− becomes smaller. This reduces the PWM duty cycle and achieves the purpose of suppressing the output current *Io*.

**Figure 3.** Waveform diagrams of a primary-side controlled flyback with FBC control working in DCM.

Figure 4 shows the theory expected V-I curves of a flyback with and without FBC. Comparing the V-I curves of the traditional method and the proposed method, the output current of the proposed method is much lower. It means that there is no need to choose a power component with a larger current rating. In this way, the power consumption

problem caused when the output load is increased or short-circuited can be suppressed, and the components with larger specifications can be avoided.

**Figure 4.** V-I curve of the traditional method and the proposed method.

In order to suppress the overflow current Δ*IP* of the flyback converter, the FeedForward Compensator (FFC) is proposed in this paper. The input voltage *Vin* of the flyback converter is detected and used to adjust the PWM duty, since the overflow current Δ*IP* is proportional to the input voltage *Vin* shown as (3). Figure 5 shows waveforms of a primary-side controlled flyback with FFC control working in DCM. As shown in Figure 5, the input voltage of the positive terminal *V+* of the comparator is extract added by *k Vin* as written as:

$$V + = V\_S + k' \cdot V\_{in} \tag{6}$$

**Figure 5.** Waveforms of a primary-side controlled flyback with FFC control working in DCM.

Equation (6) can be rewritten as:

$$V + = k\_4 \cdot V\_S + k\_5 \cdot V\_{in} \tag{7}$$

where *k4* and *k5* are positive constant. It is clear that when the input voltage *Vin* increases, the voltage *V+* becomes larger. When *V+* becomes larger, the power switch *S*1 will be turned off early. When (8) is held, the overflow current Δ*IP* caused by *tdelay* is eliminated.

$$\frac{k\_5}{k\_4} = \frac{t\_{delay} \cdot R\_S}{L\_P} \tag{8}$$

Based on the above discussion, the block diagram of the proposed CPC-PWM controller mentioned in this paper can be drawn as Figure 6b. Compared with the traditional peak current mode control PWM shown in Figure 6a, we can see that the FBC is added, thereby achieving the purpose of suppressing the output protection current. On the other hand, the FFC is also added, thereby suppressing the purpose of the overflow current Δ*IP*.

**Figure 6.** Control block diagrams of the traditional peak current mode control PWM (**a**) and the proposed CPC-PWM (**b**).

Design Example:

In order to verify the feasibility of the proposed CPC-PWM, a 5 W prototype is designed and realized. The specifications and circuit diagram of the prototype are listed and shown in Table 1 and Figure 7, respectively.

**Table 1.** Specifications of the realized prototype.


**Figure 7.** Circuit diagram of the proposed compensated peak current mode controlled PWM method.

The flyback converter proposed in this paper is mainly constructed by a transformer, an FBC, an FFB, and a power switch *S*1 as shown in Figure 7. The transformer includes a primary winding, a secondary winding, and an auxiliary winding or third winding. The output voltage of the third winding is injected into the feedback compensator circuit to adjust the PWM duty of the power switch. FBC is composed of a diode *D*1, four resistors *R*1, *R*2, *R*3, and *R*5, and three capacitors *C*1, *C*2, and *C*3, as shown as a red block in Figure 7. Due to the characteristics of the flyback converter, the energy is transferred to the secondary

side when the power switch is turned off. At the same time, the third winding is used to sample the output voltage condition to obtain the voltage *VT*. Due to the transformer leakage inductance, there will be a spike voltage and the voltage *VA* can be obtained only after being processed by a low-pass filter. A first-order RC filter is used and meet to (9) to filter out spike voltage

$$R1 \cdot \mathbb{C}1 \ge t\_{spike} \tag{9}$$

where *tspike* is the period of the spike voltage.

The feedback compensator is a network circuit and can be simplified as Figure 8. The simplified circuit is composed of three voltage sources *VA*, *Vref*, and *VLIMIT*, and four resistors *R*2, *R*3, *R*5, and *R*6. Voltage *V*− can be obtained and shown as (10) by using KCL law. Compared with (5), parameters *k*1, *k*2, and *k*<sup>3</sup> can be obtained and shown as (11)–(13).

$$V - = \frac{V\_{ref} \cdot G\_5 + V\_{LIMIT} \cdot G\_6 + V\_A \cdot G\_3}{(G\_5 + G\_6 + G\_3 + G\_2)} \tag{10}$$

where *GX* is the reciprocal of *RX*, that is a conductance.

$$k\_1 = \frac{G\_6}{(G\_5 + G\_6 + G\_3 + G\_2)}\tag{11}$$

$$k\_2 = -\frac{n\_3 \cdot G\_3}{n\_2 \cdot (G\_5 + G\_6 + G\_3 + G\_2)}\tag{12}$$

$$k\_3 = \frac{V\_{ref} \cdot G\_5}{(G\_5 + G\_6 + G\_3 + G\_2)} \tag{13}$$

**Figure 8.** Simplified FBC circuit.

The FFC is a network circuit composed of two voltage sources *Vin* and *Vs*, and two resistors *R*4 and *R*7. Voltage V+ can be obtained and shown as (14) by using KCL law. Compared with (7), parameters *k*<sup>4</sup> and *k*<sup>5</sup> can be obtained and shown as (15) and (16). In addition, the relation between resistor *R*4 and *R*7 is shown as (17).

$$V + = \frac{V\_{in} \cdot G\_7 + V\_S \cdot G\_4}{(G\_7 + G\_4)} \tag{14}$$

where *GX* is the reciprocal of *RX*, that is a conductance.

$$k\_4 = \frac{G\_4}{(G\_7 + G\_4)}\tag{15}$$

$$k\_5 = \frac{G\_7}{(G\_7 + G\_4)}\tag{16}$$

$$R\_{\overline{\mathcal{I}}} = \frac{R\_4 \cdot L\_P}{t\_{delay} \cdot R\_S} - R\_4 \tag{17}$$

The used components of the designed flyback converter as shown in Figure 7 are listed in Table 2.


**Table 2.** The used components and parameters in the design example.

#### **3. Experimental Results**

The feasibility and superiority of the proposed method are verified by discussing and comparing "overload current variation", "input power consumption during short circuit" and "overflow current variation".

Figure 9a–c shows the V-I curves obtained by using the traditional peak current control. Figure 9d–f shows the V-I curves obtained by using the proposed FBC method.

It can be seen from Figure 9a–c that the V-I curve has an obvious relationship with the input voltage *Vin*. When the input voltage *Vin* is higher, the overload point will also be higher. Figure 9d–f shows the V-I curves obtained using the proposed FBC method. It can be seen that when the input voltage *Vin* changes from 17 V to 34 V, there is no significant difference in the output current changes. It indicates that the proposed FBC method is significantly better than the traditional peak current control. From Figure 9d–f, we can also see that the output current during overload can be suppressed effectively by the proposed FBC as the theory predicted.

Figure 10a shows the comparison results of the measured overload point current using the traditional peak current control and the proposed FBC method. The variation rate of overload point current under different input voltages of the proposed FBC method is about 2% far better than the traditional 34.5%. In this design example, the traditional method requires at least a diode with a 1.7 A current stress. However, the proposed FBC method only needs a diode with 1.3 A current stress. Figure 10b shows the comparison results of the measured input power consumption using the traditional peak current control and the proposed FBC method under the output short circuit condition. Moreover, Figure 11b shows that the input power consumption of the proposed method under short-circuit protection is far superior to the traditional method. This means that there is no need to choose a power component with a larger current rating. In this way, the power consumption problem caused by the overload or short-circuited can be suppressed, and the components with larger specifications can be avoided.

Figure 11a–f shows the experimental waves under different input voltages of 17 V, 28 V, and 34 V when the flyback converter with/without FFC. In these figures, the positive terminal input voltage *V+* of the comparator, the negative terminal input voltage *V*− of the comparator, and the output voltage Vout waveforms of the flyback converter are shown. It can be seen from Figure 11a–c that without using FFC, the voltage *V*− starts to climb from zero voltage under various input voltages. Until voltage *V*− is greater than voltage *V+*, the power switch is turned off after the time *tdelay*. Observing the *V*− waveform, it can be seen that the input voltage *Vin* is larger and the overflow current Δ*IP* is larger. From Figure 11d–f, can be seen that an offset voltage is injected into *V*−, so that the overflow current Δ*IP* is suppressed. The injected voltage is about 51 mV, 90 mV, and 105 mV when the input voltage is 17 V, 28 V, and 34 V, respectively. According to the experimental results, the proposed method is close to the expected theoretical result. The voltage injected by

different input voltages will also be different, which can reach the *V+* voltage early to achieve the purpose of effectively reducing the overflow current Δ*IP*.

**Figure 9.** V-I curves obtained by using the traditional peak current detection circuit with input voltage (**a**) 17 V, (**b**) 18 V, and (**c**) 34 V, and by using the proposed FBC method with input voltage (**d**) 17 V, (**e**) 18 V, and (**f**) 34 V.

**Figure 10.** Experimental results (**a**) Overload current under different input voltage, (**b**) Input power consumption under different input voltage.

**Figure 11.** *V*−, *V*+, and Vout curves obtained by using the traditional peak current detection circuit with input voltage (**a**) 17 V, (**c**) 18 V, and (**e**) 34 V, and by using the proposed FFC with input voltage (**b**) 17 V, (**d**) 18 V, and (**f**) 34 V.

It is known that different voltage levels are required for different input voltages to be injected in the proposed FFC. From the experimental results, the accuracy of the VCS is still not enough. If we can analyze the characteristics of the control IC, such as the *tdelay* time of different voltages, it will help the FFC to be more accurate. On the other hand, the circuits of the proposed CPC-PWM can be digitalized and simplified. For example, a small Micro-controller can be used to replace the proposed circuit, which will contribute to its simple structure, accuracy, and flexibility.

#### **4. Conclusions**

In this paper, a feedback compensator (FBC) and a feedforward compensator (FFC) were successfully proposed to construct a novel Compensated Peak Current mode control PWM (CPC-PWM) for primary-side controlled flyback converters. The relevant theories and methods proposed in this paper have been confirmed by circuit implementation. A 5 W prototype with a wide input range has been designed and realized to access system performance. Using the proposed FBC, the PWM duty of a flyback converter working in overload can be descended to limit the current. The power consumption problem caused by the overload or short-circuited can be suppressed, and the components with larger specifications can be avoided. Using the proposed FFC, the effect of delay time can be descended to reduce the overflow current. The experimental results show that the proposed CPC-PWM can validate in a wide input voltage range and output short conditions, which also has good current accuracy and reduces power dissipation by about 68%.

**Author Contributions:** Conceptualization, C.-H.W., G.-R.H. and L.-R.C.; methodology, C.-H.W.; software, G.-R.H.; validation, C.-H.W. and L.-R.C.; formal analysis, C.-H.W., G.-R.H. and L.-R.C.; investigation, G.-R.H. and L.-R.C.; resources, C.-C.C.; data curation, C.-H.W. and C.-C.C.; writing—original draft preparation, C.-H.W., G.-R.H. and C.-C.C.; writing—review and editing, C.-C.C., C.-M.L. and L.-R.C.; visualization, C.-C.C., C.-H.W. and C.-M.L.; supervision, L.-R.C. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research received no external funding.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** Not applicable.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


**Luigi Schirone 1,\*, Matteo Ferrara 1, Pierpaolo Granello 1, Claudio Paris <sup>2</sup> and Filippo Pellitteri <sup>3</sup>**

<sup>1</sup> Scuola di Ingegneria Aerospaziale, Sapienza University of Rome, 00138 Rome, Italy;


**Abstract:** In space vehicles, the typical configurations for the Solar Array Power Regulators in charge of managing power transfer from the solar array to the power bus are quite different from the corresponding devices in use for terrestrial applications. A thorough analysis is reported for the most popular approaches, namely Sequential Switching Shunt Regulation and parallel-input Pulse Width Modulated converters with Maximum Power Point Tracking. Their performance is compared with reference to a typical mission in low Earth orbit, highlighting the respective strengths and weaknesses. A novel solar array managing technique, the Sequential Maximum Power Tracking, is also introduced in the trade-off and was demonstrated able to boost energy harvesting, especially in the presence of mismatching in the solar array. It also can achieve top levels of reliability using a rather simple control hardware. Its operation was verified both by a Matlab–Simulink model and by an experimental breadboard.

**Keywords:** satellite power sources; solar array regulation module; battery charge/discharge regulation module; maximum power point tracking (MPPT); sequential switching shunt regulation (S3R); power conversion unit

#### **1. Introduction**

Electrical power systems for space applications are highly demanding in terms of reliability: the related constraints of component screening and Single Point Failure Free (SPFF) circuitry set severe limits on available design solutions. Therefore, specific circuitry and regulation architectures were developed, quite different from those normally in use for stand-alone applications in the terrestrial environment, taking into account the other unique constraints of mass budget, electromagnetic compatibility, and not-convective heat exchange.

In addition, even the operating environment is quite different from terrestrial applications [1]. Spacecraft are exposed to a severe radiative environment that affects both solar cells, via crystallographic damage mainly related to absorption of energetic particles, and electronic components, that are also affected by the secondary radiation generated as a byproduct of the interaction between cosmic rays and spacecraft materials. Sunlight is also different as, unfiltered by the atmosphere, it is richer in photons in the visible and ultraviolet (UV) range, up to the UV-B spectral region (AM0 spectrum). Solar irradiance is 1367 W/m2, with ±3.5% seasonal variations for eccentricity of the Earth's orbit around Sun, plus some minor random fluctuations related to solar activity. Spacecraft periodically undergo eclipses with characteristics dependent on orbit geometry: in the most common Earth orbits the time spent in darkness ranges between 30 and 70 min, and sunlight time between successive eclipses varies from 1 h to some months.

**Citation:** Schirone, L.; Ferrara, M.; Granello, P.; Paris, C.; Pellitteri, F. Power Bus Management Techniques for Space Missions in Low Earth Orbit. *Energies* **2021**, *14*, 7932. https://doi.org/10.3390/en14237932

Academic Editors: Yitao Liu and Ching-Ming Lai

Received: 18 October 2021 Accepted: 23 November 2021 Published: 26 November 2021

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

The average albedo for Earth orbits is commonly assumed to be around 30%: in reality, it varies over the sunlight time, reaching its maximum when a spacecraft flies over the icy and cloudy poles, and its minimum over the "dark" oceans.

Solar panels in a common configuration are arranged as wings, continuously rotating around their axis to ensure normal incidence of direct solar radiation. Continuity of the current paths is achieved by dedicated slip rings inside the Solar Array Drive Mechanism (SADM). Many satellites otherwise have solar cells integrated in the external surfaces of the spacecraft body. In this case, the tilt angle of solar cells may be not uniform, leading to a diminished use of their photovoltaic surfaces. On the other hand, body-mounted solar arrays benefit from reduced complexity (no SADM or slip rings are needed) and are characterized by a smaller moment of inertia, enabling a more agile attitude control of the spacecraft.

The actual solar cell temperature depends on the details of the solar panels and the specific orbit: in the case of body-mounted solar cells, their good thermal conduction keeps solar cell temperature within a few degrees with respect to the satellite body, which is typically around 0 ◦C, whereas in the case of solar panels arranged as solar wings the deviations can increase to several tens of degrees, due to the ineffective heat exchange with the satellite body and to the higher relevance of radiative heat exchange to the dark space and to the Earth's surface. The orbit's altitude also affects temperature via the Earth's field of view: the minimum temperatures decrease to ≈−150 ◦C passing from LEO orbits (300–1000 km altitude) to Geostationary orbits (35,786 km altitude), whereas the maximum temperatures typically vary in the range +40 ◦C to +80 ◦C. In solar wings, the operating temperature also depends on the back-surface finish of the panels. Due to the small rate of heat exchange and to the high solar cell efficiency (typically in the 28–31% range), when a solar panel is in MPPT (Maximum Power Point Tracking) the heat to be dissipated is more than 400 W/m2 smaller than that observed in the open-circuit conditions, with a temperature drop that can reach a few tens of degrees.

Temperature transition rate also is a peculiar stress source for space solar arrays: in near-Earth orbits, at the end of eclipses (from eighty to six thousand times a year), the temperature of solar cells in a few minutes rises from a deeply negative value (−30/−150 ◦C, depending on the orbit altitude and on the satellite layout) to a positive value (+40 ◦C to +80 ◦C, depending on the layout of solar panels and the electrical operating point).

Mismatching is also an issue in space solar arrays. Controlled-pointing solar panels are not always used in spacecraft as sometimes the more compact approach of bodymounted solar cells is preferred. If this is the case, the different tilt angles affect the current–voltage characteristics of the single photovoltaic strings. Even in the most common case of controlled-pointing solar panels, several sources of mismatching can modify the current–voltage characteristics of a photovoltaic (PV) string in unpredictable ways. Among them, worth mentioning are temperature gradients, arising whenever the spacecraft enters eclipse. Other sources of mismatching may be partial shading, statistical dispersion of technological parameters, and solar cell failures. All of them can affect solar array uniformity by modifying the current–voltage characteristics of a string in unpredictable ways.

Since the 1970s the most widely used approach for spacecraft power conditioning has been Sequential Switching Shunt Regulation (S3R) [2], because of its high power density, modularity, simplicity, and inherently high reliability. Such shunt regulators also provide high power-path efficiency [3,4], as a solar array is split into sections that can be either directly connected-to or disconnected-from the power bus, as happens in the other regulation schemes belonging to the wider family of Direct Energy Transfer (DET) regulators: the Sequential Switching Shunt Series Regulator (S4R) [5], the Astrobus™ [6], the shunt module developed for the Galileo Power Conversion and Distribution Unit (PCDU) [7], and the Sequential Switching Shunt Maximum Power Point Regulator (S3MPPR) [8].

Power regulation schemes implementing Maximum Power Point Tracking (MPPT) techniques have been introduced since the 1990s [9,10]. At the expense of a larger complexity [11,12], they provide optimal energy harvesting in a wide range of operating

conditions. This is critical in missions in Deep Space, such as Rosetta-Mars Express [11,13] or GOCE [14], and in certain low Earth orbits, where the solar array characteristics undergo wide variations for temperature, intensity of solar radiation, or aging. The typical MPPT Solar Array Regulators are based on classical Pulse Width Modulated (PWM) series switching converters [15]. The converter is a stepdown in most applications, such as Globalstar 1 [9], Mars Express, Rosetta [11], Venus Express [16], Goce [14], Swarm [17], Lisa Pathfinder [18], Juice, and Exomars [19]. In most cases, the configuration is the two-inductors buck configuration [20]. Step-up configurations were used for Globalstar 2 and some high-power spacecraft such as BepiColombo [13,21]. Top flexibility in the solar array configuration is achieved by using Solar Array Power Regulators (APR) comprising step-up/step-down converters [22,23], so that the solar array voltage may vary across the power bus voltage.

A first attempt to gather advantages of both approaches by introducing MPPT capability in S3R power units was proposed in [24]. It was further developed in [8,25] and then specialized for applications in spacecraft with electrical propulsion [26] or in geostationary satellites [27].

All previously introduced regulation approaches provide specific advantages and limitations so their trade-off has been widely debated [15,27]; so far, no power conditioning technique has been established as a standard. The heritage of manufacturers and agencies also affects the trade-off.

This work is intended to contribute to the debate taking into account in the trade-offs of other specific solar array management techniques capable of providing advantages with respect to all previously reported approaches.

In sectional MPPT power units [15], the solar array is split into several sections, each fitted up with a dedicated Solar Array Power Regulator (APR) with a multimode controller, capable of either independently performing MPPT or harmonically contributing to the regulation of the bus voltage or the battery current. Coordinate operation of the different APR in regulation mode is a major issue with these systems so some authors [28] developed to the purpose algorithms to be embedded in powerful supervisors.

An expedient solution appears to be provided by the Sequential Maximum Power Tracking (SMPT) bus regulation technique: the coordination problem is solved by implementing an operational sequence such that just one section at a time is kept in control mode, while the others are kept either in MPPT or in standby.

A thorough description of the main regulation techniques and SMPT operation is given in Section 2. A comparative analysis of S3R and the regulators based on MPPT or SMPT techniques is discussed in Section 3 with reference to a typical space mission in low Earth orbit, in the presence of relevant mismatching in the solar array. Section 4 is dedicated to the demonstration of SMPT operation, based on both a Matlab–Simulink model and on the experimental results provided by a breadboard built with automotive-grade components.

#### **2. Solar Array Regulation Approaches**

#### *2.1. Sequential Switching Shunt Regulation*

In S3R systems, the solar array is split into N sections directly connected to a power bus via blocking rectifiers. Each of them is also equipped with a shunt switch that can be tripped on in order to block power transfer to the bus (Figure 1). In order to reach a power balance between solar array generation and load absorption, the active solar array sections are set according to a pre-ordered sequence [4]: when the required solar array generation GSA is smaller than the power supplied by M solar array sections, but larger than the power supplied by M − 1 of them, rough regulation is provided by keeping M − 1 sections permanently enabled and the other N-(M − 1) permanently disabled. Fine regulation is achieved by hysteretic control of the duty cycle on the shunt switch of a single solar array section.

**Figure 1.** Power module with Sequential Switching Shunt Regulation.

The battery is typically interfaced to the bus via a Battery Charge Regulator (BCR) and a Battery Discharge Regulator (BDR) (full-regulated bus configuration). The BDR may be replaced by a simple rectifier (sun-regulated bus), especially in the missions involving a small Depth of Discharge (DoD).

Regulation control is performed by a Main Error Amplifier, generating both the activation sequence for the direct-current (dc) shunts and the duty cycle for the switching solar array section. It is based on a consolidated, simple, and Single Point Failure Free (SPPF) circuitry, with very high reliability.

A variant DET regulation scheme, the Sequential Switching Shunt Series Regulation (S4R) has also been proposed, with an original configuration of the battery charge regulator [29] that is more efficient and decoupled from the bus regulation control. The improvement comes with a reliability issue, as in the original layout the battery-charging path is not SPFF [30].

For the sake of the analyses proposed in this work, minor differences in performance are observed among Direct Energy Transfer (DET) regulation approaches and thus only S3R will be considered.

#### *2.2. Maximum Power Point Tracking Regulation*

The photovoltaic source supplies the power bus via a series dc–dc converter enslaved to a multimode controller that can operate in either regulation or maximum power point tracking (MPPT) modes.

A survey of Maximum Power Point Tracking techniques is given in [31], whereas deeper insight about modelling and stability issues can be found in [32] and [15,33], respectively. The same algorithms used in stand-alone terrestrial applications may be used: Perturb and Observe [34] is preferred when the MPPT controller is embedded in software, whereas Incremental Conductance can be implemented by a hardware circuit, as described in [11]. The first one is more flexible and can be easily upgraded to manage quick transients or multiple maximum power points. On the other hand, some kind of digital processor is required, which can be quite expensive when carried out with space-qualified devices. The latter only requires a few discrete components but can face some stability problems in managing fast load variations [12]. The main difference with the MPPT algorithms for terrestrial applications is in the dynamical model of solar panels, which are made with solar cells based on technologies not used in terrestrial applications.

When load absorption is small, the multimode controller is in either constant-current or constant-voltage regulation mode and the operating point of the solar array typically is in the low-current region. Thus, in response to an increase of power absorption from the loads, the feedback loop increases the duty cycle, pushing the SA operating point towards higher currents [34]. When current exceeds the Maximum Power Point, further increases of duty cycle result in power reductions, and the controller switches to the MPPT mode. From there, the operating point is driven to and kept close to the global maximum power point, according to a proper tracking technique. The regulation mode starts again when the load absorption returns below the maximum available power from the solar array.

On the other hand, the system architectures are heavily affected by the requirements of reliability: several redundancies are normally introduced in the power conversion unit in order to avoid the risk of Single Point Failures. In the configuration used for many space missions [11,16], the whole solar array is split into two parts, corresponding to the spacecraft wings. In each of them (Figure 2), all photovoltaic strings are connected in parallel to supply a power module comprising three hot-redundant converters. Precisely the redundancy scheme is two-out-of-three partial redundancy [11] because each converter is sized to carry up to 50% of the overall power so that losing one of them will not affect spacecraft operation. In the space power literature, this configuration for the solar array regulator is commonly referred to as "MPPT".

**Figure 2.** Power Module with the classic MPPT regulation for space solar arrays.

The controller also consists of three modules connected according to the majority voting redundancy scheme, allowing for the detection and dismissal of a single unmatched signal. The output bus is regulated, involving the use of both battery interface converters, with their mass and power losses.

#### *2.3. Comparing MPPT and S3R*

The trade-off between MPPT and S3R has been widely debated in the space power community [4,11], as both provide specific advantages. This led to several proposals to combine the specific advantages of both techniques [23,24], also developing techniques tailored for specific applications [26,27].

The S3R controller is based on a consolidated circuitry, simple and SPFF, that easily matches the required levels of reliability.

The MPPT-SAR scheme reported in Figure 2 involves more complex circuitry, and reliability has to be increased by the redundant connection of parallel converters. In practice, in addition to using reliable and SPFF circuitry inside the different converter blocks for their coordination, it is necessary to make them functionally independent, preventing propagation of any type of failure along any power or signal lines, and also avoiding harmful thermal couplings.

The shunt regulation approach used in S3R minimizes dc losses in the power path, as just the blocking rectifiers are in series to the electrical connections. The switching losses also are small, because alternate current (ac) flows only in the section performing

fine regulation, and the ac losses are substantially limited to charging/discharging of the switch capacitances, at a frequency that is typically in the 10–20 kHz range. The ripple is filtered out by a capacitor bank with no inductors. Thus, efficiency can be larger than 96%, depending on the bus voltage.

In reality, the serial dc–dc conversion used in MPPT regulators involves larger power losses [35], as the whole current undergoes switching at a frequency of a few hundreds of kHz [11], generating appreciable ac power losses both in the active devices and in the magnetic components. In space missions with few eclipses and stable operating conditions for the solar arrays, e.g., geostationary satellites, the related losses (typically a few per cent) can offset the benefits of the Maximum Power Point Tracking capability, and DET converters are preferred.

On the other hand, energy harvesting in S3R is less effective, because the solar array has the voltage tied to the bus voltage, independent of its actual current–voltage characteristics. Thus, wide margins must be taken in the solar array design in order to avoid that—in the most unfavorable conditions—parametric variations (e.g., due to heating or aging) may cause the Open Circuit Voltage of any string to fall below the bus voltage. This causes inefficient use of the solar panels, which normally are operating at voltages far from their maximum power point voltage (VMP) even during the load peaks.

Otherwise, in the case of MPPT, especially when a converter configuration with buckboost capabilities is chosen [22,23], all available power can be exploited independently of solar array voltage. This capability may be used for more effective sizing of solar arrays, and/or to produce extra power. It could simply be used to reduce the depth of the battery cycles, allowing for smaller batteries, with advantages also from a systems point of view. In some missions the extra available power can be used to increase, even temporarily, payload capability (e.g., in a TLC spacecraft to increase the number of transmission channels) and/or to widen the payload duty cycle.

In MPPT-APR the bus voltage is decoupled from solar array voltage, thus enabling the direct connection of the battery to the bus (unregulated bus configurations), at least in the missions involving small battery Depth of Discharge. Therefore, the mass and the power losses of both BCR and BDR may be avoided, even if they are still used in specific spacecraft, e.g., in [11].

The challenge of merging MPPT functionality into S3R systems with no reduction in reliability and a negligible increase in complexity was first faced in [24]. The proposed approach was to enslave the bus voltage in S3R to an MPP tracker [4]. This can be done by minimal modifications to the classical S3R circuitry and has a main drawback, related to the wide variations of the bus voltage (tens of volts) arising from VMP variations. Such variations can be managed either by widening the input range for all devices connected to the bus, at the expense of their performance, or by introducing some bound to the voltage tracking range, at the expense of the energy harvesting capability. In either case, using a full battery interface is mandatory, with the related mass and power losses.

In the systems based on the MPPT-SAR in Figure 2, as in S3R, all photovoltaic strings are connected in parallel so that any source of mismatching would make the overall maximum power smaller than the sum of the maximum contributions that would be available from individual strings. Therefore, both approaches appear to be not perfectly fitted for missions in low Earth orbit, where eclipses frequently trigger temperature transitions, with the related thermal gradients inside the solar array, and sometimes partial shading.

#### *2.4. Sequential Maximum Power Tracking Regulation*

The effects of mismatching are reduced with the sectional MPPT configurations [15], first used in [9]: the solar array is split into N sections independently interfaced to the power bus by means of dedicated APRs (Figure 3) capable of tracking their individual MPP to provide optimal energy harvesting. This feature appears particularly interesting in spacecraft with body-mounted solar cells, where the variable angles of incidence may force photovoltaic strings to work at different operating points. Sectional MPPT may also reduce

the effects of other sources of mismatching, such as temperature gradients, partial shading, statistical dispersion of technological parameters, and solar cell failures. All of them can affect solar array uniformity by modifying the current–voltage characteristics of any string in unpredictable ways.

Despite these advantages, and all other advantages of MPPT–SAR that still are effectual, sectional MPPT has seldom been used in space. An issue for its application with battery buses is the need to coordinate the different APRs during the regulation modes through effective and reliable circuitry. SMPT provides an effective solution to this issue.

Each APR can either autonomously perform current/voltage regulation based on shared feedback signals or can manage MPPT for the dedicated solar array section. At the same time, all APRs share their operational status via redundant I/O lines. Thus, the SMPT algorithm is implemented on the basis of both shared status signals and of shared feedback signals. The issue of coordinating the operation of the APRs is faced by keeping just one of them in regulation mode, with the others either in MPPT or in standby. The power-up sequence outlined in Figure 4 clarifies SMPT operation: at turn-on an APR starts operating in regulation mode, autonomously adjusting its output power to enforce the desired control law. If the feedback loop drives it in MPPT, the next APR in the sequence is turned on and takes charge of regulation. The sequence continues until the desired bus condition is achieved, e.g., with APRM in regulation mode, APR1 to APRM−<sup>1</sup> in MPPT mode, and APRM+1 to APRN in standby. In response to a decrease of the load absorption, the sequence is run in the opposite direction: when the feedback loop is going to quench APRM, APRM−<sup>1</sup> exits MPPT mode to start regulation, while APRM ends in standby.

**Figure 4.** Power-up sequence in a SMPT regulator with four solar array sections. Left plot: overall power absorption vs. time. Right plot: power supplied by the single APRs and by the battery.

Thus, the operational state of all APR's is coordinated based on a small number of signals, that can be easily made SPFF.

An option for the sequence control is to use a central device, in charge of exchanging status signals and enabling signals with all APRs. The control circuitry as well as all I/O lines must be redundant and Single Point Failure Free, to avoid that a single malfunction may result in a failure for the entire power system.

In the case of low-cost missions based on Components Off The Shelf (COTS), the reliability of single components is not easily predictable, and the two-out-of-three redundancy scheme may not be sufficient to ensure required reliable operation. Thus, it could be convenient to use a distributed sequence control, where each APR autonomously manages its operational mode according to the shared status signals and a wired sequence. In order to avoid that the loss of control on a single APR may affect the target performance, it is easy to use the SMPT modularity to implement partial redundancy schemes, such as N-of-(N + 1), so that the need for a Failure Free central control unit is offset to the requirement of no-failure-propagating interfaces (signal, power and thermal) among different APRs.

In any case, SMPT also is intrinsically more reliable than the classical parallel MPPT, first because there is no input node with all PV strings connected in parallel. Moreover, the last APRs in the sequence can spend most of their time on standby and therefore undergo a reduced failure rate [36].

When SMPT regulation is compared to S3R, all advantages of sectional MPPT are confirmed: it allows high flexibility in designing solar array voltage and can use MPPT to get top power harvesting even in mismatched solar arrays. It also shares some drawbacks, related to the larger complexity of the switching cells, even if this is partially compensated by the possibility of using an unregulated bus, thus avoiding the burden of the battery interface converters.

A summary of the main features of the investigated regulation techniques is provided in Table 1. The first row reports the efficiency of the conversion cell, as it represents the top efficiency theoretically reachable by the converter when neglecting all the power used to supply controllers, telemetries, redundancies, and all service circuitry. For instance, in the case of the two-out-of-three partially redundant systems reported in [11], three dc–dc converter cells are continuously running at a power level that is not exceeding 66%, until a failure event blocks one of the converter cells. Thus, the efficiency of the overall regulator is reduced due to a non-optimal power level and is also affected by the triple control circuits, so that it can hardly be evaluated, despite the fact that losses in the conversion cell are easily predicted.


**Table 1.** Summary of the main features of the investigated regulation techniques.

#### **3. Comparison among the Regulation Techniques**

A trade-off analysis of the considered regulation techniques has been developed. The analyses are in reference to a specific case study, an Earth Observation Spacecraft flying in a Sun-synchronous orbit at 380 km altitude, characterized by [1], an orbital period T0 = 90 min, with 30 min eclipse duration. This trend is typical for low Earth orbits: the exact value of the irradiance duty cycle depends on orbital altitude, inclination, and eccentricity, and in a circular orbit it is lightly larger than 66% at 300 km, and smaller than 60% at 1500 km. Only in very special orbits it can be close to 100% (e.g., in downdusk orbits, where the orbital plane is almost orthogonal to the solar vector). Due to this variability, we were forced to develop our analyses in reference to a very specific space mission, assuming that the general conclusions could be extended to similar applications, including many low Earth orbits with pulsed loads.

In order to perform a straight trade-off analysis, the solar radiation collected by the panels has been assumed to be only affected by eclipses (step transitions from darkness to sunlight, neglecting penumbra times) and by solar panel temperature. As the actual solar cell temperature depends on the details of the solar panels, in our analyses we referred to typical textbook data for low Earth orbit missions [37] (Sections 9.3–4) and assumed that temperature was in the range −60 ◦C (at the end of eclipse) to +40 ◦C (at the beginning of eclipse). Figure 5 reports the trends considered for this trade-off analysis for irradiation (orange curve, right axis) and temperature (blue curve, left axis).

**Figure 5.** Irradiation (orange curve, right axis) and solar cell temperature (blue curve, left axis) in the considered orbit.

The solar array considered for this case study was able to provide 1.4 kW in AM0 at Beginning of Life and consisted of 1088 triple-junction solar cells, model CTJ30 by CESI, arranged in 64 strings of 17 series-connected cells, grouped as 8 independent sections. The analyses were based on their expected performance after aging by absorption of a radiation fluence of 5 × <sup>10</sup><sup>14</sup> equivalent 1 MeV electrons, corresponding to several years in a typical Sun-synchronous polar orbit.

In order to stress differences among the regulation approaches investigated in this work, mismatching among solar array sections has been taken into account. In particular, it was assumed that a section underwent a relevant reduction of the output voltage, which in real operation may be caused by damaging or shadowing a group of solar cells, with activation of the dedicated bypass diodes.

Table 2 collects the values of Open Circuit Voltage (VOC), Short Circuit Current (ISC) and their thermal coefficients considered for the different solar array sections.


**Table 2.** Electrical parameters of the solar array sections.

The model for Solar Arrays accounts for temperature effects on the solar cell characteristics. Based on the thermal coefficients and other specification data published by the manufacturers [38], estimated current–voltage pairs for a representative set of temperatures were collected in a Look-Up-Table, allowing derivation by interpolating the current–voltage characteristics at any temperature in the considered range.

The available power depends on the regulation approach, as reported in Figure 6. When the loads absorb all available power from the solar array, in S3R all sections in parallel are tied to the bus voltage; in MPPT all sections in parallel are kept at the voltage corresponding to the maximum power point of the overall solar array; in SMPT optimal energy harvesting is achieved as each section independently is kept at the voltage corresponding to its Maximum Power Point.

**Figure 6.** Available power from the solar array with the different regulation approaches.

The difference between the curves related to SMPT and MPPT is related to mismatching in the solar array: the common node in basic MPPT regulators keeps some sections at a voltage different from their actual VMP, whereas in the sectional MPPT approaches, such as SMPT regulation, all solar array sections are working at their optimal voltage. Otherwise, in S3R the operating voltage for solar arrays is fixed independently of the variations of VMP. Furthermore, due to the negative thermal coefficient for voltages, after some minutes in sunlight the sections starting with the smaller VOC may be forced to work in the low-current region of their characteristics, with appreciable power reductions. In Figure 7 it is clearly seen that this happens for the section 8 in the solar array, whose open-circuit voltage at 25 ◦C was just 3.3 V larger than the bus voltage.

**Figure 7.** With S3R all solar array sections but section 8 supply the same output power (section 8 has a relevant decrease in Voc, whereas minor differences among Voc of sections 1–7 exist, so that the curves are superimposed).

The load profile considered for the spacecraft is reported in Figure 8. Basic activities absorb 200 W both in sunlight and in eclipse, and periodically the operations of the payload or some spacecraft subsystems result in additional peaks of 900 W for 5 min and 3.2 kW for 1 min. The conversion efficiency was assumed to be 96% for S3R and 92% for both MPPT-APRs and SMPT-APRs.

**Figure 8.** The considered load waveforms.

The battery supplies the spacecraft during eclipses and load peaks. During sunlight it absorbs 200 W for recharging, whenever enough power for the purpose is available (see Figure 9, lower curves, left axis). During the peaks of load absorption, the battery stops charging and, when needed, sustains the load with suitable discharge pulses.

**Figure 9.** Battery State of Charge (upper curves, right axis) and Charging Power for battery (lower curves, left axis).

The trend of the battery State of Charge (SoC) (Figure 9, upper curves, right axis) shows that high load pulses may result in deep cycles in the battery: as expected, the depth of discharge is at a maximum for S3R. This could affect battery duration [37] and shall be compensated by increasing the size of the battery.

For the considered case study, the overall amounts of energy per orbit delivered by MPPT and S3R are quite similar, as the larger efficiency of S3R is compensated by the poorer harvesting of the power available on the solar array. For the chosen solar array, the MPPT regulator completes battery recharging with a small margin with respect to the available sunlight time, whereas the S3R regulator is not able to fully recharge the battery recharging: larger solar arrays would be needed to enable energy balance with S3R.

Otherwise, the larger amount of available power, as shown in Figure 6, enables the SMPT regulator to complete battery recharging well in advance of the next eclipse. It is clear that the case study was specifically built to highlight the strengths of the sectional MPPT approaches such as SMPT, but there is no doubt that these regulation techniques provide clear-cut advantages in terms of performance.

#### **4. SMPT Simulation and Experimental Results**

A model of the SMPT regulator was developed in Simulink, aiming to demonstrate the operation of the sequencing algorithm. As shown in Figure 10, the system consists of four blocks, each comprising a solar array section (in blue), an APR consisting of a dc–dc converter (in grey), and a dedicated controller in charge of managing the SMPT sequence on the basis of the status signals coming from other blocks as well as regulating the APR output current (Iout) to enforce the desired overall control law for the battery and the power bus. All converter outputs are connected in parallel and supply a battery and a variable resistive load.

The converter configuration is SEPIC [39], providing both step-up and step-down operation to allow the solar array sections to operate at voltages across the battery voltage. The circuit embedded in the submodel blocks is reported in Figure 11.

**Figure 10.** Simulink model of the SMPT technique. The subsystem blocks (in grey) model the SEPIC converters directly from their circuit schematics. The blue blocks are library blocks for photovoltaic arrays.

**Figure 11.** Submodel block for the SEPIC converters.

The control block of any APR sets the operating mode according to the observed battery current, to the Duty Cycle (DuC) of the corresponding converter and to the status signals received from other APRs (see Figure 12). Any single controller can work in three different modes:


Changes of state are triggered by the signals shared with the other APRs, namely two signal lines shared with the previous APR in the start-up sequence and one signal line with the next one. More precisely, they are:


In the Simulink model reported in Figure 10, the PID\_COM\_IN input and the MPPT\_COM output are not provided in the last converter because there is no next converter, while the PID\_COM\_OUT is not provided in the first converter because there is no previous converter.

Operation is described in detail in the flow chart reported in Figure 12. An APR enters the PID control mode when it receives a positive level on the START input line. The operating mode passes to MPPT when a Maximum Power Point is detected via a change in the slope of the power-vs-duty cycle trend. At that moment, a START signal is sent to the next APR in the sequence, that enters the PID mode. Otherwise, in case the controller drives the APR output current to zero, the operating mode passes to IDLE and a signal on the PID\_COM line forces the previous APR to exit MPPT and start PID mode. Adequate thresholds and hysteresis have been introduced to achieve smooth operation.

The simulation was carried out with the following parameters:


The system was turned on with the bus absorption at 400 W including the load, and with the charging current for the battery set to 4 A. As depicted in Figure 14, a first APR, say APR1, is activated and its output current increases attempting to achieve power balance. After a few tens of milliseconds, its output current reaches its maximum and the APR1 starts operating in MPPT while the next section is activated in regulation mode. The step is repeated for the solar array sections 2 and 3 until around 0.3 s. The power balance is achieved with APR4 in regulation mode.

**Figure 12.** Flow chart of the control algorithm.

**Figure 13.** Load profile for the simulation.

**Figure 14.** Waveforms provided by the Simulink model of the SMPT technique: Ibat: battery current; Iload: load current; Iout*n* with *n* = 1 to 4: output current of APR*n*. All currents are in amperes.

After 0.75 s the load absorption is further increased to 800 W. When APR4 also goes into MPPT, all the available power from the solar array is delivered to the load and the battery starts discharging at nearly 12 A to balance the load demand. The load absorption returns to 400 W at 1.8 s and the previous operating point is quickly recovered. At 2.5 s a further load variation reduces the load absorption to 140 W, and the solar array sections 4 and 3 sequentially quench their outputs. The final equilibrium is found with section 2 in the regulation mode. During the transients, the control on battery current loosens and some deviations with respect to the expected trend are observed. They are particularly evident at 0.75 s, 2.5 s, and 2.7 s. An improved design of the control law will reduce this effect.

The operation of the SMPT algorithm was also experimentally demonstrated by a PCDU breadboard based on SEPIC APR converters. The regulation controller and the SMPT sequencer were both embedded in automotive microcontrollers. A detailed description of the breadboard is out of the scope of this work.

The test setup is shown in Figure 15. The photovoltaic source was provided by a Keysight E4360 two-channel Solar Array Simulator, with both channels configured as VOC = 44 V, ISC = 3.3 A, VMP = 39.5 V, and IMP = 3.2 A in order to reproduce the typical current–voltage characteristics of solar array sections consisting of 102 triple-junction solar cells in AM0 conditions [38], arranged as 6 parallel strings of 17 solar cells in series. The output bus was directly connected to a storage unit consisting of a battery bank with 36 Li-ion cells (size 26650), arranged as 4 parallel strings of 9 cells (4P9S). At the beginning of the tests, the battery was at a voltage VBAT = 30 V. During the tests, the load was provided by a Hewlett Packard 6060B electronic load, and the overall bus absorption was varied in the range 0–180 W in current-control mode, with the current for battery charging stabilized at 2 A.

**Figure 15.** The test setup (**left**): the breadboard PCDU is supplied by a Keysight E4360 Solar Array Simulator and drives a power bus connected to a 4P9S Li-ion battery and to the loads. The converter board of the PCDU (**right**), designed to accommodate up to eight channels.

The solar array voltages observed during the tests are shown in Figure 16. As it is possible to see, the controllers used short-circuit as a starting condition so that the operating point moved in the V < VMP region, where the current is almost a constant. Therefore, the reported solar array voltage waveforms provide a glance at the input power of the different APRs.

At system turn-ON (t1), the overall output power was POUT < 120 W, resulting from battery charging at 2 A, and an additional 60 W load in parallel. The APR1 (yellow trace) was controlling the charging current, while APR2 (blue trace) was set to a base condition, with output power smaller than 20 W, just to keep the converter in Continuous Conduction Mode. At t2 the load was increased to 120 W (overall output power Pout = 180 W), the APR1 was forced into MPPT, and the control passed to APR2 (blue trace). Then, at t3, the load returned to 60 W: APR1 first kept the MPPT mode until the output power of APR2 went below base power level (at t4), then APR1 started again to operate in the control mode. In the meantime, APR2 was set again to 20 W. The waveforms also show the system turn-off at t5.

**Figure 16.** Solar array voltages during a load peak. At turn-ON the operating point is controlled by the APR1 (yellow trace) with the APR2 (blue trace) at a base power level. When a load peak forces APR1 into MPPT, APR2 takes control of the operating point. The reverse transient for a load reduction also is shown.

#### **5. Conclusions**

Operation of the power bus regulation techniques most popular in space applications and that of the novel SMPT bus regulation technique have been introduced and analyzed with reference to a mission in low Earth orbit. It was shown that SMPT could provide appreciable improvements: it has optimal energy harvesting in the presence of a mismatched solar array, it is suitable to drive unregulated power buses, and uses quite a simple controller that can be easily designed to be SPFF. Performance improvements are particularly evident in the presence of pulsed loads. An experimental prototype and a Simulink model allowed us to demonstrate the functionality of the SMPT technique. Future activities will be intended to develop an improved controller, capable of providing faster transient responses while remaining robust against variations of the dynamic response of both solar panels and battery. Extensive characterization of the prototype also will be carried out to assess the boundaries of the APRs' safe operating area in the perspective of future use in actual spacecraft. The research will proceed, aiming at developing new power management configurations, with enhanced reliability and larger efficiency.

**Author Contributions:** Conceptualization, methodology, investigation (equal), writing, and supervision, L.S.; software, investigation (equal), and data curation, M.F.; prototyping, investigation (support), P.G.; investigation (support), C.P. and F.P. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research received no external funding.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** Not applicable.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


### *Article* **Adaptive Tracking Method of Distorted Voltage Using IMM Algorithm under Grid Frequency Fluctuation Conditions**

**Haoyao Nie 1,2 and Xiaohua Nie 3,\***


**Abstract:** This paper newly proposes an interactive multiple model (IMM) algorithm to adaptively track distorted AC voltage with the grid frequency fluctuation. The usual tracking methods are Kalman filter (KF) algorithm with a fixed frequency and KF algorithm with frequency identifier. The KF algorithm with a fixed frequency has a larger covariance parameter to guarantee the tracking robustness. However, it has a large tracking error. The KF algorithm with frequency identifier overly depends on the accuracy and stability of frequency identifier. The advantage of the proposed method is that it is decoupled from frequency detection and does not depend on frequency detection accuracy. First, the orthogonal vector dynamic (OVD) tracking model of the sine wave is established. Then, a model set covering the grid frequency fluctuation range is formed, and a new OVD-IMM tracking algorithm is proposed in combination with IMM algorithm. In the end, the effectiveness and accuracy of the proposed OVD-IMM algorithm are verified through simulations and experiments.

**Keywords:** frequency fluctuation; distorted voltage; Kalman filter; dynamic tracking model; interacting multiple model algorithm

#### **1. Introduction**

The Kalman filter (KF), which is widely used in some power electronics fields, represents its advantages such as zero steady-state error, high real-time performance, better division of signal state and noise, and so on [1]. For example, it applies to the following fields such as harmonic estimation [2–8], travelling-wave fault location [9,10], waveform envelope detection of AC signals for power quality control equipment [11–17], power quality disturbance detection and classification [18–26], and synchronization control methods [27–33], and so on.

As we all know, as the source-grid-load changes, the power grid frequency is not fixed at 50 Hz but fluctuates with time. Frequency fluctuation obeys non-Gaussian distribution. Its fluctuation range generally reaches 49.5 Hz–50.5 Hz [34]. Some methods in the literature are to use the KF algorithm with a fixed frequency [27,28]. When tracking the AC voltage, the KF algorithm covariance parameter is 0.05. The parameter of 0.05 is larger and the frequency band is wider. It guarantees the robustness of the KF algorithm when the frequency fluctuates. However, it has a large tracking error. Another method uses KF algorithm with real-time frequency identifier, as shown in Figure 1 [29–33]. This kind of tracking method realizes adaptive tracking by feeding back the estimated value of the fundamental frequency. Different frequency detection algorithms are used in the literature, such as extended Kalman filter (EKF) combined with integrator estimation method [29], generalized averaging method [30], frequency locked loop (FLL) [31–33], etc. The disadvantage of the KF algorithm with frequency identifier is that it requires a large amount of calculation and high frequency accuracy. If the frequency identifier is inaccurate

**Citation:** Nie, H.; Nie, X. Adaptive Tracking Method of Distorted Voltage Using IMM Algorithm under Grid Frequency Fluctuation Conditions. *Energies* **2021**, *14*, 7944. https:// doi.org/10.3390/en14237944

Academic Editor: Muhammad Aziz

Received: 3 November 2021 Accepted: 22 November 2021 Published: 26 November 2021

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

or unstable, it will affect the electrical signal tracking and parameter measurement accuracy, and even cause tracking failure.

**Figure 1.** Tracking method based on KF algorithm with frequency identifier.

This paper presents a new method for tracking the distorted AC grid voltage of the frequency fluctuation using (interacting multiple models) IMM algorithm. It is shown in Figure 2. By comparing Figures 1 and 2, the advantage of IMM algorithm is that it does not require frequency detection and feedback tracking, and the tracking method is not affected by frequency detection accuracy and can achieve full self-adaptation. The IMM algorithm is an algorithm with Markov switching coefficients, in which multiple models of different frequencies work in parallel, and the tracking output is the result of the interaction of multiple filters [35–41]. The transfer between models is determined by Markov probability transfer matrix, which can effectively adjust the probability of each model. IMM estimates through the interaction between multiple models. Compared with the single-model algorithm, IMM is more adaptable to the fluctuation of the estimated object. It is used in hybrid control system tracking [38], maneuvering target tracking [39], human pose estimation [40], dynamic state estimation of distribution network [41], etc.

**Figure 2.** Proposed tracking method based on IMM algorithm.

The contributions of this paper are as follows: (a) the orthogonal vector dynamic (OVD) model is re-derived from the stochastic process theory [42], which made it clear that the covariance matrix is related to the sampling cycle. The orthogonal vector (OV) model used in conventional KF algorithm lacks theoretical derivation, and the covariance coefficient is only a fixed value of 0.05 [27,28]. The derivation of the OVD model lays the foundation for the application of the IMM algorithm. (b) The OVD-based IMM (OVD-IMM) algorithm of two models is proposed to adaptively track distorted AC grid voltage with the frequency fluctuation.

Section 1 introduces a new method for tracking the distorted AC grid voltage of the frequency fluctuation using (interacting multiple models) IMM algorithm. In Section 2, the OVD model is re-derived according to of stochastic process theory. The state space of the OVD is expanded. In Section 3, the OVD-IMM algorithm is presented and developed. In Sections 4 and 5, the performances of OVD-IMM algorithm are evaluated and compared by simulation and the experiment data. Section 6 makes a conclusion of the paper.

#### **2. OVD Model**

In Section 2, we illustrate the principle of OVD modeling. The covariance matrix of state noise for OVD model is reorganized according to the theory. The relationship between the model and the sampling cycle is clarified. We expand the state space dimension of OVD model.

#### *2.1. Derivation of OVD Model*

In two-dimensional space, the circular movement of the object along the midpoint is projected on the x, y axis as a pure sine and a pure cosine waveform, as shown in Figure 1. It can be expressed as

$$\begin{cases} \begin{array}{l} \boldsymbol{x}(t) = A\_{\text{m}} \sin(\omega\_{0}t + \theta) \\ \boldsymbol{y}(t) = A\_{\text{m}} \cos(\omega\_{0}t + \theta) \end{array} \tag{1} $$

where, *Am* is the amplitude, *ω*<sup>0</sup> is the angular frequency, and *θ* is the phase angle. The diagram demonstrates how the object circular movement being projected in Figure 3.

**Figure 3.** Diagram of the object circular movement being projected.

The first derivative can be expressed as

$$\begin{cases}
\dot{x}(t) = \omega\_0 A\_{\text{m}} \cos(\omega\_0 t + \theta) + w\_{\text{x}}(t) = \omega\_0 y(t) + w\_{\text{x}}(t) \\
\dot{y}(t) = -\omega\_0 A\_{\text{m}} \sin(\omega\_0 t + \theta) + w\_{\text{y}}(t) = -\omega\_0 x(t) + w\_{\text{y}}(t)
\end{cases} \tag{2}$$

where *wx*(*t*) and *wy*(*t*) are the input white noise, *wx*(*t*)⊥*wy*(*t*). *wx*(*t*) ∼ (0, *<sup>σ</sup>*<sup>2</sup> *<sup>w</sup>*), *wy*(*t*) ∼ (0, *σ*<sup>2</sup> *<sup>w</sup>*).

The state equation can be obtained from (1).

$$
\frac{d}{dt} \begin{bmatrix} \varkappa(t) \\ \varkappa(t) \end{bmatrix} = A \begin{bmatrix} \varkappa(t) \\ \varkappa(t) \end{bmatrix} + B \begin{bmatrix} w\_x(t) \\ w\_y(t) \end{bmatrix} \tag{3}
$$

where

$$A = \begin{bmatrix} 0 & \omega\_0 \\ -\omega\_0 & 0 \end{bmatrix}, B = \begin{bmatrix} 1 & 0 \\ 0 & 1 \end{bmatrix}.$$

Equation (3) is discretized, and we get the state equation as follows

$$
\begin{bmatrix} \mathbf{x} \\ \mathbf{y} \end{bmatrix}\_{k+1} = \Phi\_k \begin{bmatrix} \mathbf{x} \\ \mathbf{y} \end{bmatrix}\_k + W\_k \tag{4}
$$

where

$$\Phi\_k = e^{AT} = L^{-1}([sI - A]^{-1}) = \begin{bmatrix} \cos(\omega\_0 T) & \sin(\omega\_0 T) \\ -\sin(\omega\_0 T) & \cos(\omega\_0 T) \end{bmatrix} \tag{5}$$

$$\mathcal{W}\_k = \int\_{kT}^{(k+1)T} e^{A[(k+1)T - \tau]} \cdot B \cdot w(\tau) d\tau \tag{6}$$

The covariance matrix of state noise *Wk* can be expressed as

$$Q\_k = E\left[\mathcal{W}\_k \mathcal{W}\_k^T\right] = \sigma\_w^2 \begin{bmatrix} T & 0 \\ 0 & T \end{bmatrix} = \sigma\_w^2 T \begin{bmatrix} 1 & 0 \\ 0 & 1 \end{bmatrix} \tag{7}$$

From Equation (7), an important conclusion can be known that *Qk* is related to sampling cycle *T*.

#### *2.2. Dimension Expansion of OVD Model*

The waveform of the distorted AC signal sampled at time *t* would be presented as

$$s(t) = \sum\_{i=1}^{N} A\_i(t) \sin[i\omega T + \theta\_i(t)] + \sum\_{i=1}^{N} w\_i(t) \tag{8}$$

where *i* = 1, 2, 3, ··· , *N* represents the number of fundamental and harmonic components, *T* is the sampling cycle. The fundamental frequency is *ω* = 100*π* ± e, while e is the frequency fluctuation value. *<sup>N</sup>* ∑ *i*=1 *Ai*(*t*) sin[*iω<sup>T</sup>* <sup>+</sup> *<sup>θ</sup>i*(*t*)] and *<sup>N</sup>* ∑ *i*=1 *wi*(*t*) represent the fundamental and harmonic components, and their state noise, respectively.

For Equation (1), the dimensionality of the OVD model is expanded under the consideration of fundamental and harmonic components.

$$X(t) = \begin{bmatrix} \ x\_1(t) & y\_1(t) & x\_2(t) & y\_2(t) & \cdots & x\_n(t) & y\_n(t) \end{bmatrix}^T \tag{9}$$

where *yi*(*t*) is the orthogonality of *xi*(*t*). In the condition of continuous time, the state space expression is established.

$$\frac{dX(t)}{dt} = \begin{bmatrix} M\_1 & 0 & \cdots & 0\\ 0 & M\_2 & 0 & \vdots\\ \vdots & 0 & \ddots & 0\\ 0 & \cdots & 0 & M\_n \end{bmatrix} X(t) + \begin{bmatrix} w\_1(t)\\ w\_2(t)\\ \vdots\\ w\_n(t) \end{bmatrix} \tag{10}$$

.

where the state noise vector is *<sup>w</sup>*1(*t*) *<sup>w</sup>*2(*t*) ··· *wn*(*t*) *<sup>T</sup>*

$$M\_1 = \begin{bmatrix} 0 & \omega\_m \\ -\omega\_m & 0 \end{bmatrix}, M\_2 = \begin{bmatrix} 0 & 3 \times \omega\_m \\ -3 \times \omega\_m & 0 \end{bmatrix}, M\_n = \begin{bmatrix} 0 & \mathbf{i} \times \omega\_m \\ -\mathbf{i} \times \omega\_m & 0 \end{bmatrix}.$$

where *ω<sup>m</sup>* represents the fixed frequency of this model, different values of *ω<sup>m</sup>* represent different models.

The measurement equation is

$$z(t) = \begin{bmatrix} 1 & 0 & 1 & 0 & \cdots & 1 & 0 \end{bmatrix} X(t) + v(t) \tag{11}$$

where the measurement noise vector is *v*(*t*).

We discretize Equations (10) and (11) in accordance with the principle of OVD model. Then, the state and measurement equation can be

$$\begin{cases} \begin{array}{c} X\_{k+1} = \begin{bmatrix} \Phi\_1 & \cdots & 0 \\ \vdots & \dots & \vdots \\ 0 & \cdots & \Phi\_n \end{bmatrix} X\_k + + \begin{bmatrix} W\_1 \\ W\_2 \\ \vdots \\ W\_n \end{bmatrix} \\\ z\_k = H\_k X\_k + V\_k \end{cases} \tag{12}$$

where *Xk* <sup>=</sup> *<sup>x</sup>*1*<sup>k</sup> <sup>y</sup>*1*<sup>k</sup> <sup>x</sup>*2*<sup>k</sup> <sup>y</sup>*2*<sup>k</sup>* ··· *xnk ynk <sup>T</sup>* , *<sup>W</sup>*<sup>1</sup> *<sup>W</sup>*<sup>2</sup> ··· *Wn T <sup>k</sup>* is the state noise. The state transition matrixes and the measurement transfer matrix are shown below as

$$\Phi\_i = \begin{bmatrix} \cos(i\omega\_m T) & \sin(i\omega\_m T) \\ -\sin(i\omega\_m T) & \cos(i\omega\_m T) \end{bmatrix} \tag{13}$$

$$H\_k = \begin{bmatrix} 1 & 0 & 1 & 0 & \cdots & 1 & 0 \end{bmatrix} \tag{14}$$

The covariance matrix of state noise *Wki* is

$$Q\_{i\_k} = E\left[\boldsymbol{W\_{i\_k}}\boldsymbol{W\_{i\_k}}^T\right] = \sigma\_{OV}^2 T I\_{2n \times 2n} \tag{15}$$

The difference from the traditional *OV* model in the [27,28] is that *Q* is different. The OVD model clarifies the relationship between the covariance matrix and the sampling cycle. The IMM algorithm cannot just adopt the traditional *OV* model's covariance coefficient of 0.05. Otherwise, the IMM algorithm will bring tracking errors.

If we just choose the fixed value of 0.05, when the frequency fluctuates, the traditional *OV* algorithm still adjusts the amplification factor K according to the covariance *Q* of the fixed frequency. The lack of dynamic tracking performance results in the algorithm not being able to track the dynamic fluctuations in time. The IMM algorithm uses maximum likelihood estimation to determine the transition probability between models to adaptive tracking dynamic fluctuations. Therefore, the IMM algorithm has stronger and more stable adaptive tracking capability.

#### **3. OVD Model-Based IMM Algorithm**

In this section, the OVD Model-based IMM Algorithm (OVD-IMM) is proposed by combining OVD models and IMM algorithm. Then, the parameters of two model OVD-IMM algorithms are selected.

#### *3.1. OVD-IMM Algorithm*

The block diagram of IMM Algorithm is presented in Figure 4. The IMM algorithm formula is shown in Table 1.

**Figure 4.** Block diagram of IMM Algorithm.

In the Table 1, *<sup>j</sup>* represents the number of different models, *<sup>π</sup>ji* and *<sup>μ</sup>*(*j*) *<sup>k</sup>*−<sup>1</sup> denote the initial given values of mode probability and mixing weight, respectively. **<sup>X</sup>**<sup>ˆ</sup> (*i*) *<sup>k</sup>*|*<sup>k</sup>* and **<sup>P</sup>**(*i*) *k*|*k* represent state estimate of filter *<sup>i</sup>* at k and its covariance. **<sup>X</sup>**(*i*) *<sup>k</sup>*|*<sup>k</sup>* and **<sup>P</sup>**(*i*) *<sup>k</sup>*|*<sup>k</sup>* denote mixed conditions for filter *<sup>i</sup>* at time *<sup>k</sup>*. **<sup>X</sup>**<sup>ˆ</sup> *<sup>k</sup>*+1|*k*+<sup>1</sup> and **<sup>P</sup>***k*+1|*k*+<sup>1</sup> indicate combined state estimate and its covariance. *μ*(*i*) *<sup>k</sup>* is mode probability at time *<sup>k</sup>*. *<sup>μ</sup>j*|*<sup>i</sup> <sup>k</sup>* is mixing probability at time *<sup>k</sup>*. **<sup>L</sup>**(*i*) *k* expresses the likelihood function of filter *i*.

Multiple models with different frequencies *ω<sup>m</sup>* in (12) and (13) form a model set, and substituting them into formula Table 1 to form the OVD Model-based IMM (OVD-IMM) algorithm.


**Table 1.** One cycle of IMM algorithm.

#### *3.2. OVD-IMM Application Development*

When the IMM algorithm is applied to AC signal dynamic tracking, in order to obtain the best tracking effect, a model set that covers the frequency fluctuation mode range as much as possible must be used. However, increasing the number of models in the model set will not only increase the computational complexity, but may not necessarily improve the tracking performance. This is because an overly refined pattern space may destroy the completeness of Bayesian inference and the independence between models. Unnecessary competition from too many models will cause algorithm performance degradation.

Therefore, two frequency models covering the upper and lower limits of frequency fluctuations are adopted as a model set in this paper. The frequency of the lower limit model is *f*<sup>1</sup> = 48.5 Hz, the angular frequency *ωm*<sup>1</sup> = 2*π* × *f*<sup>1</sup> = 2*π* × 48.5 rad/s. The frequency of the upper limit model is *f*<sup>2</sup> = 51.5 Hz, the angular frequency *ωm*<sup>2</sup> = 2*π* × *f*<sup>2</sup> = 2*π* × 51.5 rad/s.

We calculate the amplitude and the phase angle.

$$\mathcal{U}\_{i\_{k+1}} = \sqrt{\hat{\mathfrak{X}}\_{i\_{k+1}}^2 + \hat{\mathfrak{Y}}\_{i\_{k+1}}^2} \tag{16}$$

$$\phi\_{i\_{k+1}} = \arctan\left(\frac{\p\_{i\_{k+1}}}{\hat{\rho}\_{i\_{k+1}}}\right) \tag{17}$$

where *i* = 1 is the fundamental components, *i* = 2,3,4, ... is the harmonic components. *x*ˆ*ik*+<sup>1</sup> ,*y*ˆ*ik*+<sup>1</sup> is the fundamental components of the overall estimator in Table 1(4).

The harmonics ratio for voltage (HRU) is defined as follow

$$\text{HRU}\_{\text{n}} = \frac{\mathcal{U}\_{\text{n}}}{\mathcal{U}\_{\text{1}}} \times 100\% \tag{18}$$

where *U*<sup>1</sup> is rms value of voltage fundamental components, *Un* is rms value of *n*-th voltage harmonic components.

#### **4. Simulation and Evaluation**

In Section 4, a fixed frequency 50 Hz model is selected to form the KF algorithm as a comparison mark to better illustrate the tracking results. We evaluate and compare OVD-IMM and KF algorithms by simulations. The HRU serves as a statistical indicator. The root means squared error (RMSE) values are adopted as statistical indicators for evaluation. At first, we set the setting of simulation. Then the tracking results of simulation data are shown in Section 4.2. Next to it, we obtain RMSE results of simulation data.

#### *4.1. Simulation Setting*

The distorted AC voltage signal formula with harmonics components is

$$\mathbf{u}(t) = 220\sqrt{2} \times \left[ 1.0 \sin(\omega t) + 0.05 \sin(3\omega t) + 0.1 \sin(5\omega t) + 0.08 \sin(7\omega t) \right] + 3.11v(\mathbf{t})\tag{19}$$

The amplitude is 220√<sup>2</sup> V. The percentages of harmonic components are 5% of 3rd, 10% of 5th, and 8% of 7th. The measurement white noise is *<sup>σ</sup><sup>v</sup>* <sup>=</sup> 0.01 <sup>×</sup> <sup>220</sup>√<sup>2</sup> <sup>V</sup> <sup>=</sup> 3.11 V. The sampling cycle is 0.00004 s. *ω* = 2 × *π* × *f* is variable. The simulation scene is divided into four situations in the condition of voltage frequency heavy fluctuations: (a) Frequency is 49.5 Hz; (b) Frequency is 50.5 Hz; (c) Frequency swell from 49.5 Hz to 50.5 Hz; (d) Frequency sag from 50.5 Hz to 49.5 Hz. The simulation voltage situations are shown in Figure 5 which includes the voltages, frequency and spectrogram of data. The simulation scene is divided into four situations in the condition of voltage frequency slight fluctuations: (a) Frequency is 49.98 Hz; (b) Frequency is 50.02 Hz; (c) Frequency swell from 49.98 Hz to 50.02 Hz; (d) Frequency sag from 50.02 Hz to 49.98 Hz. The simulation voltage situations are shown in Figure 6.

**Figure 5.** Simulation data for voltage frequency heavy fluctuations. (**a**) Frequency 49.5 Hz; (**b**) Frequency 50.5 Hz; (**c**) Frequency swell; (**d**) Frequency sag.

The parameters of the two algorithms are selected as follows. The *R* of the two algorithms is 3.11 V. The initial covariance matrices of two algorithms are employed as *P*0/0 = 1000 × *I*10×10.

KF algorithms: the covariance of fundamental and harmonics components are all *Qi* = 0.05 × *I*10×10, like [27,28]. The covariance *Q* array of KF is larger and the frequency band is wider.

**Figure 6.** Simulation data for voltage frequency slight fluctuations. (**a**) Frequency 49.98 Hz; (**b**) Frequency 50.02 Hz; (**c**) Frequency swell; (**d**) Frequency sag.

IMM algorithms: The initial given values of mode probability and mixing weight, respectively, are: *πji* = 0.98 0.02 0.02 0.98 , *μ*(1) *<sup>k</sup>*−<sup>1</sup> <sup>=</sup> 0.5 *<sup>μ</sup>*(2) *<sup>k</sup>*−<sup>1</sup> <sup>=</sup> 0.5. The covariance matrix of the two models is: *Qik* = *<sup>σ</sup>*<sup>2</sup> *OV T* = <sup>10</sup> × *T* × *I*10×<sup>10</sup> = 0.0004 × *I*10×10. In the condition of voltage frequency heavy fluctuations, the frequencies of the two models are *ωm*<sup>1</sup> = 2*π* × 48.5 rad/s, *ωm*<sup>2</sup> = 2*π* × 51.5 rad/s. And in the condition of voltage frequency slight fluctuations, the frequencies of the two models are *ωm*<sup>1</sup> = 2*π* × 49.85 rad/s, *ωm*<sup>2</sup> = 2*π* × 50.15 rad/s.

#### *4.2. Tracking Results of Simulation Data*

The simulation tracking results of two algorithms for heavy and slight fluctuations are shown in Figures 7 and 8. The tracking results include fundamental and harmonics components.

It can be seen from Figures 7 and 8 that the IMM algorithm is stable and accurate in tracking no matter the fundamental wave or harmonic elements, and is not affected by frequency fluctuations. In Figures 7c,d and 8c,d, the accuracy of fundamental wave amplitude and harmonic tracking results is more obvious. Although the Q matrix of KF is large (0.05) and robust, the frequency mismatch also brings large tracking errors.

In order to quantitatively analyze the tracking results, the RMSE tracking results are evaluated at Section 4.3.

**Figure 7.** Simulation tracking results for voltage frequency heavy fluctuations. (**a**) Simulation tracking results for frequency 49.5 Hz; (**b**) Simulation tracking results for frequency 50.5 Hz; (**c**) Simulation tracking results for frequency swell; (**d**) Simulation tracking results for frequency sag.

**Figure 8.** *Cont*.

**Figure 8.** Simulation tracking results for voltage frequency slight fluctuations. (**a**) Simulation tracking results for frequency 49.98 Hz; (**b**) Simulation tracking results for frequency 50.02 Hz; (**c**) Simulation tracking results for frequency swell; (**d**) Simulation tracking results for frequency sag.

#### *4.3. RMSE Results of Simulation Data*

The RMSE results of two algorithms calculated by 100 times Monte Carlo simulations are shown in Figures 9 and 10. The RMSE evaluation results are shown in Tables 2 and 3.

**Figure 9.** Simulation RMSE results for voltage frequency heavy fluctuations. (**a**) Simulation RMSE results for frequency 49.5 Hz; (**b**) Simulation RMSE results for frequency 50.5 Hz; (**c**) Simulation RMSE results for frequency swell; (**d**) Simulation RMSE results for frequency sag.

**Figure 10.** Simulation RMSE results for voltage frequency slight fluctuations. (**a**) RMSE results for frequency 49.98 Hz; (**b**) RMSE results for frequency 50.02 Hz; (**c**) RMSE results for frequency swell; (**d**) RMSE results for frequency sag.




**Table 3.** Simulation RMSE results for voltage frequency slight fluctuations.

RMSE is defined as follows

$$\text{RMSE} = \sqrt{\frac{1}{N} \sum\_{k=1}^{N} \left(\alpha\_{ij} - \mathfrak{k}\_{ij}^{k}\right)^{2}} \tag{20}$$

where *N* = 100 is the number of simulations, *xij* is j-sampled values of *xi* and *x*ˆ*ij* j-sampled values of *x*ˆ*<sup>i</sup>* .

From Figures 9 and 10, the simulation tracking results of the IMM algorithm are stable and accurate. The KF algorithm has a large error. Especially after 200 ms, the KF algorithm has large errors in both the fundamental and the harmonics components, while the IMM algorithm is not affected.

From Table 2 to Table 3, we know that the IMM algorithm is better than the KF algorithm whether tracking results are fundamental components or harmonic components.

#### **5. Experiment and Evaluation**

In Section 5, we employ experiment data to evaluate and compare two algorithms. At the beginning, we introduce the experiment settings. Secondly, we compare tracking results of experiment sampling data for voltage frequency heavy and slight fluctuations.

#### *5.1. Experiment Settings*

The experiment platform is introduced in Figure 11a. It includes the programmable power supply and the oscilloscope. The schematic diagram of the programmable power supply is introduced in Figure 11b. Experiment data for voltage frequency heavy and slight fluctuations is conducted through a programmable power supply. The percentages of harmonic components are 5% of 3rd, 10% of 5th, and 8% of 7th. The oscilloscope of Tektronix GDS-2102 serves to sample the experiment voltage data.

**Figure 11.** Experiment platform and Schematic diagram. (**a**) Experiment platform. (**b**) Schematic diagram of the programmable power supply.

The sampling cycle is selected to be 0.00004 s. The experiment sampling voltage situations are shown in Figures 12 and 13.

**Figure 12.** Experiment data for voltage frequency heavy fluctuations. (**a**) Frequency 49.5 Hz; (**b**) Frequency 50.5 Hz; (**c**) Frequency swell; (**d**) Frequency sag.

**Figure 13.** Experiment data for voltage frequency slight fluctuations. (**a**) Frequency 49.98 Hz; (**b**) Frequency 50.02 Hz; (**c**) Frequency swell; (**d**) Frequency sag.

#### *5.2. Tracking Results of Experiment Sampling Data*

The model parameters of the two algorithms are the same as that of the simulation evaluation in Section 4. The experiment tracking results of voltage frequency heavy and slight fluctuations are shown in Figures 14 and 15.

**Figure 14.** Experiment tracking results for voltage frequency heavy fluctuations. (**a**) Experiment tracking results for frequency 49.5 Hz; (**b**) Experiment tracking results for frequency 50.5 Hz; (**c**) Experiment tracking results for frequency swell; (**d**) Experiment tracking results for frequency sag.

From comparison results in Figures 14 and 15, the IMM algorithm is significantly better than the KF algorithm in the estimation. It is consistent with the simulation tracking results and conclusions.

**Figure 15.** Experiment tracking results for voltage frequency slight fluctuations. (**a**) Experiment tracking results for frequency 49.98 Hz; (**b**) Experiment tracking results for frequency 50.02 Hz; (**c**) Experiment tracking results for frequency swell; (**d**) Experiment tracking results for frequency sag.

#### **6. Conclusions**

This paper newly presents the IMM algorithm to track the fundamental and harmonic components of the AC voltage signal under grid frequency fluctuation conditions. First of all, the orthogonal vector dynamic (OVD) model is re-derived from the stochastic process theory, which made it clear that the covariance matrix is related to the sampling cycle. Then, the IMM algorithm based on the two OVD models (OVD-IMM) is proposed. The advantage of the proposed OV-IMM algorithm is that it does not require the signal frequency detection and feedback like conventional tracking algorithms. In this paper, we simulate by two kinds of scenario data separately, which are (a) voltage frequency heavy fluctuations and (b) voltage frequency slight fluctuations. The experiment applies the same scenario data as the simulation. The results show that the fundamental and harmonic components tracking accuracy of IMM algorithm is higher than single model algorithm. Both the fundamental and harmonic components, the proposed OVD-IMM algorithm is stable and accurate, and is not affected by grid frequency fluctuations. In the future, it would be employed in some real world applications, such as synchronous control in power system [43].

**Author Contributions:** Conceptualization, H.N. and X.N.; methodology, H.N. and X.N.; software, H.N.; validation, H.N. and X.N.; formal analysis, H.N.; investigation, H.N.; resources, H.N.; data curation, H.N.; writing—original draft preparation, H.N.; writing—review and editing, H.N.; visualization, H.N.; supervision, X.N.; project administration, X.N.; funding acquisition, X.N. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by National Natural Science Foundations of China, grant number 51867017 "Research on Power Quality Dynamic Tracking and Real-time Detection Method for Microgrid Complex Source Load Environment".

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


**Haoyao Nie 1,2 and Xiaohua Nie 3,\***


**Abstract:** Kalman filter (KF) is often based on two models, which are phase angle vector (PAV) model and orthogonal vector (OV) model, in the application of distorted grid AC signal detection. However, these two models lack rigorous and detailed derivation from the principle of dynamic modeling. This paper presents a phase angle vector dynamic (PAVD) model and an orthogonal vector dynamic (OVD) model, which are combined with Kalman filter for detecting distorted grid AC signal. They reveal that the state noise covariance of the dynamic model−based KF is related to the sampling cycle, and overcome the defect of more detecting error for conventional model−based KF. Experiment and evaluation results show that the proposed KF algorithms are reasonable and effective. Therefore, this paper contributes a guiding significance for the application of KF algorithm in harmonic detection.

**Keywords:** distorted AC signal; Kalman filter; phase angle dynamic model; orthogonal vector dynamic model; state noise covariance; sampling cycle

#### **1. Introduction**

The Kalman filter (KF) plays an increasingly important role in the real−time detection of grid AC signal [1]. It was first applied to the power signal processing field by Dr. A. A. Girgis in 1981 [2–4]. It mainly applies to the following fields: fundamental and harmonic components detection of grid voltage/current [5–10], phase−locked loop synchronization [11–15], power quality detection and compensation equipment [16–20], power disturbance feature extraction and machine classification [21–24], and etc. In these applications, two conventional models, phase angle vector (PAV) model and orthogonal vector (OV) model, are mainly used. The phase angles were used as vectors to establish a state-space model which could be called the phase angle vector (PAV) model through cosine expansion [3]. The orthogonal vector was used to establish a state-space model that could be called the orthogonal vector (OV) model [4]. However, the state noise covariance of the two models is only a given value based on empirical statistics of the AC signal. It is selected as a fixed value, such as Q = 0.05 × *I* (*I* represents the unit matrix), when AC signal is the grid voltage [10,11]. It is selected as a fixed value, such as Q = 0.01 × *I*, when the AC signal is the sampling current [20]. It is mainly to avoid big tracking error and enable to detect response without time delay. With the development of computer hardware and sensor technology, the sampling cycle is getting smaller, and the accuracy requirements are getting higher. The detecting accuracy of the fundamental and harmonics components for the conventional detecting model−based KF algorithm cannot meet the requirements of modern engineering applications.

The current issue is that the detecting accuracy of the fundamental and harmonics components for the conventional detecting model–based KF algorithm cannot meet the requirements of modern engineering applications. There is no fixed rule as references

**Citation:** Nie, H.; Nie, X. Research on Dynamic Modeling of KF Algorithm for Detecting Distorted AC Signal. *Energies* **2021**, *14*, 8175. https:// doi.org/10.3390/en14238175

Academic Editor: Jaroslaw Krzywanski

Received: 5 November 2021 Accepted: 2 December 2021 Published: 6 December 2021

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

to find the fixed value by applying different sampling cycles. As a result, the detection accuracy cannot achieve the expected goal.

Also, the discretization model lacks of theoretical basis. In view of the fact that the previous literature did not detailedly derive the PAV and OV model from the principle of dynamic modeling. This paper proposes a phase angle vector dynamic (PAVD) model−based KF (PAVD−KF) algorithm and the orthogonal vector dynamic (OVD) model−based KF algorithm (OVD−KF) through model derivation according to the stochastic process theory [12]. It reveals that the state noise covariance of the conventional detecting model is related to the sampling cycle.

This paper contributes:


Section 1 introduces the Kalman filter mainly applies to the following fields and model−based KF existing problems. In Section 2, the related works about conventional PAV and OV model are introduced. In Section 3, the PAVD and OVD models are rederived according to of stochastic process theory. Then, the PAVD−KF and OVD−KF algorithms are proposed. In Section 4, the performances of PAVD−KF and OVD−KF algorithms are evaluated and compared by the experimental current and voltage sampling data. Section 5 concludes the paper.

#### **2. Related Work**

In this section, we proposed the expression of distorted AC signal first, and introduce the conventional PAV−KF and OV−KF algorithms then.

#### *2.1. Distorted AC Signal*

The waveform of the distorted AC signals sampled at time t can be expressed as

$$s(t) = \sum\_{i=1}^{N} A\_i(t) \sin[i\omega\_0 T + \theta\_i(t)] + \sum\_{i=1}^{N} w\_i(t) \tag{1}$$

where *i* = 1, 2, 3, ··· , *N*, *T* denotes the sampling cycle. For the fundamental frequency of 50 Hz, *<sup>ω</sup>*<sup>0</sup> <sup>=</sup> <sup>100</sup>*π*. *<sup>N</sup>* ∑ *i*=1 *Ai*(*t*) sin[*iω*0*T* + *θi*(*t*)] represents the fundamental and harmonic components. *<sup>N</sup>* ∑ *i*=1 *wi*(*t*) is the state noise of fundamental and harmonic components.

#### *2.2. PAV Model*

The vector of fundamental and harmonic components is expressed as

*Xk* <sup>=</sup> *<sup>x</sup>*<sup>1</sup> *<sup>y</sup>*<sup>1</sup> ··· *xn yn T* , where *x*<sup>1</sup> = *A*<sup>1</sup> cos *θ*1, *y*<sup>1</sup> = *A*<sup>1</sup> sin *θ*1,*xn* = *An* cos *θn*, *yn* = *An* sin *θn*.

The measurement equation of model is expressed as [3]

$$z\_k = H\_k X\_k + V\_k = \begin{bmatrix} \cos(\omega\_0 kT) \\ -\sin(\omega\_0 kT) \\ \vdots \\ -\cos(n\omega\_0 kT) \\ -\sin(n\omega\_0 kT) \end{bmatrix}^T \begin{bmatrix} x\_1 \\ y\_1 \\ \vdots \\ x\_n \\ y\_n \end{bmatrix}\_k + V\_k \tag{2}$$

The state equation of model is expressed as

$$X\_{k+1} = \Phi\_k X\_k + \mathcal{W}\_k = \begin{bmatrix} 1 & 0 & \cdots & 0 & 0 \\ 0 & 1 & \cdots & 0 & 0 \\ \vdots & \vdots & \vdots & \vdots & \vdots \\ 0 & 0 & \cdots & 1 & 0 \\ 0 & 0 & \cdots & 0 & 1 \end{bmatrix} \begin{bmatrix} \mathbf{x}\_1 \\ \mathbf{y}\_1 \\ \vdots \\ \mathbf{x}\_n \\ \mathbf{y}\_n \end{bmatrix}\_k + \begin{bmatrix} W\_{\mathbf{x}\_1} \\ W\_{\mathbf{y}\_1} \\ \vdots \\ W\_{\mathbf{x}\_n} \\ W\_{\mathbf{y}\_n} \end{bmatrix}\_k \tag{3}$$

The covariance matrix of state noise *Wk* can be expressed as

$$Q\_k = E\left[\mathcal{W}\_k \mathcal{W}\_k^T\right] = \sigma\_{PAV}^2 I\_{2n \times 2n} \tag{4}$$

#### *2.3. OV Model*

Considering a signal *Ak* sin(*ωktk* + *θk*) with amplitude *Ak*, angular frequency is *ω<sup>k</sup>* and phase is *θ<sup>k</sup>* [4,11]. Let *xk* = *Ak* sin(*ωktk* + *θk*), *yk* = *Ak* cos(*ωktk* + *θk*), initially, consider *Ak*<sup>+</sup>1/*<sup>k</sup>* ≈ *Ak*, *ωk*+1/*<sup>k</sup>* ≈ *ω<sup>k</sup>* and *θk*+1/*<sup>k</sup>* ≈ *θk*. At the time *tk*<sup>+</sup><sup>1</sup> = *tk* + *T*, the signal *xk* can be expressed as

$$\mathbf{x}\_{k+1} = A\_{k+1} \sin(\omega\_k t\_k + \omega\_k T + \theta\_k) = \mathbf{x}\_k \cos(\omega\_k T) + y\_k \sin(\omega\_k T) \tag{5}$$

where, *T* is the sampling cycle. Additionally,

$$y\_{k+1} = A\_{k+1} \cos(\omega\_k t\_k + \omega\_k T + \theta\_k) = -\mathbf{x}\_k \sin(\omega\_k T) + y\_k \cos(\omega\_k T) \tag{6}$$

the state−space is extended for detection of distorted AC signal existed n frequencies harmonic components.

The vectors are expressed as *Xk* <sup>=</sup> *<sup>x</sup>*<sup>1</sup> *<sup>y</sup>*<sup>1</sup> ··· *xn yn T <sup>k</sup>* , where, *<sup>x</sup>*1*<sup>k</sup>* <sup>=</sup> *<sup>A</sup>*1*<sup>k</sup>* sin *ωktk* + *θ*1*<sup>k</sup>* , *<sup>y</sup>*1*<sup>k</sup>* <sup>=</sup> *<sup>A</sup>*1*<sup>k</sup>* cos *ωktk* + *θ*1*<sup>k</sup>* , *xnk* <sup>=</sup> *Ank* sin *nωktk* + *θnk ynk* <sup>=</sup> *Ank* cos *nωktk* + *θnk* .

Then, the state and measurement equation is expressed as [4]

$$\begin{cases} \begin{array}{cccc} \mathbf{X}\_{k+1} = \begin{bmatrix} \Phi\_1 & \cdots & 0 \\ \vdots & \dots & \vdots \\ 0 & \cdots & \Phi\_n \end{bmatrix} \mathbf{X}\_k + \mathbf{W}\_{\bar{l}\_k} \\\ z\_k = \begin{bmatrix} 1 & 0 & \cdots & 1 & 0 \end{bmatrix} \mathbf{X}\_k + \mathbf{V}\_k \end{array} \tag{7}$$

,

where, the state transition matrixes Φ*<sup>i</sup>* are shown below as

$$\Phi\_i = \begin{bmatrix} \cos(i\omega\_k T) & \sin(i\omega\_k T) \\ -\sin(i\omega\_k T) & \cos(i\omega\_k T) \end{bmatrix} \tag{8}$$

The covariance matrix of state noise *Wki* can be expressed as

$$Q\_{i\_k} = E\left[\mathcal{W}\_{i\_k}\mathcal{W}\_{i\_k}^\top\right] = \sigma\_{OV}^2 I\_{2n \times 2n} \tag{9}$$

in (4) and (9), *<sup>I</sup>*2*n*×2*<sup>n</sup>* is a unit matrix. *<sup>σ</sup>*<sup>2</sup> *PAV* and *<sup>σ</sup>*<sup>2</sup> *OV* are selected as 0.05, when AC signal is sampling voltage [10,11]. *σ*<sup>2</sup> *PAV* and *<sup>σ</sup>*<sup>2</sup> *OV* are selected as 0.01, when AC signal is sampling current [20].

#### *2.4. PAV-KF and OV-KF Algorithm*

The discrete PAV−KF and OV−KF algorithm for detecting distorted AC signal can be expressed as follow by combining PAV and OV model.

$$\begin{cases} \pounds\_{k+1/k+1} = \Phi\_{k}\pounds\_{k+1/k} + K\_{k+1}\left(Z\_{k+1} - H\_{k}\pounds\_{k+1/k}\right) \\\K\_{k+1} = \Phi\_{k}P\_{k+1/k}H\_{k}^{T}\left(H\_{k}P\_{k+1/k}H\_{k}^{T} + R\_{k}\right)^{-1} \\\ P\_{k+1/k+1} = \Phi\_{k}P\_{k+1/k}\Phi\_{k}^{T} - K\_{k+1}H\_{k}P\_{k+1/k}\Phi\_{k}^{T} + Q\_{k} \end{cases} \tag{10}$$

The amplitude and the phase angle for the fundamental and harmonic components can be calculated as follows.

$$A\_{i\_{k+1}} = \sqrt{\mathfrak{k}\_{i\_{k+1}}^2 + \mathfrak{g}\_{i\_{k+1}}^2} \tag{11}$$

$$\phi\_{i\_{k+1}} = \arctan\left(\frac{\p\_{i\_{k+1}}}{\hat{\rho}\_{i\_{k+1}}}\right) \tag{12}$$

#### **3. PAVD-KF and OVD-KF Algorithm**

In Section 3, we construct the AC signal continuous differential equation of phase angle vector and orthogonal vector, and derive the discretization PAVD and OVD model in accordance with stochastic process theory. Next, we combine the proposed models with KF algorithm, to obtain PAVD−KF and OVD−KF algorithm.

#### *3.1. PAVFIGURE*

D-KF Algorithm

The phase angle vectors of fundamental components in (2)−(3) are expressed as

$$\begin{cases} x(t) = A\cos\theta\\ y(t) = A\sin\theta \end{cases} \tag{13}$$

The first derivative can be expressed as

$$
\frac{d}{dt} \begin{bmatrix} \varkappa(t) \\ y(t) \end{bmatrix} = A \begin{bmatrix} \varkappa(t) \\ y(t) \end{bmatrix} + B \begin{bmatrix} w\_x(t) \\ w\_y(t) \end{bmatrix} \tag{14}
$$

where, *wx*(*t*) and *wy*(*t*) are the input white noise, *wx*(*t*)⊥*wy*(*t*). *wx*(*t*) ∼ (0, *<sup>σ</sup>*<sup>2</sup> *<sup>w</sup>*), *wy*(*t*) ∼ (0, *σ*<sup>2</sup> *<sup>w</sup>*). Where, *A* = 0 0 0 0 , *B* = 1 0 0 1 .

Equation (11) is discretized, and the state equation can be obtained as follows [25].

$$
\left[\begin{array}{c}\mathbf{x} \\ \mathbf{y}\end{array}\right]\_{k+1} = \Phi\_{\mathbf{k}} \left[\begin{array}{c}\mathbf{x} \\ \mathbf{y}\end{array}\right]\_{k} + W\_{\mathbf{k}} \tag{15}
$$

where,

$$\Phi\_k = e^{AT} = L^{-1}([sI - A]^{-1}) = \begin{bmatrix} 1 & 0 \\ 0 & 1 \end{bmatrix} \tag{16}$$

$$\mathcal{W}\_k = \int\_{kT}^{(k+1)T} e^{A[(k+1)T - \tau]} \cdot B \cdot w(\tau) d\tau \tag{17}$$

The covariance matrix of state noise *Wk* can be expressed as

$$Q\_w = E\left[\mathcal{W}\_k \mathcal{W}\_k^T\right] = \sigma\_w^2 \begin{bmatrix} T & 0 \\ 0 & T \end{bmatrix} = \sigma\_w^2 T \begin{bmatrix} 1 & 0 \\ 0 & 1 \end{bmatrix} \tag{18}$$

from (18), an important conclusion can be known that *Qw* is related to sampling cycle *T*.

The state−space dimension of the distorted AC signal is extended under the consideration of fundamental and harmonic components. The state-space formulas of PAVD model

are the same as the conventional PAV model (2)−(3). The difference is that the state noise covariance in (4). The state noise covariance of the PAVD model is

$$Q\_k = \sigma\_{\text{PAVD}}^2 l\_{2n \times 2n} = \rho T l\_{2n \times 2n} \tag{19}$$

where, *σ*<sup>2</sup> *PAVD* is the state noise covariance of PAVD model. *ρ* ≤ 1 is a coefficient. When high detection precision is required, *ρ* is selected as a small value. When dynamic fast detecting is required, *ρ* is selected to a large value. Then, the discrete PAVD−KF algorithm can be obtained by combining model (2), (3), (15) and KF algorithm.

### *3.2. OVD*−*KF Algorithm*

In the two−dimensional space, the circular movement of the object along the midpoint is projected on the x, y axis as a pure sine and a pure cosine waveform. It is shown in Figure 1.

**Figure 1.** Diagram of the object circular movement being projected.

It can be expressed as

$$\begin{cases} \begin{array}{l} \boldsymbol{x}(t) = A\_{\text{m}} \sin(\omega\_{0}t + \theta) \\ \boldsymbol{y}(t) = A\_{\text{m}} \cos(\omega\_{0}t + \theta) \end{array} \tag{20} \end{cases} \tag{20}$$

where, *Am* is the amplitude, *ω*<sup>0</sup> is the angular frequency, and *θ* is the phase angle. The first derivative of (10) can be expressed as

$$\begin{cases}
\dot{x}(t) = \omega\_0 A\_m \cos(\omega\_0 t + \theta) + w\_x(t) = \omega\_0 y(t) + w\_x(t) \\
\dot{y}(t) = -\omega\_0 A\_m \sin(\omega\_0 t + \theta) + w\_y(t) = -\omega\_0 x(t) + w\_y(t)
\end{cases} \tag{21}$$

where, *wx*(*t*) and *wy*(*t*) are the input white noise, *wx*(*t*)⊥*wy*(*t*). *wx*(*t*) ∼ (0, *<sup>σ</sup>*<sup>2</sup> *<sup>w</sup>*), *wy*(*t*) ∼ (0, *σ*<sup>2</sup> *<sup>w</sup>*).

The state equation can be obtained from (21).

$$
\frac{d}{dt} \begin{bmatrix} \mathbf{x}(t) \\ \mathbf{y}(t) \end{bmatrix} = A \begin{bmatrix} \mathbf{x}(t) \\ \mathbf{y}(t) \end{bmatrix} + B \begin{bmatrix} w\_x(t) \\ w\_y(t) \end{bmatrix} = \begin{bmatrix} 0 & \omega\_0 \\ -\omega\_0 & 0 \end{bmatrix} \begin{bmatrix} \mathbf{x}(t) \\ \mathbf{y}(t) \end{bmatrix} + \begin{bmatrix} 1 & 0 \\ 0 & 1 \end{bmatrix} \begin{bmatrix} w\_x(t) \\ w\_y(t) \end{bmatrix} \tag{22}
$$

Equation (22) is discretized, and the state equation can be obtained as follows [25].

$$
\left[\begin{array}{c}\mathbf{x} \\ \mathbf{y}\end{array}\right]\_{k+1} = \Phi\_{\mathbf{k}} \left[\begin{array}{c}\mathbf{x} \\ \mathbf{y}\end{array}\right]\_{k} + W\_{\mathbf{k}} \tag{23}
$$

where,

$$\Phi\_k = e^{AT} = L^{-1}([sI - A]^{-1}) = \begin{bmatrix} \cos(\omega\_0 T) & \sin(\omega\_0 T) \\ -\sin(\omega\_0 T) & \cos(\omega\_0 T) \end{bmatrix} \tag{24}$$

$$\mathcal{W}\_k = \int\_{kT}^{(k+1)T} e^{A[(k+1)T - \tau]} \cdot B \cdot w(\tau) d\tau \tag{25}$$

The state noise covariance matrix can be expressed as

$$\mathcal{Q}\_{w} = E\left[\mathcal{W}\_{k}\mathcal{W}\_{k}^{T}\right] = \sigma\_{w}^{2}\begin{bmatrix} T & 0\\ 0 & T \end{bmatrix} = \sigma\_{w}^{2}T\begin{bmatrix} 1 & 0\\ 0 & 1 \end{bmatrix} \tag{26}$$

from Equation (16), an important conclusion can be drew that *Qw* is related to the sampling cycle *T*.

The state-space dimension of the distorted AC signal is expanded under the consideration of fundamental and harmonic components. The state and measurement equations of OVD model are the same as the conventional OV model (4) and (5). The difference is that state noise covariance matrix of the OV model in (6). That is

$$Q\_k = \sigma\_{\text{SVD}}^2 l\_{2n \times 2n} = \rho T l\_{2n \times 2n} \tag{27}$$

where *σ*<sup>2</sup> *OVD* is the covariance of OVD model. *ρ* ≤ 1 is a coefficient. When high detection precision is required, *ρ* is selected as a small value. When dynamic fast detecting is required, *ρ* is selected to a large value.

Then, there are the combinations of the model (7), (8), (27), and KF algorithm. The discrete OVD−KF algorithm can be obtained.

#### **4. Experiment and Evaluation**

In this section, we conduct the detection of the current and the voltage with the sampling cycle of 10 μs and 40 μs. Then, comparing the detecting results for fundamental and harmonics components in PAVD−KF and PAV−KF algorithm, and in OVD−KF and OV-KF algorithm. At the last, we come to a conclusion of these results.

#### *4.1. Experiment and Evaluation for AC Current Detection*

#### 4.1.1. Experiment Settings

As an experimental example, we sample the AC distorted current signal. Experiment platform consists of AC grid (380 V, 50 Hz), oscilloscope (Tektronix GDS−2102) and nonlinear load (the three−phase rectifier, R = 100 Ω and L = 1.5 mH). It is shown in Figure 2. The AC current signals are sampled by the oscilloscope. Sampling cycles are selected as 10 μs and 40 μs. The experiment sampling current data and spectrogram are shown in Figures 3 and 4. The HRI of harmonic components are measured to be approximately 24% of 5th, 10% of 7th, 10% of 11th, 5% of 13th, 5% of 17th, 4% of 19th by spectrum analysis.

**Figure 2.** Experiment platform. (**a**) Current sampling experiment platform (**b**) Principle diagram of experiment platform.

HRI is defined as follows

$$\text{HRI}\_{\text{In}} = \frac{I\_{\text{n}}}{I\_{\text{1}}} \times 100\% \tag{28}$$

where *I*<sup>1</sup> is the voltage rms value of fundamental component, *In* is the voltage rms value of n−th harmonic components.

**Figure 3.** Experiment current for sampling cycle 10 μs. (**a**) The sampling current data. (**b**) Spectrogram of sampling current data.

**Figure 4.** Experiment current for sampling cycle 40 μs. (**a**) The sampling current data. (**b**) Spectrogram of sampling current data.

The measurement noise covariance R of the algorithms is all selected as 0.06 A, that is the measurement error of the sensor. The initial covariance matrices are selected as *P*0/0 = 1000 × *I*14×14. The state noise covariance is selected as *Qk* = 0.01 × *I*14×<sup>14</sup> in (4). The state noise covariance is selected as *Qk* = 0.01 × *T* × *I*14×<sup>14</sup> in (19).

#### 4.1.2. Detection Results for PAVD−KF Algorithm

Two algorithms of PAV−KF and PAVD−KF are evaluated and compared. The evaluation results for sampling cycle 10 μs and 40 μs are shown in Figures 5 and 6.

**Figure 5.** PAVD−KF current detecting results for sampling cycle 10 μs. (**a**) Fundamental components detecting results (**b**) HRI detecting results.

**Figure 6.** PAVD−KF current detecting results for sampling cycle 40 μs. (**a**) Fundamental components detecting results (**b**) HRI detecting results.

### 4.1.3. Detection Results for OVD−KF Algorithm

Two algorithms of OV−KF and OVD−KF are evaluated and compared. The evaluation results for sampling cycle 10 μs and 40 μs are shown in Figures 7 and 8.

**Figure 7.** OVD−KF current detecting results for sampling cycle 10 μs. (**a**) Fundamental components detecting results (**b**) HRI detecting results.

**Figure 8.** OVD−KF current detecting results for sampling cycle 40 μs. (**a**) Fundamental components detecting results (**b**) HRI detecting results.

#### 4.1.4. Summary for AC Current Detecting

It can be seen from Figures 5 and 8, when Q = 0.01 × *I*, the detecting errors of the conventional PAV−KF and OV−KF algorithms are big. In particular, the detecting errors of the conventional algorithms for sampling cycle 40 μs are rather big. The errors are too big to affect the normal operation.

Corresponding to it, when Q combines with the sampling cycle, Q = 0.01 × *T* × *I*, regardless of the fundamental or harmonic components, the proposed detecting accuracies in PAVD−KF and OVD−KF algorithm are much higher than the conventional algorithms.

#### *4.2. Experiment and Evaluation for AC Voltage Detection*

#### 4.2.1. Experiment Settings

The AC signal is grid voltage as an experimental example. Experiment platform is shown in Figure 9. The experiment of superimposing harmonics in fundamental voltage is carried out through a programmable power supply device. The AC voltage signals are sampled and the sampling cycles *T* are selected by the oscilloscope of Tektronix GDS−2102.

The harmonics ratio for voltage (HRU) is defined as follows

$$\text{HRU}\_{\text{n}} = \frac{\text{U}\_{\text{n}}}{\text{U}\_{\text{1}}} \times 100\text{\%} \tag{29}$$

where *U*<sup>1</sup> is the voltage rms value of the fundamental component, and *Un* is the voltage rms value of n−th harmonic components.

Experiment voltage data for sampling cycle 10 μs is in Figure 10. Experiment voltage data for sampling cycle 40 μs is in Figure 11, and the HRU of harmonic components all are set as 5% of 3rd, 10% of 5th, and 8% of 7th.

**Figure 10.** Experiment voltage for sampling cycle 10 μs. (**a**) The sampling voltage data. (**b**) Spectrogram of sampling voltage data.

**Figure 11.** Experiment voltage for sampling cycle 40 μs. (**a**) The sampling voltage data. (**b**) Spectrogram of sampling voltage data.

The R of the algorithms are all selected as 3.11 V, that is the measurement error of the sensor. The initial covariance matrices of algorithms are selected as *P*0/0 = 1000 × *I*10×10. The state noise covariance matrix of algorithms is selected as *Qk* = 0.05 × *I*10×10. The state noise covariance matrix of algorithms is *Qk* = 0.1 × *T* × *I*10×10.

### 4.2.2. Detection Results for PAVD−KF Algorithm

PAVD−KF and PAV−KF algorithms are evaluated and compared. The detecting results of the sampling cycle 10 μs and 40 μs are shown in Figures 12 and 13.

**Figure 12.** PAVD−KF voltage detecting results for sampling cycle 10 μs. (**a**) Fundamental components detecting results (**b**) HRU detecting results.

**Figure 13.** PAVD−KF voltage detecting results for sampling cycle 40 μs. (**a**) Fundamental components detecting results (**b**) HRU detecting results.

#### 4.2.3. Detection Results for OVD−KF Algorithm

OVD−KF and OV−KF algorithms are evaluated and compared. The detecting results of the sampling cycle 10 μs and 40 μs are shown in Figures 14 and 15.

**Figure 14.** OVD−KF voltage detecting results for sampling cycle 10 μs. (**a**) Fundamental components detecting results (**b**) HRU detecting results.

**Figure 15.** OVD−KF voltage detecting results for sampling cycle 40 μs. (**a**) Fundamental components detecting results (**b**) HRU detecting results.

#### 4.2.4. Summary for AC Voltage Detecting

It can be seen from Figures 12 and 13 that the amplitudes of the fundamental components of the conventional model−KF algorithm detecting are fluctuating, the stability of its detection shows poorly. Specifically, when we use the sampling cycle 40 μs, the error is too big to be ignored. From Figures 14 and 15, we know that detecting errors of the harmonics components for the conventional OV−KF algorithm are also big, though the error seems smaller compared to PAV−KF. Corresponding to it, the detecting accuracies of the fundamental and harmonic components for the OVD−KF algorithm are higher than that of the OV−KF algorithm.

Generally, when Q = 0.05 × *I*, the conventional algorithms could basically meet the engineering requirements with some big errors under different sampling cycle conditions. When Q = 0.05 × *T* × *I*, all the novel algorithms could fulfill the requirements.

#### *4.3. Summary for Experiment and Evaluation*

In general, when using the fixed value, the error of PAV model is the biggest, neither current nor voltage can meet the demand. OV model performs better, when using the sampling cycle 10 μs, the voltage can be used normally, and the current error is too big to be used. But when using the sampling cycle 40 μs, both current and voltage cannot operate normally.

The proposed algorithms in this paper, whether it is PAVD model or OVD model, it is related to the sampling cycle, so the voltage and current detecting results can meet the engineering requirement.

Take PAV model with 40 μs in current and voltage tracking for example, the conventional methods produce big errors when Q = 0.01 × *I* detecting the current and Q = 0.05 × *I* detecting the voltage. Only when Q = 0.00001 × *I* detecting the current, the accuracy of it would be almost close to that of our proposed algorithm, as Figure 16 shows. When Q = 0.0005 × *I* detecting the voltage, the accuracy would satisfy the requirement, as Figure 17 shows.

**Figure 16.** PAVD−KF current detecting results for sampling cycle 40 μs. (Q = 0.00001 × *I*).

**Figure 17.** PAVD−KF voltage detecting results for sampling cycle 40 μs. (Q = 0.0005 × *I*).

#### **5. Conclusions**

This paper presents the PAVD−KF and OVD−KF algorithm derived from the stochastic process theory. It enhances the knowledge about the Kalman algorithms applied to the harmonic detection of the distorted AC grid. It gives a rule that the KF algorithms in the application of distorted grid AC signal detection is related to the sampling cycle and their state noise covariance cannot be simply considered as a constant.

This paper applies the actual current and voltage data of the sampling cycle 10 μs and 40 μs to detection and evaluation. The conventional algorithms have big errors in general and unable to meet engineering requirements. When using a fixed value of covariance, if we are going to obtain the ideal results, we need to spend a lot of time debugging (trying to make up) the parameters. Also, there is no theoretical source to set the fixed value of covariance. To solve it, we propose the algorithms to save much time and workload to get the ideal results. Besides, we make the algorithms more feasible and effective based on stochastic process theory. From which the results show that the proposed PAVD−KF and OVD−KF algorithms are effective and improve the dynamic detecting accuracy of grid AC signal significantly. This paper would provide a reference for the application of KF algorithms to harmonic detection, power quality control and grid synchronization in the future.

**Author Contributions:** Conceptualization, H.N. and X.N.; methodology, H.N. and X.N.; software, H.N.; validation, H.N. and X.N.; formal analysis, H.N.; investigation, H.N.; resources, H.N.; data curation, H.N.; writing—original draft preparation, H.N.; writing—review and editing, H.N.; visualization, H.N.; supervision, X.N.; project administration, X.N.; funding acquisition, X.N. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by National Natural Science Foundations of China, grant number 51867017 "Research on Power Quality Dynamic Tracking and Real-time Detection Method for Microgrid Complex Source Load Environment".

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** Not applicable.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


## *Article* **One-Dimensional and Three-Dimensional Numerical Investigations of Thermal Performance of Phase Change Materials in a Lithium-Ion Battery**

**Van-Tinh Huynh, Kyoungsik Chang and Sang-Wook Lee \***

Department of Mechanical Engineering, University of Ulsan, Ulsan 44610, Korea; hvtinh97@gmail.com (V.-T.H.); kschang76@ulsan.ac.kr (K.C.)

**\*** Correspondence: leesw@ulsan.ac.kr

**Abstract:** The thermal performance of a large-format (52.3 Ah) Li-ion pouch battery with an noctadecane PCM was investigated. A simplified 1D model was employed to estimate the transient thermal behavior. Two design parameters, the thickness and the thermal conductivity of the PCM, were considered. A 0.5 mm thick n-octadecane PCM integrated with aluminum foam reduced the battery temperature to 34.3 ◦C and 50.7 ◦C at the end stage of discharging under 3C and 5C discharge rates, respectively. The 1D results compared to the 3D results were able to predict the temperature dissipation by the PCM method at the end of discharging. The 1D approach clearly produced reliable results in predicting the thermal behavior of the PCM cooling and was superior in practical applications with its low cost and time consumption. A 3D CFD simulation was able to describe the detailed temperature uniformity in the cell, which is an important factor in the design and evaluation of a battery cooling system.

**Keywords:** lithium-ion battery; phase change material; large-format cell; electric vehicle

#### **1. Introduction**

Energy storage systems, such as fuel cells, batteries, flywheels, and ultracapacitors, play important roles in pure electric vehicles and the hybrid electric vehicle industry. There are currently three leading types of batteries in the market: Li-ion, nickel–metal hydride, and lead–acid. The Li-ion battery is a promising candidate with outstanding features, including a low self-discharge rate, high specific energy, and fast charging capacity without a memory effect [1]. However, the internal electrochemical reactions and resistances in its cells produce a considerable amount of heat. This results in fairly high and non-uniform cell temperatures when it is charged and discharged. The optimal operating temperature of a Li-ion battery ranges from 25 ◦C to 40 ◦C [2]. In addition, the maximum temperature difference within a cell should be less than 5 ◦C to maintain a balance between its life cycle and efficiency [3]. When the maximum temperature is higher than 80 ◦C, thermal runaway could happen and exothermic reactions will occur, eventually leading to catastrophic results [4].

Various thermal management strategies have been proposed, which can be classified into the active (air and liquid cooling), passive (phase change material (PCM) cooling and heat pipes), and hybrid methods. Chen et al. [5] optimized the distance between cells to improve the air cooling performance, whereby the maximum temperature of the battery pack was decreased by 4 K and the maximum temperature difference was decreased by 69%. Under uphill conditions (high heat generation and/or a high discharge rate), liquid cooling may be required to sufficiently dissipate the thermal energy. Shang et al. [6] achieved the best performance of liquid cooling when the width of the cooling plate was 70 mm, the inlet had a temperature of 18 ◦C, and the mass flow rate was 0.21 kg/s. In that setup, the maximum temperature was decreased by 12.61% and the temperature uniformity was increased by 20.83%.

**Citation:** Huynh, V.-T.; Chang, K.; Lee, S.-W. One-Dimensional and Three-Dimensional Numerical Investigations of Thermal Performance of Phase Change Materials in a Lithium-Ion Battery. *Energies* **2021**, *14*, 8386. https:// doi.org/10.3390/en14248386

Academic Editor: Calin Iclodean

Received: 20 October 2021 Accepted: 8 December 2021 Published: 13 December 2021

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

PCMs have been shown to greatly improve the temperature uniformity of Li-ion batteries. Wang et al. [7] showed that the melting process can be sped up by using a paraffin/aluminum foam composite. Compared with pure paraffin, the heat storage time of that composite PCM was 74.4% when the heat flux was 12,000 W/m2. Jilte et al. [8] proposed the best design with seven cells, seven primary containers, and one secondary container. At the environment temperature of 40 ◦C, the use of a nanoparticle-enhanced PCM (nePCM) can reduce the temperature of a cell to under 46 ◦C with the effect of natural convection.

Heat pipes are employed as effective systems to maintain homogeneity on the evaporator surface at a constant temperature while having high thermal conductivity. Putra et al. [9] investigated the cooling capacity of alcohol, acetone, and distilled water at a heat flux load of 1.61 W/cm2. They demonstrated that acetone is a potential candidate with a thermal resistance of 0.22 W/◦C and an evaporation temperature of 50 ◦C. For the hybrid method, Yang et al. [10] studied the thermal performance of a battery thermal management system (BTMS) integrated with mini-channel liquid cooling and air cooling. At 80% depth of discharge (*DOD*), the maximum temperature and the temperature difference were decreased by 11.12 K and 9.52 K, respectively, when the water flow rate increased by 2.2 × <sup>10</sup>−<sup>4</sup> kg/s. If the air velocity increased from 0 to 4 m/s, the battery temperature was reduced by 2.22 K, and the temperature uniformity was decreased by 2.04 K.

Kiani et al. [11] designed a hybrid thermal management system with a nanofluid integrating metal foam and a PCM. Compared with water cooling, the nanofluid with volume fraction of 2% increased the operating time of the battery by 29% at a Reynolds number of 420. Jilte et al. [12] investigated heat dissipation in cylindrical batteries with liquid channels and a PCM. At an environment temperature of 40 ◦C, the surface temperature of the battery was kept under 43 ◦C if the PCM was applied, and under 41.2 ◦C if the PCM and liquid channels were used simultaneously. Depending on the desired effectiveness, the BTMS can be applied either alone or in combination, but it should meet several criteria: high reliability, easy maintenance, low power consumption, and insignificant mass.

Different numerical modeling approaches have been used to investigate the thermal behavior of Li-ion batteries. They vary from 1D thermal models without thermal interaction among the cells, to complex 3D thermal models which consider non-isothermal and heat generation rates. Jollyn et al. [13] developed a 1D transient battery model based on daily cycles, such as 12 min and 72 min. They found that a proper PCM thickness was 1.75 mm when the maximum temperature decrease was 12.9 ◦C. Greco et al. [14] performed simplified battery thermal management using a PCM/compressed expanded natural graphite (CENG) composite. Their 1D solutions were in good agreement with their 3D results. Hallaj et al. [15] successfully demonstrated that the maximum temperature at the core of a battery pack was 80 ◦C with a small temperature variation of 3 ◦C at a 10 A discharge rate. Furthermore, they designed a battery pack integrating a PCM matrix with a significant decrease in charge time and weight for plug-in hybrid vehicles.

In the field of Li-ion battery research, for a 1D model, Hallaj et al. [16] developed a transient-state battery prototype with a thermally homogenous domain. An example is the Sony US18650 battery, which can be scaled up to a Li-ion cell of 100 Ah capacity in safe operating conditions. Sato et al. [17] categorized the heat-generating factors of reaction in a battery as reaction heat, polarization heat, and joule heat. Yi et al. [18] estimated temperature variations over time from electrochemical reactions and ohmic heat. They found that under a constant discharge rate, the potential density on the electrodes is a function of discharge time.

Akeiber et al. [19] predicted the heat storage capacity of a PCM of paraffin (40% oil and 60% wax) by solving a 1D numerical model. Fortunato et al. [20] obtained a 2D solution for different temperature profiles and total melting times with a PCM. Samar et al. [21] investigated 2D melting procedures for paraffin wax in ANSYS Fluent software, and showed that a PCM container induced a faster melting process.

In the present study, a 1D and a 3D Li-ion battery model were evaluated and compared with experimental data under 3C and 5C discharge rates. For a 3D model, two common approaches have been developed: the equivalent circuit model and the Newman, Tiedemann, Gu, and Kim (NTGK) model; the latter was used here. The main objective was to investigate the effect of PCM thickness and thermal conductivity on thermal management performance using the CFD technique with an NTGK model.

#### **2. Methodology**

A Li-ion battery with a 52.3 Ah pouch cell made by SM Bexel Co., Ltd. (Gumi, Korea) was used here. A 2.3 mm thick aluminum envelope covered the active zone, and the other fundamental characteristics of the battery are listed in Table 1.


**Table 1.** Battery specifications.

The melting point is the primary criterion when selecting a PCM. It must be both lower than the heat source temperature and higher than the ambient environment to which the system will be subjected [22]. For systems that are designed preferentially for thermal management, the usual advice is to choose a PCM with the highest possible melting point that is considerably below the desired thermal control point (40 ◦C). Based on our literature review, n-octadecane was suitable for this study with its *Tsolidus* = 301.15 K (solidus temperature) and *Tliquidus* = 303.15 K (liquidus temperature). Its main properties are summarized in Table 2.

**Table 2.** The material properties of n-octadecane.


#### *2.1. One-Dimensional Mathematical Model*

In this study it was assumed that heat transfer only took place through the side surfaces since the battery was thin (8 mm). In such cases, thermal behavior can be estimated in a cell without considering the thermal interaction among the cells [13]. Bernardi et al. [23] reliably predicted cell temperature and heat generation by a 1D model and proposed a simplified overpotential heat form, taking into account irreversible and reversible heat, as follows:

$$q\_b = q\_{irr} + q\_{rev} \tag{1}$$

$$q\_{irr} = RI^2 \tag{2}$$

$$q\_{rev} = -IT\_b \frac{\partial E}{\partial T\_b} \tag{3}$$

Figures 1 and 2 show the experimental measurement of currents over time under different discharge rates.

**Figure 1.** Measured electric current through the battery under 3C discharge rate.

**Figure 2.** Measured electric current through the battery under 5C discharge rate.

The *DOD* is the percentage of the battery capacity that has been discharged from the fully charged battery as presented in Equation (4). An alternative form of *DOD* is the state of charge (*SOC*), wherein 0% refers to a fully discharged battery and 100% refers to a fully charged battery, as shown in Equation (5) and Figure 3a.

$$DOD = (Q/Q\_0) \cdot 100\tag{4}$$

$$\text{SOC} = 100 - DOD \tag{5}$$

The open-circuit voltage is determined from the terminal voltage by Equation (6). The entropic heat coefficient, which is estimated in Equation (7), is the derivative of the open-circuit voltage with respect to battery temperature, as shown in Figure 3b.

$$E = \mathcal{U} + I \cdot \mathcal{R} \tag{6}$$

$$\frac{\partial E}{\partial T\_b} = \frac{E^{j+1} - E^j}{T\_b^{j+1} - T\_b^j} \tag{7}$$

**Figure 3.** (**a**) *SOC* over time at different discharge rates. (**b**) Entropic heat coefficient as a function of *SOC*.

Reversible heat produces an entropy change that can be either negative or positive. Therefore, the entropic heat in Equation (3) is positive if endothermic, negative if exothermic during discharge. The discharge capacity and terminal voltage are also experimentally measured.

The next step is to consider the energy conservation principle. The heat generation rate equals the rate of change in the thermal energy in the cell, plus the rate of heat loss by natural convection, as represented in Equation (8). Thermal resistance for convection (*Rconv* = 3.34 K/W) on a vertical surface is determined by the Nusselt number, related with the Rayleigh number and the Prandtl number, as shown in Equation (9). The Grasof number is an important standard in determining whether there is laminar flow or turbulent flow in natural convection. In this vertical plate case, the fluid flow was laminar since the Grasof number was equal to 6.11 × <sup>10</sup>7. The initial battery and environment temperature were set to 25 ◦C, the same as in the experimental setup.

$$q\_b = m\_b c\_b \frac{dT\_b}{dt} + \frac{2(T\_b - T\_a)}{R\_{conv}} \tag{8}$$

$$\mathrm{Nu} = 0.68 + \frac{0.67 \mathrm{Ra}^{1/4}}{\left[1 + \left(0.492/\mathrm{Pr}\right)^{9/16}\right]^{4/9}}\tag{9}$$

The PCM was stored in an aluminum container, one surface of which was in contact with the battery and the other was cooled by natural convection. The dominant heat transfer mechanism was conduction in the PCM due to the thin PCM layers. Thermal energy was conducted from a battery source throughout the aluminum case and the PCM to the air at room temperature, as shown in Figure 4. In accordance with the instantaneous energy balance, heat produced by the battery could either be stored by itself or flowed into the PCM region, as follows:

$$q\_b = m\_b c\_b \frac{dT\_b}{dt} + q\_{PCM} \tag{10}$$

**Figure 4.** Schematic of the battery and PCM positions.

A 1D transient heat conduction equation, without heat generation, was applied to evaluate the temperature distribution in the PCM, as shown in Equation (11) [24]:

$$\frac{\partial T}{\partial t} = \alpha \frac{\partial^2 T}{\partial^2 \mathcal{X}} \tag{11}$$

$$\alpha = \frac{k}{\rho \cdot c} \tag{12}$$

Boundary conditions were applied as follows:

$$\text{At } \mathbf{x} = 0 \quad kA \frac{\partial T}{\partial \mathbf{x}} = \frac{T\_b - T(\mathbf{x})}{R\_{int} + R\_{\text{cas}}} = \frac{q\_{\text{PCM}}}{2} \tag{13}$$

$$\text{At } \mathbf{x} = d \qquad \qquad \qquad \qquad \qquad \mathbf{k}A \frac{\partial T}{\partial \mathbf{x}} = \frac{T(\mathbf{x}) - T\_{\mathbf{a}}}{R\_{\text{cas}} + R\_{\text{conv}}} \tag{14}$$

It is truly necessary to clarify two forms of heat when using a PCM. Sensible heat results in a change in material temperature without a phase change. By contrast, latent heat does not increase the temperature within the material but does cause a change of substance state [22]. Assuming that the roughness of the aluminum plates was 10 μm, thermal contact conductance was calculated to be 3640 W/m2·K. Jollyn et al. [13] used a case thickness of 5 mm; accordingly, the thermal resistance for conduction was equal to 3.732 × <sup>10</sup>−<sup>5</sup> K/W.

#### *2.2. Three-Dimensional Mathematical Model*

Numerical simulation of the heat transfer was carried out using ANSYS Fluent software. Kim et al. [25] introduced the multi-scale, multi-dimensional approach for solving interactions appearing in a vast number of length scales. This framework efficiently deals with separate solution domains at the particle (10−<sup>9</sup> to 10−8), electrode (10−<sup>6</sup> to 10−4), and cell (10−<sup>2</sup> to 100) levels. At the cell scale, the current flux is governed by the following equations:

$$\nabla \cdot (\sigma\_+ \nabla \varphi\_+) = -j \tag{15}$$

$$\nabla \cdot (\sigma\_- \nabla \varphi\_-) = j \tag{16}$$

The NTGK model assumes the current flux to be a function of the potential difference between the positive and negative electrodes. Ho et al. [26] estimated two empirical fitting parameters from their experimental data. Those depend on the *DOD* of the battery and the temperature. For a 3D thermal model of Li-ion batteries, the thermal source is roughly similar to 1D modeling and the ohmic heating is also considered in the batteries, as follows:

$$q\_b = j\left[E - \left(\varphi\_+ - \varphi\_-\right) - T\frac{dE}{dT\_b}\right] + \sigma\_+ \cdot \nabla^2 \varphi\_+ + \sigma\_- \cdot \nabla^2 \varphi\_- \tag{17}$$

where *j*[*E* − (*ϕ*<sup>+</sup> − *ϕ*−)] is expressed as an irreversible source term and *jT*(*dE*/*dTb*) refers to a reversible source term. The thermal energy generated in the current collecting tab and lead wire was neglected.

Voller et al. [27] successfully solved phase change problems in the convection–diffusion– controlled mushy zone with the enthalpy–porosity technique, which relies on fixed-grid methodology. Depending upon the PCM temperature, the liquid fraction is defined as:

$$\begin{cases} \beta = 0 & \text{for } T < T\_{soliding} \\ \beta = 1 & \text{for } T > T\_{liquids} \\ \beta = \frac{T - T\_{solulus}}{T\_{liquids} - T\_{solulus}} & \text{for } T\_{solulus} < T < T\_{liquids} \end{cases} \tag{18}$$

Instead of tracking the melting interface, the liquid fraction referring to the liquid state in a computational domain is computed per iteration. The latent heat content is as follows:

$$
\Delta H = \beta \cdot L \tag{19}
$$

For melting simulations, the momentum equation is not employed. The energy equation analyzing the temperature distribution can be derived as follows:

$$\frac{\partial}{\partial t}(\rho H) + \nabla \cdot (\rho \mathbf{v} H) = \nabla \cdot (k \nabla T) + \mathbf{S} \tag{20}$$

where **v** is the fluid velocity vector.

#### *2.3. Validation*

2.3.1. Validation of 1D Modeling

The 1D battery heat transfer model was validated against the experimental data. The error between the 1D model prediction and the experimental data was found to be within 1% at the last stage of both the 3C and 5C discharge processes. Figure 5 shows good quantitative agreement for the 3C and 5C discharge rates.

**Figure 5.** Comparison of the 1D model and the experimental maximum temperatures in the battery.

#### 2.3.2. Validation of 3D Modeling

Ho et al. [26] conducted simulations on the same kind of Li-ion battery using ANSYS Fluent software. The NTGK model was used to predict the thermal behavior of the battery under various discharge rates: 1C, 2C, 3C, 4C, and 5C. A cell was immersed in air that had an initial temperature of 25 ◦C. As seen in Figure 6, there were similar trend lines between this current work and that of Ho et al. At the end of discharging, there was a 0.1% error for the 3C rate and a 0.5% error for the 5C rate. This confirmed that NTGK battery modeling was valid for various rates of discharge.

**Figure 6.** Comparison of temperatures by the NTGK model in this study and by Ho et al. [26].

A transient simulation of the thermal behavior of a Li-ion battery with a PCM was validated to the results of Javani et al. [28]. The error was found to be within an acceptable range (a maximum error of less than 1% at the end of discharging), as shown in Table 3. In order to model a cell, those researchers assumed a uniform heat generation rate within the cell domain. Due to the inconsequential thickness of the battery, this assumption was appropriate for the lumped system evaluation. We considered a transient model of a 54,374.5 W/m<sup>3</sup> heat source, especially because there was anisotropic thermal conductivity in the cell: 25 W/m·K along the cell surface and 1 W/m·K normal to the cell surface. N-octadecane, the length of which was 3 mm, was integrated around the periphery of the battery with the same thickness. It was assumed that free convection took place at all the surfaces where the battery and the PCM interfaced with the ambient air. The heat transfer coefficient was 7 W/m2·K and the temperature of the environment was 294.15 K. The geometrical features of this model, which had 300,800 elements, are summarized in Table 4.

**Table 3.** Comparison of maximum temperature for the validation of the battery model at 20 min.


A thorough grid independence test should be carried out to demonstrate that the element size does not affect the quantity of interest. We recorded the temperature in the cell at the end of discharging at the 5C discharge rate. As shown in Figure 7, the grid with 1,360,891 elements was sufficient to predict the temperature distribution in the computational domain.

**Table 4.** Dimensions of the battery and PCM geometry in the simulations of Javani et al. [28].


**Figure 7.** Grid independence test with different numbers of elements.

#### **3. Results and Discussion**

In this study, the effect of the thickness and thermal conductivity of a PCM on the cooling performance of a Li-ion battery are investigated. The PCM was of three different thicknesses, 0.5 mm, 0.55 mm, and 0.6 mm, and the thermal conductivity of the PCM was enhanced based on the practical application.

#### *3.1. Effect of PCM Thickness*

The major drawback with most organics, particularly the family of paraffins, is that they possess low thermal conductivity. A thin PCM easily melts fully and does not produce sufficiently effective temperature reduction. With a thick PCM there is a solid region farther from the battery and a superheated liquid region next to the battery, so instead of behaving as a thermal sink, the PCM may behave as a thermal isolator.

As shown in Figure 8, the maximum temperatures of the Li-ion batteries without a PCM were 64.86 ◦C and 86.83 ◦C at the end of the 3C and 5C discharge rates, respectively. As mentioned previously, the best temperature range is 25 ◦C to 40 ◦C and the safe temperature range is −20 ◦C to 60 ◦C for Li-ion battery operation. Moreover, the capacity fade of Li-ion cells can be 36.21% after 800 cycles when the operating temperature is around 45 ◦C, and the loss can even reach 70.56% after 500 cycles when the operating temperature is approximately 55 ◦C. At the 3C discharge rate, a PCM with a thickness of 0.6 mm or thinner can maintain the battery temperature in a safe condition. With a 0.6 mm thick PCM layer, the maximum temperature can decrease by 1.28 ◦C or 6.54 ◦C, depending on the fast or slow discharge rate.

**Figure 8.** Battery temperatures for different PCM thicknesses at: (**a**) 3C discharge rate; (**b**) 5C discharge rate.

Three stages along the temperature elevation curve clearly exist in the battery with a PCM (Figure 8).


Figure 9 is a close-up of the battery temperature change at the initial stage of the discharging process. Under the high discharge rate of 5C, it took 17.4 s to rise above 40 ◦C. This process could be extended to 34.8 s when the PCM thickness was 0.5 mm. Similarly, with the 3C discharge rate, it took much longer (40.3 s) to reach 40 ◦C. This operation could take up to 144.3 s with a 0.5 mm thick PCM.

As shown in Figure 10, at the end of the discharging process the battery temperature linearly varied with the thickness of the PCM. When the thickness decreased by 0.05 mm, the temperature also declined 5.3 ◦C at the 5C discharge rate. This compares with a decline of 2.7 ◦C at the low discharge rate of 3C.

#### *3.2. Effect of PCM Thermal Conductivity*

The response time is a substantial factor in the design of a PCM system. There are several approaches to improve heat dissipation, such as enhancing the thermal conductivity, setting the ullage space far from the heat source via a potential container, and installing the PCM in the heat flow path. It is generally agreed that a material that has a high energy storage capacity will have low thermal conductivity. Therefore, much research interest has been focused on enhancing the thermal conductivity of PCMs.

**Figure 9.** Rapid increases in the temperature below 40 ◦C at: (**a**) the 3C discharge rate; (**b**) the 5C discharge rate (1: sensible heating of solid; 2: latent heat of fusion; 3: sensible heating of liquid).

**Figure 10.** The highest battery temperature as a function of PCM thickness.

Recently, Venkateshwar et al. [29] investigated heat storage performance when embedding aluminum metal foam (MF) in n-octadecane. They used Equations (21) and (22) to determine the effective thermal conductivity of that PCM–MF composite, given as:

$$k\_{s,eff} = A\_1 \left[ \varepsilon \cdot k\_{s,PCM} + (1 - \varepsilon) k\_{MF} \right] + \frac{1 - A\_1}{\frac{\varepsilon}{k\_{s,PCM}} + \frac{1 - \varepsilon}{k\_{MF}}} \tag{21}$$

$$k\_{l,eff} = A\_1 \left[ \varepsilon \cdot k\_{l,PCM} + (1 - \varepsilon)k\_{MF} \right] + \frac{1 - A\_1}{\frac{\varepsilon}{k\_{l,PCM}} + \frac{1 - \varepsilon}{k\_{MF}}} \tag{22}$$

With the porosity *ε* set to 0.972, the structure with a thermal conductivity of 2.394 W/m·K conducted faster than pure n-octadecane without sacrificing the available volume.

Sari et al. [30] examined the transient thermal influence of paraffin absorbed into expanded graphite (EG). They determined that the PCM composite, with a 10% mass fraction of EG, had stable properties. The thermal conductivity of the PCM–EG linearly varied with the mass fraction of the EG. Compared with pure n-octadecane, the thermal conductivity could reach 0.828 W/m·K when integrated with the proper amount of EG.

In a macroscopic approach, the use of carbon fibers (CF) was considered by Fukai et al. [31] as an advanced technique. The effective thermal conductivity of the PCM composite was around three times higher than the pure PCM at *Xf a* = 0.012, as calculated in the following formula:

$$k\_{eff} = \left[ \left( 3.31 \times 10^{-3} + 1.69 X\_{fa} - 2.65 \times 10 \times X\_{fa}^2 \right) \cdot \left( \frac{k\_f}{k\_m} - 1 \right)^{0.67} + 1 \right] k\_m \tag{23}$$

As a result, the thermal conductivity of paraffin combined with CF was 0.678 W/m·K. Figure 11 shows the battery temperature change during the discharging process under natural convection. The higher the thermal conductivity of the PCM composite is, the more effective the heat dissipation capacity is. Additionally, aluminum foams make the melting process more uniform. The thermal improvements of PCM composites are summarized in Table 5. At the end of the discharging process, the percentage of temperature reduction with PCM–MF was about 1.2 and 1.3 times higher than with PCM– EG and PCM–CF, respectively.

**Figure 11.** Battery temperature with various PCM composites at: (**a**) the 3C discharge rate; (**b**) the 5C discharge rate (1: sensible heating of solid; 2: latent heat of fusion; 3: sensible heating of liquid).


**Table 5.** Specifications of PCM composites and their performances.

#### *3.3. Comparison of 1D Calculation and 3D Simulation*

We compared our 1D analysis and a 3D simulation of the 0.5 mm thick PCM–MF model. A hexahedral grid was generated for the battery and the PCM domain, while the ambient air domain was divided by polyhedral elements, as shown in Figure 12. The bottom was set to be adiabatic and the other surfaces were set to atmospheric pressure. For the pressure–velocity coupling, the ANSYS Fluent coupled algorithm was employed. A second-order interpolation scheme was used to approximate the convection terms in

the momentum, energy, and potential equations, whereas a PREssure STaggering Option (PRESTO) scheme was selected for the pressure field. For the conjugate heat transfer problem, the following assumptions were applied:


**Figure 12.** (**a**) Battery and PCM immersed in air. (**b**) The computational domain.

The data from the late stage of the analysis for the 1D calculation was excluded because it was too noisy; nevertheless, we found that the 1D and 3D solutions matched well when extending the results while maintaining the curve slope (Figure 13). This agreed with the results of Greco et al. [14], who showed that cooling paths were totally dissimilar in the initial periods of the analytical and computational approaches, but they definitely matched at the end stages.

**Figure 13.** Comparison of 1D and 3D simulation results for battery temperatures under: (**a**) the 3C discharge rate; (**b**) the 5C discharge rate (1: sensible heating of solid; 2: latent heat of fusion; 3: sensible heating of liquid).

Figure 14 shows the temperature uniformity in the 3D Li-ion battery model. At the low discharge rate of 3C, the tmperature disparity in the cell was maintained under 5 ◦C. At the higher discharge rate of 5C, it markedly escalated due to sudden heat generation. However, the PCM exhibited outstanding improvement, with a 6.6 ◦C peak difference of temperature.

**Figure 14.** Investigation of temperature uniformity in the 3D Li-ion battery model.

At the center plane of the cell, two monitoring lines were selected to explore the temperature change at z = 0.1245 m and y = 0.1135 m, as depicted in Figure 15a. Figure 15b shows the temperature along the vertical line at the end of discharging. There was a large difference of 15.5 ◦C between the top and bottom positions under the 5C rate without a PCM. The use of PCM–MF caused a sudden change in temperature in the lower area of the cell at the 3C discharge rate, due to a liquid mushy PCM zone. It can be seen in Figure 15c that the temperature varied slightly in the horizontal direction and tended to be more stable when the PCM was applied. All of the differences were below 1 ◦C. Because the heat source was concentrated in the region close to the current collecting tabs, the temperature variation was clearly greater in the vertical direction than in the horizontal direction.

**Figure 15.** (**a**) Temperature monitoring lines. (**b**) The temperature distribution at line 1. (**c**) The temperature distribution at line 2.

Basically, the temperature distribution on the battery surface can be divided into two parts: an upper region with higher temperature and a lower region with lower temperature. Without a PCM, the battery temperature increased more continuously and homogeneously from the bottom to the top under the 3C discharge rate. This difference was 6.8 ◦C. However, there was greater difference in temperature (18.8 ◦C) under the 5C discharge rate. The highest temperature was located near the positive and negative tabs, as shown in Figure 16.

**Figure 16.** Contour of temperature on battery surfaces (◦C) at the end of discharging: (**a**) without PCM; (**b**) with PCM.

Similar trends were observed in the case with the PCM. However, there was a smaller temperature difference at the 3C as well as the 5C discharge rates because thermal energy from the battery was absorbed into latent heat. The maximum temperature was located at the negative tab (left tab), which was not cooled by the PCM. For this reason, an active cooling method, such as forced convection, may be necessary. The differences in temperature were 4.5 ◦C and 8.2 ◦C on the entire battery surface under 3C and 5C discharge rates, respectively.

Depending on the amount of heat generated, the PCM can be partly or totally melted. The PCM remained in the mushy zone in the lower region under the 3C discharge rate, while it completely transformed to a liquid state under the 5C discharge rate.

#### **4. Conclusions**

A 1D thermal management model of a large-format Li-ion battery (52.3 Ah) with different PCM properties was evaluated. This pouch-type battery was sandwiched between two n-octadecane layers, and the heat generation agreed well with experimental data under both the 3C and 5C discharge rates. The diffusion equation that governed the thermal transfer capacity in the PCM was also solved simultaneously. By considering different PCM thicknesses and thermal conductivities, a potential model was proposed, which was an assemblage with aluminum foam embedded in n-octadecane. The average conductivity of the resulting enhanced PCM–MF was 2.394 W/m·K. The maximum temperature of the Li-ion battery reached 86.8 ◦C after 550 s under the 5C discharge rate and 64.9 ◦C after 900 s under the 3C discharge rate without a cooling system. It was shown that the 0.5 mm thick PCM–MF composite reduced the maximum battery temperature to 49.7 ◦C and 33.9 ◦C at the 5C and 3C discharge rates, respectively.

Then, 3D transient thermodynamic simulations were carried out with an NTGK model using ANSYS Fluent software. Based on comparison with these 3D simulations, we found that the 1D analysis was capable of accurately estimating the heat dissipation by the PCM– MF at the end stage of discharging. The 1D approach clearly produced reliable results in predicting the thermal behavior of the PCM–MF cooling and was superior in practical application terms with its low cost and less time consumption.

Further study on the thermal behavior of active cooling systems with PCMs will be necessary.

**Author Contributions:** Conceptualization, V.-T.H. and K.C.; methodology, K.C.; software, V.-T.H.; resources, S.-W.L.; writing—original draft preparation, V.-T.H.; writing—review and editing, V.- T.H., K.C. and S.-W.L.; supervision, K.C. and S.-W.L.; project administration, K.C. and S.-W.L.; funding acquisition, K.C. and S.-W.L. All authors have read and agreed to the published version of the manuscript.

**Funding:** This work was supported by Upbringing Business with Innovative Urban Public Institution by the Korean Ministry of Trade, Industry, and Energy (MOTIE) (project name: Establishment of battery/ESS-based energy industry innovation ecosystem) and by the Technology Innovation Program (20006974, "Development of the multi-layered sheets and their forming/joining technologies for the fabrication of 28% lightweight battery pack/module components of electric vehicles") funded by MOTIE.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** Not applicable.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **Nomenclature**



#### **References**


**Hae-In Kim 1, Su-Hwan Kim 1, Seung-Woo Baek 1,\*, Hag-Wone Kim 1,\*, Kwan-Yuhl Cho <sup>1</sup> and Gil-Dong Kim <sup>2</sup>**


**Abstract:** The voltage and current ripples in the three-level bi-directional converter (TLBC) can be reduced by an interleaving technique that controls a phase difference between the modules of power converter. On the other hand, the inductor current ripple in TLBC is increased due to the circulating current between the modules. In this paper, the effects of two interleaving methods on a two-phase TLBC, Z-type and N-type, are investigated and compared. In particular, capacitor current ripple, and voltage ripple are compared by two interleaving methods verified through Powersim (PSIM) simulation.

**Keywords:** three-level bi-directional converter (TLBC); interleaving control; capacitor current ripple; parallel control

#### **1. Introduction**

In the transportation facilities including electric locomotive and electric vehicle, the kinetic energy in braking mode is converted into the electrical energy. This regenerative energy generated by the electric machine can be stored in a battery by a bidirectional power converter [1–3]. The high voltage semiconductor switches are required in such high power, high voltage applications, and this results in large losses in semiconductor switches. Therefore, research on three-level bidirectional converter (TLBC) is being actively carried out to lower the voltage stress of power semiconductors [4–7]. Figure 1 shows a TLBC circuit.

**Figure 1.** Single-module TLBC circuit diagram.

**Citation:** Kim, H.-I.; Kim, S.-H.; Baek, S.-W.; Kim, H.-W.; Cho, K.-Y.; Kim, G.-D. Comparison of Interleaving Methods of Parallel Connected Three-Level Bi-Directional Converters. *Energies* **2022**, *15*, 6. https://doi.org/10.3390/en15010006

Academic Editors: Antonio T. Alexandridis and Teuvo Suntio

Received: 27 October 2021 Accepted: 10 December 2021 Published: 21 December 2021

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

Because the TLBC in Figure 1 has a structure in which the two-level bidirectional converters are vertically symmetric, the voltage stress of the switching devices is reduced by half. This makes it feasible to reduce the loss of the elements [8]. Furthermore, the ripple of the inductor and output currents, and output voltage can be reduced by half. A decrease in the ripple of current and voltage has a positive effect on the lifespan and efficiency of passive elements [9–12].

In addition, if the power converter is configured in parallel, it can provide benefits such as the reduction of losses and heat dissipation under heavy loads, and increase in power capacity [13,14]. TLBCs that are configured in parallel generally perform interleaving operations with a phase difference on one period [5,15]. In this case, each pair of switches operate alternately so that the input current, output current and voltage ripples can be reduced. However, by the interleaving control, a circulating current is generated, which flows from the inductor of one module to that of the other module. This increases the ripple of the current flowing through the inductor [16,17]. An increase in the ripple of the inductor current results in an increase in the loss of the inductor as well as a decrease in the efficiency of the converter module. There are two interleaving methods, Z-type and N-type, in TLBCs with two-phase parallel configuration according to the order of operating switches [18]. N-type interleaving operates all the switches of one module first and then those of another. In contrast, Z-type interleaving operates the high-side switches of all the modules first and then the low-side switches. In the case of Z-type interleaving, because the phase difference between the high-side switches is smaller than that for N-type interleaving, the amount of circulating current generated between the modules of Z-type interleaving is smaller then that of N-type interleaving.

The effect of the interleaving method on the inductor current has been analyzed extensively in the reference document [18]. However, the effects on the filter capacitor are not discussed in that paper. Generally, filter capacitors can be the largest failure's sources of converter modules [19]. Therefore, in this study, the effects of interleaving methods on the filter capacitor of the current of the filter capacitor was analyzed according to the two interleaving operation methods for the two phase parallel TLBC structure. Furthermore, the control methods of two types interleaving were also analyzed. The analysis results were verified through Powersim (PSIM) simulations. This paper is organized as follows: Section 2 describes the basic operation of two-phase parallel TLBCs. Section 3 analyzes the current ripple of the filter capacitor and the control method that depend on the interleaving method. Section 4 verifies the analytical results given in Section 3 by simulations. Finally, conclusions are presented in Section 5.

#### **2. Parallel Operation of Two-Phase Parallel TLBC**

#### *2.1. Circuit of Two-Phase Parallel TLBC*

To configure TLBCs in parallel, two aspects need to be considered in connecting single TLBC. Firstly, the neutral points of the two capacitors placed between the high-side and low-side in the TLBCs in parallel must be connected. By connecting the neutral point, the current ripple of the capacitor is divided between capacitors connected in parallel, which reduces the loss of the capacitor and increases the lifespan [20]. Second, a low-side inductor must be added to prevent the short-circuiting of low-side capacitors. While interleaving the TLBC, there is a switching instance in which two low-side capacitors are short circuited. Figure 2a illustrates the low-side capacitors are short-circuited during interleaving control in TBLC.

**Figure 2.** Circuit diagram of two-phase parallel TLBC.

In such a case, the entire output voltage is applied to the high-side capacitors so that these capacitors may be destroyed by over voltage failure. Therefore, a low-side inductor should be added to prevent short circuit failure of the low-side capacitor. Figure 2b illustrates a circuit diagram of a two-phase TLBC configured in parallel with an inductor at the bottom. As described above, the two-phase parallel TLBC circuit used in this study has low-side inductors, and the neutral points of capacitors in each module are connected.

#### *2.2. Interleaving Methods of 2 Parallel Three-Level Bi-Directional Converters*

In the conventional single-phase TLBC, the two switches at the high-side and low-side operate with a phase difference of 180°. However, because there are a total of four activated switches in the two-phase parallel TLBC, it must operate with a phase difference of 90° (obtained by dividing a cycle into four parts). At this time, it is categorized as N-type or Z-type interleaving according to the order of phase difference [18]. Figure 3 illustrates the switching sequence for two types of interleaving methods, N-type and Z-type. Moreover, the two filter capacitors connected in parallel are expressed equivalently as one capacitor. In N-type interleaving, the switches of first module operate in the top and bottom order, then those of second module operate in the top and bottom order—while, in Z-type interleaving, the high-side switches of two modules are turned on sequentially and then the low-side switches are turned on.

Meanwhile, a circulating current (*IDM*) is generated when the parallel modules are subjected to interleaving control. This circulating current is not completely transferred to the output power, but it flows into another module. This circulating current increases the power losses as well as a current ripple of the inductor. The next section describes the circulating current for two types of interleaving methods.

#### *2.3. Circulating Current Variation with an Interleaving Method*

The circulating current (*iDM*) flowing between the modules owing to interleaving control and the common current (*iCM*) flowing to the output terminal (without flowing to another module) are defined as in Equations (1) and (2):

$$i\_{CM} = \frac{i\_{LH1} + i\_{LH2}}{2} \tag{1}$$

$$i\_{DM} = \frac{i\_{LH1} - i\_{LH2}}{2} \tag{2}$$

where *iLH*1and *iLH*<sup>2</sup> refer to inductor currents flowing through the high-side inductors of modules 1 and 2, respectively. The inductor current of each module can be expressed as Equations (3) and (4) using the circulation current and common current

$$i\_{LH1} = i\_{CM} + i\_{DM} \tag{3}$$

$$i\_{LH2} = i\_{CM} - i\_{DM} \tag{4}$$

Figure 4a shows the circuit diagram of two-phase parallel TLBC. Figure 4b shows an equivalent circuit obtained by replacing the switch and output voltage terminal of a two-phase parallel TLBC with a square wave voltage source. Point G, which is the middle point of the input voltage, is a virtual node. Point O, which is the neutral point of the capacitor, is defined as a node for interpreting the circuit by dividing it into high-side and low-side ends.

(**a**) Switching operation of Z-type interleaving

(**b**) Waveform of Z-type interleaving

① ②③ ④ ⑤ ⑥ ⑦ ⑧ SH1 SL1 SH2 SL2 (**d**) Waveform of N-type interleaving

(**c**) Switching operation of N-type interleaving

**Figure 3.** Switching operation according to interleaving methods.

**Figure 4.** (**a**) Circuit diagram of a two-phase parallel TLBC; (**b**) equivalent circuit diagram of a TLBC with interleaving control.

The voltages applied to the inductor in Figure 4 (*vLH*1, *vLH*2, *vLL*1, *vLL*2) can be expressed by Equations (5)–(8):

$$
v\_{LH1} = \frac{v\_{\text{in}}}{2} - v\_{\text{OG}} - v\_{\text{no}} \tag{5}$$

$$
v\_{LH2} = \frac{v\_{\text{in}}}{2} - v\_{\text{OG}} - v\_{\text{lo}} \tag{6}$$

$$v\_{LL1} = -\frac{v\_{in}}{2} - v\_{OG} - v\_{co} \tag{7}$$

$$
v\_{LL2} = -\frac{v\_{in}}{2} - v\_{OG} - v\_{do} \tag{8}$$

where the square wave voltage sources *vao*, *vbo*, *vco* and *vdo* mean voltages corresponding to half of the output voltage according to the operation of the switch. *vao*, *vbo*, *vco*,and *vdo* are expressed by Equations (9)–(12):

$$v\_{no} = (1 - S\_{H1}) \* \frac{v\_{out}}{2} \tag{9}$$

$$v\_{bv} = (1 - S\_{H2}) \ast \frac{v\_{out}}{2} \tag{10}$$

$$v\_{co} = -(1 - S\_{L1}) \* \frac{v\_{out}}{2} \tag{11}$$

$$v\_{do} = -(1 - S\_{L2}) \* \frac{v\_{out}}{2} \tag{12}$$

where *SH*1, *SH*2, *SL*1, *SL*<sup>2</sup> represent switching functions of the high-side switch of module 1, the high-side switch of module 2, the low-side switch of module 1, and the low-side switch of module 2, respectively. Equation (13) defines a switch function. It is defined that the value of switching function is one when the switch is on and zero when it is off.

$$S\_{H1} = \begin{cases} 1 & \text{Switch } S\_{H1} \text{ is On} \\ 0 & \text{Switch } S\_{H1} \text{ is OFF} \end{cases} \quad S\_{H2} = \begin{cases} 1 & \text{Switch } S\_{H2} \text{ is On} \\ 0 & \text{Switch } S\_{H2} \text{ is OFF} \end{cases}$$

$$S\_{L1} = \begin{cases} 1 & \text{Switch } S\_{L1} \text{ is On} \\ 0 & \text{Switch } S\_{L1} \text{ is OFF} \end{cases} \quad S\_{L2} = \begin{cases} 1 & \text{Switch } S\_{L2} \text{ is On} \\ 0 & \text{Switch } S\_{L2} \text{ is OFF} \end{cases} \tag{13}$$

The neutral voltage of the output capacitor *vOG* can be derived by applying KCL (Kirchhoff's current law) to point O as follows:

$$\begin{aligned} i\_{LH1} + i\_{LH2} + i\_{LL1} + i\_{LL2} &= 0\\ \frac{v\_{LH1}}{Z} + \frac{v\_{LH2}}{Z} + \frac{v\_{LL1}}{Z} + \frac{v\_{LL2}}{Z} &= 0\\ v\_{LH1} + v\_{LH2} + v\_{LL1} + v\_{LL2} &= 0 \end{aligned} \tag{14}$$

where *Z* denotes the impedance of each inductor (it is assumed that the inductors have equal impedance). The following equation is obtained when it is substituted into Equations (5)–(8):

$$-4\upsilon\_{OG} - \upsilon\_{ao} - \upsilon\_{bo} - \upsilon\_{co} - \upsilon\_{do} = 0\tag{15}$$

Finally, the neutral voltage *vOG* can be expressed as follows from Equations (9), (12) and (15):

$$v\_{OG} = \left(\mathcal{S}\_{H1} + \mathcal{S}\_{H2} - \mathcal{S}\_{L1} - \mathcal{S}\_{L2}\right) \* \frac{v\_{out}}{8} \tag{16}$$

The high-side inductor voltages (*vLH*1, *vLH*2) according to the switch operation in the circuit can be rearranged by Equations (17) and (18):

$$\begin{aligned} v\_{LH1} &= \frac{v\_{in}}{2} - v\_{OG} - v\_{ao} \\\\ &= \frac{v\_{in}}{2} + \left(3S\_{H1} - S\_{H2} + S\_{L1} + S\_{L2} - 4\right) \ast \frac{v\_{out}}{8} \\\\ v\_{LH2} &= \frac{v\_{in}}{2} - v\_{OG} - v\_{bo} \\\\ &= \frac{v\_{in}}{2} + \left(-S\_{H1} + 3S\_{H2} + S\_{L1} + S\_{L2} - 4\right) \ast \frac{v\_{out}}{8} \end{aligned} \tag{17}$$

It is difficult to distinguish the common current from the circulating current in Figure 4b; therefore, the interpretation is carried out by dividing the common mode (CM) circuit that generates a common current and the differential mode (DM) circuit that generates the circulating current. Figure 5 illustrates the two-phase parallel three-level converters divided into a CM circuit and a DM circuit. The voltages across the high side inductors in the CM circuit have the same polarity, whereas those in the DM circuit have the opposite polarity.

**Figure 5.** Equivalent circuit for the analysis of circulating current.

The *vCM* expressed in Figure 5 is defined by the sum of the mean of *vao* and *vbo*, and *vOG* (Equation (19)). In addition, *vDM* is defined by half of difference of *vao* and *vbo* (Equation (21)). Furthermore, these voltages can be expressed by switching functions as given in Equations (20) and (22):

$$v\_{\mathbb{C}M} = \frac{v\_{\text{ao}} + v\_{\text{bo}}}{2} + v\_{\text{OG}} \tag{19}$$

$$\mathbf{x} = \left(\mathbf{4} - \left(\mathbf{S}\_{H1} + \mathbf{S}\_{H2} + \mathbf{S}\_{L1} + \mathbf{S}\_{L2}\right)\right) \* \frac{\upsilon\_{out}}{8} \tag{20}$$

$$
v\_{DM} = \frac{-v\_{ao} + v\_{bv}}{2}\tag{21}$$

$$=\frac{\left(\mathcal{S}\_{H1} - \mathcal{S}\_{H2}\right)}{4} \ast v\_{out} \tag{22}$$

Here, *vLH*<sup>1</sup> and *vLH*<sup>2</sup> can be expressed by Equations (23) and (24), using *vCM* and *vDM*, respectively:

$$v\_{LH1} = \frac{v\_{in}}{2} - v\_{CM} + v\_{DM} \tag{23}$$

$$
v\_{LH2} = \frac{v\_{in}}{2} - v\_{CM} - v\_{DM} \tag{24}$$

Moreover, the high-side inductor voltage *vLH CM* in the CM circuit can be expressed as Equation (25) according to the Kirchhoff voltage law of the CM circuit:

$$\begin{split} v\_{LH\ CM} &= \frac{v\_{in}}{2} - v\_{CM} \\ &= \frac{v\_{in}}{2} + \left( S\_{H1} + S\_{H2} + S\_{L1} + S\_{L2} - 4 \right) \* \frac{v\_{out}}{8} \end{split} \tag{25}$$

Figure 6 shows the switching waveforms (*SH*1, *SH*2, *SL*1, and *SL*2) for the Z-type and N-type interleaving method, the common mode inductor voltages (*vLH CM*), the differential mode inductor voltages (*vDM*), and the circulating currents (*iDM*). The common mode voltages across high-side inductors for each module (*vLH CM*) generate the common current, and the differential mode voltages generate a circulating current.

**Figure 6.** (**a**) Circulating current generated during Z-type interleaving; (**b**) circulating current generated during N-type interleaving.

As shown in Figure 6, the time in differential mode operation for Z-type interleaving is shorter than for N-type interleaving so that the circulating current for Z-type interleaving is smaller than that for N-type interleaving. The increase in the circulating current increases the ripple of the inductor current. Figure 7 illustrates the inductor current *iL* according to the interleaving method. The inductor current ripple in Z-type interleaving is smaller than that in N-type interleaving due to the small circulating current. This implies that the inductor losses in Z-type interleaving can be smaller than that of N-type interleaving. In the aspect of filter capacitor, however, different results may be obtained. This will be discussed in the next section.

**Figure 7.** Inductor Currents for interleaving methods.

#### **3. Comparison of Interleaving Methods for Capacitor's Current and Voltage**

*3.1. Impact of Interleaving on Capacitor Current Ripple of Parallel TLBC*

The effect of interleaving of the two-phase parallel TLBC on the inductor current is analyzed extensively in the reference document [18]. However, the effect on the filter capacitor is not discussed. Therefore, in this study, the effect of the interleaving method on the filter capacitor of the two-phase parallel TLBC is analyzed. The current ripple of the filter capacitor is related to the rms value of the capacitor current that is proportional to heat loss generated in the capacitor. Equation (26) represents the loss due to the equivalent series resistance (ESR) of the capacitor:

$$P\_{\mathbb{C}\text{ Loss}} = i\_{\text{c rms}}^2 \ast R\_{\mathbb{C}\text{ ESR}} \tag{26}$$

Increased heat and loss adversely affect the capacitor lifespan and reduce the converter's efficiency. Capacitor is foremost among the causes of failure in converter modules; therefore, a capacitor's lifespan is directly related to that of the converter module [19]. The current ripple of the filter capacitor is an important indicator of the converter's lifetime. Hence, it is essential to consider the effect of the interleaving methods on the current ripple of the capacitor, which will be discussed in Sections 3.1.1 and 3.1.2.

#### 3.1.1. Capacitor Current for Z-Type Interleaving

First, this section discusses the case of Z-type interleaving. Figure 3a illustrates the operating modes and switching status for Z-type interleaving method. As mentioned earlier, the high-side switches of each module operate prior to the low-side switches.

Based on the operation of the switch, a cycle of operational modes was divided into eight states. As illustrated in Figure 8, the current of the high-side and low-side capacitors according to the switching states the switch operation is expressed as Equations (27) and (28):

$$i\_{FCH} = (1 - S\_{H1}) \ast i\_{LH1} + (1 - S\_{H2}) \ast i\_{LH2} - I\_o \tag{27}$$

$$i\_{F\mathcal{L}} = (1 - S\_{L1}) \* i\_{LL1} + (1 - S\_{L2}) \* i\_{L12} - I\_o. \tag{28}$$

**Figure 8.** Operating modes and switching status for Z-type interleaving.

For example, in state 1, the high-side switch of module 1 and low-side switch of module 2 are turn-on, and the positive terminal of the high-side capacitor is connected to the high-side inductor of module 2 and the output terminal (see Figure 8a). Thus, the current of the high-side capacitor *iFCH* can be expressed as the difference between the high-side inductor current of module 2 and the output current by Kirchhoff's current law. Equation (29) represents the current *iFCH* flowing through the high-side capacitor at state 1, as the difference of the high-side inductor current *iLH*<sup>2</sup> of module 2 and the output current *Io*:

$$\dot{\iota}\_{\rm FCH} = \dot{\iota}\_{\rm LH2} - I\_{\rm o} \tag{29}$$

In addition, in state 3, only the high-side switches of module 1 and 2 (*SH*1, *SH*2) are turned on, and the positive terminal of the high-side capacitor is connected only to the output terminal (see Figure 8). This implies that the inductor currents are separated from the capacitors, and the output current is supplied by only capacitors. The current flowing through the high-side capacitor *iFCH* at state 3 is expressed as Equation (30):

$$i\_{FCH} = -I\_o \tag{30}$$

From this analysis, the current of the high-side filter capacitor in each state can be obtained, as shown in Table 1. The current of the low-side filter capacitor can also be obtained similarly. As shown in Table 1, the high-side capacitor current *iFCH* in eight states for Z-type interleaving can be expressed by the high-side inductor currents of modules 1 and 2 (*iLH*<sup>1</sup> and *iLH*2) and the output current Io.

**Table 1.** High-side capacitor current for eight operating states of a Z-type interleaving method.


#### 3.1.2. Capacitor Current for N-Type Interleaving

This section describes the capacitor current ripple for N-type interleaving. Figure 3b of the previous section presents a switching pattern for N-type interleaving method. Unlike Z-type interleaving (where the high-side switches of the two modules turn-on first and then the low-side switches turn-on), the high-side and low-side switches of one module turn-on first and then those of the other module turn-on in N-type interleaving.

As in the case of Z-type interleaving, a cycle was divided into eight states according to the operation of the switch. As shown in Figure 9, in state 1, a high-side switch of module 1 and a low-side switch of module 2 are turned on (this is similar to the case of Z-type interleaving), and a positive terminal of the high-side capacitor is connected to a high-side inductor of module 2 and an output terminal. Therefore, the current of the high-side capacitor *iFCH* can be expressed as the difference between the high-side inductor current of module 2 and the output current using Kirchhoff's current law. This is similar to state 1, Equation (29) of Z-type interleaving. However, states 3 and 4 alongside states 6 and 7 appear differently. For example, in state 4 of Z-type interleaving, all of the high-side switches of modules 1 and 2 are turned off. At this time, the positive terminals of the high-side capacitor are connected to both the high-side inductors and output terminals of modules 1 and 2. Therefore, the current of the top capacitor *iFCH* in the corresponding state can be expressed as the difference between the sum of the top inductor currents of modules 1 and 2 and the output current. Equation (31) represents the high-side capacitor current *iFCH* at state 4 during N-type interleaving as a function of the high-side inductor currents of modules 1 and 2 (*ILH*<sup>1</sup> and *ILH*2) and the output current *Io*:

$$\dot{a}\_{\rm FCH} = \dot{t}\_{LH1} + \dot{t}\_{LH2} - I\_o \tag{31}$$

This is different from *iLH*<sup>1</sup> − *Io* which is *iFCH* in state 7 of N-type interleaving. At the remaining states 3, 6, and 7, the Z-type and N-type interleaving yield different results. Table 2 illustrates the current of the high-side capacitor *iFCH* in each state according to the operating modes for n-type interleaving with the high-side inductor currents of modules 1 and 2 (*iLH*<sup>1</sup> and *iLH*2) and the output current *Io*.

**Figure 9.** Circuit diagram according to the N-type interleaving switching operation.

**Table 2.** High-side capacitor current for eight operating states of the N-type interleaving method.


The capacitor current was analyzed for two types of interleaving methods. The current ripple behavior for both interleaving methods appears differently due to a certain state in Z-type interleaving, which is absent in N-type interleaving. The high-side capacitor current of state 3, which exists only in the Z-type interleaving method, is equal to −*Io*. This is an important contributing factor for the increase in the capacitor current ripple. Figure 10 illustrates the high-side capacitor current waveforms for each interleaving method. This was verified in the simulation described in Section 4.

**Figure 10.** Capacitor current waveforms.

#### *3.2. Comparative Analysis of Capacitor Voltage*

The disadvantages of Z-type interleaving control include not only an increase in loss and a decrease in the lifespan of the capacitor due to an increase in the capacitor current ripple but a negative impact on EMI. Figure 11 shows the high-side capacitor voltages according to the interleaving method.

**Figure 11.** High-side capacitor voltage waveforms.

Figure 11 shows the high-side capacitor voltage waveforms for Z-type and N-type interleaving. The capacitor voltage of Z-type interleaving has similar waveforms to the conventional non-interleaving control, and the capacitor current is charged and discharged once per cycle. However, the high-side capacitor charges and discharges twice per cycle in N-type interleaving so that the capacitor voltage ripple is decreased. When the ripple frequency is doubled, similar to the voltage of the high-side capacitor in N-type interleaving, the cutoff frequency of the EMI filter can be increased. This enables the EMI filter size to be reduced, thereby leading to price reduction [21].

#### *3.3. Current Imbalance with Z-Type Interleaving by the Capacitor Voltage*

The two interleaving methods differ in terms of control as well. First, the Z-type interleaving method cannot evenly drive module currents with open loop drive. Open loop drive means that the current or voltage of the converter have no feedback signals. This implies that, in the absence of external disturbance, two module currents must be the same under same duty. However, the inductor current imbalance occurs in the Z-type interleaving control, so the inductor current is concentrated in the inductor of any one module. so that the electric power is concentrated in one module. This results in higher energy losses and heat generation. Furthermore, when the system operates at more than half the rated load, the excess power over the rated power flows on one side only. This can result in module destruction. Figure 12 illustrates the inductor current waveform for each interleaving method. In the Z-type interleaving open loop drive, the electric power is not evenly distributed to the modules, and the inductor current is concentrated in module 1. On the other hand, it can be observed that imbalance does not occur in an N-type interleaving open loop drive.

**Figure 12.** Current response in two modules for open loop drive.

The inductor current imbalance occurs due to the different voltages applied to the inductors. To describe this phenomenon, Figure 13 illustrates the high-side and low-side capacitor voltages *vFCH* and *vFCL*, inductor voltages *vLH*<sup>1</sup> and *vLH*<sup>2</sup> applied to the high-side inductor of each module; and a high-side inductor current of module 1 *iLH*<sup>1</sup> with Z-type interleaving under an open loop drive.

**Figure 13.** Voltage and current waveforms for Z-type interleaving with an open loop drive.

States 1–8 in Figure 13 are defined according to the switching behavior of the Z-type interleaving method. As described above, interleaving control of a module of two or more phases generates a circulating current owing to differential voltage. The differential voltages between two high-side and two low-side inductors are generated by the voltages of the high-side and low-side capacitors, respectively. However, the capacitors repeatedly charge and discharge according to the switching operation, so the potential of capacitors continuously varies. The high-side inductor voltage of module 1 is positive in states 1, 2, 3, and 7 and negative in states 4, 5, 6, and 8. During states 3, 6, 7, and 8, the current imbalance does not occur because the same voltage is applied across the high-side inductors in both modules 1 and 2. In states 1 and 2, inductor current of module 1 is more increased where the voltage of the high-side capacitor is relatively high, and for states 4 and 5, the inductor current of module 1 is less decreased where the voltage of the high-side capacitor is relatively low. As a result, the current of the high-side inductor of module 1 gradually increases as more positive and less negative voltages are repeatedly applied. This is opposite to the scenario of the high-side inductor of module 2, the inductor current of module 2 is increased by a relatively low voltage, and inductor current of module 2 is decreased by a relatively high voltage. Therefore, the current of module 2 decreases gradually with repeated charging and discharging cycles. The more the cycle is repeated, the more severe the current imbalance. In contrast, the N-type interleaving method does not cause a current imbalance. Figure 14 illustrates the states according to the switching operation in the N-type interleaving method.

In Z-type interleaving control, the voltages of the high-side capacitor in the states 1 and 2 for the module 1 inductor are different from those in states 4 and 5. In contrast, the current imbalance does not occur during N-type interleaving control because the voltages of the highside capacitor states 1, 2, and 3 are equal to those in the states 5, 6, and 7.

As a result, in open loop (non-feedback) drive, the Z-type interleaving method leads to current imbalance. Hence, it is essential to control the closed loop with a current controller in each module with the Z-type interleaving. In contrast, with the N-type interleaving method, a relatively simple control method with low computation requirements, such as an open loop drive or closed loop current control, may be used. This was verified by the simulation described in Section 4.

**Figure 14.** Waveforms observed when N-type interleaving is performed on a TLBC as an open loop.

#### **4. Simulation**

In this section, to compare and analyze the effects of the interleaving methods of the two-phase parallel TLBC, the circulating current and filter capacitor voltage and current for each interleaving method are compared. The current imbalance is also investigated for each control method. Table 3 presents the parameters used in the simulation. Two converter modules with an input voltage of 1000 V and an output voltage of 1500 V were operated under a load of 300 kW each (totally 600 kW).



Figure 15 illustrates the circuit diagram used for the simulation, where the circuit consists of two-phase parallel TLBC with added low-side inductors connected to the neutral point of the filter capacitors. Closed loop control was simulated to measure and control the output voltage and inductor current, and the master–slave method was applied as parallel control. The master controller transmits phase information for interleaving operations to each slave controller and performs imbalance compensation control to match the voltages across the high-side and low-side capacitors. Figure 16 presents the circulating current *iDM* for two types of the interleaving method. As shown in Figure 16, the ripple of the circulating current for Z-type and N-type interleaving control is approximately 70 A and 100 A, respectively. This indicates that the ripple of circulating current is larger in N-type control, and, accordingly, the effective value and harmonic component are also larger in this case.

**Figure 15.** Simulation analysis circuit diagram.

**Figure 16.** Comparison of circulating current by the interleaving methods.

Now, consider the filter capacitor voltage and current for Z-type and N-type interleaving methods. Figure 17 shows the high-side filter capacitor current *iFCH* and FFT analysis for each interleaving method. As previously discussed, the filter capacitor current ripple in Z-type interleaving is larger than that in N-type interleaving. Moreover, the rms value of the capacitor current is in Z-type interleaving is larger (93 A) than that in N-type interleaving (72 A). The results for the N-type interleaving method are affected increasing the frequency of the fundamental wave component of harmonics to a double frequency. Moreover, the magnitude of (major) harmonic component of N-type interleaving is reduced. These are significantly lower than the fundamental component without interleaving as well as the fundamental component of the Z-type interleaving method.

**Figure 17.** (**a**) Capacitor current for Z-type interleaving; (**b**) capacitor current for N-type interleaving.

The interleaving method affects also the capacitor voltage as well as capacitor current. Figure 18 presents the capacitor voltage waveform *vFCH*<sup>1</sup> for each interleaving method.

**Figure 18.** (**a**) Capacitor voltage for Z-type interleaving; (**b**) capacitor voltage for N-type interleaving.

Figure 18 reveals that the voltage ripple of a filter capacitor in Z-type interleaving control is larger than that in N-type interleaving, and that the ripple cycle is two times as long in the former than in the latter. The simulation analyses described earlier used two current controllers for each module in a voltage controller (see Figure 19a). However, for N-type interleaving, as illustrated in Figure 19b, the average current of the two modules can be controlled using a current controller. However, even in this case, Z-type interleaving causes current imbalance, as discussed in Section 3.3.

**Figure 19.** (**a**) TLBC with two current controllers; (**b**) TLBC with single current controllers.

First, as shown in Figure 19a, when single current controller is used per module, the current is effectively divided for both interleaving methods without current imbalance (Figure 20).

However, the different current response may be appeared when only one current controller is used. Figure 21 shows the current waveform for two-phase TLBC with single current controller for both interleaving methods. For the Z-type interleaving method, as illustrated in Figure 21, the inductor current is concentrated in one module, similar to the case of open loop drive. However, with the N-type interleaving method, the inductor currents are evenly distributed in each module.

**Figure 20.** (**a**) Inductor currents for Z-type interleaving with two current controller; (**b**) inductor currents for N-type interleaving with two current controller; (**c**) enlarged (a); (**d**) enlarged (b).

**Figure 21.** (**a**) current imbalance occurring during Z-type interleaving control in single current controller system; (**b**) current unbalance that does not occur during N-type interleaving control in a single current controller system; (**c**) enlarged (a); (**d**) enlarged (b).

The following table compares the performance of TLBC according to the interleaving method. According to each method, the rms current value of the filter capacitor (*iFCHrms*), the voltage ripple of the filter capacitor and whether the open-loop control is possible and the efficiency were compared. In comparison, good things are highlighted with green, and bad things are highlighted with red.

Efficiency analysis was also carried out by PSIM simulation, and ESR of passive devices and forward voltage of IGBT were considered. Efficiency analysis was performed and considered with the same ESR for inductor and capacitor. In this analysis, copper loss was only considered for module loss. The N-type interleaving method has more inductor loss than the Z-type interleaving method, but since the capacitor loss is reduced more than that, the efficiency is good as a result. As a result, Table 4 shows that the N-type interleaving method is better.


**Table 4.** Performance comparison table according to the interleaving method.

#### **5. Conclusions**

In this study, the effect of two interleaving methods on a two-phase parallel three-level bidirectional DC/DC converter was investigated. First, the current of the filter capacitor was formulated through a switching function. Furthermore, the current and voltage of the filter capacitor were investigated by analyzing the operating modes and switching status of switches depending on the interleaving method. In the case of Z-type interleaving control, there is a state in which the capacitor bears all of the output current. Thus, the ripple of the current and voltage of the filter capacitor increases. Furthermore, the inductor current imbalance occurs between two modules due to the difference in the inductor voltages during the charging and discharging states of the high-side and low-side inductors under open loop drive. In conclusion, the N-type interleaving method has more merits to control parallel TLBC because it is superior to the Z-type interleaving method in terms of capacitor of life, EMI noise, and convenience of filter capacitor control. This has been verified by PSIM simulations, which will then be pursued through parallel control techniques for two or more phases of TLBC and other topologies.

**Author Contributions:** H.-I.K. conceptualized, wrote original draft preparation, and did simulations. S.-H.K. assisted in visualizing the data. H.-W.K. and S.-W.B. conceived the idea and wrote the paper. K.-Y.C. and G.-D.K. assisted in idea development and paper writing. All authors have read and agreed to the published version of the manuscript.

**Funding:** The research was supported by a grant from the Academic Research Program of Korea National University of Transportation in 2021. This research was supported by a grant from "Material parts technology development project" of Korea Evaluation Institute of Industrial Technology (KEIT) of the republic of Korea (No. 20001101).

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


**Kiyohiro Iwama \* and Toshihiko Noguchi**

Graduate School of Science and Technology, Shizuoka University, Hamamatsu 432-8561, Japan; noguchi.toshihiko@shizuoka.ac.jp

**\*** Correspondence: iwama.kiyohiro.14@shizuoka.ac.jp

**Abstract:** This paper describes an interior permanent magnet synchronous motor (IPMSM) based on a new adjustable field method. The proposed PM motor achieved magnetic field control utilizing magnetic saturation. In this paper, a back electromotive force (e.m.f.) measurement test and a load test using the prototype motor were conducted to clarify if the proposed motor had a wide operation range. In the back e.m.f. measurement test, it was confirmed that the proposed motor had a wide magnetic field controllable range of 51.7%. In addition, it was revealed, through the load test, that the proposed motor had a wide operating range, including both low-speed high-torque and high-speed low-torque driving conditions. Moreover, based on electromagnetic field analysis, the magnetic field control performance of the proposed adjustable field method was compared with the conventional field weakening control and other adjustable field methods. As a comparison result, it was verified that the proposed motor had less copper loss for the magnetic field control and fewer losses in the high-speed operating range.

**Keywords:** adjustable field; IPMSM; magnetic saturation; permeability; 3D magnetic path

#### **1. Introduction**

Since the Paris agreement was signed in 2015, countries around the world have been working intensively to save energy. Particularly, in the electric machine technical field, the high-efficiency motor has actively been researched. A permanent magnet synchronous motor (PMSM) using high-power density permanent magnets (PMs) has widely been used because the PMSM can make the high-efficiency and high-power density drive possible [1,2]. In addition to the efficiency and the power density, a wide driving range is one of the most important evaluation items of the motor used in automotive applications. Generally, a design that achieves both low-speed high-torque and high-speed low-torque operations is required. However, it is challenging to achieve these operations at the same time because the magnetic field of the PMSM is not adjustable. Conventionally, field weakening control has been applied to expand the high-speed operation range [3,4]. The field weakening control has traditionally employed and can undermine the magnetic field of the PMSM by using the negative *d*-axis current *id*. However, there is a problem whereby the copper loss increase in the high-speed operation range is not ignorable, because the field weakening control requires much current to give a counter magnetic field against the PM field. To make matters worse, the counter magnetic field generated by the negative *id* may cause irreversible demagnetization of PMs in the rotor.

To solve this problem, in previous studies, an adjustable field PMSM that can control the PM-based magnetic field has been attracting attention in recent years [5–11]. The adjustable field PMSM introduced in the references [5,6] can control the magnetic field density on the rotor surface with a consequent pole structure by using a field winding. However, it has low torque density as implemented in surface permanent magnet synchronous motor (SPMSM) configuration. As known well among the researchers, the SPM configuration does not have capability to generate a reluctance torque additional to the magnet torque.

**Citation:** Iwama, K.; Noguchi, T. Operation Characteristics of Adjustable Field IPMSM Utilizing Magnetic Saturation. *Energies* **2022**, *15*, 52. https://doi.org/ 10.3390/en15010052

Academic Editors: Yitao Liu and Ching-Ming Lai

Received: 16 November 2021 Accepted: 21 December 2021 Published: 22 December 2021

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The PMs of the adjustable field SPMSM can easily demagnetize due to the long air gap length. In the reference [7], the magnetic field passing through the magnetic leakage path on the rotor core is controlled by *q*-axis magnetomotive force (m.m.f.). This adjustable field method can realize the magnetic field control with a single inverter, because the additional m.m.f. source is not required. As a result, the magnetic field is dependent on motor operation. The adjustable field principle utilizing the motor harmonics is described in the reference [8]. This method uses the 2nd order space harmonics generated by the concentrated winding structure for the magnetic field control. However, this method cannot control the magnetic field actively and arbitrarily, because the rotating speed governs the quantity of the magnetic field. Furthermore, this motor must use soft magnetic composite (SMC) material, which is difficult to produce.

The adjustable field method proposed in the reference [9] can make an expansive driving range possible, because this method can change the drive circuits that correspond to three-phase or six-phase windings, etc. However, multiple six single-phase inverters are indispensable to switch over the winding configurations. For this reason, there is a drawback that the drive system of this adjustable field PMSM can be larger than other conventional motors. Furthermore, this method has only four discrete magnetic field outputs, resulting in a discrete adjustment of the magnetic field. The IPMSM utilizing the de- and re-magnetization of the PMs can achieve wide-range control of the magnetic field and highly efficient drive [10,11]. However, the drive system for the adjustable field IPMSM based on this approach tends to be bulky, because an extremely high m.m.f. is indispensable for de- and re-magnetization. In general, several significant problems in existing adjustable field methods are the motor type, which cannot deliver the reluctance torque; detrimental influence on the motor operation and rotating speed; demagnetization of PMs; magnetic field controllability; difficulty in manufacturing; and high copper loss for magnetic field control.

The authors have been investigating a new adjustable field method focusing on the magnetic saturation of the magnetic material [12]. The magnetic saturation is a phenomenon in which magnetic permeability changes according to the intensity of the external magnetic field. Typically, this phenomenon detrimentally affects the performance of the motor output in conventional motor drives [13,14]. In the reference [13], it was confirmed, through the analysis, that d- and q-axis flux linkage and torque are affected by the magnetic saturation. In another reference about the influence of the magnetic saturation [14], the relationship between the rotor bridge and the performance of a spoke-type PMSM was mathematically derived. In addition, it was revealed that the magnetic saturation in the bridge part has a significant influence on the motor performance. As mentioned above, the magnetic saturation usually deteriorates the motor output and complicates the design and the control.

As a novelty, the authors propose a motor with an adjustable field method utilizing the magnetic saturation (the proposed motor) in this paper to overcome disadvantages of the conventional field weakening control and the previous adjustable field methods. Detailed contributions of this paper are as follows:


Finally, the proposed motor had a wider controllable range of the magnetic field by 51.7%.

In the following section, the principle of the proposed adjustable field method is introduced and explained in detail. Back e.m.f. characteristics are explained in Section 3. The drive system of the prototype motor and its load characteristic test results are described

in Sections 4 and 5, respectively. Finally, the paper concludes in Section 6 with some highlights of the research study.

#### **2. Principle of Adjustable Field Method Utilizing Magnetic Saturation**

As mentioned above, the proposed adjustable field method uses magnetic saturation of the magnetic material. Figure 1 shows the relationship between the magnetic flux density and the magnetic field (B–H curve) of 35JNE230, used for the prototype motor's core. The permeability is defined as a slope of the B–H characteristic. As shown in Figure 1, the permeability of the core changes depending on the external magnetic field.

**Figure 1.** B–H curve of 35JNE230.

The magnetic circuit and specifications of the prototype motor are shown in Figure 2 and Table 1, respectively. As shown in Figure 2, the prototype motor was an IPMSM. Therefore, the prototype motor could deliver the reluctance torque. The stator and rotor cores of the prototype motor were split into two parts and an additional winding was inserted between the split stator cores. The additional winding generated a magnetic flux to cause magnetic saturation and to control the magnetic field. There were magnetic leakage paths between PMs in the rotor core in the prototype motor. The magnetic flux modulated the permeability of the magnetic leakage paths. Therefore, the additional winding and the magnetic flux were called modulation winding and modulation flux, respectively. The resistance of the modulation winding was larger than that of the armature winding. The voltage drop and inductance became large by designing the modulation winding with a large resistance value. However, the voltage drop was negligibly small compared to the phase voltage and DC-bus voltage, so the effect was small. In addition, there was no effect of the large inductance because the DC modulation current was used. S45C, a carbon steel material, was used as the rotor shaft and the stator frame to penetrate the modulation flux in the 3-dimensional (3D) magnetic path. Generally, the iron loss in the 3D magnetic path was reduced by constructing the 3D path with an SMC [15,16]. However, it costs a lot to make the SMC core, because high pressure around 1000 MPa is indispensable [17]. On the other hand, the proposed IPMSM could use a steel material as the 3D magnetic path because the modulation flux included only a DC or low-frequency component. For this reason, the 3D magnetic path could easily be realized.

**Table 1.** Specifications of prototype motor.


**Figure 2.** Magnetic circuit of prototype motor.

Figure 3 shows a vector plot of the modulation flux when the m.m.f. *Fm* used for magnetic field control was given to the modulation winding. In this paper, all analysis results were obtained from the FEM using JMAG-Designer. As shown in Figure 3a, the modulation flux penetrated in the radial direction. There was a leakage flux passing through the air between the two stator cores, as shown in Figure 3b. However, the amount of the leakage flux was negligibly small because the air gap between the two stator cores was 15 mm, which is much larger than the air gap length between the stator core and the rotor core. In addition, the rotor shaft and the stator frame were magnetized by the DC modulation flux, but the residual flux was negligibly small because S45C, which is a soft magnetic material, was used as the material for the rotor shaft and the stator frame.

**Figure 3.** Vector plot of modulation flux with *Fm* of 1200 AT: (**a**) modulation flux; (**b**) leakage modulation flux passing through air.

It was confirmed, from Figure 3, that the modulation flux penetrated in the radial direction. In the stator, no iron loss occurred because the modulation flux was DC flux. In addition, there was also no iron loss in the rotor due to the modulation flux. Figure 4 was prepared to examine why iron loss did not occur in the rotor. Figure 4a shows a usual DC flux and Figure 4b shows a radial DC flux similar to the modulation flux. As shown in Figure 4a, the observation point in front of the N-pole magnet was defined and the change in magnetic flux in the observation point was verified. Figure 5 shows the magnetic flux fluctuations of the *d*- and the *q*-axis components. Usually, as can be seen in Figure 5a, when the magnetic flux was transmitting, the magnetic flux component in the rotor fluctuated due to the rotation of the rotor, even if the magnetic flux was DC. On the other hand, as can be seen in Figure 5b, when the magnetic flux penetrated in all radial directions, there was no variation in the magnetic flux with respect to time. From the above results, it can be inferred that there was no effect on iron loss when the DC modulation flux was used for the adjustable field.

**Figure 4.** DC flux in rotor: (**a**) usual DC flux; (**b**) radial DC flux.

**Figure 5.** Variation in magnetic flux: (**a**) usual DC flux; (**b**) radial DC flux.

Figure 6 shows vector plots of the PM flux and the modulation flux with an *Fm* of 0 AT, 720 AT and 1200 AT. Without the *Fm*, many PM fluxes leaked in the rotor core. In this case, the permeability of both the N- and S-pole side magnetic leakage path was 50. With an *Fm* of 720 AT, the permeability of the N-pole side magnetic leakage path decreased to 24 by the modulation flux. Therefore, it became difficult for the N-pole PM flux to leak through the magnetic leakage path and the N-pole PM flux interlinking to the stator core increased. However, since the modulation flux penetrated in the direction weakening the N-pole magnet, it was necessary to study the de-magnetization of the N-pole PM. On the other hand, the permeability of the S-pole side magnetic leakage path increased to 3000 by the modulation flux. In this case, many modulation fluxes penetrated through the S-pole side magnetic leakage path and strengthened the magnetic field of the S-pole. With an *Fm* of 1200 AT, the magnetic field of the proposed motor reached its limit, because the permeability of both the N- and S-pole side magnetic leakage paths decreased and the modulation flux could no longer penetrate. In this way, the proposed motor can realize magnetic field control by using magnetic saturation and modulating the permeability of the magnetic leakage paths.

**Figure 6.** Vector plot of magnetic flux density: (**a**) PM flux without *Fm*; (**b**) PM and modulation flux with *Fm* of 720 AT; (**c**) PM and modulation flux with *Fm* of 1200 AT.

Figure 7 shows the magnetic flux density in the air gap between the upper stator core and rotor core with an *Fm* of 0 AT, 720 AT and 1200 AT. By giving the *Fm*, the fundamental component increased. There are even-order components, however. Because the even-order components in the lower-side air gap were observed in the opposite phase with the evenorder components in the upper-side air gap, no even-order component was generated in the back e.m.f. In addition, the DC component was also included in the gap magnetic flux density due to the radial modulation flux, but it did not affect the back e.m.f. because it did not vary with respect to time.

Figure 8 shows the rotor and the stator of the prototype motor. The rotor cores were skewed at an angle of 3.75 deg, taking advantage of the construction whereby the rotor is split into two parts. Thereby, 12th order space harmonics could be reduced because the angle between the teeth and the slots of the stator core was 3.75 deg. The gap between the stator core and the stator frame was minimized by inserting the stator core in the stator frame by shrink-fitting. Besides, slits were provided to the stator frame to suppress the iron loss. Figure 9 shows a magnetic flux density vector plot when a *q*-axis current of 80 A was supplied. However, the rotating speed was 1000 r/min. The model shown in Figure 9a had slits and the model shown in Figure 9b did not. As illustrated in Figure 9, by providing the slits, the armature flux passing in a circumferential direction could be reduced. Figure 10 shows an eddy current loss of the stator frames of the two models. The eddy current loss of the model with slits was 40.4% lower than that of the model without slits. It can be seen, from this result, that the slits were helpful in terms of iron loss.

**Figure 7.** Gap magnetic flux density: (**a**) waveforms; (**b**) FFT results.

**Figure 8.** Configuration of prototype motor: (**a**) photograph of rotor; (**b**) photograph of stator.

**Figure 9.** Magnetic flux density vector on *x–y* cross-section with *q*-axis current of 80 A: (**a**) with slit; (**b**) without slit.

**Figure 10.** Eddy current loss of stator frame with *q*-axis current of 80 A.

#### **3. Back E.m.f. Characteristic**

#### *3.1. Analysis of Back E.m.f.*

Figure 11 shows the rotor geometry of the prototype motor model. It is crucial to design appropriately the saturation areas A and B shown in Figure 11 because the motor with the proposed adjustable field method achieves the magnetic field control by modulating the permeability of the magnetic leakage paths in the saturation areas. As shown in Figure 11, in the prototype motor, the width of the magnetic leakage paths in saturation area A was 3.2 mm and the widths of saturation area B were 1.5 mm and 0.5 mm. As shown in Table 2, the widths were parametrically changed to investigate the relationship between the width and the proposed motor performance.

**Figure 11.** Magnetic saturation areas of prototype motor.

**Table 2.** Width of magnetic leakage paths in saturation areas A and B.


Figure 12 shows the analysis results of the magnetic field Ψ*a*. As shown in Figure 12, the minimum Ψ*<sup>a</sup>* was determined with the width of the magnetic leakage paths. On the other hand, in all models, the gradient in the Ψ*<sup>a</sup>* decreased when the Ψ*<sup>a</sup>* was about 39.6 mWb. Therefore, the maximum Ψ*<sup>a</sup>* was set at 39.6 mWb for all models to evaluate the performances with the same maximum fundamental component of the air gap flux. Table 3 shows the copper losses and controllable ranges of the Ψ*<sup>a</sup>* of each model. As shown in Table 3, the relationship between the controllable range of the Ψ*<sup>a</sup>* and the copper loss for

the magnetic field control was a trade-off. Therefore, when the proposed motor is designed to increase the controllable range, the motor efficiency deteriorates and the motor volume is enormous.

**Figure 12.** Magnetic fields of proposed motor models with different magnetic leakage path widths. **Table 3.** Magnetic field control performances of proposed motor models.


The ultimate design target of the proposed motor when the *Fm* is given is to output a large Ψ*<sup>a</sup>* equivalent to when the saturation areas A and B shown in Figure 11 are replaced with air. In addition, the ideal design without the *Fm* is to leak a much larger PM flux on the rotor core, equivalent to when the saturation areas A and B are replaced with 35JNE230. Therefore, the prototype motor shown in Figure 11 was compared with these two ideal designs. Figure 12 shows the magnetic field amount of the motor with saturation areas replaced with air or 35JNE230. There was a difference in the magnetic field quantity and the magnetic field quantity of the prototype motor was inferior to that of the models simulating the ideal design. Regarding the rotor geometry of the prototype motor, only the widths of the magnetic leakage paths were parametrically adjusted to make the controllable range 50% of the maximum magnetic field amount while considering the mechanical strength. In other words, there is still room to consider other elements, such as PM shape, a flux barrier position, etc. Therefore, the optimized design of the IPMSM with the proposed adjustable field method will be investigated in future works.

#### *3.2. Back E.m.f. Measurement Test*

Figure 13 shows an experimental setup used in this paper. In the measurement test, the prototype motor was connected with a torque transducer TMNR-50NM, MinebeaMitsumi Inc. (Tokyo, Japan) and a load motor and the rotating speed of the prototype motor was controlled by the load motor. In this section, the back e.m.f. of the prototype motor was investigated by opening the terminal of the prototype motor and measuring the phase voltage. As mentioned above, the m.m.f. source *Fm* for magnetic field control was required in addition to the armature m.m.f. source. The *Fm* was supplied by the DC voltage supply.

**Figure 13.** Experimental setup.

Figure 14 shows waveforms and FFT results of the back e.m.f. when an *Fm* of 0 AT or 1200 AT was given to the modulation winding. However, the rotating speed was controlled at a constant speed of 1000 r/min by the load motor. It can be confirmed, from Figure 14, that the experimental value corresponded reasonably well with the analysis value and the fundamental component of the back e.m.f. increased by supplying the *Fm*. The fundamental components of experimental values without the *Fm* were approximately 3% smaller than that of the analysis value. This decrement of the e.m.f. was possibly caused by the manufacturing error of the width of the magnetic leakage paths and the air gap length. In addition, the mesh used in the FEM was also a factor that may have caused the error. On the other hand, the fundamental component of the back e.m.f. with the *Fm* of 1200 AT was 2.1 times larger than that without the *Fm*. Therefore, this result indicates that the prototype motor had a wide controllable range of the magnetic field.

**Figure 14.** U-phase back e.m.f. at rotating speed of 1000 r/min: (**a**) waveforms; (**b**) FFT results.

Figure 15 illustrates the relationship between the magnetic field Ψ*<sup>a</sup>* and the modulation current *im* of the prototype motor. As can be seen in the figure, the Ψ*<sup>a</sup>* depends on the absolute value of *im* and can be approximated as

$$\left|\Psi\_{\rm d}(i\_{\rm m}) = -1.84 \times 10^{-3} \left|i\_{\rm m}\right|^{4} + 0.39 \left|i\_{\rm m}\right|^{2} + 18.\mathcal{T} \text{ (mWb)}\tag{1}$$

**Figure 15.** Experimental result of Ψ*<sup>a</sup>* and its approximate line.

#### *3.3. Magnetic Field Control Performance Comparison with Other Methods*

In this section, based on the back e.m.f. measurement test results, the magnetic field control performance of the prototype motor was compared with that of the motor with other magnetic field control methods. The proposed motor was compared with three motors based on conventional techniques. The first benchmark was a conventional IPM motor. The magnetic field of the conventional IPM motor was weakened with a negative *id*. The second benchmark motor was a hybrid motor proposed in the reference [5,6]. The gap magnetic flux density of the hybrid motor was adjusted by the field current *if*. The third benchmark motor was a variable leakage flux motor introduced in the reference [7]. The magnetic leakage paths were provided in the rotor and the leakage PM flux could be adjusted by *q*-axis m.m.f. Therefore, the magnetic field of the variable leakage flux IPM motor was a function of the *q*-axis current *iq*.

Figures 16–18 show analysis models of the conventional IPM motor, the hybrid motor and the variable leakage flux motor, respectively. In addition, Table 4 shows the specifications of the compared motors. For a fair comparison, all motors had the same material, stator geometry, core stack length, number of winding turns, PM volume and maximum current density. The rotor bridge of the conventional IPM motor was set at 1.0 mm, considering mechanical strength. Because a 3D magnetic circuit and an additional winding were not needed, the stack length and the armature winding resistance of the conventional IPM motor and the variable leakage flux motor were lower than the proposed motor and the hybrid motor. When designing an SPM motor that rotates at higher than 10,000 r/min, it is common to use a protection tube for the rotor to prevent the PM from scattering. Therefore, the air gap length is usually designed longer than the IPM motor. In this paper, the air gap length of the prototype motor, the conventional IPM motor and the variable leakage flux motor was 0.7 mm and that of the hybrid motor was 1.0 mm. It can be seen, from Table 4, that the prototype motor was inferior in terms of torque density because the motor volume, including the 3D magnetic circuit, was the most enormous and output torque was the lowest among all analysis models. The deterioration of the output torque of the prototype motor was greatly affected by the magnetic saturation of the stator teeth due to the radial modulation flux.

**Figure 16.** Analysis model of conventional IPM motor.

**Figure 17.** Analysis model of hybrid motor.

**Figure 18.** Analysis model of variable leakage flux motor.

Figure 19 shows the relationship between the Ψ*<sup>a</sup>* and the manipulating variable of the Ψ*<sup>a</sup>* of the compared motors. However, in the conventional IPM motor, the Ψ*<sup>a</sup>* could not be directly controlled and the *id* was used to weaken the d-axis flux Ψ*d*. As shown in Figure 15, a Ψ*<sup>a</sup>* of 20.5 mWb could be adjusted in the prototype motor by supplying an *im* of 10 A. As shown in Figure 19a, in the conventional IPM motor, a Ψ*<sup>d</sup>* of 20.5 mWb was weakened with an *id* of −63 A. In addition, from Figure 19b, in the hybrid motor, the maximum Ψ*<sup>a</sup>* was 53.0 mWb when an *if* of 4.2 A was supplied and the minimum Ψ*<sup>a</sup>* was 32.3 mWb when an *if* of −4.2 A was supplied. Thus, a Ψ*<sup>a</sup>* of 20.7 mWb could be controlled by an *if* from −4.2 A to 4.2 A. On the other hand, as shown in Figure 19c, in the variable leakage flux motor, even if a maximum *iq* of 80 A was supplied, it was not possible to control a Ψ*<sup>a</sup>* of 20.5 mWb, which was roughly the same as the other motors. From this result, the variable leakage flux motor had a drawback in terms of the controllable range of the magnetic field. Table 5 shows the comparison result of the magnetic field control performance when a Ψ*<sup>a</sup>* of around 20.5 mWb was adjusted. However, as described above, the limit value of the magnetic field control range was 10.1 mWb in the variable leakage flux motor. It can be seen, from Table 5, that the copper loss when the Ψ*<sup>a</sup>* was around 20.5 mWb was 180 W for the proposed motor and 151 W for the hybrid motor, while it was 544 W for the conventional IPM motor. In other words, the proposed motor and the hybrid motor had higher magnetic field control performance.


#### **Table 4.** Specifications of compared motors.

**Figure 19.** Relationship between magnetic field and variable for magnetic field control: (**a**) conventional IPM motor with field weakening control; (**b**) hybrid motor; (**c**) variable leakage flux motor.



Figure 20 shows a vector plot of magnetic flux density when the rotor shafts of the prototype motor and the hybrid motor were most strongly magnetized. Although the rotor shaft diameter of the hybrid motor was larger than that of the prototype motor, the magnetic flux density of the hybrid motor rotor shaft was much higher than the prototype motor. Only the modulation flux passed through the rotor shaft in the prototype motor. On the other hand, in addition to the field flux, the PM flux penetrated to the rotor shaft of the hybrid motor. Therefore, the flux passing through the rotor shaft of the hybrid motor was higher than that of the prototype motor, resulting in a large diameter design for the rotor shaft. Figure 21 shows the B–H curve of the N39UH used for the PM and the operating points of the PM when magnetic field control was carried out in each compared model. The PM of the hybrid motor was easily demagnetized due to a low permeance coefficient caused by a wide air gap. On the other hand, it can be seen that the PM in the prototype motor was hardly demagnetized even if the same amount of the Ψ*<sup>a</sup>* was weakened by applying the conventional field weakening control to the IPM motor.

**Figure 20.** Analysis results of magnetic flux density: (**a**) prototype motor rotor shaft with *im* of 10 A; (**b**) hybrid motor rotor shaft with *if* of −4.2 A.

**Figure 21.** B–H characteristic of N39UH and PM operating points of each compared motor.

#### **4. Drive System of Prototype Motor**

From Equation (1), it can be seen that the magnetic field of the proposed motor depends on the absolute value of the *im*. Therefore, this paper examines magnetic field control methods by supplying the DC *im*.

The DC *im* was controlled with the DC power supply ZX-800L, Takasago Ltd. and the armature currents were supplied by the three-phase inverter MWINV-5R022, Myway Plus Corporation. The electrical conditions and the control block diagram are shown in Table 6 and Figure 22, respectively. As shown in Table 6, the dead time was 4 μs and the error voltage of the dead time was compensated based on the reference [18,19]. In addition, as shown in Figure 22, the relationship between the Ψ*<sup>a</sup>* and *im* expressed in Equation (1) was used for the decoupling item.


**Table 6.** Experimental conditions of current control of prototype motor.

**Figure 22.** Control block diagram of current control of prototype motor when using DC *im*.

Figure 23 shows the experimental results at the rotating speed of 1000 r/min when an *im* of 0 A or 6 A, an *id* of 0 A and an *iq* of 20 A were given to the prototype motor. It can be confirmed from the waveforms of the three-phase line currents and *im* that the line currents could be controlled regardless of the *im*.

**Figure 23.** Experimental results of current control: (**a**) with *iq* of 20 A and *im* of 0 A; (**b**) with *iq* of 20 A and *im* of 6 A.

Table 7 shows the output torque *Tave* when a DC *im* of 0 Adc or 6 Adc was given to the modulation winding. As shown in Table 7, the output torque increased from 1.49 Nm to 2.40 Nm by supplying a DC *im* of 0 Adc or 6 Adc. This result reveals that the prototype motor could control the Ψ*<sup>a</sup>* by the DC *im* because the *Tave* increased with the DC *im* under the same armature current condition.

**Table 7.** Comparison of output torque.


In this section, based on the relationship between the Ψ*<sup>a</sup>* and the *im*, the drive system for the prototype motor is examined. The above results show that the drive system shown in Figure 22 could control the line currents independently of the DC *im*.

Moreover, Equation (1) means that the square wave *im* can be used to output the constant Ψ*<sup>a</sup>* because the absolute value of the square wave is constant. The ability to control the Ψ*<sup>a</sup>* with the square wave *im* is one of the unique points of the proposed adjustable field method. In other words, the power electronics for the proposed motor have a lot of flexibility. The proposed motor can be driven by different power electronics, optimized for magnetic field adjustment by taking advantage of the flexibility. Therefore, we will study the suitable drive system for the proposed motor in the near future. When the power electronics circuit is optimally designed for the field adjustment, the number of switching devices and the complexity of the circuit must be deeply considered because they easily deteriorate the total efficiency [20].

#### **5. Load Characteristics**

#### *5.1. Load Analysis*

Figure 24 shows the relationships between *iq* and torque *T* characteristic (I–T characteristic) of the proposed motor models with different magnetic leakage path widths shown in Figure 11 and Table 2. Figure 24a shows the I–T characteristics when the *Fm* was not supplied. From this Figure, it can be seen that the torque constant, which is defined as the gradient of the I–T characteristic, depended on the minimum Ψ*<sup>a</sup>* shown in Table 3. Figure 23b shows the I–T characteristics with *Fm*. The torque constant was the same among all models because the maximum Ψ*<sup>a</sup>* was unified to 39.6 mWb for all models. However, the required *Fm* was more significant for smaller minimum Ψ*a*.

**Figure 24.** I–T characteristics of proposed motor models with different magnetic leakage path widths: (**a**) without *Fm*; (**b**) with *Fm*.

Figure 25 shows the relationships between rotating speed *N* and *T* characteristic (N–T characteristic) of the proposed motor models when the maximum *iq* of 80 A was applied. Figure 25a shows the N–T characteristics without the *Fm*. As shown in the Figure, the model with the smaller minimum Ψ*<sup>a</sup>* had a wider high-speed operating range. On the other hand, as can be seen in Figure 25b, for the same reason valid for the I–T characteristic, the N–T characteristics with the *Fm* were the same for all models.

**Figure 25.** N–T characteristics of proposed motor models: (**a**) without *Fm*; (**b**) with *Fm*.

It is confirmed, from this result, that the prototype motor model could achieve the low-speed high-torque operation when the *Fm* was given and the high-speed low-torque operation when the *Fm* was not given. In addition, in comparing the models with the same maximum Ψ*<sup>a</sup>* and the different controllable range of the Ψ*a*, it could be revealed that the copper volume and the copper loss for the magnetic field control were in a trade-off relationship with the motor operating range.

The losses at the low-speed high-torque operating point X and the high-speed lowtorque operating point Y shown in Figure 25 were evaluated in comparison with the losses of other compared models shown in Figures 16–18. Table 8 shows the current conditions at each operating point. At the operating point X, the current that maximized the Ψ*<sup>a</sup>* of each motor was supplied and, at the operating point Y, the current that minimized the Ψ*<sup>a</sup>* was supplied. Figure 26 shows the loss analysis results. In this paper, the analysis method of iron loss was common to all motors. The hysteresis loss of the electromagnetic steel sheet 35JNE230 was calculated by considering its hysteresis loop. On the other hand, there are no data about the hysteresis loops of the carbon steel S45C and the PM N39UH in JMAG-Designer. Therefore, the iron loss of these parts included only the eddy current loss. Figure 26a shows the loss analysis results at the operating point X. The copper loss of the prototype motor was significant at the operating point X because the *Fm* was necessary to cause the magnetic saturation and increase the Ψ*a*. In addition, the copper loss of the armature winding was also the largest because the maximum Ψ*<sup>a</sup>* of the prototype motor was the smallest among the compared motors, as can be seen in Table 5. The modulation flux penetrated to the PM when the *Fm* was given. However, there was almost no increase in PM eddy current loss due to the modulation flux because the modulation flux was a DC. For the same reason, additional losses of the stator frame and rotor shaft due to the modulation flux were also small. Figure 26b shows the loss analysis results at the operating point Y. Because the negative *id* was supplied to the conventional motor at the operating point Y, the conventional IPM motor delivered the reluctance torque in addition to the PM torque. Therefore, the conventional IPM motor was advantageous over the other motors at the operating point Y. However, in the high-speed range, the loss of the prototype motor was the smallest among the compared motors because the additional

m.m.f. was not necessary to decrease the Ψ*a*. The PM eddy current loss of the hybrid motor was higher than the other benchmark IPM motors because of the SPM structure. Therefore, the PMs of the hybrid motor were prone to de-magnetization due to heat in addition to the temperature rise of the PMs as well as the counter magnetic field to the PMs.


**Figure 26.** Loss analysis results: (**a**) loss at operating point X; (**b**) loss at operating point Y.

The above results show that the proposed motor could be driven at a high-speed range with less copper loss and iron loss than the field weakening control and the other adjustable field methods. However, in the analysis using FEM, there was often a difference in iron loss between the experimental and the analysis. Therefore, as a future task, it is necessary to accurately measure the drive system's efficiency and evaluate the prototype motor's performance in more detail [21].

#### *5.2. Load Test*

Figure 27 shows the experimental result of the I–T characteristic. In the actual load test, to evaluate the performance of the prototype motor as an adjustable field IPMSM, the *id* was not included in the armature current. Besides, the maximum *iq* was 24 A due to the current limitation of the three-phase inverter MWINV-5R022. The prototype motor was controlled at 1000 r/min by the load motor. The *Fm* was supplied by the DC power supply, similar to the measurement test of the back e.m.f. As shown in Figure 25, the experimental value was in good agreement with the analysis value except in the low *Fm* condition. The torque constant could be changed according to the *Fm*. There was a difference between the experimental and analysis values when the *Fm* was 0 AT or 360 AT. The leading cause of the difference is the decrement of Ψ*<sup>a</sup>* due to the production and mesh error found in the measurement test of the back e.m.f. From the above results, it is confirmed that the prototype motor could control the torque constant freely according to the *Fm*.

**Figure 27.** Experimental results of I–T characteristic.

Figure 28 shows the experimental result of the N–T characteristic. The phase voltage at most 30 V was supplied to the prototype motor assuming an input DC bus voltage of 60 V, because the maximum rotating speed was as low as 3000 r/min due to the speed limitation of the load system. In addition, the maximum torque was 3.7 Nm because the maximum *iq* was 24 A due to the current limitation of the inverter. Since the analysis did not consider iron loss and mechanical loss, the torque of the analysis result was slightly larger than that of the experimental result over the entire N–T characteristic. Especially with a large *Fm*, the harmonics were also high. Therefore, the difference between the observed and analysis values became large. In addition, when the *Fm* was low, the measured magnet torque was slightly lower than the analyzed value because the Ψ*<sup>a</sup>* was smaller than expected due to the production error, similar to the I–T characteristic measurement test. However, the tendency of the N–T characteristic was in good agreement.

**Figure 28.** Experimental results of N–T characteristic.

Based on the above results, it can be seen that the proposed motor could achieve both the low-speed high-torque and the high-speed low-torque operation according to the *Fm*.

#### **6. Conclusions**

In this paper, the essential operating characteristics of the IPMSM with the proposed adjustable field method utilizing magnetic saturation were examined by conducting the measurement test of the back e.m.f. and the actual load tests.

As a result of the back e.m.f. measurement test, it was confirmed that 51.7% of the Ψ*<sup>a</sup>* of the prototype motor was controllable. Based on the test results, the magnetic field control performance was compared with the field weakening control and other adjustable field methods under the same amount of the magnetic field control. The proposed method has some advantages, such as a broader controllable range of magnetic field, less copper loss and anti-demagnetization capability. Detailed contributions of the proposed motor are as follows:


In addition, the losses of the proposed motor at two operating points, which are the low-speed high-torque point and the high-speed low-torque point, were compared with that of the benchmarks. As a result, it was seen that the copper loss of the proposed motor was the largest among the compared motors at the low-speed high-torque operating point. On the other hand, the efficiency considering the copper loss and the iron loss of the proposed motor was the highest at the high-speed low-torque operating point.

In the actual load test, the I–T characteristic and the N–T characteristic were measured. It was confirmed through the I–T characteristic measurement test that the torque constant of the prototype motor could be varied continuously according to the *Fm*. Besides, from the measurement test of the N–T characteristic, it can be seen that the prototype motor could change the operating characteristics, which are the low-speed high-torque and the high-speed low-torque, depending on the *Fm*. However, the actual load test considering the reluctance torque was not conducted. In the adjustable field PMSM, the conventional vector controls, such as maximum torque per ampere (MTPA) control, maximum torque per voltage (MTPV) control and field weakening control, considered under the constant Ψ*<sup>a</sup>* condition, had to be extended because the Ψ*<sup>a</sup>* was adjustable. Therefore, the derivation of the extended vector control algorithm for the adjustable field PMSM is an essential topic for future work.

**Author Contributions:** Conceptualization, K.I. and T.N.; methodology, K.I. and T.N.; software, K.I.; validation, K.I. and T.N.; formal analysis, K.I.; investigation, K.I.; data curation, K.I.; writing—original draft preparation, K.I.; writing—review and editing, K.I. and T.N.; visualization, K.I.; supervision, T.N.; project administration, T.N.; funding acquisition, T.N. All authors have read and agreed to the published version of the manuscript.

**Funding:** This work was supported by JSPS KAKENHI, grant number JP21K04022.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** Not applicable.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


### *Article* **Investigation of AlGaN Channel HEMTs on** β**-Ga2O3 Substrate for High-Power Electronics**

**A. Revathy 1,\*, C. S. Boopathi 1,\*, Osamah Ibrahim Khalaf <sup>2</sup> and Carlos Andrés Tavera Romero <sup>3</sup>**


**Abstract:** The wider bandgap AlGaN (Eg > 3.4 eV) channel-based high electron mobility transistors (HEMTs) are more effective for high voltage operation. High critical electric field and high saturation velocity are the major advantages of AlGaN channel HEMTs, which push the power electronics to a greater operating regime. In this article, we present the DC characteristics of 0.8 μm gate length (*LG*) and 1 μm gate-drain distance (*LGD*) AlGaN channel-based high electron mobility transistors (HEMTs) on ultra-wide bandgap β-Ga2O3 Substrate. The β-Ga2O3 substrate is cost-effective, available in large wafer size and has low lattice mismatch (0 to 2.4%) with AlGaN alloys compared to conventional SiC and Si substrates. A physics-based numerical simulation was performed to investigate the DC characteristics of the HEMTs. The proposed HEMT exhibits sheet charge density (*ns*) of 1.05 <sup>×</sup> <sup>10</sup><sup>13</sup> cm<sup>−</sup>2, a peak on-state drain current (*IDS*) of 1.35 A/mm, DC transconductance (*gm*) of 277 mS/mm. The ultra-wide bandgap AlGaN channel HEMT on β-Ga2O3 substrate with conventional rectangular gate structure showed 244 V off-state breakdown voltage (*VBR*) and field plate gate device showed 350 V. The AlGaN channel HEMTs on β-Ga2O3 substrate showed an excellent performance in *ION*/*IOFF* and *VBR*. The high performance of the proposed HEMTs on β-Ga2O3 substrate is suitable for future portable power converters, automotive, and avionics applications.

**Keywords:** AlGaN channel; β-Ga2O3 Substrate; breakdown voltage; high-power electronics; wide bandgap semiconductors

#### **1. Introduction**

Group III-nitride-based heterostructure devices showed excellent performance in highpower switching electronics [1–3]. Owing to the unique material properties of GaN such as high breakdown field (3.3 MV/cm), high mobility (>1200 cm2/v.s), and wide bandgap (3.4 eV), the GaN-based high electron mobility transistors (HEMTs) are exhibited high 2DEG density (two-dimensional electron gas), low on-resistance (*Ron*), low conduction loss, and high breakdown voltage (*VBR*). Which enable the devices for high-temperature and high-power switching applications [4,5]. However, it is difficult to obtain high breakdown voltage for GaN-channel based HEMTs for smaller dimensions for portable high power switching applications like power converters, automotive electronics, and avionics. Therefore, further enhancing the power handling capability of the HEMTs, the ultra-wide bandgap (>3.4 eV) AlxGa1−xN channel-based devices are widely used [6–11]. There is a wide bandgap and superior thermal stability in AlGaN material adopted as a channel for improving the high-power handling and high-temperature operations of HEMTs. Gate length 2 μm (*LG*) AlN/Al0.5Ga0.5N HEMT on sapphire substrate demonstrated remarkable breakdown voltage improvements [6]. *LG* = 0.8 μm and *LGD* = 1 μm Al0.31Ga0.69N/Al0.1Ga0.9N double-channel HEMTs recorded a *VBR* of 143.5 V [8]. However, the device has shown a

**Citation:** Revathy, A.; Boopathi, C.S.; Khalaf, O.I.; Romero, C.A.T. Investigation of AlGaN Channel HEMTs on β-Ga2O3 Substrate for High-Power Electronics. *Electronics* **2022**, *11*, 225. https://doi.org/ 10.3390/electronics11020225

Academic Editor: Amjad Anvari-Moghaddam

Received: 25 November 2021 Accepted: 6 January 2022 Published: 12 January 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

large negative threshold voltage (*VTH* = −11.2 V), which will increase the power loss of the device at off-state. An Al-rich AlN/Al0.85Ga0.15N HEMTs on sapphire substrate showed 810 V of breakdown voltage (*VBR*) for a gate-drain distance of (*LGD*) of 10 μm [9]. Another Al-rich AlN/Al0.65Ga0.35N HEMTs on the sapphire substrate demonstrated 770 V off-state blocking voltage for 9 μm *LGD* [10]. *LG* = 3 μm Al0.3Ga0.7N/Al0.1Ga0.9N heterostructure on sapphire substrate exhibited excellent sheet carrier density and electron mobility [11], and hybrid ohmic/Schottky drain device configuration showed excellent off-state breakdown voltage. Despite high off-state blocking voltage of Al-rich AlGaN channel HEMTs [6,9,10], the current driving capability is very low due to alloy disorder scattering effects. On other hand, low Al composition AlGaN channel-based HEMTs [8,11] exhibited excellent sheet charge density and carrier mobility.

Apart from channel engineering, substrate engineering is one of the key issues in group III-nitride-based HEMTs. Sapphire (13% lattice mismatch with GaN), SiC (3.8% lattice mismatch with GaN), and Si (16% lattice mismatch with GaN) are widely used as substrate materials for GaN-based HEMTs [1–11]. Due to lattice mismatch between buffer and substrate materials, an additional AlN layer is required in between for lattice match, which involves additional costs and increases the device fabrication complexity.

Recently, β-Ga2O3 is an emerging material for power electronics applications. The wide bandgap (4.7 eV), high critical electric field (6–8 MV/cm), large-scale, high-quality bulk substrate, low defect density, and nearly lattice match (0 to 2.4% lattice mismatch for AlGaN alloys) with III-Nitride alloys make β-Ga2O3 a promising material for future high-power applications [12–18]. A numerical study on normally-off AlN/β-Ga2O3 based HEMT with GaN back barrier showed a suppressed leakage current and excellent DC characteristics [19]. In spite of high-power performance, the β-Ga2O3 channel-based HEMTs experienced low electron mobility and low sheet charge concentration [18] as a result of low current driving capability. In this work, we used β-Ga2O3 as a substrate for the following reasons. 1. Low lattice mismatch with AlGaN alloys and therefore an additional thick AlN nucleation layer is not required 2. Relatively low cost compared to GaN and SiC, and 3. Availability of large wafer size. The novelty of the work is gate field plate AlGaN channel HEMTs on β-Ga2O3 substrate.

The first Al0.1Ga0.9N channel-based HEMTs on the β-Ga2O3 substrate is proposed in this work for simultaneous improvement in both power handling and current driving capability of HEMTs. The proposed gate field plate Al0.31Ga0.69N/Al0.1Ga0.9N HEMTs on β-Ga2O3 substrate is investigated using ATLAS TCAD [20] and the device DC characteristics are presented. The device simulation models are validated with the experimental results. The field plate gate low Al composition (Al = 10%) AlGaN channel HEMT on β-Ga2O3 substrate showed remarkable improvement in breakdown voltage (*VBR*), on-state drain current density, and low on-resistance.

#### **2. Device Structure and Simulation Model**

Figure 1a shows the schematic cross-section of the conventional gate Al0.1Ga0.9N channel HEMT (Device A) on β-Ga2O3 substrate and field plate gate HEMT (Device B) is displayed in Figure 1b. Both device's epi-stack consist of 100 nm Al0.1Ga0.9N channel, 23 nm Al0.31Ga0.69N barrier, and 2.2 μm Al0.31Ga0.69N buffer, 100 nm SiN passivation (Er~7). Low Al-composition Al0.1Ga0.9N channel is used in this to improve the sheet charge density (2DEG) and enhance electron mobility (μ) [8,11]. The Al0.1Ga0.9N layer is directly grown on the β-Ga2O3 substrate. A low lattice mismatch (<2.4%) between AlGaN buffer and β-Ga2O3 substrate alleviates the interface defects and enhanced the device performance. Moreover, the β-Ga2O3 wafer is available in a larger size and low cost compared with SiC and GaN [12–18]. Device gate length is defined as 0.8 μm (*LG*) and asymmetrical gate to source (*LGS* = 0.8 μm) and gate to drain distance (*LGD* = 1 μm) is considered for this work in order to reduce the source resistance. To analyze the impact of filed plate structure on the breakdown performance of the AlGaN channel HEMT, a 0.75 μm field plate (*LFP*) was used in Device B. Ohmic contact was realized for source and drain contact by defining the

work function of the electrode as 3.4 eV and Schottky gate contact enabled by defining electrode work function as 5.2 eV. Field plate gate structure used for the proposed HEMT for improving the off-state blocking voltage of the device by re-shaping the electric field across the gate to the drain access region. The SiN passivation avoids the surface-related trapping effects and avoids the current collapse phenomena.

**Figure 1.** (**a**) Schematic of Conventional HEMT. (**b**) Gate field plate HEMT.

The TCAD simulation energy band diagram is plotted in Figure 2 at zero gate bias and drain bias. It shows the conduction band discontinuity at the interface of Al0.31Ga0.69N/Al0.1Ga0.9N and forms a 2DEG due to spontaneous and piezoelectric polarization effects. The sheet charge density (*ns*) of 1.05 × <sup>10</sup><sup>13</sup> cm−<sup>2</sup> extracted from the device simulation. The corresponding polarization charge details are displayed in Figure 3. The material parameters for the simulation are taken from [16–22] and are presented in Table 1.

**Figure 2.** Energy band details of heterostructure at no bias conditions.

**Table 1.** Material parameters used for the TCAD simulation.


The basic device physics models that operate on any semiconductor devices have been derived from Schrodinger's equation, Shockley–Read–Hall (SRH) recombination model, Poisson's equations, the continuity equations, and the transport equations. The quantum electron density relies on the one-dimensional (1D) Schrodinger's equation, which relates the eigen state energies *Eiv*(*x*) and wave function *ϕiv*(*x*, *y*).

$$-\frac{h^2}{2}\frac{\partial}{\partial y}\left(\frac{1}{m\_y^v(\mathbf{x},y)}\frac{\partial \varrho\_{iv}}{\partial y}\right) + E\_\mathbb{C}(\mathbf{x},y)\varrho\_{iv} = E\_{iv}\varrho\_{iv} \tag{1}$$

where *m<sup>v</sup> <sup>y</sup>*(*x*, *y*) indicates spatial dependent effective mass and *EC*(*x*, *y*) represents the conduction band edge. Poisson's equations relate the electric field (E), electrostatic potential (ψ), and space charge concentration (*ρ*). Which is written as follows [20];

$$
\nabla^2 \Psi = -\nabla E = \frac{\rho}{\varepsilon} \tag{2}
$$

The continuity and transport equations describe the time-dependent electron (*n*) and hole (*p*) densities due to carrier transport, carrier generation (*Gn* and *Gp*), and carrier recombination (*Rn* and *Rp*) process. The continuity equations are defined by the following equations [20];

$$\frac{\partial n}{\partial t} = \frac{1}{q} \nabla f\_n + G\_n - R\_n \tag{3}$$

$$\frac{\partial p}{\partial t} = -\frac{1}{q}\nabla f\_p + G\_p - R\_p \tag{4}$$

The drift-diffusion carrier transport model is based on Boltzmann transport theory, which relates the current densities (*Jn* and *Jp*) with quasi-Fermi levels (∅*<sup>n</sup>* and ∅*p*) and the quasi-Fermi levels are related with carrier concentrations and potentials through Boltzmann approximations [20].

$$J\_n = -q\mu\_n n \nabla \mathcal{Q}\_n \tag{5}$$

$$J\_p = -q\mu\_p p \nabla \mathcal{Q}\_p \tag{6}$$

The polarization property of group III-nitride is the major source for 2DEG, the spontaneous (*PSP*) and piezoelectric polarization (PPZ) models are used for the device simulation. The carrier mobility impacts the device on-state current density (*IDS*) and transconductance (*gm*). Therefore, the temperature, composition, and doping dependent Farahmand Modified Caughey Thomas low field mobility model (FMCT.N) and nitride specific high field mobility (GANSAT.N) models [20] are used in this work. In order to capture the trap-assisted recombination due to crystal defects and dopant, Shockley–Read– Hall (SRH) recombination model is used for the device simulation. Which is described by the following equations [20];

$$R\_{net}^{SRH} = \frac{n - n\_{ie}^2}{\tau\_p \left[ p + n\_{ie} \exp\left(\frac{-E\_{trsp}}{KT}\right) \right] + \tau\_n \left[ p + n\_{ie} \exp\left(\frac{-E\_{trsp}}{KT}\right) \right]} \tag{7}$$

where *τ<sup>p</sup>* and *τ<sup>n</sup>* are electron and hole lifetime, respectively, and *Etrap* defines the intrinsic Fermi energy level to trap energy level. The impact ionization model described by Selberherr used for device breakdown simulation, which relates the carrier generation (*G*) rate with electron (*αn*) and hole ionization coefficients (*αp*), and electron (*Jn*) and hole current densities (*Jp*) [20];

$$G = \alpha\_p \left| f\_p \right| + \alpha\_n \left| f\_n \right| \tag{8}$$

#### **3. Results and Discussions**

The current driving (*J* = *qvns*) capability of the HEMTs relies on the electron velocity (*v*), sheet charge, and 2DEG density (*ns*). The proposed HEMT showed 1.12 × 107 cm/s of electron velocity and sheet charge density (*ns*) of 1.05 × 1013 cm<sup>−</sup>2. The DC characteristics of proposed AlGaN channel HEMTs on β-Ga2O3 are presented in this section. The device output characteristics is plotted in Figure 4 for *VGS* = −4 V to 8 V and *VDS* from 0 V to 20 V. The HEMT showed a peak on-state drain current (*IDS*) of 1.35 A/mm at *VGS* =2V and the extracted ON-resistance (*RON* = Δ*VDS*/Δ*IDS*) from the V-I curve corresponding to *VGS* = 0 V is 8.83 Ω.mm. The DC transfer characteristics of HEMT is displayed in Figure 5a at *VDS* = 10 V and *VGS* swept from −10 V to 8 V. A peak transconductance (*gm*) of 277 mS/mm obtained at *VGS* = −1.5 V and extracted a threshold voltage of −4.31 V. The device transfer characteristics log-scale plot displayed in Figure 5b and the HEMT showed an excellent *ION*/*IOFF* ratio of ~1014. The obtained *IDS* and *gm* are the highest results among the AlxGa1−xN channel HEMTs [6–11]. The TCAD simulation is validated with the *LG* = 0.8 μm gate length AlGaN channel HEMT experimental results for transfer and breakdown performance [8] and depicted in Figure 6, which shows the simulation results are well correlated with experimental results.

**Figure 4.** Output characteristics.

**Figure 5.** (**a**) Input characteristics. (**b**) Input characteristics in log-scale plot.

**Figure 6.** Simulation models validation with experimental results (**a**) Transfer characteristics, (**b**) Breakdown characteristics [8].

For power electronics applications, low ON-resistance (*RON*) and high breakdown voltage (*VBR*) are the most critical parameters to minimize the resistive losses during high power operation of HEMTs, which determine the efficiency of the power devices. In IIInitride-based HEMTs, the 2DEG is induced by polarization, and the breakdown voltage depends on the gate-to-drain distance (*LGD*). The ON-resistance of the HEMT expressed as following expressions [23];

$$R\_{on} = R\_{channel} + R\_{drain} = \frac{L\_G}{\mathcal{W}\_G} \cdot \frac{1}{q\mu n\_s} + \frac{L\_{GD}}{\mathcal{W}\_G} \cdot \frac{1}{q\mu n\_s} \tag{9}$$

where *Rchannel* is the channel resistance and *Rdrain* is drain side access resistance. Primarily, the off-state breakdown voltage depends on *LGD* = *VBR Ecrit* when source and drain contact resistances are neglected. In general, longer gate length and larger gate-drain spacing HEMTs typically exhibit high *VBR* but the ON-resistance also increased with *LG* [23]. Shorter gate length and small *LGD* HEMTs showed low breakdown voltages. Hence, the optimization of HEMTs structure is the key component for achieving high breakdown field and low RON for future low loss power semiconductor devices with smaller device sizes. In this work, we used *LG* = 800 nm gate length and *LGD* = 1000 nm ultra-wide bandgap AlGaN channel along with gate field structure. In addition, the obtained results were compared with existing HEMTs with same *LG* and *LGD* [8].

The high critical electric field of AlGaN channel (~4×) HEMTs to GaN-channel HEMTs leads to high voltage operation of the device. Figure 7 shows the forward blocking characteristics of the conventional AlGaN channel and gate field plate AlGaN channel HEMTs. The off-state breakdown voltage (*VBR*) is extracted from VD-ID when drain leakage current reaches 1 mA/mm. As shown in Figure 7, *LG* = 0.8 μm conventional AlGaN channel HEMT on β-Ga2O3 substrate demonstrated 244 V of *VBR* and *LG* = 0.8 μm and *LFP* = 0.75 μm gate field plate HEMT on β-Ga2O3 substrate showed a *VBR* of 350 V. The field plate HEMT modulates the electric field in the device access regions (gate-drain space) and able to sustain high electric fields, which leads to enhanced breakdown voltage. Logarithmic electron concentration of the HEMTs is displayed in Figure 8 at the breakdown condition. The Depletion region of gate field plate HEMT in Figure 8b is larger than the conventional gate HEMT Figure 8a. This represents that the higher depletion width leads to high *VBR* and the smaller depletion width would decrease the *VBR* of the HEMT. Gate field plate AlGaN channel HEMT on β-Ga2O3 substrate exhibited excellent breakdown characteristics and low ON-resistance than existing AlGaN channel HEMT with identical device size [8]. This reveals the potential of AlGaN channel HEMTs on β-Ga2O3 substrate for future power switching applications with smaller device sizes. The comparison of proposed AlGaN channel HEMTs breakdown performance with previously reported AlGaN channel HEMTs [8–11,24–29] are presented in Figure 9. Our device showed excellent breakdown voltage than existing HEMTs for smaller gate length (*LG*) and gate-drain distance (*LGD*).

**Figure 7.** Off-state breakdown characteristics.

**Figure 8.** (**a**) Logarithmic electron concentration of conventional HEMT. (**b**) Logarithmic electron concentration of gate field plate HEMT.

**Figure 9.** Benchmark of breakdown voltage for AlGaN channel HEMTs.

The tentative fabrication steps of the proposed HEMT are depicted in Figure 10. The epitaxial growth can be performed by the MOCVD process (Metal Organic Chemical Vapor Deposition) on the β-Ga2O3 substrate. Device mesa isolation will reduce the reducing leakage currents. This can be achieved through dry etching ICP-RIE (Inductively Coupled Plasma Reactive Ion Etching). The patterned deposition of source and drain contacts will be conducted through optical lithography and e-beam evaporation followed by hightemperature annealing. The minimum feature size used is 1 micron hence patterning is possible through optical lithography for lower feature sizes one has to depend on e-beam lithography. Then, patterning and deposition of gate metal followed by contact annealing at a lower temperature to ensure Schottky nature of the contact. Blanket deposition of silicon nitride through PECVD (Plasma Enhanced Chemical Vapor Deposition) and ALD (Atomic Layer Deposition) over the entire substrate. Selective etching of SiN for source, gate, and drain pad openings through ICP-RIE.

**Figure 10.** Tentative fabrication flow of AlGaN channel HEMTs.

#### **4. Conclusions**

AlGaN channel HEMTs on β-Ga2O3 substrate are proposed and the device DC characteristics with rectangular and gate field plate structures are analyzed. The wide-bandgap AlGaN channel along with field plate gate HEMT showed improved breakdown voltage (*VBR*) of 350 V for *LG* = 0.8 μm and *LGD* = 1 μm, whereas the conventional gate HEMT with identical device dimensions showed 244 V of *VBR*. The improved breakdown voltage from the larger depletion region at breakdown condition in field plate HEMT. The low Al composition Al0.1Ga0.9N channel also demonstrated a peak ON-state current density of 1.35 A/mm, 8.83 Ω.mm of RON, and *gm* of 277 mS/mm. TCAD simulation and DC characteristics of the β-Ga2O3 substrate-based AlGaN channel HEMTs indicates the suitability of proposed HEMTs for future portable less weight power converters, motor driver, consumer electronics, automotive, and avionics applications. In addition, the β-Ga2O3 substrate can be utilized for all group III-nitride-based transistors for better performance.

**Author Contributions:** Conceptualization, methodology, software, validation, A.R.; formal analysis, investigation, resources, data curation, writing—original draft preparation, supervision, C.S.B.; writing—review and editing, visualization, O.I.K.; project administration, funding acquisition, C.A.T.R. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research has been funded by Dirección General de Investigaciones of Universidad Santiago de Cali under call No. 01-2021.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** The data presented in this study will be provided based on reasonable request to corresponding authors.

**Acknowledgments:** The authors would like to thank to the SRM Institute of Science and Technology, Chennai and Universidad Santiago de Cali for providing necessary support to carry out the research work.

#### **Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


28. Wu, Y.; Zhang, J.; Zhao, S.; Zhang, W.; Zhang, Y.; Duan, X.; Chen, J.; Hao, Y. More Than 3000 V Reverse Blocking Schottky-Drain AlGaN-Channel HEMTs with >230 MW/cm2 Power Figure-of-Merit. *IEEE Electron Device Lett.* **2019**, *40*, 1724–1727. [CrossRef] 29. Xiao, M.; Zhang, J.; Duan, X.; Zhang, W.; Shan, H.; Ning, J.; Hao, Y. High Performance Al0.10Ga0.90N Channel HEMTs. *IEEE Electron Device Lett.* **2018**, *39*, 1149–1151. [CrossRef]

### *Article* **A Bi-Directional DC Solid-State Circuit Breaker Based on Flipped Γ-Source**

**Jing Gao 1,\*, Ziming Liu 1, Jinming Luo 1, Hongjiang Wang 1, Yiqi Liu <sup>2</sup> and Junyuan Zheng <sup>2</sup>**


**Abstract:** As the continuous consumption of non-renewable energy leads to resource shortages, distributed PV generation technology has received widespread attention. The DC microgrid is an effective way to connect distributed PV generation. However, DC microgrids have numerous challenges, such as the absence of zero current crossing point and high fault current rising rate. In the paper, a bi-directional DC solid-state circuit breaker based on flipped Γ-source is proposed to overcome some of the challenges in DC microgrid. The topology uses the mutual inductance current generated by the transformer to force the SCR naturally commutates off. Which can rapidly interrupt and isolate the faulty part, and at the same time, there will be no circulating current impact on the source side. The diode bridges allow the response to faults on either the source or load side with only a single controlled switch. Therefore, the topology is simplified while enabling it to obtain the capability of bidirectional operation protection. Finally, using the simulation software PSCAD/EMTDC and experimental platform verifies the effectiveness of the topology in this paper.

**Keywords:** PV generation; DC microgrid; solid-state DC circuit breaker; bi-directional operation protection

#### **1. Introduction**

In recent years, as the consumption of non-renewable energy leads to resource shortages and the deterioration of environmental pollution, distributed renewable energy power generation technologies such as wind power generation and solar power generation have received widespread attention. DC microgrid serves as effective access to distributed power generation technologies. Compared with the AC microgrid, the DC microgrid can more efficiently and stably receive distributed renewable energy power generation systems such as wind energy and photovoltaics, energy storage devices, electric vehicles, and other DC loads. Although the DC microgrid has many advantages, the low system impedance of the DC microgrid will cause the short-circuit current to rise rapidly when the DC side fails. At the same time, the current in the DC system cannot naturally cross the zero point, and it is difficult to shut down. These problems have become the key to restricting the wide application of DC microgrids [1–4].

DC circuit breakers are divided into pure mechanical DC circuit breakers broken off by traditional mechanical switches. Solid-state circuit breakers perform interruption by power electronic devices and hybrid circuit breakers combining the above two structures [5–9]. Compared with the pure mechanical DC breakers, the solid-state circuit breakers have no mechanical switch part, and power electronic devices have good functional characteristics. The solid-state circuit breakers use the advantage of power electronic devices to realize arc-free shutdown and rapidly isolate the fault current. At the same time, its usual time is significantly increased, which is suitable for operation protection of medium and low voltage DC microgrid [10–13].

**Citation:** Gao, J.; Liu, Z.; Luo, J.; Wang, H.; Liu, Y.; Zheng, J. A Bi-Directional DC Solid-State Circuit Breaker Based on Flipped Γ-Source. *Energies* **2022**, *15*, 745. https:// doi.org/10.3390/en15030745

Academic Editor: Enrique Romero-Cadaval

Received: 15 October 2021 Accepted: 9 January 2022 Published: 20 January 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

With the rapid development of power electronic devices, solid-state DC circuit breakers have also made great developments. Literature [14,15] proposed three Z-source DC circuit breaker topologies. The Z-source solid-state DC circuit breaker is relative. The traditional structure is simpler. Its special circuit structure realizes automatic commutation, which optimizes the insufficiency of forced commutation of standard DC circuit breakers. At the same time, the Z-source solid-state DC circuit breaker does not need to use additional control circuits when the short-circuit fault current rises rapidly. It can realize the natural zero-crossing point of the SCR circuit current and automatically isolate the short-circuit fault current. Utilizing the inductance current in the circuit and the characteristics of the SCR, the function of automatic detection and arc-free isolation of the fault current is realized. The problem of the complex structure of the traditional solid-state DC circuit breaker detection circuit is solved. Reference [16] proposed a novel topology of T-source DC solid-state breakers. However, the unidirectional DC circuit breaker limits its application in practical engineering. Four types of bi-directional Z-source DC circuit breakers are proposed in references [17–20]. However, these bi-directional topologies have some problems, such as an excessive number of components, a complex circuit structure, fault current having a particular impact on the source side, etc.

This paper proposed a bi-directional DC solid-state circuit breaker based on flipped Γ-source (ΓSCB). Based on keeping interrupted and isolating short circuit fault currents rapidly to reduce the cost and volume. The topology can rapidly isolate the fault current without external control, simplifying the overall circuit. There will be no circulating current impact on the source side after the fault isolation. The paper is structured as follows: Section 2 describes the overview of Z-source breakers and their operational principles. Section 3 provides the design of the ΓSCB. Section 4 analysis the fault current change rates. In Sections 5 and 6, the results of the simulation and experiment are given. Section 7 concludes the paper.

#### **2. Overview of Z-Source Circuit Breakers**

The DC microgrid has promoted the development of DC solid-state circuit breakers. The topology of traditional Z-source DC circuit breakers is divided into crossed topology, parallel-connected topology and series-connected topology. Table 1 explains the type of circuit breaker represented by the symbol.


**Table 1.** Nomenclature.

As shown in Figure 1, the three types of DC circuit breakers are mainly composed of SCR, capacitor, inductance, and RD buffer circuits. The red line in Figure 1 is the working state when the fault occurs. The fault current on the load side passes through the Z source capacitor and flows to the short-circuit point. Since the current in the line inductance cannot change suddenly when the reverse current in the SCR equals the steady-state load current of the line, the SCR is automatically closed, and the energy in the line decays to zero through the buffer circuit, thereby achieving the effect of quickly isolating the fault current.

Circuit structures, such as Γ-source and Z-source, are first applied to the research of inverters. With the development of PV Generation, they are applied to the field of solid-state DC circuit breakers. The crossed topology, shown in Figure 1a, fails to provide a common ground point between the source and load, so the actual application of the project is affected. The parallel-connected topology is shown in Figure 1b. The structure is transformed on the basis of the crossed type so that there is a common point between the source and the load, but when a fault occurs, the fault current will have a circulating current impact on the source side—Figure 1c shows the series-connected topology. Along with the common point, the structural characteristics of the Z-source capacitor greatly reduce the impact of the fault current on the source side, so it has become a relatively ideal solution at present. As shown in Figure 2, Three topology structures of bidirectional Z-source DC circuit are proposed by references [13,14]. Figure 2a,b shows that the characteristics of diode and SCR need to be used to achieve bidirectional operation, but the number of capacitors and inductances needs to be increased, and the current of LC branch will still have an impact on the source side. As shown in Figure 2c, the bidirectional Z-source DC circuit breaker adopting coupled inductors uses the mutual inductance current in the coupled inductors to realize automatic shutdown of the SCR, but the two sets of coupled inductors increase the volume and cost.

**Figure 1.** Previously proposed Z-source DC circuit breaker: (**a**) parallel-connected topology; (**b**) series-connected topology; (**c**) crossed topology.

**Figure 2.** Three Bidirectional Z-source circuit breakers with coupling inductors: (**a**) Bidirectional crossed topology; (**b**) series-connected topology; (**c**) Bidirectional topology with coupled inductor.

#### **3. Design of Bidirectional DC Circuit Breaker Based on Flipped** Γ**-Source**

The bidirectional DC circuit breaker based on flipped Γ-source is shown in Figure 3, which is composed of a transformer, an SCR, capacitors, a diode bridge, a load capacitor and a load. Compared with the topology in Figure 1, the topology in this paper uses the mutual inductance current produced by the transformer to force the SCR naturally commutate off, which replaces the LC branch of the traditional Z-source topology solves the problem of circulating current impact on the source side. The bidirectional dc circuit breaker proposed in this paper has full-bridge diodes. The full-bridge arrangement of diodes allows load current to flow in either direction while retaining the same conduction path through SCR. Thus, the bidirectional dc circuit breaker limits and interrupts fault current regardless of the direction of power flow. Owing to the diode bridge circuit in the topology, only one controlled switch can realize bidirectional operation protection. Compared with the topology in Figure 2, only an SCR and a two-winding transformer are utilized to reduce the number RD buffer circuit. Thus, the topology is simplified while enabling it to have the capability of bidirectional operation protection.

To figure out the characteristics of different types of DC circuit breakers, the characteristics of various circuit breakers are analyzed in detail in Table 2. The advantages of bi-based on flipped ΓSB proposed in this paper are discussed by comparing the common ground, bidirectional operation protection capability, fault current clearing capability, and the number of SCR. Compared with traditional ZSCBs, the ΓSCB using a transformer instead of two separate inductors can offer three advantages. The first advantage is a smaller volume, the second advantage is a settable turns ratio to optimize the protection, and the third advantage is the anti-saturation characteristic. The proposed topology can achieve bidirectional energy flow and achieve bidirectional fault interruption and isolation. Obviously, this topology has a simpler circuit, fewer components, and common ground compared with the previous approach.


**Table 2.** Comparison of different DC circuit breakers.

#### *3.1. Working Principle*

Different operating states of ΓSCB are presented in Figure 4. The forward energy flow channel consists of an SCR, the diode *D*<sup>1</sup> and *D*2, capacitor *C*, the primary coil *L*<sup>1</sup> of the transformer. Similarly, the SCR, the diode *D*<sup>2</sup> and *D*3, capacitor *C*, the primary coil *L*<sup>1</sup> of the transformer, constitute the channel of the reverse energy flow.

**Figure 3.** A bidirectional DC Solid-state circuit breaker based on flipped Γ-source.

**Figure 4.** Various operating states of the flipped Γ-source DC circuit breaker: (**a**) steady state condition; (**b**) fault condition; (**c**) freewheeling state.

The normal operating states of the circuit are shown in Figure 4a. At this time, the left side is the source, and the right side is the load. In the operating state, the conduction path from the source side to the load side through *L*<sup>1</sup> and SCR is shown in the red line of the Figure. The voltage across the capacitor *C* can be regarded as equal to the supply voltage under the premise of neglecting the voltage drop of SCR. When the fault occurs on the load side, the working state of ΓSCB is shown in Figure 4b. Part of the fault current generated by capacitor *C* flows through the second coil of the transformer *L*<sup>2</sup> and *D*<sup>4</sup> to compensate for the fault current. The other part flows through load capacitor *CL* to compensate for the fault current. During this process, the current in the secondary coil of the transformer *L*<sup>2</sup> will rise rapidly. Due to the mutual inductance of the transformer, the primary coil of the transformer *L*<sup>1</sup> will generate an induced current opposite to the original current *is*, and when the two are equal, the SCR is turned off. After the SCR is turned off, the fault is completely isolated from the source side, and the current flows in the circulating path on the load side until the remaining energy decay to zero, as shown in Figure 4c. Due to the diode bridge circuit, ΓSCB does not need to add a buffer circuit, and the working principle of the forward energy flow is equal to the reverse energy flow.

#### *3.2. Analysis of the Impedance Network*

*k* is the coupling coefficient of the two coupling coils, in this paper, *k* = 1. When the DC circuit breaker is in normal working condition, the mutual inductance value of the two-winding transformer is *M*.

$$M = k\sqrt{L\_1 L\_2} \tag{1}$$

The inductance of the primary and secondary coils of the transformer is *L*<sup>1</sup> and *L*2. According to the normal working equivalent circuit of DC circuit breakers in Figure 5, the input and output voltage transfer function is determined, and the steady-state characteristics of the circuit are analyzed. In the case of a resistive load, through theoretical derivation, the output and input voltage transfer function can be obtained as:

$$Z\_{\rm eq} = \frac{(L\_1 + M)(L\_2 + M)\mathbf{C}s^3 + R\_L}{(L\_2 + M)\mathbf{C}s^2 + R\_L\mathbf{C}s + 1} + \frac{(L\_1 + L\_2 + 2M)R\_L\mathbf{C}s^2 + (L\_1 + M)s}{(L\_2 + M)\mathbf{C}s^2 + R\_L\mathbf{C}s + 1} \tag{2}$$

$$G\_v(s) = \frac{V\_o}{V\_s} = \frac{R\_L}{Z\_{eq}} = \frac{(L\_2 + M)R\_L \mathbb{C}s^2 + R\_L^2 \mathbb{C}s + R\_L}{(L\_1 + M)(L\_2 + M)\mathbb{C}s^3 + (L\_1 + L\_2 + 2M)R\_L \mathbb{C}s^2 + (L\_1 + M)s + R\_L} \tag{3}$$

**Figure 5.** Circuit diagram when DC circuit breaker works normally.

Substituting the relevant data of the simulation parameters into Formula (3), the specific Bode diagram can be obtained, as shown in Figure 6, in the normal working state, the gain of the transfer function in the low-frequency range is approximately unity gain and the phase angle is close to zero degrees, which does not affect the normal operation of the system. In the high frequency range, it is very close to the function of the low-pass filter. Therefore, the topology structure plays a filtering role under the premise of protecting the system's normal operation and guarantees the operating efficiency of the DC microgrid.

**Figure 6.** Circuit diagram when DC circuit breaker works normally.

#### **4. Analysis of Fault Current Change Rate**

For the parameter design of the topological structure of the reversed ΓSCB, when a fault occurs on the load side, the SCR can force automatic commutation only when the fault current rises to a critical value to achieve the purpose of fault isolation, so the rate of rising of the fault current and the sum current are important parameters that determine the automatic shutdown of the SCR. According to Figure 4b, the fault current *i*fault, the secondary coil of the transformer *L*2, capacitor *C* and the load capacitor *CL* form a loop. The current path of a short-circuit fault in the DC circuit breaker shows that the fault current *i*fault can be expressed by the two capacitor line currents as:

$$\dot{q}\_{\text{fault}} = \frac{\mathbb{C} + \mathbb{C}\_L}{\mathbb{C}} \dot{q}\_{\mathbb{C}} \tag{4}$$

$$i\_{\text{fault}} = \frac{\text{C} + \text{C}\_L}{\text{C}\_L} i\_{\text{CL}} \tag{5}$$

In the initial state of short-circuit fault, *i*fault can indicate:

$$i\_{\text{fault}} = GV\_0 \tag{6}$$

In Formula (6), *Vo* is the output voltage of the load, *G* is the fault conductance. Neglecting the system line voltage drop, according to Formulas (4) and (6):

$$G\_{\rm min} = \frac{\mathcal{C} + \mathcal{C}\_L}{\mathcal{C} \mathcal{R}\_L} \tag{7}$$

In Formula (7), *G*min expresses as the smallest detectable fault conductance.

The rate of rising of the short-circuit fault current determines the detection capability of the DC circuit breaker. The following analysis assumes that the change in fault conductance with time is a linear relationship, and the fault change rate *K* can be expressed as:

$$K = \frac{G}{\Delta t} \tag{8}$$

where Δ*t* is a time interval for the ramp. The fault current in terms of *K* can be expressed as

$$i\_{\text{fault}} = KV\_{\text{o}}t \tag{9}$$

According to Formula (5), we can receive

$$K V\_o t = \frac{\mathcal{C} + \mathcal{C}\_L}{\mathcal{C}\_L} \frac{\mathbf{d} V\_o}{\mathbf{d} t} \tag{10}$$

In the initial state when a fault occurs, *Vo* = *Vs*, from Formulas (4)–(6), we obtain

$$V\_o = V\_s e^{-\frac{K}{2(C+C\_L)}t^2} \tag{11}$$

*Vs* is the source input voltage, from Formulas (9) and (11), the fault current *i*fault and the current through Z-source capacitor are rewritten as

$$\dot{a}\_{\text{fault}} = V\_s K t e^{-\frac{K}{2(C+C\_L)}t^2} \tag{12}$$

$$d\_{\mathbb{C}} = \frac{\mathbb{C}}{\mathbb{C} + \mathbb{C}\_L} V\_{\mathbb{S}} K t e^{-\frac{K}{2(\mathbb{C} + \mathbb{C}\_L)} t^2} \tag{13}$$

By solving Formula (13), the time at which capacitor current becomes maximum can be derived as

$$t\_{\text{max}} = \sqrt{\frac{\mathbb{C} + \mathbb{C}\_L}{K}} \tag{14}$$

Substituting (14) into (13), maximum capacitor current can be obtained as

$$i\_{\mathcal{C}\_{\text{max}}} = V\_s \mathcal{C} \sqrt{\frac{K}{\varepsilon (\mathcal{C} + \mathcal{C}\_L)}} \tag{15}$$

N is the turn of the winding *L*<sup>1</sup> and *L*<sup>2</sup> of the transformer, respectively. The ratio of the induced current between the primary coil and the secondary coil of the two-winding transformer is *iL*1:*iL*<sup>2</sup> = 1:*N*, and the induced current *iL*<sup>2</sup> on the secondary coil equals to capacitor current *ic*, so when a fault occurs, the SCR can be automatically turned off when <sup>1</sup> *<sup>N</sup> iC* ≥ *is*, *is* is the steady-state load current, so it can be obtained from Formula (15):

$$\frac{1}{N}V\_s\mathcal{C}\sqrt{\frac{K}{\varepsilon(\mathcal{C}+\mathcal{C}\_L)}} \ge i\_s = \frac{V\_s}{R\_L} \tag{16}$$

$$K \ge N^2 e \frac{\mathcal{C} + \mathcal{C}\_L}{\mathcal{C}^2 R\_L^2} \tag{17}$$

Therefore, when the change rate of the short-circuit fault conductance satisfies Formula (17), ΓSCB can work normally. Otherwise, the DC circuit breaker will not work normally. When determining the size of the system parameters, it needs to be based on the minimum fault current. It is required to select the appropriate *CL*/*C* ratio, set the minimum fault change rate by changing the size of the capacitor value, and also consider the short-term fault current level of the SCR and the reverse recovery time to ensure the normal operation of the DC circuit breaker

In order to achieve the appropriate minimum fault ramp rate *K*min and to ensure the safe commutation of the SCR in sufficient time, the optimal value of the inductor must be selected, and the inductor current can be obtained:

$$\dot{q}\_{L1} = I\_L + \frac{V\_s}{12(\text{C} + \text{C}\_L)L\_1} \text{Kt}^3 \tag{18}$$

According to Formulas (13) and (18), the current flow SCR can be obtained:

$$i\_{\rm SCR} = i\_{L1} + \frac{V\_s \mathbb{C}}{2\left(\mathbb{C} + \mathbb{C}\_L\right)^2} K^2 t^3 - \frac{V\_s \mathbb{C}}{\mathbb{C} + \mathbb{C}\_L} K t \tag{19}$$

The inductor current should remain constant under fault conditions to minimize the detectable change rate of short-circuit faults. Therefore, the value of the inductance should be large enough so that the influence of the inductor current on the capacitor current is kept to a minimum. At the same time, the current through the SCR will not be affected.

$$L\_1 = \frac{\mathcal{C} + \mathcal{C}\_L}{6K\mathcal{C}}\tag{20}$$

In this paper, *N* = 2, substituting (20) into (17), we obtain

$$L\_1 = \frac{1}{24e} R\_L^2 \mathbb{C} \tag{21}$$

Formula (21) shows the important relationship between the load *RL* and the system parameters, and the result also shows that the two-winding transformer is proportional to the capacitance *C*.

#### **5. Extended the** Γ**SCB Simulation**

In order to verify the effectiveness of the DC microgrid protection design based on the bidirectional DC circuit breaker based on flipped Γ-source in this paper. A simulation model with source voltage *U*DC = 1 kV, the steady-state load current *is* = 0.1 kA, and the short-circuit fault current peak value are 0.65 kA is established in the PSCAD/EMTDC software, and the working status of the DC circuit breaker when a short-circuit fault occurs on the load side is also analyzed. The two-way topology adopts two operating modes of the forward power flow and reverse power flow in the simulation. The mutual inductance value of the two-winding transformer is *M* = 400 μH, and other relevant component parameters are shown in Table 3.

**Table 3.** The parameters of circuit breaker.


The simulation result of the topology of the ΓSCB is shown in Figure 7. When the forward energy flow channel is running, the fault occurs on the load side when the simulation is set for 0.5 s, and the capacitor *C* and the load capacitor *CL* begin to discharge. The fault current rises rapidly, the magnetic flux of the secondary coil *L*<sup>2</sup> begins to increase, and the line current *iL*<sup>2</sup> rises.

Due to the mutual inductance between the transformer windings, the line current of the primary coil *L*<sup>1</sup> continues to rise, forcing the SCR current to cross zero. Due to the symmetrical structure of the diode bridge circuit, there is no resonance effect, and the fault current is cleared after 400 μs. The voltage *VSCR* on both sides of the SCR is stabilized at 1.8 kV, the voltage *Vc* on both sides of the capacitor *C* is stabilized at 0.75 kV, the voltages *VL*<sup>1</sup> and *VL*<sup>2</sup> on both sides of the primary and secondary windings are reduced to zero after a period of sine, and the load-side output voltage *Vo* drops to zero. However, as the simulation time increases, the voltage on both sides of the SCR and capacitor *C* will slowly drop to zero after about 5.5 s.

As a result of the design of the diode bridge circuit, the ΓSCB is a symmetrical structure, so the simulation results under the reverse power flow operation of the bidirectional topology are consistent with the forward power flow operation. In the process of clearing the short-circuit fault current, it can be seen from the analysis of the simulation results that the bidirectional DC circuit breaker is designed to be suitable for the bidirectional operation of energy between different nodes and loads in the DC microgrid. Owing to the characteristics of the circuit structure, there is no need to add a buffer circuit and the ability to clear fault currents in a short time, which verifies the rationality of the topology of the ΓSCB.

**Figure 7.** Simulation results of bidirectional DC circuit breaker based on flipped Γ-source.

The comparison simulation results of ΓSCB under different transformer parameters are shown in Figure 8. The Figure shows the change of the short-circuit fault turn-off time and the fault current peak value of ΓSCB with the capacitor *C* when the mutual inductance value is 400 μH and 600 μH. The circular line and the triangular line indicate the change under the condition of 400 μH, and the straight line and the diamond line indicate the change under the condition of 600 μH. Compared with the 600 μH conditions, the fault turn-off time under the 400 μH condition is short, and the fault current peak value is relatively high. With the continuous increase in the capacitor *C*, the difference between the fault current peak value and the turn-off time under the two values also increases. When the capacitor *C* is 200 μF, their gap is the smallest.

**Figure 8.** Comparison of simulation results under different parameters of ΓSCB.

#### **6. Experimental Validation**

In order to verify the principle of the DC microgrid protection design based on the reversed Γ source bidirectional DC solid-state circuit breaker proposed in this paper, this section builds an experimental platform with a power supply voltage of 48 V, a steady-state load current of 1.2 A. The experimental platform verifies the load-side short-circuit fault detection and breaking process. A two-way experimental circuit is built for the diode bridge structure, and the experimental circuit schematic diagram of the ΓSCB turned over is shown in Figure 9. In the diode bridge structure in Figure 9, *L*<sup>1</sup> and SCR are long-term current-passing branches, RL simulates load resistance, Ro simulates load-side short-circuit fault resistance, short-circuit fault occurs after the air switch *K*sw is closed, capacitor *C* starts to discharge, and the magnetic flux of *L*<sup>2</sup> rises until the SCR Automatic shutdown.

**Figure 9.** Bidirectional DC circuit breaker based on flipped Γ-source test circuit diagram.

Because the voltage level of the experiment platform is relatively low, the currentlimiting module does not need to be added. Because the circuit current rises rapidly after the Ro resistance is connected, the circuit breaker is turned off according to the expected effect. In selecting experimental devices, full consideration should be given to the withstand voltage level and rated current to avoid breakdown and damage of the experimental devices and ensure the experimenters' personal safety. The physical diagram of ΓSCB turned over is shown in Figure 10.

**Figure 10.** Bidirectional DC circuit breaker based on flipped Γ-source physical drawing.

After the system works normally, *K*sw is closed, Ro is connected to the circuit to simulate a short-circuit fault, and the SCR reaches the critical value to force automatic commutation, and the entire experimental operation process ends. Part of the experimental waveforms of the ΓSCB is shown in Figure 11. The experimental waveforms are SCR current waveform, output current waveform, SCR voltage waveform and output voltage waveform, and the time scale is 2 ms/div. It can be seen from the current and overvoltage waveform diagrams that under the condition of the source voltage of 48 V, the normal operating current of the entire DC system is 1.2 A, and the interruption fault current of the entire DC circuit breaker is about 400 μs. The circuit breaker topology designed in this paper reduces the number of SCR used and simplifies the overall structure on the basis of quickly shutting down the fault current. The experiment verifies the effectiveness of the topology of the flip Γ source DC circuit breaker.

**Figure 11.** Part of bidirectional DC circuit breaker test waveform.

#### **7. Conclusions**

This paper proposed a DC microgrid protection design based on the flip Γ source DC circuit breaker, expounds the working principle of the flip Γ source DC circuit breaker topology and the analysis method of the failure rate. Finally, it is verified by simulation and experimental platform, and the following conclusions are obtained:


**Author Contributions:** J.G.: data curation, writing original draft preparation. Z.L.: project administration. J.L.: visualization. H.W.: supervision. Y.L.: software. J.Z.: validation. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by Science and Technology Talents and Natural Science Foundation grant number 2021-NLTS-13-05.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** The study did not report any data.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


### *Article* **Design and Implementation of the Bidirectional DC-DC Converter with Rapid Energy Conversion**

**Bing-Zhang Chen 1, Hsuan Liao 1,\*, Linda Chen <sup>2</sup> and Jiann-Fuh Chen <sup>1</sup>**


**\*** Correspondence: n28064046@gs.ncku.edu.tw

**Abstract:** The bidirectional DC-DC converters are widely used in the energy storage system (ESS) and DC distribution system. The power capacity is limited when the converter is operated with smooth power transfer. In addition, the directions of the inductor current and the capacitor voltage cannot change instantaneously. In this study, a rapid energy conversion technique for smoothing and accelerating the energy transfer under the same specification of the main components in steady state is proposed. Moreover, a bidirectional DC-DC converter with a high conversion ratio is proposed to overcome the commonly low voltage input from renewable energy sources. The operating principles of the proposed converter's step-down and step-up modes are discussed in this study. Furthermore, to achieve rapid energy conversion, digital control is a crucial component in the converter system. A digital signal processor is used as the control platform, and a control strategy is formulated to achieve rapid energy conversion. The bidirectional DC-DC prototype converter with a 24 V battery, a DC bus of 200 V, and an output power of 500 W is constructed to confirm the feasibility of rapid energy conversion. The proposed converter can be operated in CCM, BCM, and DCM conditions. The transfer period can be completed within one switching cycle when the proposed converter is operated in BCM or DCM. The energy is freewheeled before energy conversion when the proposed converter is operated in CCM condition. In the experiment, the minimum transfer period is 6.29 μs on the DCM stage.

**Keywords:** bidirectional DC-DC converter; rapid energy conversion; smooth power transfer

#### **1. Introduction**

In recent years, because of fast economic development, energy demands have increased rapidly, which, in consequence, caused damages to the environment and accelerated global warming during power generation. To achieve sustainable development of society and economy, environmental protection and the usage of energy have become the most important aspects [1–6]. In addition, renewable energy sources such as wind energy and solar energy are regeneratable and cause less environmental pollution when compared with conventional fossil fuel power generation. However, due to the instability in the renewable energy sources, the methods for smoothing the input energy are essential. Therefore, it is getting more common for the renewable energy system (RES) to integrate with the energy storage system (ESS) [7–10]. Figure 1 shows the RES incorporating batteries as the backup power [11]. Bryden et al. illustrated the advantages of the usage of stationary energy storage [11]. The electric vehicle (EV) charging stations can buffer the energy between the electricity grid and EVs, minimizing the maximum power required for grid connection. There are, however, some issues with the connection between the grid and converters, such as the stability of the power flow and the time required for energy transfer. The quality of the power flow and the length of the conversion time for energy transfer are the main aspects being studied in this research.

**Citation:** Chen, B.-Z.; Liao, H.; Chen, L.; Chen, J.-F. Design and Implementation of the Bidirectional DC-DC Converter with Rapid Energy Conversion. *Energies* **2022**, *15*, 898. https://doi.org/10.3390/en15030898

Academic Editors: Alon Kuperman, Ching-Ming Lai and Yitao Liu

Received: 27 December 2021 Accepted: 21 January 2022 Published: 26 January 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

In modern days, uninterruptible power supply (UPS) systems are usually used at the utility grid as the main power source and the batteries are used as a backup power source [12,13]. Thus, for systems interfacing the ESS with the DC bus, the bidirectional DC-DC converters with power flow control have been widely discussed for effective power conversion [14–21]. Several research groups have discussed the possible methods of improving the quality of the power flow by modifying the circuit topology [14–17]. Vuyyuru et al. and Khan et al. have also illustrated different control strategies for improving the power flow quality [18–20]. In this study, we combined a control strategy designed for the proposed topologies of the DC-DC converter with a short conversion period.

The terminal voltages of renewable energy sources are usually low and with timedependent variations. Hence, a bidirectional DC-DC converter with a high conversion ratio is commonly used to interface with the DC bus to provide stable power energy. The converter needs to reduce the load current for a smooth power transfer [21–26], which, in consequence, limits the power capacity during conversion [19,26]. Thus, this paper also analyzes the energy conversion between operating modes and proposes a technique for rapid energy conversion.

A bidirectional DC-DC converter with a short conversion period is proposed in this paper. Two different condition modes are discussed. One is the discontinuous conduction mode (DCM), or boundary conduction mode (BCM), and the other is the continuous conduction mode (CCM). In general, the inductor current decreases to zero within one switching period which allows the completion of the energy conversion in one switching cycle. However, the change of the value of the inductor current is not instantaneous. To prevent damages to components in the converter due to the high voltage spike, the inductor current should be freewheeling in the CCM condition. Therefore, the freewheeling path period needs to be considered as well.

In this paper, Section 2 discusses the operational principle of the proposed DC-DC converter with a high conversion ratio. The operational principles of the step-up mode and step-down mode are discussed. Section 3 describes the proposed control strategy of the transferring state for rapid energy conversion. A bidirectional DC-DC converter circuit is constructed with a battery voltage of 24 V and a 200 V DC bus voltage for the validation of the proposed topology design. The experimental results are presented in Section 4, followed by the conclusions and future works in the final section.

**Figure 1.** A backup battery in interfacing with various power supplies.

#### **2. Operational Principle of Proposed Converter**

The operational principles of the proposed bidirectional DC-DC converter are analyzed and presented in this section. Figure 2 shows the topology of the proposed bidirectional DC-DC converter, which is composed of a battery voltage *Vbat*, a DC bus voltage *Vdc*,*bus*, five power switches *S*1, *S*2, *S*3, *SAux*1, and *SAux*2, two inductors *L*<sup>1</sup> and *L*2, and two capacitors *Cbat* and *Cbus*. Two auxiliary switches are used as the bidirectional switches for the power flow control. The following assumptions are made to simplify the circuit analysis:


There are two operation modes when the proposed converter is analyzed in the CCM condition. The simulated waveforms of the step-up mode are shown in Figure 3 and the waveforms of the step-down mode are shown in Figure 4.

**Figure 2.** The topology of the proposed bidirectional DC-DC converter.

#### *2.1. Step-Up Mode*

#### 2.1.1. Mode I (*t*0–*t*1)

At time *t*0, when the switches *S*<sup>1</sup> and *S*<sup>2</sup> are turned on, the switch *S*<sup>3</sup> is turned off. Figure 5 shows the current flowing paths of this mode. The inductors *L*<sup>1</sup> and *L*<sup>2</sup> are charged by battery voltage *Vbat*. This results in the inductor currents *iL*<sup>1</sup> and *iL*<sup>2</sup> to be linearly increased. The output capacitor *Cbus* provides energy to load *Rload*. The *vL*<sup>1</sup> and *vL*<sup>2</sup> are the voltage across the inductors *L*<sup>1</sup> and *L*2, which can be represented as the Equation (1). During this interval, the rate of change in *iL*<sup>1</sup> and *iL*<sup>2</sup> can be derived from both Equations (2) and (3).

$$
v\_{L1} = v\_{L2} = V\_{\text{bat}} \tag{1}$$

$$
\Delta i\_{L1}{}^I = \frac{|v\_{L1}|}{L\_1}(t\_1 - t\_0) = \frac{V\_{bat}}{L} D\_{dis} T\_s \tag{2}
$$

$$
\Delta i\_{L2}{}^I = \frac{|v\_{L2}|}{L\_2}(t\_1 - t\_0) = \frac{V\_{bat}}{L}D\_{dis}T\_s \tag{3}
$$

**Figure 3.** The waveforms of the step-up mode.

**Figure 4.** The waveforms of the step-down mode.

#### 2.1.2. Mode II (t1–t2)

At time *t*1, when the switch *S*<sup>3</sup> is turned on, the switches *S*<sup>1</sup> and *S*<sup>2</sup> are turned off. The current flowing paths of this mode are shown in Figure 6. The battery voltage *Vbat* and the stored energies in the inductors *L*<sup>1</sup> and *L*<sup>2</sup> begin to charge to the output capacitor *Cbus* and transfer energy to the load *Rload*. The inductor currents *iL*<sup>1</sup> and *iL*<sup>2</sup> are linearly decreased during this period. The voltage across the inductors *vL*<sup>1</sup> and *vL*<sup>2</sup> can be represented as Equation (4). During this interval, the rate of change in *iL*<sup>1</sup> and *iL*<sup>2</sup> can be represented as Equations (5) and (6).

$$v\_{L1} = v\_{L2} = \frac{V\_{bat} - V\_{dc,bus}}{2} \tag{4}$$

$$
\Delta \dot{i}\_{L1}{}^{II} = \frac{|v\_{L1}|}{L\_1}(t\_2 - t\_1) = \frac{V\_{dc,bus} - V\_{bat}}{2L}(1 - D\_{dis})T\_s \tag{5}
$$

$$
\Delta i\_{L2}{}^{II} = \frac{|v\_{L2}|}{L\_2}(t\_2 - t\_1) = \frac{V\_{dc,bus} - V\_{bat}}{2L}(1 - D\_{dis})T\_s \tag{6}
$$

where Δ*iL*<sup>1</sup> *II* is the current ripple of the inductor *L*<sup>1</sup> during mode II, Δ*iL*<sup>2</sup> *II* is the current ripple of the inductor *L*<sup>2</sup> during mode II, and *Ddis* is the duty ratio of step-up mode.

**Figure 5.** The current flow paths of step-up Mode I.

**Figure 6.** The current flow paths of step-up mode II.

#### *2.2. Step-Down Mode*

#### 2.2.1. Mode i (*t*0–*t*1)

At time *t*0, when the switch *S*<sup>3</sup> is turned on, the switches *S*<sup>1</sup> and *S*<sup>2</sup> are turned off. The current flowing paths of mode i are shown in Figure 7. In this mode, the inductors *L*1, *L*2, and the capacitor *Cbat* are charged in series by DC bus voltage *Vdc*,*bus*. Therefore, the inductor currents *iL*1, *iL*<sup>2</sup> are linearly decreased.

**Figure 7.** The current flow paths of step-down mode i.

#### 2.2.2. Mode ii (t1–t2)

At time *t*1, when the switch *S*<sup>3</sup> is turned off, the switches *S*<sup>1</sup> and *S*<sup>2</sup> are turned on. The current flowing paths of mode ii are shown in Figure 8. In this mode, the inductors *L*1, *L*2, and the capacitor *Cbat* release energies to the battery voltage *Vbat*. This results in the inductor currents *iL*<sup>1</sup> and *iL*<sup>2</sup> to be linearly increased.

**Figure 8.** The current flow paths of step-down mode ii.

According to the voltage-second balance principle, the average voltage on inductors *L*<sup>1</sup> and *L*<sup>2</sup> in one switching cycle is zero. This can be expressed as Equations (7) and (8).

$$\frac{1}{T\_s} \int\_0^{T\_s} v\_{L1} dt = 0 \implies \int\_0^{t\_1} v\_{L1} dt + \int\_{t\_1}^{t\_2} v\_{L1} dt = 0 \tag{7}$$

$$\frac{1}{T\_s} \int\_0^{T\_s} v\_{L2} dt = 0 \implies \int\_0^{t\_1} v\_{L2} dt + \int\_{t\_1}^{t\_2} v\_{L2} dt = 0 \tag{8}$$

Based on Equations (1) and (4), the Equations (7) and (8) can be simplified as Equation (9):

$$V\_{\rm bat}D\_{\rm dis}T\_s + \frac{V\_{\rm bat} - V\_{\rm dc,bus}}{2}(1 - D\_{\rm dis})T\_s = 0,\tag{9}$$

The voltage conversion ratio of the step-up mode can be derived as Equation (10). Similarly, the voltage conversion ratio of the step-down mode can use the same approach to derive as Equation (11).

$$\frac{V\_{dc,bus}}{V\_{bat}} = \frac{1 + D\_{dis}}{1 - D\_{dis}} \,\prime \tag{10}$$

$$\frac{V\_{\text{but}}}{V\_{\text{dc,bus}}} = \frac{D\_{\text{ch}}}{2 - D\_{\text{ch}}}.\tag{11}$$

where *Ddis* is the duty ratio of the step-up mode, and *Dch* is the duty ratio of the step-down mode.

#### **3. Control Strategy of Transferring State**

In this section, the transferring states from step-up mode to step-down mode and vice versa are described in detail. The direction of all energy storage components in the circuit must be considered carefully because the direction of the inductor current or capacitor voltage cannot be reversed immediately.

To achieve the power flow control of the bidirectional converter, it is necessary to execute the following steps:


#### *3.1. Transferring State from Step-Up Mode to Step-Down Mode*

For the converters operating in CCM condition, the driving signals of all the power switches during the transferring state are shown in Figure 9, illustrating the procedure of the transferring state, and the timing of the transferring state occurring from mode II of the step-up mode to mode i of the step-down mode. For the converters operating in BCM or DCM conditions, the transfer state occurs when the inductor current reaches zero.

During the transferring stage, the switch *S*<sup>3</sup> is turned on for a switching cycle to provide a path for the freewheeling of the inductor current. The inductor currents *iL*<sup>1</sup> and *iL*<sup>2</sup> are linearly decreased until the inductor currents demagnetize to zero. The original operating mode of the bidirectional switches *SAux*<sup>1</sup> and *SAux*<sup>2</sup> is changed. After time *t*2, the gate driving signals of the main switches *S*1, *S*2, and *S*<sup>3</sup> are restored, and the circuit enters into the step-down mode. This results in the inductors *L*<sup>1</sup> and *L*<sup>2</sup> beginning to store the energy.

#### *3.2. Transferring State from Step-Down Mode to Step-Up Mode*

For converters operating in CCM condition, the gate driving signals of all the power switches during the transferring state are shown in Figure 10, illustrating the procedure of the transferring state and the timing of the transferring state occurring from mode II of the step-up mode to mode i of the step-down mode. For the converters operating in BCM or DCM conditions, the transfer state occurs when the inductor current reaches zero.

During the transferring stage, the switch *S*<sup>3</sup> is turned off and the bidirectional switches *SAux*<sup>1</sup> and *SAux*<sup>2</sup> remain in the original operating mode. The switches *S*<sup>1</sup> and *S*<sup>2</sup> are then turned on for two switching cycles to provide a path for the freewheeling of the inductor current. The inductor currents *iL*<sup>1</sup> and *iL*<sup>2</sup> are linearly increased until the inductor currents demagnetize to zero. The original operating mode of the bidirectional switches *SAux*<sup>1</sup> and *SAux*<sup>2</sup> is changed. After time *t*3, the gate driving signals of the main switches *S*1, *S*2, and *S*<sup>3</sup> are restored, and the circuit enters the step-up mode. This results in the inductors *L*<sup>1</sup> and *L*<sup>2</sup> beginning to store energy.

**Figure 9. The** timing of the transferring state from step-up mode to step-down mode.

**Figure 10.** Timing of the transferring state from step-down mode to step-up mode.

#### *3.3. Flow Chart of the Digital Control System*

In general, the digital control program can be divided into the main program and the interrupt subroutine. The purpose of the main program is to configure system parameters, declare variables, and arrange the subroutines in order. In addition, the interrupt subroutine is not executed until the interrupt event occurs. The interrupt subroutine is used to evaluate events and perform complex calculations.

The flow chart of the main program is shown in Figure 11. The system parameters are first initialized at the beginning of the program and the function blocks of MCU, such as I/O pins of GPIO modules, ADC modules, and pulse width modulation (PWM) modules, are then configured. Finally, the trigger condition of the interrupt register is configured.

**Figure 11.** Flow chart of the main program.

The flow chart of the interrupt subroutine is shown in Figure 12. For the power flow control of the bidirectional converter to work, the following procedures should be made:


**Figure 12.** Flow chart of the interrupt subroutine.

After entering the interrupt service routine, the transfer signal is determined by the DSP. When the transfer signal is detected as 0, the converter operates in the step-up mode. On contrary, when the transfer signal is detected as 1, the converter operates in the stepdown mode. In addition, the feedback circuits detect the values of the battery voltage and the DC bus voltage for voltage regulation. Finally, before leaving the interruption, the flag of interruption is cleared for the next interruption to occur. The block diagram of the control strategy is shown in Figure 13.

**Figure 13.** Block diagram of the control strategy.

#### **4. Experimental Results**

The experimental system consists of a bidirectional DC-DC converter and a DSPbased digital compensator, as shown in Figure 14. The bidirectional DC-DC converter is implemented with a battery voltage of 24 V, and a 200 V DC bus voltage. The related specifications are listed in Tables 1 and 2.

**Figure 14.** Block diagram of the experimental system for bidirectional power flow control.

**Table 1.** Specifications of the experimental system.


**Table 2.** Parameters of the experimental system.


The hardware circuit of the proposed converter is shown in Figure 15, which is composed of synchronous rectification switches and bidirectional switches. The DSP is used to provide synchronous control and power flow control in the bidirectional DC-DC converter.

#### *4.1. Step-Up Mode to Step-Down Mode (CCM Condition)*

The experimental waveforms with 50% load condition are shown in Figure 16. The gate driving signals *vgs*<sup>1</sup> and *vgs*<sup>2</sup> are complementary to the gate driving signal *vgs*3. Moreover, the gate driving signal *vgs*,*Aux*<sup>1</sup> is complementary to the gate driving signal *vgs*,*Aux*2. When the transfer signal changes from 0 to 1, the inductor currents *iL*<sup>1</sup> and *iL*<sup>2</sup> linearly demagnetize to zero, and the direction of the inductor currents immediately reverses to the opposite direction. Thus, the experimental results presented in Figure 16 validate that the proposed control strategy can effectively switch from the step-up mode to the step-down mode.

**Figure 15.** Photography of the experimental system.

**Figure 16.** Waveforms of dynamic performances with 50% load condition. (**a**) *vgs*1, *vgs*2, *vgs*3, *vgs*,*Aux*1, *vgs*,*Aux*2, *iL*1, *iL*2, transfer signal. (**b**) Change from the step-up mode to the step-down mode.

#### *4.2. Step-Down Mode to Step-Up Mode (CCM Condition)*

The experimental waveforms with 50% load condition are shown in Figure 17. The gate driving signals *vgs*<sup>1</sup> and *vgs*<sup>2</sup> are complementary to the gate driving signal *vgs*3. Moreover, the gate driving signal *vgs*,*Aux*<sup>1</sup> is complementary to the gate driving signal *vgs*,*Aux*2. When the transfer signal changes from 1 to 0, the inductor currents *iL*<sup>1</sup> and *iL*<sup>2</sup> linearly demagnetize to zero, and the direction of the inductor currents immediately reverses to the opposite direction. The experimental results presented in Figure 17 validate that the proposed control strategy can effectively switch from the step-down mode to the step-up mode.

**Figure 17.** Waveforms of dynamic performances with 50% load condition. (**a**) *vgs*1, *vgs*2, *vgs*3, *vgs*,*Aux*1, *vgs*,*Aux*2, *iL*1, *iL*2, transfer signal. (**b**) Change from the step-down mode to the step-up mode.

#### *4.3. Step-Up Mode to Step-Down Mode (BCM Condition)*

The experimental waveforms with BCM load conditions are shown in Figure 18. The gate driving signals *vgs*<sup>1</sup> and *vgs*<sup>2</sup> are complementary to the gate driving signal *vgs*3. Moreover, the gate driving signal *vgs*,*Aux*<sup>1</sup> is complementary to the gate driving signal *vgs*,*Aux*2. When the transfer signal changes from 0 to 1, the inductor currents *iL*<sup>1</sup> and

*iL*<sup>2</sup> linearly demagnetize to zero, and the direction of the inductor currents immediately reverses to the opposite direction. The experimental results presented in Figure 18 validate that the proposed control strategy can effectively switch from the step-up mode to the step-down mode within one switching cycle.

**Figure 18.** Experimental results of dynamic performances with BCM load condition. (**a**) *vgs*1, *vgs*2, *vgs*3, *vgs*,*Aux*1, *vgs*,*Aux*2, *iL*1, *iL*2, transfer signal. (**b**) Change from the step-up mode to the step-down mode.

#### *4.4. Step-Up Mode to Step-Down Mode (DCM Condition)*

The experimental waveforms with DCM load conditions are shown in Figure 19. The gate driving signals *vgs*<sup>1</sup> and *vgs*<sup>2</sup> are complementary to the gate driving signal *vgs*3. Moreover, the gate driving signal *vgs*,*Aux*<sup>1</sup> is complementary to the gate driving signal *vgs*,*Aux*2. When the transfer signal changes from 0 to 1, the inductor currents *iL*<sup>1</sup> and *iL*<sup>2</sup> linearly demagnetize to zero and then commutate immediately. The experimental results

in Figure 19 validate that the proposed control strategy can effectively switch from the step-up mode to the step-down mode within one switching cycle.

**Figure 19.** Experimental results of dynamic performances with DCM load condition. (**a**) *vgs*1, *vgs*2, *vgs*3, *vgs*,*Aux*1, *vgs*,*Aux*2, *iL*1, *iL*2, transfer signal. (**b**) Change from the step-up mode to the step-down mode.

When the converter operates in DCM or BCM, because the inductor current decreases to zero within one switching cycle, the energy conversion can be completed in one switching cycle. The controller combines analog and digital methods for the transfer state. On the other hand, when the converter operates in CCM, the path for the freewheeling of the inductor current must be provided to avoid the occurrence of voltage spikes on the power switches. Therefore, the inductor current of the converter in the CCM condition requires longer duration for reaching the steady state. The comparison of the transition times of the converter operating in different modes is shown in Table 3.

**Table 3.** Comparisons of transition time.


#### *4.5. Efficiency under Step-Up Mode*

The efficiency curve of the converter at step-up mode with different load conditions is illustrated in Figure 20. The result shows that the maximum efficiency is 96.37% at 40% load and the full load efficiency is 93.66%.

**Figure 20.** Efficiency curve under step-up mode.

#### *4.6. Efficiency under Step-Down Mode*

The efficiency curve of the converter at step-down mode for different load conditions is illustrated in Figure 21. The result shows that the maximum efficiency is 94.02% at 60% load and the full load efficiency is 93.08%.

**Figure 21.** Efficiency curve under step-down mode.

#### **5. Conclusions**

The DC-DC converters have been widely used for connecting RES and ESS systems due to the need for energy storage for power generation with renewable energy. This paper proposes a bidirectional DC-DC converter with rapid energy conversion as the main circuit architecture for the energy conversion between the DC bus and the battery. The proposed method can improve the time required for energy transfer and provide smooth power flow under the same specification of the main components. In addition, the operational principles and the transferring states are analyzed in this paper.

A prototype converter for a 24 V battery, 200 V DC bus, and 500 W output power is constructed to confirm the feasibility of theoretical analyses. When the converter is operating in the step-up mode, the maximum efficiency of 96.37% is obtained at 40% load. In addition, the maximum efficiency of 94.02% is obtained at 60% load in the step-down

mode. The experimental results presented indicated that the minimum transfer period is about 6.29 μs on the DCM stage. The resulting transition time for the experiment circuit can be completed within one switching cycle on DCM and BCM, and a minimum conversion time of 15.8 μs was obtained for the converter operating on CCM condition when stepup mode changed to step-down mode. Finally, the experimental results validate the effectiveness and precision of the proposed control strategies and rapid energy conversion.

While this study proposed a simplified idea for the feasibility of the theoretical proposal, many concerns can be discussed for future works. This includes constructing a complete system environment to control the converter, deriving a small-signal model of the converter, and improving the digital control design for a better conversion period.

**Author Contributions:** Conceptualization, J.-F.C. and B.-Z.C.; methodology, B.-Z.C.; validation, B.- Z.C. and H.L.; original draft preparation, H.L.; writing—Review and editing, L.C.; supervision, J.-F.C. All authors have read and agreed to the published version of the manuscript.

**Funding:** This study is supported by the Delta Electronics Foundation, and it was financially supported by the Hierarchical Green-Energy Materials (Hi-GEM) Research Center, from The Featured Areas Research Center Program within the framework of the Higher Education Sprout Project by the Ministry of Education (MOE) in Taiwan, and the Ministry of Science and Technology under Project MOST 110-2221-E-006-125, MOST 110-2634-F-006-017.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


### *Article* **Design and Control of Modular Multilevel Converter for Voltage Sag Mitigation**

**Fazal Muhammad 1,\*, Haroon Rasheed 1, Ihsan Ali 2, Roobaea Alroobaea <sup>3</sup> and Ahmed Binmahfoudh <sup>4</sup>**


**Abstract:** Voltage sag in a power system is an unavoidable power quality issue, and it is also an urgent concern of sensitive industrial users. To ensure the power quality demand and economical operation of the power system, voltage sag management has always drawn great attention from researchers around the world. The latest research that realizes the power quality conditioning has used dynamic voltage restorers (DVRs), static VAR compensator (SVCs), adaptive neuro-fuzzy inference systems (ANFISs), and fuzzy logic controllers based on DVR to mitigate voltage sag. These devices, methods, and control strategies that have been recently used for voltage sag mitigation have some limitations, including high cost, increased complexity, and lower performance. This article proposes a novel, efficient, reliable, and cost-effective voltage sag mitigation scheme based on a modular multilevel converter (MMC) that ensures effective power delivery at nominal power under transient voltage conditions. The proposed method, the MMC, compensates for the energy loss caused by voltage sags using its internal energy storage of the submodules, and ensures reliable power delivery to the load distribution system. Furthermore, control strategies are developed for the MMC to control DC voltage, AC voltage, active power, and circulating current. Detailed system mathematical models of controllers are developed in the dual synchronous reference frame (DSRF). Validation of the results of back-to-back MMC for dynamic load distribution system is analyzed which proves the effectiveness of the proposed scheme for voltage sag mitigation.

**Keywords:** dynamic load distribution; voltage sag mitigation (VSM); modular multilevel converter (MMC); circulating current suppression control (CCSC); dual synchronous reference frame (DSRF); proportional resonance controller (PRC); inner current controller (ICC)

#### **1. Introduction**

Voltage sag is one of the major concerns of the modern industry, as it can interrupt sensitive electrical loads and in the worst case cause production problems. According to the official definition of voltage sag, "It is the phenomenon in which the magnitude of voltage is reduced below 10% of nominal RMS value over a time ranging from one half-cycle to one minute" [1]. A voltage sag is defined by IEEE standard 1159–1995 as "A decrease in the RMS voltage from 10% to 90% of nominal value for the duration of 0.5 cycles to 1 min" [2]. Time duration and voltage drop for voltage sag differ from one grid code to another. According to different countries' grid codes and regulations, different limits are allowed for voltage drop and time duration in case of voltage sag events, as shown in Table 1 [3].

**Citation:** Muhammad, F.; Rasheed, H.; Ali, I.; Alroobaea, R.; Binmahfoudh, A. Design and Control of Modular Multilevel Converter for Voltage Sag Mitigation. *Energies* **2022**, *15*, 1681. https://doi.org/10.3390/ en15051681

Academic Editor: Andrea Mariscotti

Received: 8 January 2022 Accepted: 18 February 2022 Published: 24 February 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).


**Table 1.** The voltage drop and time duration allowed differently based on grid codes in different countries.

It is one of the serious power quality challenges that are caused by faults, energization of heavy distribution feeders, and abrupt rise of heavy load. Voltage sag can damage sensitive industrial load equipment and create high power losses in power systems [4]. Different devices, methods, and control strategies were used, i.e., dynamic voltage restorer (DVR) in [5], static VAR compensator (SVC) in [6], ANFIS-based UPQC in [7], and fuzzy logic controller based DVR in [8], to mitigate voltage sag and to address power quality conditioning of load distribution system.

#### *1.1. Voltage Sag Mitigation Based on Various Technologies*

Power system quality has gained a lot of interest over the last decade. There are a variety of devices and control methods used to mitigate the risks associated with power quality in the power system. Different technologies and methods are developed based on power system quality to control the voltage sag of the AC grid system.

#### 1.1.1. Dynamic Voltage Restore (DVR)

Dynamic voltage restorer is the device that ensures optimal power system performance while minimizing the adverse effects of voltage sags, harmonics, unbalanced voltages, and voltage swells. A DVR includes four components, i.e., voltage source inverter, energy storage system, passive filters, and injection transformer (IT), as illustrated in Figure 1. In ref. [9], a DVR is used to inject three-phase voltages in series with grid voltage to compensate for voltage disturbances caused by asymmetrical faults.

**Figure 1.** Dynamic voltage restorer–integrated AC grid system to mitigate voltage sag.

It maintains nominal voltages at the point of connection and compensates voltage sag, harmonics, and voltage unbalance. Nevertheless, some limitations in terms of low-voltage ride-through still exist. Ref. [5] mitigated voltage sag effectively during different types of grid faults using an efficient dynamic voltage restorer (DVR) since its cost is high and it

has high complexity. In ref. [10], a fuzzy logic controller-based dynamic voltage restorer was designed that mitigates voltage sag up to 50%, but the system has the limitation of the frequency fluctuation. The DVR in ref. [11] mitigates voltage sag, voltage unbalance factor to less than one percent, and voltage total harmonic distortion to less than five percent.

#### 1.1.2. Static VAR Compensator (SVC)

In an electrical power system, a static VAR compensator controls parameters such as bus voltage by utilizing static VAR generators or absorbers. It is a flexible AC transmission system device as shown in Figure 2, which has been extensively used in recent years to rectify various power quality problems caused by faults causing voltage sags in the system. In ref. [12], the authors compared static VAR compensators' effectiveness for managing voltage sag events and concluded that SVC contributes the least to transient margin (TM). In ref. [6], the static VAR compensator is used in the AC grid system to enhance power quality and ensure power efficiency, but its performance was lower than that of STATCOM and DVR.

**Figure 2.** Typical configuration of SVC used for mitigation of voltage sag in AC grid system.

1.1.3. Unified Power Quality Conditioner

Similar to a DVR, UPQC has the capability of dealing with power quality issues of the power system, such as harmonics and voltage fluctuations. It is designed to enhance power system performance while minimizing disturbances that adversely affect the performance of critical loads. In addition to regulating the flow of power, UPQCs compensate for harmonics, reactive power, and voltage disturbances. A UPQC contains two voltage source converters linked with a common DC link in a single-phase/three-phase configuration. In Figure 3, the UPQC combines shunt and series controllers into one DC bus. Shunt controllers can produce or absorb reactive power at the common point of coupling.

**Figure 3.** General configuration of UPQC for voltage sag mitigation in AC grid system.

Accordingly, the series controller is connected to the AC grid systems and controls the parameters of the lines, as it is described in detail in [13]. Ref. [14] used UPQC with the fuzzy logic controller to minimize voltage sag and current harmonics. Its results indicate a reduction in a harmonic distortion from 8.93% to 3.34%. According to [15], UPQC is used in a hybrid PV and wind system microgrid to reduce voltage sag and swell by using reactive current injection or absorption. Ref. [7] apply an adaptive neuro-fuzzy interference system (ANFIS) based on a unified power quality conditioner (UPQC) to address voltage sag mitigation and THD reduction since it is costly and quite complex. A power quality controller will additionally compensate for voltage sags, surges, and harmonics, and will limit voltage imbalance in microgrids that are linked to the main grids in the ref. [16]. Table 2 presents a comparison between the various popular technologies used for voltage sag mitigation.


**Table 2.** Comparison of various technologies used for voltage sag mitigation.

The comparison of different voltage sag mitigation technologies includes cost, rating, and various aspects of performance. In conclusion, a DVR provides superior stability to that of SVC in terms of voltage sag, voltage swell, and voltage fluctuation mitigation, while UPQC provides superior protection against poor-quality sources for sensitive loads. The different control methods and devices used to mitigate voltage sag, mentioned in Table 2, has some limitations, i.e., increased complexity, high cost, and lower performance.

Modular multilevel converter (MMC) is an emerging and state-of-the-art power electronic-based technology first introduced in ref. [17]. It has the potential of scalability to meet voltage level requirements, low level of power losses, high reliability, enhanced efficiency, and better harmonic suppression quality [18–20]. It requires the grid side filter to be smaller in size since it has lower harmonics in its output voltage [21]. A modular multilevel converter is an ideal converter with the flexibility of hundreds of output voltage levels for high-voltage three-phase motor drives [22], electric railways, and high-voltage transmission [23]. To address the limitations of the above methods and control strategies mentioned for voltage sag mitigation technologies in Table 2, the MMC can be designed to operate continuously in islanded mode with satisfactory power quality. The voltage sag in the upstream AC grid system caused by asymmetrical faults can be successfully mitigated by using the MMC to ensure satisfactory power delivery to the load distribution system. Using modern MMC technology, this paper presents a novel approach to efficiently mitigate voltage sag sustained in upstream AC grid systems.

#### *1.2. Contributions*

The following contributions are summarized in this paper:


#### *1.3. Organization*

The remainder of this article is organized as follows: Section 2 of this article explains the design principles of MMC, selection of characteristic parameters, component sizing, and all the relevant involved procedures in detail. Section 3 describes the proposed system in detail. Section 4 explains the mathematical modeling of different control systems of the MMC and the control strategies developed for the regulation of circulating current, active and reactive power, and AC and DC voltages of the MMC-rectifier and the MMCinverter. Section 5 of this research article explains, in detail, the simulation results for the voltage sag mitigation strategy of the MMC and gives a comparison of the commonly employed and proposed control strategy for voltage sag mitigation. Section 6 concludes the research article.

#### **2. MMC Component Design Principles**

It requires extensive planning to design a modular multilevel converter, including sizing, and dimensioning of its components. The design procedure of the MMC includes determining the number of submodules (SMs) per arm, DC link voltage, submodule switching devices as per industrial standards and ratings, submodule capacitor's capacitance, and arm inductance.

The flow chart of the MMC design is shown in Figure 4. Initially, it is required to determine the apparent power of MMC, which can be calculated by

$$S = \sqrt{3} V\_{LL} I\_{RMS} \tag{1}$$

**Figure 4.** Component design flow chart of modular multilevel converter.

The DC-link voltage of a modular multilevel converter determines the average voltage of a submodule capacitor. The ratings of semiconductor-based IGBT technology limit the average voltage *vSM* of a submodule of the MMC. The DC-link voltage of the MMC can be determined by multiplying the average voltage of the capacitor with the total number of submodules per arm, taking into account standard current and voltage ratings of semiconductors. The submodule capacitor acts as an energy buffer, and its capacitance dimensioning is necessary for energy storage calculations. The capacitance of the capacitor of SM should be chosen with a low level of voltage ripples. The submodule capacitor must be dimensioned properly so that it allows the maximum arm current of the converter. Arm inductance of the MMC is required to limit the circulating current in the arms, short-circuit current, and to isolate the lower and upper arms of the MMC.

#### *2.1. DC-Link Voltage of the MMC*

According to the ideal relationship between the AC and DC side of the modular multilevel converter, without taking account of internal losses, this equation must hold.

$$P\_{dc} = P\_{ac} \tag{2}$$

$$V\_{dc}I\_{dc} = \sqrt{3}V\_{LL}I\_{Phase}$$

where *IPhase* is

$$I\_{\text{Phasc}} = \frac{2\sqrt{2}}{3m\_a} I\_{dc}$$

$$V\_{dc} = \frac{2\sqrt{2}V\_{LL,rms}}{\sqrt{3}m\_a} \tag{3}$$

*Vdc* can be easily calculated from

$$V\_{dc} = 1.6330 \frac{V\_{LL,rms}}{m\_a} \tag{4}$$

The DC-link voltage of the modular multilevel converter has a direct relation with the RMS value of the AC grid line-to-line voltage and inverse proportion with the modulation index of the converter.

#### *2.2. Submodule Capacitance, CSM*

The capacitor of the submodule (Figure 5) is the main component of the converter which acts as an energy buffer. Its sizing and dimensioning play a vital role while designing the submodule of the converter. The capacitor of the submodule is floating in nature owing to its charging and discharging by converter arm currents. The arm current causes inevitable voltage ripples, which have an inverse relation with the capacitance of the capacitor of the submodule.

**Figure 5.** Submodule of MMC.

Choosing a reasonable capacitance of capacitor for submodule can reduce the magnitude of voltage ripple. Capacitor voltage ripple can also be controlled by eliminating the harmonics in circulating currents. Selection of the arbitrary high value of capacitance of capacitor for submodule may be exorbitant and unnecessary. The value of *CSM* can be calculated as proposed in [24].

$$C\_{SM} = \frac{S}{3Nm\_aV\_c^2\varepsilon\omega} (1 - (\frac{m\cos\theta}{2})^{\frac{3}{2}}) \tag{5}$$

where *S* is the apparent power of converter that is *S* = *<sup>P</sup> cos<sup>θ</sup>* , *N* is the total number of submodules per arm, *ma* is voltage modulation index, *Vc* is time average of submodule capacitor voltage, *ω* is the fundamental frequency, *ε* is ripple voltage of the capacitor (peak to average), and *θ* is the power factor of AC upstream grid side power factor. The above equation offers to derive the capacitance of capacitor *CSM*; only the voltage ripple of capacitor needs consideration in designing and dimensioning of the capacitor of submodule. In ref. [25], 10% voltage ripple of the capacitor of SM is considered suitable. Another approach in reference [25] that calculates the capacitance of the capacitor of SM by using the stored energy *Ec* in all submodules is given by

$$E\_{\mathfrak{c}} = 6N \frac{1}{2} C V\_{\mathfrak{c}}^2 \tag{6}$$

$$E\_c = 3\text{NC} (\frac{V\_{dc}}{N})^2$$

$$E\_c = \frac{3CV\_{dc}^2}{N} \tag{7}$$

To bring some abstraction and to ease in the comparison of different systems, energy– power ratio, E.P., is defined by

$$Energy\,\,power\,\,ratio = \frac{E\_c}{S} \tag{8}$$

from the above equation of *CSM* and energy to power ratio, the capacitance of the capacitor of the submodule can be written in terms of energy to power ratio, total number of submodules, apparent power, and DC-link voltage. Using energy–power ratio, the capacitance of the capacitor can be adjusted as

$$\mathcal{C}\_{arm} = \frac{E P.N.S}{3V\_{dc}^2} \tag{9}$$

$$\mathbb{C}\_{SM} = \mathbb{C}\_{arm}N \tag{10}$$

In ref. [25], 30–40 kJ/MVA energy is needed per converter station HVDC-based MMC, and 60–80 kJ/MVA for back to back converter system.

#### *2.3. Determining of Submodules per Arm of MMC*

The potential advantage of an MMC over a conventional VSC is its adaptability and scalability to different power and voltage levels. While designing the MMC for different power and voltage levels, the number of SMs per arm is one of the basic parameters to be determined. The selection of the number of submodules per arm plays an important role to handle the high voltage and power of the system. DC-link voltage is equally distributed to the "*N*" number of submodules of an arm, and the average voltage *VSM* of a submodule capacitor is *Vdc*/*N*. The mathematical expression for determining the number of submodules is

$$N = \frac{V\_{dc}}{V\_{SM}}\tag{11}$$

To determine the number of submodules also needs a deep consideration of the selection of semiconductor ratings because semiconductors limit the voltage of submodules. Current and voltage ratings are the key parameters of the integrated gate bipolar transistor (IGBT) module. Today, commercially available semiconductor-based IGBT technology has limited kV ratings. The limitation of the kV ratings should be considered while determining the number of submodules. The semiconductor-based high-voltage IGBT module with the modules package available in the market is shown in Table 3.

**Table 3.** Market availability of high-voltage IGBT modules.


In case of failure or damage of any submodule in either arm, redundant submodules should be provided to improve the reliability and stability of the system.

#### *2.4. Arm's Inductance, Larm*

The arm inductor *Larm* of the MMC is also called outdoor air-core reactor, which has multiple functions in a modular multilevel converter. It allows the converter to control reactive power and second harmonic circulating current, and limits the rise of the current in short circuit conditions. The concept in ref. [26] is of an arm inductor forming a resonance frequency *ω<sup>r</sup>* with submodule capacitance

$$
\omega\_r = \sqrt{\frac{N}{L\_{arm}\mathbb{C}\_{SM}}} \cdot \sqrt{\frac{2(n^2 - 1) + m^2 n^2}{8n^2(n^2 - 1)}}\tag{12}
$$

In the above equation, *n*-th harmonic currents can only be limited by arm resistance. Modular multilevel converter should operate above the high value of resonant frequency (RF) which occurs at *m* = 1 and *n* = 2. The harmonic number n is given by the equation *n* = 3*k* ± 1. The above equation can be written as

$$f\_{\mathcal{I}} = \frac{1}{2\pi} \sqrt{\frac{5N}{48L\_{arm}C\_{SM}}}\tag{13}$$

The product of arm inductance and SM capacitance must have minimum value depending on operating frequency *ω<sup>r</sup>* and the number of SM per arm:

$$L\_{arm}C\_{SM} > \frac{5N}{\omega^2} \tag{14}$$

Arm inductance also limits fault current in the case of DC-link short-circuit condition. It is affected by several factors, including the submodule capacitor voltage *Vdc*/*n*, the modulation technique, the switching frequency, and a controller optionally used for suppression of circulating current. Based on the literature, the typical value for arm inductance is 0.15 p.u. of base AC input in [27].

#### **3. Proposed System Description**

A system of back-to-back MMC that ensures the power quality demand of load distribution is shown in Figure 6. It consists of an upstream AC grid system, back-toback MMC, DC grid system, and dynamic load distribution system. In the proposed system, we intend to explore the feasibility of the MMC for voltage sag mitigation and to achieve reliable power for load distribution. The concept and feasibility of the proposed system are to be proven through simulation results studies, showing the functionality of sag mitigation, effective control system, and quick response of the MMC converter. Characteristic parameters, component sizing, and dimensioning are performed as per design participles of MMCs described in Section 2 of this article.

A 10 MW/11 kV dynamic load distribution system is connected with 220 kV AC and 135 kV DC grid systems linked through the MMC-rectifier and the MMC-inverter. The MVA rating of the MMC-rectifier and the MMC-inverter is 220 MVA. The structure of the MMC is illustrated in Figure 7. The structure of the MMC contains six arms, each of them consisting of 60 submodules with a capacitance of 0.0105 p.u. and a series arm reactor with an inductance of 0.0164 p.u. The upstream 220 kV AC grid voltage is stepped down by core type (Y-D) power transformer to 66 kV and fed to the MMC-rectifier, which is linked with 135 kV DC grid system. The (Y-D) power transformers have the capability of limiting the zero-sequence current. Since the MMC will not experience zero-sequence current, the zero-sequence current controller is not necessary. A core type (Y-D) power transformer is used to step down MMC-inverter voltage from 66 kV to 11 kV, feeding the 10 MW dynamic load distribution system. The proposed system is built up to mitigate voltage sag occurring in upstream AC grid systems due to asymmetrical faults using the internal energy stored in the submodules of back-to-back MMC to compensate the voltage sag and to ensure satisfactory power delivery for the operation of dynamic load distribution.

**Figure 6.** A detailed control system model of the MMC-rectifier and the MMC-inverter.

Therefore, to accomplish the principal objective of the proposed scheme, it requires an effective control system for quick response to the system. A dual synchronous reference frame (DSRF)-based current controller is developed for the current control mode of the MMC-rectifier and the MMC-inverter. The outer control loop for the MMC-rectifier consists of AC and DC voltage control, whereas AC voltage and active power control for the MMCinverter. Circulating current suppression controller is designed to control the differential current in between the phases of modular multilevel converter which distorts the arm currents and increases the peak value of arm current causing system power losses.

**Figure 7.** Equivalent circuit of MMC.

During the unbalanced grid conditions, positive-sequence and negative-sequence current components exist which are fully controllable for an MMC. The controller for positive- and negative-sequence current components is illustrated in Figure 6.

Moreover, for efficiency and accuracy in reproducing dynamic behavior, analytical and simulation reasons, and increasing performance for the analysis of converter response, we use the aggregate model of a modular multilevel converter. This MMC model relies on the assumption of perfect capacitor balancing. The equivalent circuit of the MMC for the mathematical modeling of system-level control design is illustrated in Figure 7. In an equivalent circuit of the MMC, *uap*, *ubp*, and *ucp* are the upper arm voltages, whereas *uan*, *ubn*, and *ucn* are lower arm voltages. *iap*, *ibp*, *icp* and *ian*, *ibn*, *icn* are the upper and lower arm currents in three-phase legs of the MMC. The sum of currents in the upper and lower arm of each phase of the MMC yields phase currents *ia*, *ib*, and *ic*.

$$\begin{bmatrix} i\_a & i\_b & i\_c \end{bmatrix}^T = \begin{bmatrix} i\_{ap} & i\_{bp} & i\_{cp} \end{bmatrix}^T + \begin{bmatrix} i\_{an} & i\_{bn} & i\_{cn} \end{bmatrix}^T \tag{15}$$

The differential current in the arm of each phase is *iad*, *ibd*, and *icd* given by

$$[i\_{ad} \quad i\_{bd} \quad i\_{cd}]^T = \frac{[i\_{ap} \quad i\_{bp} \quad i\_{cp}]^T - [i\_{an} \quad i\_{bn} \quad i\_{cn}]^T}{2} \tag{16}$$

Currents in the upper arm and lower arm in terms of their difference are illustrated in the following equations:

$$[\begin{bmatrix} i\_{ap} & i\_{bp} & i\_{cp} \end{bmatrix}^T = \frac{1}{2} [\dot{\imath}\_a \quad \dot{\imath}\_b \quad \dot{\imath}\_c]^T + [\dot{\imath}\_{ad} \quad \dot{\imath}\_{bd} \quad \dot{\imath}\_{cd}]^T \tag{17}$$

$$\begin{bmatrix} i\_{an} & i\_{bn} & i\_{cn} \end{bmatrix}^T = \frac{1}{2} \begin{bmatrix} i\_{a} & i\_{b} & i\_{c} \end{bmatrix}^T - \begin{bmatrix} i\_{ad} & i\_{bd} & i\_{cd} \end{bmatrix}^T \tag{18}$$

Using Kirchhoff's voltage law, the upper and lower arm phase voltages are

$$
\begin{bmatrix} u\_a \\ u\_b \\ u\_c \end{bmatrix} - \begin{bmatrix} u\_0 + \frac{u\_{dc}}{2} - u\_{ap} \\ u\_0 + \frac{u\_{dc}}{2} - u\_{bp} \\ u\_0 + \frac{u\_{dc}}{2} - u\_{cp} \end{bmatrix} = 2L \frac{d}{dt} \begin{bmatrix} i\_{ap} \\ i\_{bp} \\ i\_{cp} \end{bmatrix} + 2R \begin{bmatrix} i\_{ap} \\ i\_{bp} \\ i\_{cp} \end{bmatrix} \tag{19}
$$

$$
\begin{bmatrix} u\_{\tt a} \\ u\_{\tt b} \\ u\_{\tt c} \end{bmatrix} - \begin{bmatrix} u\_0 - \frac{u\_{\tt d}}{2} + u\_{\tt d n} \\ u\_0 - \frac{u\_{\tt d}}{2} + u\_{\tt n} \\ u\_0 - \frac{u\_{\tt d}}{2} + u\_{\tt n} \end{bmatrix} = 2L \frac{d}{dt} \begin{bmatrix} i\_{an} \\ i\_{bn} \\ i\_{cn} \end{bmatrix} + 2R \begin{bmatrix} i\_{an} \\ i\_{bn} \\ i\_{cn} \end{bmatrix} \tag{20}
$$

where *ua*, *ub*, and *uc* are phase voltages of the AC side of the converter, and *udc* is the DC voltage between the two poles. The voltage between two neutral points and ground is *u*0. Adding Equations (19) to (20) gives

$$
\begin{bmatrix} u\_a \\ u\_b \\ u\_c \end{bmatrix} - \begin{bmatrix} u\_0 + \frac{u\_{au} - u\_{dp}}{2} \\ u\_0 + \frac{u\_{bu} - u\_{bp}}{2} \\ u\_0 + \frac{u\_{cn} - u\_{dp}}{2} \end{bmatrix} = L \frac{d}{dt} \begin{bmatrix} i\_a \\ i\_b \\ i\_c \end{bmatrix} + \mathcal{R} \begin{bmatrix} i\_a \\ i\_b \\ i\_c \end{bmatrix} \tag{21}
$$

Let *u <sup>a</sup>*, *u <sup>b</sup>* and *u <sup>c</sup>* are average of the difference between upper and lower voltages

$$
\begin{bmatrix} u'\_a \\ u'\_b \\ u'\_c \end{bmatrix} = \begin{bmatrix} \frac{u\_{an} - u\_{bp}}{2} \\ \frac{u\_{bn} - u\_{bp}}{2} \\ \frac{u\_{cn} - u\_{cp}}{2} \end{bmatrix} \tag{22}
$$

$$
\begin{bmatrix} u\_a \\ u\_b \\ u\_c \end{bmatrix} - \begin{bmatrix} u\_0 + u'\_a \\ u\_0 + u'\_b \\ u\_0 + u'\_c \end{bmatrix} = L \frac{d}{dt} \begin{bmatrix} \dot{i}\_a \\ \dot{i}\_b \\ \dot{i}\_c \end{bmatrix} + R \begin{bmatrix} \dot{i}\_a \\ \dot{i}\_b \\ \dot{i}\_c \end{bmatrix}
$$

Equation (22) mathematically presents the AC side of the MMC. Controllers are designed with this model in the following sections.

#### **4. Control System Modeling**

This section explains, in detail, the inner current loop and outer voltage loops designed for the MMC-rectifier and the MMC-inverter.

#### *4.1. Inner Current Controller under Balanced Grid Conditions*

The inner current controller is the most fundamental part of the MMC control system, as shown in Figure 8. The controller is a built-in SRF with PLL to generate frequency and phase angle information for the measurement of AC voltages. A dq vector control method is used for generating the output voltage required for the inner current controller. Applying Park and Laplace transformation to Equation (22) yields

$$
\begin{bmatrix} u\_d \\ u\_q \end{bmatrix} = \begin{bmatrix} sL+R & -wL \\ wL & sL+R \end{bmatrix} \begin{bmatrix} i\_d \\ i\_q \end{bmatrix} + \begin{bmatrix} u\_d \\ u\_q \end{bmatrix} \tag{23}
$$

Equation (23) shows that the dq components *ud* and *uq* of the AC voltage in rotating dq reference frame. The output voltage of the MMC *ud* and *uq* can be determined by following decoupled feedforward PI controller in ref. [28].

$$\begin{cases} \boldsymbol{u}\_{d} &= -(\boldsymbol{Kp} + \frac{\boldsymbol{Ki}}{s})(\boldsymbol{i}\_{d}^{\mathrm{ref}} - \boldsymbol{i}\_{d}) + \boldsymbol{w}\boldsymbol{L}\boldsymbol{i}\_{q} + \boldsymbol{u}\_{d} \\ \boldsymbol{u}\_{q} &= -(\boldsymbol{Kp} + \frac{\boldsymbol{Ki}}{s})(\boldsymbol{i}\_{q}^{\mathrm{ref}} - \boldsymbol{i}\_{q}) + \boldsymbol{w}\boldsymbol{L}\boldsymbol{i}\_{d} + \boldsymbol{u}\_{q} \end{cases} \tag{24}$$

Substituting Equation (24) into Equation (23)

$$
\begin{aligned}
\begin{bmatrix} s\dot{i}\_d\\ s\dot{i}\_q \end{bmatrix} &= -\frac{1}{L} \begin{bmatrix} R - (Kp + \frac{Ki}{s}) & 0\\ 0 & R - (Kp + \frac{Ki}{s}) \end{bmatrix} \begin{bmatrix} \dot{i}\_d\\ \dot{i}\_q \end{bmatrix} + \\\ & \begin{bmatrix} \dot{i}\_d\\ \dot{i}\_q \end{bmatrix} - \frac{1}{L}(Kp + \frac{Ki}{s}) \begin{bmatrix} \dot{i}\_d^\*\\ \dot{i}\_q^\* \end{bmatrix}
\end{aligned} \tag{25}
$$

It is clear from Equation (25) that *id* and *iq* are decoupled. The inner current control by Equation (24) is illustrated in the block diagram of the inner current control loop.

**Figure 8.** MMC inner current control loop.

#### *4.2. Inner Current Controller under Unbalanced Grid Conditions*

When the grid is under unbalanced conditions, positive-, negative-, and zero-sequence components exist. These component needs to be controlled independently. These components are derived from Equation (22) and can be separated into three independent systems.

$$
\upsilon\_{abc}^{+}(t) - \upsilon\_{abc}^{+}(t) = L \frac{d}{dt} \dot{\iota}\_{abc}^{+} + R \dot{\iota}\_{abc}^{+} \tag{26}
$$

$$
\sigma\_{abc}^-(t) - \upsilon\_{abc}^-(t) = L \frac{d}{dt} i\_{abc}^- + R i\_{abc}^- \tag{27}
$$

$$v^0(t) - (v^0(t) + v\_0(t)) = L\frac{d}{dt}i\_{abc}^0 + Ri\_{abc}^0 \tag{28}$$

Equations (26) and (27) can be expressed in *dq*<sup>+</sup> and *dq*<sup>−</sup> reference frame as

$$\frac{d}{dt}\begin{bmatrix} i\_d^+\\ i\_q^+ \end{bmatrix} = \begin{bmatrix} -\frac{R}{L} & w\\ -w & -\frac{R}{L} \end{bmatrix} \begin{bmatrix} i\_d^+\\ i\_q^+ \end{bmatrix} - \frac{1}{L} \begin{bmatrix} u\_d^+\\ u\_q^+ \end{bmatrix} + \frac{1}{L} \begin{bmatrix} u\_d^+\\ u\_q^+ \end{bmatrix} \tag{29}$$

$$\frac{d}{dt}\begin{bmatrix} \dot{i}\_d^-\\ \dot{i}\_q^- \end{bmatrix} = \begin{bmatrix} -\frac{R}{L} & -w\\ w & -\frac{R}{L} \end{bmatrix} \begin{bmatrix} \dot{i}\_d^-\\ \dot{i}\_q^- \end{bmatrix} - \frac{1}{L} \begin{bmatrix} \boldsymbol{u}\_d^-\\ \boldsymbol{u}\_q^- \end{bmatrix} + \frac{1}{L} \begin{bmatrix} \boldsymbol{u}\_d^-\\ \boldsymbol{u}\_q^- \end{bmatrix} \tag{30}$$

#### *4.3. Positive- and Negative-Sequence Current Control*

Applying Laplace transformation to *dq*<sup>+</sup> and *dq*−, the positive-sequence voltage of the MMC *u*<sup>+</sup> *<sup>d</sup>* and *<sup>u</sup>*<sup>+</sup> *<sup>q</sup>* and negative-sequence voltage *u*<sup>−</sup> *<sup>d</sup>* and *u*<sup>−</sup> *<sup>q</sup>* can be determined by following the proportional integral feedforward controller.

Positive- and negative-sequence current control is provided by using Equations (31) and (32). The outer loop provides *i* + *<sup>d</sup>* & *i* + *<sup>q</sup>* as a command reference for positive-sequence current control, whereas *i* − *<sup>d</sup>* and *i* − *<sup>q</sup>* are set to zero to eliminate negative-sequence current components, as illustrated in Figure 9.

**Figure 9.** Control system.

$$\begin{cases} \begin{array}{rcl} u\_d^+ &=& -(Kp + \frac{Ki}{s})(i\_d^\* - i\_d^+) + wLi\_q^+ + u\_d^+ \\ \dots & \dots & \nu i\_{\nu i\_1 \dots i\_{\nu 1}} \dots & \dots \end{array} \end{cases} \tag{31}$$

$$\begin{array}{rcl} \iota \mu\_{q}^{+} &=& -(Kp + \frac{Ki}{s})(\dot{i}\_{q}^{\*} - \dot{i}\_{q}^{+}) - wLi\_{d}^{+} + \iota \iota\_{q}^{+} \end{array} \tag{4.17}$$

$$\begin{cases} \boldsymbol{\mu\_{d}^{-}} &= -(\boldsymbol{Kp} + \frac{\boldsymbol{K}i}{\boldsymbol{s}})(\dot{\boldsymbol{i}}\_{d}^{\*} - \dot{\boldsymbol{i}}\_{d}^{-}) + \boldsymbol{w}\boldsymbol{Li\_{q}^{-}} + \boldsymbol{\mu\_{d}^{-}} \\ \boldsymbol{\mu\_{q}^{-}} &= -(\boldsymbol{Kp} + \frac{\boldsymbol{K}i}{\boldsymbol{s}})(\dot{\boldsymbol{i}}\_{q}^{\*} - \dot{\boldsymbol{i}}\_{q}^{-}) - \boldsymbol{w}\boldsymbol{Li\_{d}^{-}} + \boldsymbol{\mu\_{q}^{-}} \end{cases} \tag{32}$$

The inner current control from Equations (31) and (32) is illustrated in the block diagram of the DSRF inner current control loop shown in Figure 10.

**Figure 10.** MMC DSRF inner current control loop.

#### *4.4. Circulating Current Suppression Control*

An active power transform is directly responsible for circulating current in the modular multilevel converter. The transformation of energy from the AC side of the modular multilevel converter to its DC side reflects with DC circulating current. There is some low-frequency fluctuation in the submodule voltage because of the floating nature of the submodule's capacitor. This fluctuation appears at the end, at the arm voltage ∑ *v* in the form of dominated second harmonic voltage. Circulating current in between the phases of modular multilevel converter distorts the arm currents, increases the peak value of arm currents, and increases system power losses.

The equivalent circuit of the MMC for circulating current analysis is shown in Figure 11. The dynamics for circulating current can be described by the following equation:

$$V\_{dc} = \sum v + 2i\_{cc}R\_{arm} + 2L\_{arm}\frac{di\_{cc}}{dt} \tag{33}$$

$$V\_{dc} = \upsilon\_{\rm u} + \upsilon\_{\rm L} + 2i\_{\rm cc}R\_{arm} + 2L\_{arm}\frac{di\_{\rm cc}}{dt} \tag{34}$$

The above equation implies that (*vu* + *vL*) are only variables for controlling the circulating current in the arm of MMC. Splitting ∑ *V* into DC-link voltage and circulating current,

$$V\_{dc} = v\_u + v\_L + 2V\_{cc} \tag{35}$$

$$V\_{dc} - 2V\_{cc} = v\_{\nu} + v\_{L}$$

$$V\_{dc} = V\_{dc} - 2V\_{cc} + 2R\_{arm}i\_{cc} + 2L\_{arm}\frac{di\_{cc}}{dt} \tag{36}$$

$$V\_{cc} = i\_{cc}R\_{arm} + L\_{arm}\frac{di\_{cc}}{dt} \tag{37}$$

Time domain dynamics for three-phase MMC is as follows:

$$V\_{\mathfrak{C}\mathfrak{c}\_{\mathfrak{a}}} = i\_{\mathfrak{c}\mathfrak{c}\_{\mathfrak{a}}} R\_{arm} + L\_{arm} \frac{di\_{\mathfrak{c}\mathfrak{c}\_{\mathfrak{a}}}}{dt} \tag{38}$$

$$V\_{cc\_b} = i\_{cc\_b} R\_{arm} + L\_{arm} \frac{di\_{cc\_b}}{dt} \tag{39}$$

$$V\_{cc\_\varepsilon} = i\_{cc\_\varepsilon} R\_{arm} + L\_{arm} \frac{di\_{cc\_\varepsilon}}{dt} \tag{40}$$

**Figure 11.** Equivalent circuit of the MMC for circulating current.

Circulating currents are formalized in Equations (43)–(45) below. Three-phase circulating currents consist of negative-sequence double-line frequency component.

$$i\_{cc\_d} = \frac{1}{3} I\_{dc} + I\_{cc} \cos(2\omega t + \theta) \tag{41}$$

$$i\_{ccB} = \frac{1}{3}I\_{dc} + I\_{cc}\cos\left(2\omega t + \theta - \frac{2\pi}{3}\right) \tag{42}$$

$$\dot{a}\_{cc\_\varepsilon} = \frac{1}{3} I\_{dc} + I\_{cc} \cos(2\omega t + \theta - \frac{4\pi}{3}) \tag{43}$$

$$i\_{\mathcal{cc}\_a} + i\_{\mathcal{cc}\_b} + i\_{\mathcal{cc}\_c} = 0 \tag{44}$$

To control the second harmonic circulating current, DC terms are neglected in the analysis.

$$
\overrightarrow{I}\_{cc} = I\_{cc} \mathfrak{e}^{l(-2\omega t + \theta)} \tag{45}
$$

Control of the second harmonic current can be accomplished by utilizing a vector method. In a dq rotating frame, the current is controlled with 2*ω* due to its negativesequence double-line frequency component. The equations for *Vcca* , *Vccb* , and *Vccc* are transformed into *αβ*-frame by rotating vectors:

$$\overrightarrow{V}\_{cc} = I\_{cc}R\_{arm}e^{J(-2\omega t + \theta)} + I\_{arm}\frac{d(I\_{cc}e^{J(-2\omega t + \theta)})}{dt} \tag{46}$$

Converting *αβ*-frame to dq-frame, we have

$$e^{-j\theta}\overrightarrow{\mathcal{V}}\_{cc} = e^{-}j\theta I\_{cc}R\_{arm}e^{j(-2\omega t + \theta)} + \tag{47}$$

$$\left(e^{-j\theta}L\_{arm}\frac{d\left(I\_{cc}e^{j\left(-2\omega t + \theta\right)}\right)}{dt}\right) \tag{48}$$

$$\overrightarrow{V}\_{cc,dq} = I\_{cc}R\_{arm}e^{j\theta} + L\_{arm}\frac{d(I\_{cc}e^{j\theta})}{dt} - 2j\omega L\_{arm}e^{j\theta} \tag{49}$$

$$
\begin{bmatrix} V\_{\text{cc\\_}-d} \\ V\_{\text{cc\\_}-q} \end{bmatrix} = R\_{arm} \begin{bmatrix} I\_{\text{cc\\_}-d} \\ I\_{\text{cc\\_}-q} \end{bmatrix} + L\_{arm} \frac{d}{dt} \begin{bmatrix} I\_{\text{cc\\_}-d} \\ I\_{\text{cc\\_}-q} \end{bmatrix} + \begin{bmatrix} 2L\_{arm}\omega i\_{\text{cc\\_}} \\ -2L\_{arm}\omega i\_{\text{cc\\_}-p} \end{bmatrix} \tag{50}
$$

Circulating current suppression controller (CCSC) is built up with the help of Equation (52), as shown in Figure 12. The references are set to zero for current to see zero-control voltages at a steady state.

**Figure 12.** Circulating current controller of the converter.

#### *4.5. Description of Outer Loop Controllers of Proposed System*

The principal objective of this research work is to operate back-to-back MMC in islanded mode continuously with satisfactory power quality conditions. In the proposed system, the MMC-rectifier controls the DC voltage and AC voltage, whereas the MMCinverter controls AC voltage and active power.

The inner current controller is designed in a dual synchronous reference frame (DSRF) to allow negative-sequence current injection to upstream AC grid and nonlinear load system under unbalanced fault conditions. DC voltage outer control loop is designed for the MMC-rectifier to control the DC voltage, as shown in Figure 13.

**Figure 13.** Outer and inner control loop for the MMC-rectifier.

This is achieved by creating a *d*-axis reference current for the inner current loop (ICL), comparing reference DC voltage to DC voltage measured, with an error signal *Id* feeding the PI controller. Output reference *I* +*ref <sup>d</sup>* is fed to the inner current control loop.

The control loop can be represented by the following equation:

$$I\_d^{+ref} = (V\_{dc}^{ref} - V\_{dc}) . (K\_p + \frac{K\_i}{s}) \tag{51}$$

The PI controller is tuned at *kp* = 8 and *ki* = 150. Simulation results for DC voltage and power control of the MMC-rectifier is shown in Figure 14. Outer loop AC voltage controller for both the MMC-rectifier and the MMC-inverter are shown in Figures 13 and 15. The main objective of this control is the shaping of AC voltage. It is carried out by creating a *d*-axis reference current for the inner current loop (ICL), comparing reference AC voltage to AC voltage measured, with an error signal iq feeding PI controller. Output reference *I* +*ref <sup>q</sup>* is used for the inner current control loop. The control loop can be represented by the following equation:

$$I\_q^{+ref} = (V\_{nc}^{ref} - V\_{nc})(K\_p + \frac{K\_i}{s})\tag{52}$$

The PI controller is tuned at *kp* = 2 and *ki* = 260. Outer loop active power controller is designed for the MMC-inverter shown in Figure 15. The output reference *I* +*ref <sup>d</sup>* is used for inner current control loop. The control loop can be represented by the following equation:

$$P\_s = \frac{3}{2} [v\_d.i\_d] \tag{53}$$

$$I\_d^{+ref} = \frac{3}{2} (P\_s - P\_{ref}) (K\_p + \frac{K\_i}{s}) \tag{54}$$

**Figure 14.** DC voltage control of the MMC-rectifier.

**Figure 15.** Outer and inner control loop for MMC-inverter.

The PI controller is tuned at *kp* = 0.1193 and *ki* = 55.891 to control the AC side active power of MMC-inverter. Simulation results for active power control of MMC-inverter are shown in Figure 16. This shows that the load is receiving healthy nominal power. Circulating current suppression control is an outer loop control that effectively suppresses the problematic AC component of circulating differential current in modular multilevel converter arms. The controller designed for circulating current suppression control of the MMC-rectifier and the MMC-inverter is the same as that shown in Figure 12. The circulating current controller feeds its reference signals to the inner current loop (ICL). The PI controller is tuned at *kp* = 1 and *ki* = 5. A simulation for the circulating current suppression controller is shown in Figure 17.

**Figure 16.** Active power control of inverter.

**Figure 17.** Circulating current suppression control of the MMC-rectifier.

#### *4.6. Modulation Strategy*

The modulation strategy adopted for the MMC-rectifier and the MMC-inverter is the nearest level modulation technique. This modulation technique allows for the operation of the switching frequency equal to fundamental frequency, reducing the associated conduction losses of the converter effectively. It works by translating the modulating signal into discrete stair waveform, directing the pulse generator how many modules to insert. It is therefore adopted for the system because it is the most common modulation strategy for high-power modular multilevel converter applications. Figure 18 shows the NLM-generated reference signals for MMC. The *y*-axis shows the number of SMs and *x*-axis is the time in seconds.

**Figure 18.** Nearest level modulation signals for MMC.

#### **5. Results of the Simulation and Discussion**

The simulation for the proposed scheme is conducted in a MATLAB-based Simulink system. The simulation environment and system parameters are illustrated in Table 4.


**Table 4.** Parameters of upstream AC, DC grid and modular multilevel converter.

Steady-state operation of both the MMC-rectifier and the MMC-inverter with submodule voltage, arm current, and capacitors voltage is shown in Figure 19.

The voltage of the submodule of MMC is calculated in p.u. where base voltage is set to 2.25 kV, dividing DC voltage by the number of submodules "*N*". Figure 19b,g shows that the arm current flows in one phase of each of the MMC-rectifier and MMC-inverter. Arm current is calculated in p.u. as the base current is set as 1.924 kA. Voltage ripple of submodules is approximately 11% which is composed of both AC and DC quantity. Capacitors of submodules can handle this voltage efficiently. IGBT module package of 4.8 kV is used and derated to 2.25 kV having 11% ripples.

A single-phase voltage sag of up to −60% magnitude, asymmetrical fault, is modeled through the 220 kV source of the system model on the overlaying AC grid side and is the case to be simulated in this research article. A single-phase fault is applied to the simulation model, as shown in Figure 20. When the simulation time is 1.6 s, the effect of the voltage sag is −60% magnitude for 75 ms. AC grid with voltage sag of −60% magnitude feeds the MMC-rectifier.

**Figure 19.** Steady state operation of the MMC-rectifier and the MMC-inverter with SMs voltage, current, and capacitors voltage.

**Figure 20.** Upstream AC grid voltage sag of −60% magnitude.

#### *Voltage Sag Mitigation Strategy*

The main objective of this research is to explore the feasibility and potential of the MMC to mitigate voltage sag that is on the overlaying grid due to asymmetrical fault and to deliver a constant power to load distribution. During severe asymmetrical fault conditions, e.g., single-phase fault, in the overlaying grid, voltage sag is for up to −60% within 75 ms, the MMC should provide support to ensure the constant power flow for load distribution. This can be realized by supplying energy from integrated energy in the submodules of the MMC-rectifier and the MMC-inverter to compensate for the missing energy of overlaying grid due to asymmetrical fault.

#### Energy Storage of Converter

The capacitor of the submodule acts as an energy buffer. Energy stored in the capacitor of the submodule is given by the following equation:

$$E\_{\mathfrak{c}} = \frac{1}{2} C V\_{\mathfrak{c}}^2 \tag{55}$$

The capacitance of the capacitor is 10.48 mF and the submodule's voltage *VSM* is 2.25 kV. The installed energy of a submodule as per the above equation is 26.53 kJ. Energy stored in one arm and phase leg of the converter is 1.591 MJ and 3.18 MJ, respectively. The installed energy of the three-phase MMC converter with 60 submodules is 9.5 MJ. Energy stored in back-to-back MMC is 19 MJ.

During asymmetrical fault in the overlaying grid side, the capacitor of submodules should safely discharge its stored energy to compensate for energy loss made by voltage sag during asymmetrical fault. The modulation index of the MMC is 0.8, and the threshold of capacitor discharging is decided by the steady-state modulation index of MMC. Therefore, the MMC-rectifier allows for DC voltage drop from 1.0 p.u. to 0.8 p.u. without affecting its operation. During the fault conditions, the internal energy storage of the MMC-rectifier and the MMC-inverter should have supplied 10.4% and 12.4% of its installed energy, respectively, as their energy is discharged to approximately 0.896 p.u. and 0.876 p.u. The instantaneous energy of the MMC-rectifier and the MMC-inverter is shown in Figure 21.

Energy stored in the MMC-rectifier is discharged to approximately 0.896 p.u. to compensate for the energy loss caused by voltage sag in the upstream AC grid. The installed energy of the MMC-rectifier is 9.5 MJ. Only 10.4% of installed energy, 0.99 MJ, is discharged to compensate for the effect of the transient voltage sag without affecting the operation of the MMC-rectifier.

**Figure 21.** Instantaneous energy in the MMC-rectifier and the MMC-inverter.

The output DC power of the MMC-rectifier becomes oscillating, as seen in Figure 22, because of the energy interaction between the MMC-rectifier and the MMC-inverter. It can be seen that the DC power peak has reached 1.18 p.u., since it is not harmful, because the DC power equally flows in the upper and lower arms of the both the MMC-rectifier and the MMC-inverter. In this scenario, IGBT bears safely the overcurrent, which is around 25%, that lasts for a one-half cycle.

**Figure 22.** DC bus power.

The power consumed by the MMC-rectifier is shown in Figure 23. This shows that when −60% voltage sag is present, active power drawn is reduced to 0.82 p.u., while only 10.4% of installed energy, 0.99 MJ, is discharged to compensate for the effect of the transient voltage sag without affecting the operation of the MMC-rectifier. The MMC-inverter has compensated for the remaining oscillations after the MMC-rectifier using its integrated energy of the submodules.

**Figure 23.** Power drawn from grid to feed rectifier.

The installed energy of the MMC-inverter is 9.5 MJ. Only 12.4% of installed energy, 1.178 MJ, is discharged for mitigation of the transient voltage sag completely. Figure 24 shows the power delivered from MMC-inverter to the dynamic load distribution. This shows that the load distribution system is healthy and receives AC voltage at a nominal value. These results confirm that the MMC is feasible for an option to mitigate voltage sag and to ensure satisfactory power delivery to the dynamic load distribution. In Figure 25, the output voltage and current of MMC-inverter are normal and healthy with no evidence of voltage sag or energy loss.

**Figure 24.** Power delivered from MMC-inverter to load distribution system.

**Figure 25.** Inverter output voltage and current.

It is concluded from Figures 24 and 25 that transient voltage sag of about −60% for the period of 75 ms, the worst sag scenario, in upstream AC grid side is controlled effectively by back-to-back MMC-rectifier and MMC-inverter.

Table 5 shows the comparison of the commonly employed and proposed control strategies for voltage sag mitigation.

**Table 5.** Comparison of the commonly employed and proposed control strategies for voltage sag mitigation.


#### **6. Conclusions**

In this article, we focus primarily on providing satisfactory power delivery to the load distribution system and meeting nominal power demand under transient voltage sag conditions. A back-to-back modular multilevel converter is designed to mitigate transient voltage sags. Using the internal energy storage of submodules of back-to-back modular multilevel converters, transient voltage sag due to asymmetrical fault with a magnitude of −60% for 75 ms in the upstream AC grid is mitigated effectively. The ability of the improved voltage sag mitigation method is proved through simulation results studies. Furthermore, effective control strategies are developed for inner current control (ICC) in the dual synchronous reference frame (DSRF) to control undesirable components, i.e., double-line positive- and negative-sequence components of the circulating current. The effectiveness and performance of the proposed method are well-validated by the results of the simulation.

*Future Work and Limitations*

Based on this research work, future studies can explore the following aspects:


The limitation of this research scheme is as follows:

• Short circuits in the individual module, as well as flash-over faults between two arms (between the converter arms), cannot be simulated using this model, since the aggregated modeling strategy is used, which considers only the entire converter arm.

**Author Contributions:** Conceptualization, F.M. and H.R.; methodology, F.M.; formal analysis, F.M.; investigation, H.R.; writing—review and editing, I.A., R.A. and A.B.; supervision, H.R., I.A., R.A. and A.B.; funding acquisition, I.A., R.A. and A.B. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by Taif University researchers supporting Project (number TURSP-2020/36), Taif University, Taif, Saudi Arabia.This research work was also partially supported by the faculty of computer science and information technology, University of Malaya, under postgraduate research grant PG035-2016A.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Acknowledgments:** The authors are grateful to the Taif University researchers supporting Project (number TURSP-2020/36), Taif University, Taif, Saudi Arabia.This research work was also partially supported by the faculty of computer science and information technology, University of Malaya, under postgraduate research grant PG035-2016A.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


**Hao Wang 1, Tianmei Shen 2, Nairiga Wu <sup>1</sup> and Fang Tang 1,\***


**Abstract:** An improved low-power hiccup-mode technology for short-circuit protection is proposed in this paper, which can effectively suppress short-circuit currents and greatly minimize the power dissipation of hiccup mode. The circuit can start normally after the short circuit is recovered, and there is no voltage overshoot. At the same time, the proposed pre-charge circuit can effectively suppress the large initial inrush current in the pre-charge stage. These technologies are used in a Peak-Current-Mode-Control (PCMC) Pulse-Width-Modulation (PWM) DC-DC boost converter designed with a 0.35 standard CMOS process. Compared with the conventional structure, the post-simulation results show that the initial inrush current during the start-up phase in the proposed structure is reduced by about 90%. When the output short circuit occurs, the inductor current drops to approximately zero and the power dissipation of the converter is very low at this time. The converter repeatedly detects the state of the output load after a period of about 24 ms. Eventually, the converter will restart after the short circuit is recovered and there is no voltage overshoot.

**Keywords:** hiccup mode; short-circuit protection; sleep mode; low power; inrush current; voltage overshoot

#### **1. Introduction**

DC-DC converters are widely used in various electronic systems because of their high conversion efficiency, low power dissipation, large drive capability, and so on [1,2]. The trend of electronic systems developing towards high reliability and low power puts forward higher requirements for power supply systems. Nowadays, the reliable design of converters faces many challenges. The large initial current [3] and the voltage overshoot [4] of the DC-DC boost converter during the start-up phase will have a negative impact on the subsequent circuit. At the same time, both the large current caused by the output short circuit and the voltage overshoot caused by the short-circuit recovery are also important factors that cannot be ignored regarding the system failure and large power dissipation [5]. Therefore, how to reduce inrush current and voltage overshoot is important to converters. Meanwhile, the short-circuit protection technology of the converter is also one of the recent research hot spots.

There have been many studies on how to reduce the inrush current during the startup phase of the converter. Aiming at the energy transfer characteristics of the boost converter, there was a soft-start structure in [6], which reduces the inrush current to a certain extent, but in the stage of VOUT < VCC, the inrush current still exists. In [7], they proposed a two-stage circuit startup structure, which further reduces the inrush current. Some other methods are also used to reduce the initial inrush current. For example, in the start-up phase, an adaptive resistor is connected in series with the load capacitor to suppress the charging current at the load, thereby limiting the inductor current [8], but this

**Citation:** Wang, H.; Shen, T.; Wu, N.; Tang, F. A Low-Power Hiccup-Mode Short-Circuit Protection Technique for DC-DC Boost Converter. *Electronics* **2022**, *11*, 870. https:// doi.org/10.3390/electronics11060870

Academic Editor: Carlos Andrés García-Vázquez

Received: 25 January 2022 Accepted: 3 March 2022 Published: 10 March 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

method requires the design of a complex control circuit to control the resistance. There are some other methods for reducing the inrush current, but there are few methods that can effectively suppress the initial inrush current of the inductor without adding additional pins and while being easy to implement.

There are also many studies on short-circuit protection technology. The over-current limiting technology proposed by studies [9,10] have certain protective effects on the system. However, the output current during the short circuit is relatively large, which leads to high power dissipation. The methods proposed in [11] can maintain a low output current, but it ignores the voltage overshoot caused by short-circuit recovery. In addition, in [12,13], they proposed an improved short-circuit protection technology based on hiccup mode, which effectively reduces the voltage overshoot after short-circuit recovery, but the power dissipation of converters during short circuit is still a problem. In [14,15], although the power dissipation during short circuit is reduced by sleep time, the output current is still large during the detection of whether the output returns to normal.

The pre-charge circuit proposed in this paper can suppress the initial inrush current well in the circuit startup stage. At the same time, a short-circuit protection technique based on hiccup mode can reduce the inductor current to nearly zero during the short-circuit phase. The converter only consumes a small amount of current in the process of detecting whether the short circuit is recovered, which greatly reduces the power dissipation during the short-circuit period. In addition, the circuit can restart normally after the short circuit is recovered, and there is no voltage overshoot. In Section 2, the causes of both initial inrush current and voltage overshoot are briefly introduced, and the working principle of the conventional short-circuit protection technology based on hiccup mode is introduced at the same time. In Section 3, the pre-charge circuit is given, and the working principle of the proposed hiccup mode is analyzed. The simulation results are given in Section 4. Finally, the conclusion is given in Section 5.

#### **2. Analysis of Inrush Current and Overshoot and Introducing the Conventional Hiccup-Mode Technique**

The conventional structure of Peak-Current-Mode-Control (PCMC) Pulse-Width-Modulation (PWM) boost converter is shown in Figure 1a. Energy is transformed from supply to output by charging and discharging the inductor L. The error amplifier EA amplifies the difference between the output feedback voltage VFB and the reference voltage Vref, and the output result is compared with the slope-compensated current signal to obtain the clock signal, which is driven by logic to control the on and off of the power transistors MN and MP. In the soft-start phase of the converter, the linearly increasing VSS replaces Vref to guide VOUT to increase slowly, which is a popular way to reduce the output voltage overshoot.

#### *2.1. Principle of Inrush Current and Output Voltage Overshoot*

The large initial inrush current has always been a problem for boost converters, and this phenomenon has its inherent reasons. At the beginning of the converter power up, VCC > VOUT, as shown in Figure 1b, the converter operates in the TON phase, and the slope of iL can be expressed as follows:

$$\mathbf{K}\_{\rm ON} = \frac{\mathbf{V}\_{\rm CC}}{\mathbf{L}} \tag{1}$$

In the TOFF phase, as shown in Figure 1c, it can be expressed as follows:

$$\mathbf{K}\_{\rm OFF} = \frac{\mathbf{V}\_{\rm CC} - \mathbf{V}\_{\rm OUT}}{\mathbf{L}} \tag{2}$$

This means that the inductor will always be charged. In other words, the inductor current iL will rise continuously, and the result is a large initial current, as shown in Figure 1d. In order to solve this problem, pre-charge has been proposed, and it has a good effect in reducing inrush current. In the pre-charge phase, the oscillator of the converter does not operate, and the on and off of the power transistors are controlled by the precharge. At this time, the pre-charge provides a low-level signal to control MN off and MP on. The conventional pre-charge method keeps MN off and MP on to allow VOUT to be charged until it is greater than VCC. The converter always operates in the TOFF phase and the function of MP is equivalent to that of a resistor. This does reduce the inrush current, but iL still maintains an upward trend during the process, and the inrush current still exists, as shown in Figure 1e.

**Figure 1.** (**a**) The conventional structure of the PCMC PWM boost converter. (**b**) The TON phase (MN is on). (**c**) The TOFF phase (MN is off). (**d**) The generation process of inrush current. (**e**) Inrush current of the conventional pre-charging.

Output voltage overshoot is also a problem during short-circuit recovery, especially. When the circuit is short-circuited, the output current becomes very large, and a large amount of energy is stored in the inductor. When the short circuit is recovered, the energy in the inductor is transferred to the load in the form of current, which results in a large output voltage overshoot inevitably. The inductance value, load capacitance and shortcircuit current all affect the magnitude of the overshoot voltage.

#### *2.2. The Conventional Hiccup-Mode Short-Circuit Protection Technique*

In the normal operation of the converter, a mechanism is required to protect the circuit when the circuit is short-circuited, such as shutting down the converter and restarting the converter after the short circuit is recovered. Hiccup mode is a commonly used short-circuit protection technique.

The conventional mode is shown in Figure 2. Vref1, Vref2 and IREF are generated by the reference circuit. C1 is the charging capacitor used to generate a linearly increasing soft-start voltage VSS. Transistor MN1 is used as a discharge switch to discharge capacitor C1 to restart soft-start. When the converter is short-circuited, the feedback voltage VFB drops sharply. When it is lower than the reference voltage Vref1, the comparator outputs the identification voltage to allow the hiccup-mode controller to operate. The controller generates a pulse to briefly turn on MN1 to discharge C1. Due to the existence of the reference current IREF and the shutdown of MN1, VSS rises slowly from zero again in an attempt to restart the circuit. When the short circuit is not recovered, this process will be repeated, so it is also called hiccup mode. Some methods start hiccup mode by detecting the fall of VFB or VEA, as is shown in Figure 2a,b, respectively.

However, the power dissipation of hiccup mode is a problem that cannot be ignored. When the hiccup-mode controller tries to detect whether the short circuit is recovered, it needs to open the circuit. In this process, the controller attempts to restart the circuit. Although there is a peak current limit, the current at this time is still very large, as is shown in Figure 2c. At the same time, as previously analyzed, a larger current is also the main

cause of voltage overshoot during short-circuit recovery. Therefore, how to reduce the current in hiccup mode has great significance.

**Figure 2.** The conventional hiccup mode (**a**) The hiccup mode is activated by VFB. (**b**) The hiccup mode is activated by VEA. (**c**) The waveform during short-circuit recovery in the conventional hiccup mode with current limiting.

#### **3. Proposed Boost DC-DC Converter with Hiccup-Mode Short-Circuit Protection Technique**

The top level of the proposed boost converter is shown in Figure 3a. Compared with Figure 1a, it adds hiccup-mode short-circuit protection technique in the start-up module. The converter is composed of a power stage and a feedback control system. The power stage consists of a main PMOS transistor MP and a synchronous rectification NMOS transistor MN. In addition, an inductor L and a capacitor C form a filter network. Particularly, VINT is the supply voltage of the internal module, such as EA (error amplifier), CS (current sensing), oscillator and so on.

(**a**)

**Figure 3.** (**a**) Top level of the proposed boost DC-DC converter. (**b**) The proposed start-up circuit with hiccup mode.

The power-on phase of the converter can be divided into three stages. Stage 1: when VOUT < VCC, PG is low and VINT = VCC. Pre-charge module starts to operate and provides a stable charging current for the load capacitor, and VOUT increases. Stage 2: when VCC < VOUT <5V (the output of the converter during normal operation is 5 V), PG is high and VINT = VOUT. Pre-charge module closes and soft-start module starts to operate. Linearly increasing voltage VSS produced by soft-start module is used to avoid overshoot of output voltage. Meanwhile, the bandgap starts to operate and the oscillator begins providing the converter with a clock frequency. Stage 3: VOUT = VINT = 5 V, the difference between the feedback voltage VFB and the reference voltage Vref is amplified by the error amplifier, and the result VEA is compared with the current sensing signal Vsense, and finally, a control signal for controlling the power transistors on and off is obtained.

The slope compensation signal is added in Figure 3a to avoid sub-harmonic oscillation, which is well-known when the duty cycle is larger than 0.5. The start-up circuit integrates the short-circuit protection technique. When the converter is short-circuited, VOUT decreases sharply, PG becomes low, the the converter enters hiccup mode to implement short-circuit protection and can restart the converter after short-circuit recovery.

#### *3.1. Proposed Start-Up Circuit with Hiccup-Mode Circuit-Short Protection Technique*

The proposed start-up circuit is shown in Figure 3b. The start-up circuit consists of power-sel module, pre-charge module, a comparator, a 1:16 divider, a charge capacitor C1, a discharge NMOS MN1 and some other logic gates. The power-sel module realizes the function of selecting the internal power supply voltage VINT and giving the identification signal PG. The details are as follows: when VOUT < VCC, VINT = VCC and PG = 0; when VOUT > VCC, VINT = VOUT and PG = 1. When the converter is powered on, VOUT < VCC, so PG is low and VINT is equal to VCC, respectively. The pre-charge module starts to operate and provides a stable charge current for the load capacitor by controlling GP. This stable charge current avoids larger initial inrush current in the pre-charge phase. Meanwhile, the comparator is enabled and CLK1 is low, because VSS is smaller than Vref2 (Vref2 is generated by the reference circuit to determine the peak of VSS in hiccup mode). As the load capacitor is charged, VOUT increases linearly. When VOUT > VCC, PG is high and VINT is equal to VOUT. At this time, both the comparator and pre-charge module are off, then CLK1 is low and GP is controlled by logic controller, respectively. There is a logic circuit named one-shot circuit, whose function is that MN1 will open for a short time to discharge C1 while PG changes from low to high. Then, VSS increases linearly, and the converter operates in soft-start state normally. VFB increases by following VSS until that VFB = Vref, as shown in Figure 3a. Finally, VOUT keeps stable and VSS = VOUT.

When the output is shorted, VOUT falls quickly and PG becomes low. Meanwhile, the pre-charge module operates to avoid large load current. CLK1 is high and C1 discharged, because VSS is larger than Vref2. In order to ensure that the capacitor can fully discharge, enough delay time is designed. Although pre-charge operates, VOUT remains low because of short circuit. So, PG remains low and the comparator keeps operating. VSS increases until it is equal to Vref2, then CLK1 becomes high and C1 discharges again. If the short circuit persists, this process is repeated. The result is that CLK1 becomes a clock signal and the converter waits for staring-up again, and the converter operates in hiccup mode. Now the load current is also large, and if short circuit lasts for a long period of time, power dissipation is high. In order to minimize power dissipation, a 1:16 divider is designed to make sure that the converter operates in sleep mode for most of the time when output is shorted. When SSA (Sleep-Switch Auto, enables signal for entering sleep mode) is low, the pre-charge module stops operating and makes GP high to ensure PMOS power transistor closes. At this time, load current approaches zero. The corresponding waveform is shown in Figure 4. We can know from the figure that IOUT drops to zero when the output is short-circuited. This achieves short-circuit protection. The converter does not restart until both short-circuit recovery is established and SSA is high. When VOUT > VCC, PG is high, VSS drops to zero and re-increases to ensure that the converter can soft-start smoothly.

The restart process is the same as the power-on start-up process, and VOUT can rise to the normal voltage.

**Figure 4.** The corresponding waveform of the start-up circuit.

#### *3.2. The Schematic of Proposed Pre-Charge*

The proposed pre-charge circuit is shown in Figure 5. The circuit in the dotted box belongs to the external circuit and MP is PMOS power transistor.

**Figure 5.** The proposed pre-charge circuit.

When PG is low, transmission gate TG1 is on and TG2 is off. At this time, GP is controlled by pre-charge module instead of logic. The operational amplifier operates properly to stabilize GP, and the virtual short of the op amp makes VA = Vref3, so Iref1 can be expressed as:

$$\mathbf{I}\_{\text{refl}} = \frac{\mathbf{V}\_{\text{A}}}{\mathbf{R}\_2} = \frac{\mathbf{V}\_{\text{refl}3}}{\mathbf{R}\_2} \tag{3}$$

At first, VOUT is small and feedback does not work. At this time, both MP and MP1 work in the saturation region. They form a current mirror and iL is as follows:

$$\mathbf{i}\_{\rm L} = \mathbf{I}\_{\rm ref1} \frac{(\mathbf{W}/\mathbf{L})\_{\rm MP}}{(\mathbf{W}/\mathbf{L})\_{\rm MP1}} \tag{4}$$

W represents the channel width of MOS and L represents the effective channel length of MOS, respectively. Then, VOUT increases and MP works in linear region. In order to ensure that the current is as stable as possible, the feedback path is designed. When VOUT increases, I1 increases and VC increases, and the result is that VB increases as VOUT increases. Iref1 declines and VA declines, then GP declines to make sure iL is stable. Finally, the circuit can provide the load capacitor with a stable current. There is only a small drop in current when VOUT is close to VCC. When SSA is low, GP is high and MP is off. Meanwhile, the converter works in the sleep mode and output current falls to zero. In particular, when PG is high, transmission gate TG1 is off and TG2 is on. At this time, GP is controlled by logic instead of the pre-charge module.

#### **4. Simulation Results**

The proposed hiccup-mode short-circuit protection technique is designed with the 0.35 standard CMOS process. The layout of the proposed boost converter is shown in Figure 6, and the die size is about 2 × 1.6 mm2. The external inductance is 4.7 uH and the filter capacitor is 10 uF during the simulation. The converter output voltage is 5 V, and the input voltage range is 2 V to 3.5 V. The total feedback resistance is 100 kΩ, and the built-in reference is set to 0.5 V.

**Figure 6.** Layout of the proposed boost converter.

Figure 7 presents initial inrush current of both the conventional pre-charge and the proposed pre-charge. It can be seen from Figure 7 that the conventional pre-charge has a peak current of 2 A due to the inductance being continuously charged, while the proposed pre-charge has a peak current of only about 200 mA. Under the same conditions, thanks to the controllable gate voltage of the power transistor, the proposed pre-charge circuit can effectively suppress the initial inrush current, which is reduced by 90%.

Figure 8 presents the simulation results of proposed hiccup-mode short-circuit protection technique. The results of Figure 8a show that when short circuit occurs, VSS drops to 0 and repeatedly works in the form of a triangular wave, and is compared with a reference voltage to generate a clock CLK1 with a frequency of about 650 Hz. During the short-circuit period, the converter has a sleep period of about 21 ms, named sleep mode. At this time, the N and P power transistors are in the off state. After the sleep mode, there is about 3 ms to turn on the pre-charge module to detect whether the short circuit is recovered, named detection mode. When short-circuit recovery occurs in detection mode, the converter restarts directly. In particular, if the short-circuit recovery occurs during sleep mode, the converter will restart at the beginning of the detection mode. Figure 8b presents the curve of VOUT and inductor current iL during short circuit. The working frequency of the converter is 1.2 MHz during normal operation, and the working frequency is only 650 Hz during the short-circuit period. At the same time, the inductor current is close to 0, which is only 200 mA in the detection mode, which is also far smaller than the inductor current during normal operation. Therefore, the power dissipation during the short circuit is very low. Meanwhile, when the short circuit is recovered, the converter restarts normally and there is no voltage overshoot. This is because the inductor current is very small before restarting, and there is almost no stored energy in the inductor, so there is no voltage overshoot. In fact, the restart process of the converter is similar to the process of power-on startup.

**Figure 7.** Initial inrush current of the conventional pre-charge and the proposed pre-charge.

**Figure 8.** Simulation results of the proposed hiccup-mode short-circuit protection technique. (**a**) The waveform of VSS, CLK1, SSA and GP. (**b**) The waveform of VOUT and inductor current.

Figure 8 shows the corresponding simulation results when the short-circuit recovery occurs during sleep mode, while Figure 9 shows the relevant simulation results when the short-circuit recovery occurs during detection mode. It can be seen from Figure 9 that when the converter is in the detection mode, once the short circuit recovers, the circuit can be restarted immediately. The inductor current at this time charges the load through a continuous current of about 200 mA. Whenever the short circuit recovers, there is no voltage overshoot when the circuit restarts. This is because VSS will decrease to 0 immediately before the restart, which ensures the soft start works normally and VOUT can always rise slowly.

**Figure 9.** Simulation results in another case of the proposed hiccup-mode short-circuit protection technique. (**a**) The waveform of VSS, CLK1, SSA and GP. (**b**) The waveform of VOUT and inductor current.

Table 1 summaries the performance of the proposed boost converter. The effective power during the short-circuit period is 0, so the power consumed by the converter can be expressed as:

$$P\_{\rm diss} = V\_{\rm in} \mathbf{I}\_{\rm in} \tag{5}$$

where Vin is equal to 2.5 V and VOUT is equal to 5 V. When the converter is in detection mode, Iin is approximately equal to 200 mA. This is approximately equal to the inductor current, and the current consumed by the internal module is much less than 200 mA, which is almost negligible when calculating the power dissipation. The power dissipation at this time is as follows:

$$P\_{\text{diss}(\text{detection})} \approx V\_{\text{in}} \text{I}\_{\text{in}} = 2.5 \text{ V} \times 200 \text{ mA} = 500 \text{ mW} \tag{6}$$


**Table 1.** Performance of the proposed boost converter.

When the converter is in sleep mode, the converter has only a few modules that consume current, Iin is approximately equal to 280 uA, and the power dissipation at this time is as follows:

$$P\_{\rm diss}(\text{sleep} - \text{mode}) \approx \text{V}\_{\rm in} \text{I}\_{\rm in} = 2.5 \text{ V} \times 280 \text{ uA} \, = 0.7 \text{ mW} \tag{7}$$

The time ratio between sleep mode and detection mode is 7:1, so the average power dissipation during short circuit is as follows:

$$P\_{\rm diss(short-circuit)} \approx P\_{\rm diss(detection)} / 8 = 500 \text{ mW/} 8 = 62.5 \text{ mW} \tag{8}$$

It can be seen that the short-circuit power dissipation is very low.

Table 2 gives the comparison of the proposed converter with state-of-the-art converters. The inrush current of [8] is greater than that of its normal current, while inrush current of this work is only 40% of normal current. When the converter is short-circuited, other works reduce the short-circuit current to a reasonable range. Among them, ref. [12] reduces it to about 55% of the normal current, while this work reduces it to 40% of the normal current. This greatly reduces the short-circuit power dissipation. At the same time, the working frequency of the proposed converter during short circuit is only 0.55% of the normal frequency, which also reduces the short-circuit power dissipation.

**Table 2.** Comparison of the proposed converter with other state-of-the-art converters.


N/A: Not mentioned.

#### **5. Conclusions**

In this paper, a low-power hiccup-mode short-circuit protection technique with overshoot and inrush current suppression for a DC-DC boost converter is analyzed and its process is verified. Compared with the conventional pre-charge circuit, the proposed precharge circuit greatly minimizes the initial inrush current, and inrush current is reduced by about 90%. This current is also smaller than the inductor current during normal operation. When the circuit is short-circuited, the converter operates with very low power dissipation, it can restart normally after the short circuit is recovered, and there is no voltage overshoot.

**Author Contributions:** Formal analysis, H.W.; Funding acquisition, F.T.; Investigation, N.W.; Methodology, H.W.; Software, H.W.; Supervision, T.S.; Visualization, T.S.; Writing—review & editing, H.W. All authors have read and agreed to the published version of the manuscript.

**Funding:** This work was sponsored by Natural Science Foundation of Chongqing, China, No. cstc2019jcyj-zdxmX0014.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


### *Article* **Real-Time Fault Location Using the Retardation Method**

**Moneer Nabwani 1,2, Michael Suleymanov 1, Yosef Pinhasi <sup>1</sup> and Asher Yahalom 1,3,\***


**Abstract:** A new method for short-circuit fault location is proposed. The method is based on instantaneous signal measurement and its first and second derivatives, which are the novel elements of the current approach. The derivatives allow associating a precise time stamp to the occurrence of the fault. Due to retardation phenomena, the difference between the times in which a signal is registered in two detectors can be used to locate the fault. We offer several mathematical models to describe the fault. Although a description of faults in terms of a lumped circuit is useful for elucidating the methods for detecting the fault, this description will not suffice to describe the fault signal propagation; hence, a distributed models is needed, which is given in terms of the telegraph equations. Those equations were used to derive a transmission line transfer function, and an exact analytical description of the fault signal propagating in the transmission line was obtained. The analytical solution was verified both by numerical simulations and experimentally.

**Keywords:** fault location; real-time

### **1. Introduction**

One of the most important results of special relativity is the fact that no signal can travel faster than the speed of light in a vacuum *c* [1]. The same is true for a signal generated from a fault occurring in a power transmission line such as a short or a disconnection. As the signal due to the fault reaches detectors along the line at different times (due to a finite propagation speed), one can use the differences in the time of arrival to locate the fault along the line. This location technique is passive in the sense that one does not need to inject any signal to the power line in order to locate the fault; rather, the fault itself is the source of the signal. Another advantage is that the detection and location are performed in real-time. Still, several issues are raised regarding the proposed technique:


We try to answer those questions in the current paper. The discussion was limited to low-voltage transmission lines, while the discussion of high-voltage transmission lines will be the subject of a future paper.

Power transmission lines have a broad range of faults. These fault classifications appeared in various previous articles [2–9]. There are several approaches to fault location algorithms, including various approaches regarding measurements and data processing and their proposed applications. The bridge circuit method [10] employs an adjustable

**Citation:** Nabwani, M.; Suleymanov, M.; Pinhasi, Y.; Yahalom, A. Real-Time Fault Location Using the Retardation Method. *Electronics* **2022**, *11*, 980. https://doi.org/10.3390/ electronics11070980

Academic Editor: Ahmed Abu-Siada

Received: 27 December 2021 Accepted: 11 March 2022 Published: 22 March 2022

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**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

impedance to calculate the location of the fault. Mustari et al. [11] employed a neural network approach. The method of de Morais Pereira and Zanetta [12] was based on steadystate measured phasors in local terminals. M. N. Alam et al. [13] presented a method based on surface electromagnetic waves propagating along a transmission line (see also [14]). In M. Aldeen and F. Crusca's study [15], the faults were modeled as unknown inputs, decoupled from the state and output measurements through coordinate transformations, and then estimated via the use of the observer theory. The article by Qais Alsafasfeh et al. [16] presented a method that integrates the symmetrical components technique with principal component analysis (PCA) for fault classification and detection. In another research work [17], Petri nets were used to obtain the modeling and location detection of faults in power systems. Another widely used method is that of wavelet transform analysis [18–21]. We compared the accuracy of the current method to the accuracy of previous work in the concluding section.

The plan of the paper is as follows: First, we present the basic idea of the method. Then, we provide a description of the fault in terms of a lumped circuit, which is useful for elucidating the methods for detecting the fault; here, we shall demonstrate the ability to determine the signal arrival time using derivatives. This description will not suffice, however, to describe the fault signal propagation; hence, a distributed model is needed, which is given in terms of the telegraph equations [22–25]. After introducing the main formalism and the telegraph equations of the distributed system, we give a specific example of a two-wire power line. We present several models to describe the development of a short and the signal generated in a possible detector due to that short. These include exponential, Gaussian, and step function forms. For the step function model, an inverse Laplace transform allowed us to determine the time-dependent signal at the sensor position analytically. At this stage, we compared the analytical and numerical solutions. Next, the experimental setup is described. We show the high level of conformity of the theoretical and experimental measurements using the appropriate data processing. Finally, we determined the system accuracy and compared it with previous methods.

#### **2. Methodology: Fault Detection by Retardation**

Consider a fault of unknown location that causes a signal to propagate to both sided of the transmission line (see Figure 1). The signal is registered by a detector, which determines its time of arrival, *t*<sup>1</sup> for Detector 1 and *t*<sup>2</sup> for Detector 2.

**Figure 1.** Transmission line with a short and detectors.

If the unknown time at which the fault occurred is *t*<sup>0</sup> and the constant velocity of the signal propagation is *v*, the following relations follow:

$$v(t\_1 - t\_0) = d\_1; \qquad v(t\_2 - t\_0) = d\_2 \tag{1}$$

in which *d*<sup>1</sup> and *d*<sup>2</sup> are the unknown distance from the fault to Detectors 1 and 2, respectively. The total distance between the two detectors is known as:

$$d = d\_1 + d\_2 \tag{2}$$

Defining the time difference *tdi* ≡ *t*<sup>2</sup> − *t*1, the distance from Detector 1 to the short may be written as follows:

$$d\_1 = \frac{1}{2}(d - v \, t\_{di}) \tag{3}$$

Hence, if *tdi* is a random variable of the standard deviation *σtdi* , the corresponding standard deviation of *d*<sup>1</sup> is:

$$
\sigma\_{d\_1} = \frac{v}{2} \sigma\_{t\_{di}} \tag{4}
$$

provided we assume that the velocity *v* is known. Now, *σtdi* can be evaluated as:

$$
\sigma\_{t\_{di}} = \sqrt{\sigma\_{t\_1}^2 + \sigma\_{t\_2}^2 - 2\mathbf{C}\_{t\_1 t\_2}}.\tag{5}
$$

in which the covariance *Ct*1*t*<sup>2</sup> is given in terms of the following expectation value:

$$C\_{t\_1 t\_2} = E[(t\_1 - \bar{t}\_1)(t\_2 - \bar{t}\_2)], \qquad \bar{t} \equiv E[t] \tag{6}$$

If the uncertainty in *t*<sup>1</sup> is uncorrelated with the uncertainty in *t*2, the covariance is null, and we have a simplified expression:

$$
\sigma\_{t\_{\bar{d}\bar{l}}} = \sqrt{\sigma\_{t\_1}^2 + \sigma\_{t\_2}^2}.\tag{7}
$$

If *σt*<sup>1</sup> = *σt*<sup>2</sup> , this will result in:

$$
\sigma\_{t\_{di}} = \sqrt{2}\sigma\_{t\_1}.\tag{8}
$$

Thus, we can rewrite *σd*<sup>1</sup> in terms of *σt*<sup>1</sup> as follows:

$$
\sigma\_{d\_1} = \frac{v}{\sqrt{2}} \sigma\_{t\_1} \tag{9}
$$

Now, suppose that the data are sampled at intervals of *T*; if the signal is detected initially at time *tD*, this means that the signal arrived at any time between *tD* and *tD* − *T*. Since we do not have any information about what time the signal really arrived, we assumed that *t*<sup>1</sup> is a random variable distributed uniformly in the interval [*tD* − *T*, *tD*]. The probability density function of *t*<sup>1</sup> is depicted in Figure 2.

**Figure 2.** Uniform distribution probability density function of *t*1; in the illustration, we assumed *T* = 5 and *tD* = 10.

Since the moments of a uniform distribution function are known, we can easily evaluate the expectation and standard deviation of *t*<sup>1</sup> as follows:

$$
\bar{t}\_1 = t\_D - \frac{1}{2}T, \qquad \sigma\_{l\_1} = \frac{T}{2\sqrt{3}} \tag{10}
$$

Inserting the result of Equation (10) into Equation (9) leads to:

$$
\sigma\_{d\_1} = \frac{vT}{2\sqrt{6}}\tag{11}
$$

Thus, the accuracy at which we need to know the location of the fault will determine the sampling rate *fS* according to the following formula:

$$f\_S = \frac{1}{T} = \frac{v}{2\sqrt{6}\,\sigma\_{d\_1}}\tag{12}$$

As we shall show later, for a power line, the typical propagation of the signal is close to light's velocity in a vacuum:

$$v \simeq c \simeq 3 \times 10^8 \text{ m/s}.\tag{13}$$

Thus, if the required distance precision is about 1 m, then the time measurement sampling rate should be:

$$f\_{\rm S} \simeq 6.12 \times 10^7 \text{Hz} \tag{14}$$

This is much lower than the clock rate of current computer processors. We do not deal here with additional sources of uncertainty, such as the noise level of transmission lines, and leave that for future work.

#### **3. Methodology: Signal Detection**

What kind of signal should we measure for the fault location, and should it be the voltage or current? How should it be processed in order to avoid the accumulation of a large amount of unnecessary data due to the high sampling rate dictated by Equation (14)? We shall try to answer those question using a lumped circuit model, as described in Appendix A [26–28], in which we show that a fault signal can be obtained by measuring either the current or voltage.

The high sampling rate that is needed for accurate location as described in Equation (12) imposes a storage challenge as the amount of data accumulated may be prohibitive. However, taking the derivative of the signal, which may be the voltage or current, allowed us to overcome this obstacle (see Appendix A). By choosing a high detection threshold, one avoids false positives, and this allowed us to store a relatively small amount of data that was sufficient for the detection and location of the short. In some cases, a second derivative was required.

Generally, the first voltage derivative is enough (except for the load voltage), while in the case of current measurement, the second derivative is necessary.

We further noticed an additional restriction on the required resolution *T*, in order to avoid the case that the pulse goes undetected, that is between sampling points, we needed to have a resolution smaller than the pulse duration, which is the same duration as the time it takes the short to form; hence:

$$T < \mathbf{r}\_S \tag{15}$$

Now, if *<sup>τ</sup><sup>S</sup>* <sup>10</sup>−<sup>8</sup> s, this means that:

$$T < 10^{-8} \text{ s} \tag{16}$$

This limitation is even more restrictive than the one appearing in Equation (14), leading to:

$$T\_{\rm S} = \frac{1}{f\_{\rm S}} \simeq 1.63 \times 10^{-8} \,\text{s} \tag{17}$$

Obviously, a lumped model neglects the effect of spatial distances, and hence the effect of signal propagation. To describe the effect of signal propagation properly, a distributed model is needed, and with such a model we could study the short signal propagation and related phenomena including dispersion; this is discussed in the following section.

#### **4. Methodology: Distributed Model**

Until now, we have ignored the signal propagation in the circuit and assumed that the changes in the voltage and the current occur immediately and simultaneously everywhere. This assumption is not compatible with the theory of special relativity, which states that any signal must propagate with finite velocity, smaller than the speed of light in a vacuum [1]. To describe this behavior, we used the transmission line propagation model [29], a section of which is depicted in Figure 3.

**Figure 3.** Transmission line structure for a single unit length.

This approach leads to the telegraph equations. We describe this model in the time and frequency domains and draw the relevant conclusion from each presentation.

#### *4.1. The Time Domain*

The equations that describe the voltage and the current dependence in the time domain are the telegraph equations given below [29]:

$$\frac{\partial V(\mathbf{x},t)}{\partial \mathbf{x}} = -RI(\mathbf{x},t) - L\frac{\partial I(\mathbf{x},t)}{\partial t}, \qquad \frac{\partial I(\mathbf{x},t)}{\partial \mathbf{x}} = -GV(\mathbf{x},t) - C\frac{\partial V(\mathbf{x},t)}{\partial t} \tag{18}$$

where *R* is the resistance, *L* is the inductance, *G* is the conductance, and *C* is the capacitance, per unit length each (see Figure 3). This pattern is repeated indefinitely (see Figure 4).

**Figure 4.** Transmission line structure repeated.

The above equations can be solved for an infinite transmission line excited at *x* = 0 by an excitation *Vin*(*t*) representing the effect of the short on the voltage. The solution for the voltage is:

$$V(x,t) \approx V\_{\rm in} \left( t - \sqrt{L\mathcal{C}}x \right) \exp\left( -\frac{\sqrt{L\mathcal{C}}}{2} \left( \frac{R}{L} + \frac{G}{C} \right) x \right) \tag{19}$$

The above solution describes a voltage signal propagating at a velocity:

$$v = \frac{1}{\sqrt{LC}}\tag{20}$$

and an exponential decay with a decay factor of:

$$\alpha = \frac{\sqrt{LC}}{2} \left( \frac{R}{L} + \frac{G}{C} \right). \tag{21}$$

Assuming the transmission line to be a two-wire cable as described in Appendix A, the following parameters are obtained [29]:

$$R = \frac{2R\_S}{\pi d}, \quad L = \frac{\mu}{\pi \cosh^{-1}\left(\frac{D}{d}\right)}, \quad G = \frac{\pi \sigma}{\cosh^{-1}\left(\frac{D}{d}\right)}, \quad \mathbb{C} = \frac{\pi \varepsilon}{\cosh^{-1}\left(\frac{D}{d}\right)}\tag{22}$$

where each wire has a diameter *d*, and the distance between the wires is *D*. The material between the wires has a permittivity *ε*, permeability *μ*, and (a very small) conductivity *σ*. The wire resistance is calculated, as in Equation (A6), using the surface resistance given in Equation (A5). The short propagation velocity (20) can be now calculated using the parameters of Equation (22), to yield:

$$v = \frac{1}{\sqrt{\varepsilon\mu}} = \frac{c}{n} \tag{23}$$

where *n* is the index of refraction around the transmission line. It should be noted that the electromagnetic wave is propagating in the region between the conductors and not in the conductors themselves, where the propagation is much slower and the decay is very strong. We noticed that if the two wires are surrounded by air *n* 1, we would recover the velocity of Equation (13).

Notice that since according to Equations (A5) and (A6), the resistance is frequency dependent as dictated by the skin effect, the resistance term in Equation (18) is not a simple multiplication and should be replaced by a convolution. Thus, a frequency domain formalism is more adequate for this type of problem, as will be described next.

#### *4.2. The Frequency Domain*

In the frequency domain, the telegraph equation takes the form [29]:

$$\frac{\partial V(\mathbf{x},\omega)}{\partial \mathbf{x}} = -(\mathbf{R} + i\omega \mathbf{L})I(\mathbf{x},\omega),\\\frac{\partial I(\mathbf{x},\omega)}{\partial \mathbf{x}} = -(\mathbf{G} + i\omega \mathbf{C})V(\mathbf{x},\omega), \quad i \equiv \sqrt{-1} \tag{24}$$

Combining these two equations, we can separate the voltage and current variables, in terms of the following two equations:

$$\frac{\partial^2 V(\mathbf{x}, \omega)}{\partial \mathbf{x}^2} = \gamma^2 V(\mathbf{x}, \omega), \qquad \frac{\partial^2 I(\mathbf{x}, \omega)}{\partial \mathbf{x}^2} = \gamma^2 I(\mathbf{x}, \omega) \tag{25}$$

where we define:

$$\gamma \equiv \sqrt{(\mathcal{R} + i\omega L)(\mathcal{G} + i\omega \mathcal{C})} \tag{26}$$

These equations have a solution of the form:

$$\begin{aligned} V(\mathbf{x},\omega) &= V^{(+)}(\omega)e^{-\gamma \mathbf{x}} + V^{(-)}(\omega)e^{\gamma \mathbf{x}} \\ I(\mathbf{x},\omega) &= \frac{1}{Z\_0} \left( V^{(+)}(\omega)e^{-\gamma \mathbf{x}} - V^{(-)}(\omega)e^{\gamma \mathbf{x}} \right) \end{aligned} \tag{27}$$

The functions *V*(±)(*ω*) are derived from the initial conditions. The impedance *Z*<sup>0</sup> is defined as follows:

$$Z\_0 \equiv \sqrt{\frac{R + i\omega L}{G + i\omega \mathcal{C}}} \tag{28}$$

In the case where the resistivity and the leakage admittance are small enough, such that:

$$R < \preccurlyeq \omega \mathcal{L}\_{\prime} \qquad \mathcal{G} \prec\preccurlyeq \omega \mathcal{C} \tag{29}$$

we can approximate the impedance:

$$Z\_0 \approx \sqrt{\frac{L}{C}}\tag{30}$$

and the real and imaginary parts of *γ* take the form:

$$\operatorname{Re}(\gamma) \approx \frac{\sqrt{LC}}{2} \left( \frac{R}{L} + \frac{G}{\mathbb{C}} \right) = \mathfrak{a}, \qquad \operatorname{Im}(\gamma) \approx \omega \sqrt{LC} \tag{31}$$

As the frequency rises, the approximation becomes more accurate. Hence, for the higher-frequency Fourier components associated with the short formation, this approximation is more effective. Notice that while Re(*γ*) describes absorption and coincides with the same expression for absorption obtained in Equation (19), Im(*γ*) describes propagation.

#### *4.3. Time-Dependent vs. Stationary Shorts*

Steady-state shorts are easily analyzed in transmission line theory; here, we shall try to elucidate the connection between the transient phenomena of the short's appearance and its asymptotic behavior as a steady- state phenomenon. Our model is depicted in Figure 5.

**Figure 5.** Detailed short in the transmission line model.

We assumed that the short appears at some point (*x* = 0) in the transmission line, in which the continuity of the voltage and current dictates:

$$V\_1(0,\omega) = V\_2(0,\omega), \qquad I\_1(0,\omega) = I\_2(0,\omega) + I\_{short}(\omega). \tag{32}$$

We assumed that the short current does not exist at *t* = 0; likewise, the short current after a long time can be calculated using the fact that the voltage on the short vanishes at *t* → ∞. The second assumption can be formulated as:

$$\lim\_{t \to \infty} I\_{\text{short}}(t) = I\_{\text{short asymptotic}}(t) \tag{33}$$

To obtain the asymptotic short current, the following calculation was performed. First, we used the fact that after a considerable duration, the voltage on the short vanishes to obtain the following:

$$V\_{\text{short asymptotic}}(\omega) = V^{(+)}(\omega) + V^{(-)}(\omega) = 0 \tag{34}$$

This leads to the result:

$$V^{(-)}(\omega) = -V^{(+)}(\omega)\tag{35}$$

Inserting this result into Equation (27) and taking into account that *Vasymptotic*(*ω*, −*L*1) is the source voltage lead to the following result:

$$V\_{in}(\omega) = V\_{asymptoti}(\omega, -L\_1) = V^{(+)}(\omega) \left( e^{\gamma L\_1} - e^{-\gamma L\_1} \right) \tag{36}$$

Hence:

$$V^{(+)}(\\\omega) = \frac{V\_{in}(\omega)}{2\sinh(\gamma L\_1)}\tag{37}$$

The asymptotic short current in the frequency domain can be calculated using Equation (27) at *x* = 0 and taking into account Equations (35) and (37):

$$I\_{\text{short asymptotic}}(\omega) = I(\omega, 0) = \frac{2V^{(+)}}{Z\_0} = \frac{V\_{\text{in}}(\omega)}{Z\_0 \sinh(\gamma L\_1)}\tag{38}$$

Taking into account *Vin*(*t*) given in Equation (A8) (which is equivalent to a sum of delta functions in the frequency domain), the asymptotic short current in the time domain is:

$$I\_{\text{short asymptote}}(t) = \frac{A\_0}{Z\_0} \text{Re} \frac{e^{j\omega\_0 t}}{\sinh(\gamma(\omega\_0) L\_1)}\tag{39}$$

The second assumption was that the short current vanishes at *t* = 0:

$$I\_{short}(t=0) = 0\tag{40}$$

In the current model, this requirement is fulfilled by multiplying the asymptotic expression with some reasonable function that vanishes at *t* → 0 and approaches unity at *t* → ∞, for example:

$$I\_{short}(t) = I\_{short\,\,asymp}(t)\mu(t)\left(1 - e^{-\frac{t}{\Lambda}}\right) \tag{41}$$

in which *u*(*t*) is a step function. The calculation results for the short current on the load side are as follows:

$$I\_2(\mathbf{x}, t) = \frac{e^{-a(\mathbf{x} + \mathbf{L}\_1)}}{Z\_0} V\_{\text{in}}(\mathbf{t} - \mathbf{t}\_{d1}) - \frac{e^{-\alpha \mathbf{x}}}{2} I\_{\text{short}}(\mathbf{t} - \mathbf{t}\_d) - \frac{e^{-a(\mathbf{x} + 2\mathbf{L}\_1)}}{2} I\_{\text{short}}(\mathbf{t} - \mathbf{t}\_{d2}) \tag{42}$$

where *td* = *<sup>x</sup> <sup>v</sup>* , *td*<sup>1</sup> <sup>=</sup> *<sup>x</sup>*+*L*<sup>1</sup> *<sup>v</sup>* , and *td*<sup>2</sup> <sup>=</sup> *<sup>x</sup>*+2*L*<sup>1</sup> *<sup>v</sup>* . *v* is the signal propagation velocity. The current at the load side is affected by three terms, each with unique retardation. The source voltage is retarded by a time *td*1, while the short current is retarded by a time *td* for the direct signal and by *td*<sup>2</sup> for the same signal reflected by the circuit source. Each retardation time is proportional to the distance it needs to travel from its source and inversely proportional to the velocity of propagation. The model also shows that the signals suffer attenuation proportional to the distance they travel.

#### *4.4. Signal Dispersion*

We now consider the problem of dispersion. This problem is interesting since we would like to know in what ways does the line distort signals propagating on it and, in particular, how the signal produced by the short is effected. We start from the definition of *γ* given in Equation (26), and we assume that *G* = 0. Consequently, the propagation index is:

$$\gamma(\omega) = i\omega \sqrt{LC} \sqrt{1 + \frac{R}{i\omega L}}\,\tag{43}$$

Now, let us investigate the condition:

$$Ra \equiv \frac{\mathcal{R}(\omega)}{i\omega L} \ll 1\tag{44}$$

The resistance *R*(*ω*) is frequency dependent due to the skin effect and can be calculated from the surface resistance using Equations (A5) and (A6) as follows:

$$R = \frac{2}{\sqrt{\pi d}} \sqrt{\frac{\mu\_c}{\sigma\_c}} f \tag{45}$$

Thus, we obtain the ratio:

$$\frac{R}{\omega L} = \frac{1}{\sqrt{\pi^3} dL} \sqrt{\frac{\mu\_c}{\sigma\_c}} \frac{1}{\sqrt{f}} \tag{46}$$

Thus, the approximation given in Equation (44) is even better for higher-frequency components. Introducing the inductance impedance:

$$\mathbf{Z}\_{\rm L} = \mathbf{i}\omega \mathbf{L} = \mathbf{i}2\pi f \mathbf{L} \tag{47}$$

we can cast Equation (46) in the form:

$$\frac{R}{Z\_L} \cong -\frac{2.72i}{\sqrt{f}}\tag{48}$$

in which the numerical values for the parameters are taken from Tables A1, A2, and A5. Equation (48) is depicted in Figure 6, which shows that the condition given in Equation (44) holds even better for a high frequency.

For a small parameter |*x*| 1, we can write:

$$
\sqrt{1+x} = 1 + \frac{\mathbf{x}}{2} - \frac{\mathbf{x}^2}{8} + \frac{\mathbf{x}^3}{16} + O[\mathbf{x}]^4. \tag{49}
$$

Hence, taking into account that *<sup>R</sup> <sup>ω</sup><sup>L</sup>* 1, *γ*(*ω*) of Equation (43) has up to third order the form:

$$\gamma(\omega) \cong i \frac{\omega}{\mathbf{v}} \left[ 1 - j \frac{\mathbf{R}}{2\omega L} + \frac{1}{8} \left( \frac{\mathbf{R}}{\omega L} \right)^2 + \frac{j}{16} \left( \frac{\mathbf{R}}{\omega L} \right)^3 \right] \tag{50}$$

This expression can be separated into an imaginary and real parts as follows. The imaginary part of *γ* takes the form:

$$\mathrm{Im}\gamma \cong \frac{\omega}{\mathrm{v}} + \frac{\mu\_{\mathrm{c}}}{4\pi^2 d^2 L^2 \sigma\_{\mathrm{c}} \mathrm{v}}\tag{51}$$

where we have taken into account Equation (46). As Equation (51) is linear in *ω*, we concluded that there is no dispersion during the signal propagation that requires non-linear phase terms. To appreciate the linearity of Im*γ*, we depict it as a function of the frequency in both Figure 7 for low frequencies and in Figure 8 for high frequencies without making an expansion approximation; the linearity and, hence, the lack of dispersion are apparent for a wide frequency range.

**Figure 7.** Im*γ* low frequency dependence.

**Figure 8.** Im*γ* high frequency dependence.

For the real part of *γ*, we obtain:

$$\mathrm{Re}\gamma \stackrel{\curvearrowleft}{=} \frac{\sqrt{\mu\_{\rm c}}}{2^{\frac{3}{2}}L\sqrt{\sigma\_{\rm c}}\mathbf{v}}\sqrt{\omega} \tag{52}$$

The real part depends on the frequency, but this part is relatively small, compared to the imaginary part. To appreciate the frequency dependence of Re*γ*, we depict its behavior for low frequencies (Figure 9), high frequencies (Figure 10), and extremely high frequencies (Figure 11).

**Figure 9.** Re*γ* for low frequencies.

**Figure 10.** Re*γ* for high frequencies.

**Figure 11.** Re*γ* for very high frequencies.

To appreciate how small Re*γ* is with respect to Im*γ*, we plot the ratio of those quantities in Figure 12.

Another indication of the dominance of Im*γ* over Re*γ* is the frequency dependence of |*γ*|, which follows quite closely the linear behavior of Im*γ*, as depicted in Figure 13.

**Figure 12.** The ratio of the real part to the imaginary part of *γ*.

**Figure 13.** |*γ*| as a function of frequency.

Finally, we remind ourselves that we assumed zero admittance *G* = 0 in our calculations. Practically, this means that we neglected the air admittance with respect to the capacitive admittance:

$$
\Upsilon\_{\mathbb{C}} = i\omega \mathbb{C} = i2\pi f \mathbb{C}.\tag{53}
$$

To check if this assumption is justified, we calculated the ratio of the air admittance to capacitive admittance:

$$\frac{G}{Y\_{\mathbb{C}}} \simeq -\frac{1.38 \times 10^{-6}i}{f} \tag{54}$$

where we used the parameters of Table A3 for the air admittance and Equation (22) for the capacitance. The ratio, which is quite small, becomes even smaller for higher frequencies, as depicted in Figure 14, and thus justifies our initial assumption.

**Figure 14.** The frequency dependence of / / / *G YC* / / /.

The conclusion of this subsection is that dispersion is not significant in the media in which the pulse generated by the short propagates. This will be further elaborated in the next subsection, as we study the prorogation of a signal along the line.

#### *4.5. Signal Propagation*

We assumed that at the entrance to a transmission line, we inject a short signal of the form:

$$V(0,t) = 2e^{-\frac{l^2}{2\sigma\_0^2}}\cos(\omega\_0 t) \tag{55}$$

Thus, we assumed that the short generates a pulse signal, while the standard voltage is a periodic trigonometric function of frequency *ω*0, which is modulated by the pulse. The pulse was assumed to be Gaussian with a width *σ*0. The same signal in the frequency domain takes the form:

$$V(0,\omega) = \sqrt{2\pi}\sigma\_0 \left( e^{-\frac{\sigma\_0^2}{2}(\omega+\omega\_0)^2} + e^{-\frac{\sigma\_0^2}{2}(\omega-\omega\_0)^2} \right) \tag{56}$$

This signal is depicted in Figure 15.

**Figure 15.** The entrance voltage signal in the frequency domain.

Now, since that signal is injected at the entrance, it can propagate in only one direction; hence, Equation (27) takes the form:

$$V(x,\omega) = V(0,\omega)e^{-\gamma(\omega)x} \tag{57}$$

We now expand *γ* around *ω*<sup>0</sup> till the second order. This results in:

$$
\gamma \left( \omega\_0 + \omega' \right) \cong \gamma(\omega\_0) + \gamma'(\omega\_0)\omega' + \frac{1}{2}\gamma''(\omega\_0)\omega'^2. \tag{58}
$$

Taking into account Equations (56)–(58) and performing an inverse Fourier transform, we arrive at the following expression for a propagating signal:

$$V(\mathbf{x},t) = 2\sigma\_0 \text{Re} \left[ \frac{e^{i\omega\_0 t - \gamma\_0 \cdot \mathbf{x}} e^{-\frac{\left(t - t\_d\right)^2}{2\sigma^2(\mathbf{x})}}}{\sigma(\mathbf{x})} \right] \tag{59}$$

where the delay time *td* is:

$$t\_d = -i\gamma\_0' \mathbf{x} = \frac{\mathbf{x}}{\upsilon} \frac{1 + \frac{3}{4}Ra}{\sqrt{1 + Ra}} \stackrel{\sim}{\simeq} \frac{\mathbf{x}}{\upsilon};\tag{60}$$

hence, this is approximately the distance divided by the velocity, as expected. We noticed that the expression:

$$w\_{\mathcal{S}} = \left| I m \gamma\_0' \right|^{-1} = v \left( \frac{\sqrt{1 + Ra}}{1 + \frac{2}{4} Ra} \right),\tag{61}$$

is the group velocity, which is the velocity of a wave packet. The width of the signal is:

$$
\sigma(\mathbf{x}) = \sqrt{\sigma\_0^2 + \gamma\_0^{\prime\prime} \mathbf{x}} \tag{62}
$$

where:

$$\gamma\_{\!\!\!\!\/}^{\prime\prime} = \frac{-i\text{Ra}\left(1 + \frac{3}{2}\text{Ra}\right)}{16\upsilon\omega\_{0}\sqrt{1 + \text{Ra}^{3}}} \underset{\!\!\!\!\/}{\underset{\!\!\!\/}{\longrightarrow}} -\frac{\text{R}(\omega\_{0})}{16\upsilon\omega\_{0}^{2}L} \tag{63}$$

The term *γ* <sup>0</sup>*x* signifies the pulse broadening as it propagates along the line. Let us assume that *<sup>σ</sup>*<sup>0</sup> ≈ <sup>10</sup>−<sup>6</sup> s. For a frequency of 1 MHz and a distance of 1 km:

$$
\gamma\prime\prime\_0\mathbf{x} \cong -6.39 \times 10^{-19} - 2.85 \times 10^{-33} \mathbf{i} < < \sigma\_0^2 = 10^{-12};\tag{64}
$$

hence, the dispersion is negligible. However, for a frequency of 1 kHz and a distance of 10 km:

$$\gamma\prime\prime\_0\mathbf{x} \cong -6.39 \times 10^{-12} - 2.85 \times 10^{-17} \mathbf{i} \approx v\_0^2 = 10^{-12} \tag{65}$$

the widening is comparable to the initial width. Hence, despite the fact that dispersion seems small, it accumulates over long distances.

#### *4.6. Bifurcations*

A power transmission line often bifurcates, as depicted in Figure 16.

In the bifurcation junction, the signal is transmitted to the bifurcating channels and is also reflected to the original channel in which the short was originally formed. The amount of signal reflected or transmitted is quantified by the reflection *R* and transmission *T* coefficients. Those coefficients can in turn be calculated as follows:

**Figure 16.** Schematic bifurcation in a power line.

$$T\_{1\to 2} = \frac{2Z\_2}{Z\_1 + Z\_2}, \qquad T\_{2\to 1} = \frac{2Z\_1}{Z\_1 + Z\_2} \tag{66}$$

$$R\_{2 \to 1} = \frac{Z\_2 - Z\_1}{Z\_1 + Z\_2} = -R\_{1 \to 2} \tag{67}$$

in which *Z*<sup>1</sup> is the impedance of the line before the bifurcation junction and *Z*<sup>2</sup> is the impedance of the line after the bifurcation junction. In case the signal meets multiple bifurcation junctions along its path, multiple reflection occur, as depicted schematically in Figure 17.

**Figure 17.** Multiple reflections from a changing propagation media.

Multiple reflections will result in multiple signals arriving at the detector, as depicted schematically in Figure 18.

**Figure 18.** Multiple reflections arriving at the detector.

We note that reflected signals arrive at the detector later and in reduced amplitude due to the longer path they need to travel and the additional attenuation the signal suffers during propagation (see Equation (59)) and reflection. We note that if a line bifurcates into multiple identical lines as in Figure 19, the total impedance at the channel after the bifurcation will be equal to the original impedance *Z*<sup>0</sup> divided by the number of transmission lines *N*; hence:

This implies, according to Equation (66), a transmission coefficient of:

$$T\_{1\to 2} = \frac{2Z\_2}{Z\_1 + Z\_2} = \frac{2\frac{Z\_0}{N}}{Z\_0 + \frac{Z\_0}{N}} = \frac{2}{N+1} \tag{69}$$

$$R\_{1\to 2} = \frac{Z\_1 - Z\_2}{Z\_1 + Z\_2} = \frac{Z\_0 - \frac{Z\_0}{N}}{Z\_0 + \frac{Z\_0}{N}} = \frac{N - 1}{N + 1};\tag{70}$$

hence, for a bifurcation to a large number of channels, the reflection coefficient will tend to one, while for a continuation into a single identical channel, there will not be obviously a reflection.

We now examine the reflection effect and see if one can use the reflected signal instead of a second sensor, thus reducing the amount of hardware needed in order to implement the method described. First, let us look at Figure 20: The short occurs between the sensor and the bifurcation point. Thus, a signal is propagating from the short to the sensor, and an additional signal propagates to the bifurcation point where it is reflected. Provided that the short will not introduce an impenetrable obstacle, the signal will eventually reach the detector at a later time. The direct signal arrival time will be satisfied according to Equation (1):

**Figure 20.** A short occurs between the sensor and the bifurcation point.

The reflected signal will arrive at a later time such that:

$$t\_2 - t\_0 = \frac{L\_1 + 2L\_2}{v} \tag{72}$$

Hence, the time difference between the direct and reflected signal allowed us to calculate the distance between the short and bifurcation point as:

$$L\_2 = \frac{1}{2}v(t\_2 - t\_1) \tag{73}$$

Now, since the distance *L* between the sensor and the bifurcation point is known in advance, we may calculate the distance between the short and the bifurcation point as follows:

$$L\_1 = L - L\_2 = L - \frac{1}{2}v(t\_2 - t\_1) \tag{74}$$

Thus, in this case, a single detector will suffice, and we will not need two detectors, as described in Section 2. This reduces the cost of the system and removes redundant issues such as sensor synchronization. The last advantageous scenario is depicted in Figure 21.

**Figure 21.** The sensor is between the short and the bifurcation point.

The direct signal arrival time will be satisfied according to Equation (1):

$$t\_1 - t\_0 = \frac{L\_1}{v} \tag{75}$$

The reflected signal will arrive at a later time such that:

$$t\_2 - t\_0 = \frac{2L\_2 - L\_1}{v} \tag{76}$$

The time difference in this case will yield:

$$L\_2 - L\_1 = \frac{1}{2}v(t\_2 - t\_1) \tag{77}$$

which does not reveal any information about the short location, but rather, some trivial information about the distance between the sensor and the bifurcation point, which is already known. Of course, if there exist additional bifurcation points on the signal path (for example, left to the short), then we are in the previous case again, and one sensor will suffice. We may deduce that putting sensors on bifurcation points will reduce the amount of sensors needed. Finally, we looked at the case in which the signal arrives at a sensor located after the branching point of the net, as in Figure 22.

**Figure 22.** The sensor is on a bifurcation of the transmission line.

The sensor will receive a signal at:

$$t\_1 - t\_0 = \frac{L + L\_1}{v} \tag{78}$$

This will not suffice to locate the short unless a reflected signal is received from another point along the network. To conclude, we deduced that putting sensors on bifurcation points will reduce the amount of sensors needed along the network. Moreover, relying on reflections may solve the problem of sensor synchronization.

#### *4.7. Laplace Analysis*

We now address the transmission line pulse propagation problem using the technique of Laplace analysis [30]. The simplified power system of our interest is schematically presented in Figure 23.

**Figure 23.** Schematic of the fault scenario.

The fault produces two separate signals propagating towards the source and the load, where the sensors are located. In each section, as a result of the fault, the voltage perturbation is perceived as an input signal, propagating towards a sensor, as shown in Figure 24.

**Figure 24.** Schematic of the fault modeling.

In the transmission line, we assumed the validity of the telegraph Equation (24) and replaced *iω* → *s*. The Laplace form of the telegraph equations admits the solution:

$$V(x,s) = V\_{(-)}(s)e^{-x\gamma(s)} + V\_{(+)}(s)e^{x\gamma(s)}\tag{79}$$

$$I(\mathbf{x}, \mathbf{s}) = \frac{V\_{(-)}(\mathbf{s})}{Z\_0(\mathbf{s})} e^{-\mathbf{x}\gamma(\mathbf{s})} - \frac{V\_{(+)}(\mathbf{s})}{Z\_0(\mathbf{s})} e^{\mathbf{x}\gamma(\mathbf{s})} \tag{80}$$

where,

$$Z(s) = R + sL, \; Y(s) = G + sC \tag{81}$$

$$\gamma(\mathbf{s}) = \sqrt{Z(\mathbf{s})Y(\mathbf{s})} \tag{82}$$

$$Z\_0(s) = \sqrt{\frac{Z(s)}{Y(s)}}\tag{83}$$

It is realistic to presume that the conductance *G* of the separating dielectric material between the wires is insignificant. The series resistivity is calculated taking into account the skin effect:

$$R(s) = \frac{1}{\pi d} \sqrt{\frac{2\mu\_c}{\sigma\_c}} \sqrt{s} \equiv \xi \sqrt{s} \tag{84}$$

where *d* is the conductor wire diameter and:

$$
\zeta = \frac{1}{\pi d} \sqrt{\frac{2\mu\_c}{\sigma\_c}}.\tag{85}
$$

Consequently, the expression (82) can be written as follows:

$$\begin{split} \gamma(s) &= s\sqrt{LC}\sqrt{1 + \frac{R(s)}{sL}} = s\sqrt{LC}\sqrt{1 + \frac{\frac{\tilde{\zeta}}{\sqrt{sL}}}{\sqrt{sL}}} \approx \\ &\approx s\sqrt{LC}\Big(1 + \frac{\frac{\tilde{\zeta}}{2\sqrt{sL}}}{2\sqrt{sL}}\Big) = s\sqrt{LC} + \frac{\tilde{\zeta}}{2}\sqrt{\frac{\tilde{\zeta}}{L}}\sqrt{s} \end{split} \tag{86}$$

The sensor impedance *ZL* was designed to be infinite so as not to influence the measurement results. Substituting boundary conditions,

$$V\_{fault}(s) = V(0, s) = V\_{(-)}(s) + V\_{(+)}(s) \tag{87}$$

and:

$$Z\_L = \infty \tag{88}$$

which implies zero current at *x* = *l*:

$$I(l,s) = \frac{V\_{(-)}(s)}{Z\_0(s)}e^{-l\gamma(s)} - \frac{V\_{(+)}(s)}{Z\_0(s)}e^{l\gamma(s)} = 0\tag{89}$$

or:

$$V\_{(-)}(s) = V\_{(+)}(s)e^{2l\gamma(s)}\tag{90}$$

Combining the above equation with Equation (87) yields:

$$V\_{(+)} = \frac{V\_{fault}(s)}{1 + e^{2l\gamma(s)}}\tag{91}$$

and:

$$V\_{(-)} = \frac{V\_{fault}(s)}{1 + e^{-2l}r^{(s)}}\tag{92}$$

The voltage signal at the sensor due to the fault is thus:

$$V\_{out}(s) \equiv V(l,s) = \frac{2e^{-l\gamma(s)}}{1 + e^{-2l\gamma(s)}} V\_{fault}(s) \tag{93}$$

Identifying the last expression as the summation of a geometric series, it can be re-written as the sum:

$$V\_{out}(s) = 2V\_{fault}(s) \sum\_{n=0}^{\infty} (-1)^n e^{-(1+2n)l\gamma(s)}\tag{94}$$

Defining:

$$\text{and:}$$

$$x\_n \equiv (1+2n)l\sqrt{LC} \tag{95}$$

$$B\_{\rm nl} \equiv (1+2n)I \frac{\frac{\pi}{6}}{2} \sqrt{\frac{C}{L}} \tag{96}$$

the expression for the voltage at the sensor, Equation (94), takes the form:

$$V\_{\rm out}(s) = 2V\_{\rm fault}(s) \sum\_{n=0}^{\infty} \left(-1\right)^{n} e^{-\tau\_{\rm n}s + B\_{\rm n}\sqrt{s}} \tag{97}$$

This sum can be interpreted as the sum of multiple reflected waves each with its unique delay time. The system's transfer function may be now calculated as follows:

$$H(s) \equiv \frac{V\_{out}(s)}{V\_{fault}(s)} = 2\sum\_{n=0}^{\infty} (-1)^n e^{-\tau\_n s + B\_n \sqrt{s}}\tag{98}$$

This allows for obtaining the signal measured at the sensor, due to any fault waveform. For example, if the fault is a sudden short circuit at *x* = 0 and *t* = 0, the voltage at the fault location is:

$$V\_{in}(t) \equiv V(0, t) = V\_0 - V\_0 \mu(t). \tag{99}$$

Using the superposition principle, *Vout*(*t*) may be expressed as the sum of a DC input and a step function input response.

$$V\_{out}(t) = V\_{out}(V\_{in} = V\_0) \left( t \right) - V\_{out}(V\_{in} = V\_0 u(t)) \left( t \right) \tag{100}$$

Since the impedance at the edge is infinite, the voltage along the line due to the DC input is simply *V*0. Moreover, the Laplace transform of a step function satisfies:

$$
\mathcal{L}\{u(t)\} = \frac{1}{\mathbf{s}'} \tag{101}
$$

hence:

$$V\_{out(V\_{in}=V\_0u(t))}(s) = \frac{V\_0H(s)}{s} \tag{102}$$

Hence, using the transfer function definition, Equation (98), and performing an inverse transform back to the time domain, we obtain:

$$V\_{out}(t) = V\_0 - 2\mathcal{L}^{-1} \left\{ \frac{V\_0}{s} \sum\_{n=0}^{\infty} \left(-1\right)^n e^{-\tau\_n s + B\_n \sqrt{s}} \right\} \tag{103}$$

Taking a known inverse Laplace transform [22]:

$$\mathcal{L}^{-1}\left\{e^{-\tau s}\frac{e^{-B\sqrt{s}}}{s}\right\} = \operatorname{erfc}\left(\frac{B}{2\sqrt{t-\tau}}\right)u(t-\tau)\tag{104}$$

The voltage at the sensor, as a result of the fault, is:

$$V\_{out}(t) = \left. V\_0 - 2V\_0 \sum\_{n=0}^{\infty} (-1)^n \text{erfc} \left( \frac{B\_n}{2\sqrt{t - \tau\_n}} \right) \right| \tag{105}$$
 
$$\mu(t - \tau\_n) \tag{105}$$

The above result will suffice if the rise time of the short is fast enough and can be ignored.

#### **5. Methodology: Experimental Setup**

#### *5.1. Experiment Hardware*

The experimental demonstration of the fault location technique involved the setup shown schematically in Figure 25, in which a 10V DC voltage was supplied from a TTi QL355TP power supply source, shown in Figure 26, to a 50 m two-wire cable and switches. The sensor was a MS09404A Mixed Signal Oscilloscope with a 4 GHz bandwidth, which has two channels, as shown in Figure 27.

**Figure 25.** Schematic of the experimental setup.

**Figure 26.** TTi QL355TP power supply.

**Figure 27.** MS09404A Mixed Signal Oscilloscope of a 4 GHz bandwidth having two channels.

Figure 28 illustrates the dimensions of the transmission line.

**Figure 28.** Dimensions of the transmission line.

The transmission line was comprised of a two-wire power cord. Each wire was made of copper and had a *d* = 1 mm diameter, while the distance between the wires was *D* = 4 mm. These parameters allowed us to calculate the inductance L and capacitance C from the dielectric constant, magnetic permeability, and conductivity as follows (see Equation (22)):

$$\begin{aligned} \varepsilon\_{r(insulator)} &= 3.45, \mu\_{r(insulator)} = 1, \\ \sigma\_{cap \, \nu \tau} &= 3 \times 10^6 \frac{\text{S}}{m}, n = \sqrt{\varepsilon\_r \mu\_r} \simeq 1.86 \\ \mathcal{L} &= \frac{2 \pi \varepsilon}{\cosh^{-1} \left(\frac{D^2 - 2d^2}{2d^2}\right)} = 7.22 \times 10^{-11} \frac{F}{m} \\ L &= \frac{\varepsilon \mu}{\mathcal{C}} = 5.27 \times 10^{-7} \frac{H}{m} \end{aligned}$$

#### *5.2. Experimental Process*

On one side of the transmission line, we connected the DC source, 2 switches, and the scope channel; another channel was connected to the other side. Closing the first switch when the second switch is open, we obtained a steady-state DC voltage along the line. The short circuit fault was achieved by closing the second switch.

#### **6. Results: Data Processing**

#### *6.1. Location Accuracy*

Measuring the voltage of both sides of the line, we can see clearly the delay in signal propagation along the line. Additional reflected waves (Figures 29 and 30) are also seen. The scope channel data were exported and processed using the MATLAB software.

**Figure 30.** Comparison of the sensor voltage and its derivative.

Our aim was of course to discover how long it takes the signal to arrive from the fault to the measuring point. Because the waves arriving at the edge are reflected in the opposite direction (towards the fault), where they are repeatedly reflected, one fault may supply several data points that we can process to our advantage, depending on how fast the transient signals decay. In this study, it was possible to measure five signals (peaks) each time, and so, we chose the optimal data processing technique.

To obtain the best accuracy, we performed numerous voltage smoothing and voltage derivative smoothing, changing the time window and thus the number of samples. Obviously, the wider the window, the less noise we had to distort our results. However, a wide window may distort the reflection signal as well, compromising our accuracy. We used five different averaging windows and thus obtained five different errors for each reflection. The data are given in the Appendix B; in the table, each line represents a different value of the voltage smoothing window and voltage derivative smoothing window and the errors that were deduced for each reflection and processing method.

Figure 30 shows that the voltage derivative peaks were much sharper; therefore, the short circuit fault location was calculated by finding the time intervals between the local extremum points in the voltage derivative at the transmission line edge. In addition, the smoothing filter window may slightly change the results, and the optimum configuration was 200 points in a window. In this situation, the accuracy in the short circuit fault location detection was ±0.005% using the second peak.

This can be compared to the theoretical accuracy predicted by Equation (11). In the current case, the sampling rate was 4 GHz, and hence, the time between samples was *<sup>T</sup>* <sup>=</sup> 2.5 <sup>×</sup> <sup>10</sup>−<sup>10</sup> s and the velocity *<sup>v</sup>* <sup>=</sup> *<sup>c</sup> <sup>n</sup>* = 1.62 × 108 m/s. Thus, the accuracy may be as high as 0.008 m, which is ±0.008%, quite close to the best experimental result. This indicates that the theoretical limit is achievable provided the data are processed correctly.

#### *6.2. Comparison with Theory*

We now compare the results of the theory given in Equation (105) to the (smoothed) experimental results. The signal reflection scheme is shown in Figure 31. The results of the comparison are depicted in Figure 32.

**Figure 31.** The propagation times for the pulse reflections.

**Figure 32.** Comparison results between Equation (105) and the smoothed scope channel.

The unprocessed timings of various peaks were correlated with signal reflections and are given in Table 1.


**Table 1.** Distance calculations based on raw data without applying any processing technique.

The same results derived from the theoretical calculation are given in Table 2.

**Table 2.** Distance calculations from the simulation results.


Obviously, the theoretical distance evaluation was better than the experimental one; however, processing dramatically improved the situation, as we saw in the previous section. The distances can be derived from the time differences since <sup>Δ</sup>*<sup>L</sup>* = *<sup>v</sup>* <sup>Δ</sup>*<sup>t</sup>* = 1.62 × <sup>10</sup><sup>8</sup> <sup>Δ</sup>*<sup>t</sup>* m. In the above, we denote Δ*ti* and Δ*t <sup>i</sup>* for one-direction experimental and theoretical propagation times, respectively. As we can see, the propagation times were sufficiently stable and consistent with the theoretical model. Hence, the pulse location information can also be obtained from the voltage signal (without the signal derivative if precision is not required).

However, there was a difference between the theoretical and the experimental graphs. In the experimental data, there were additional peaks in the first reflected waves; after the third (main) peak, the "oscillation" frequency was twice as great as in the theoretical model. This was because of the reflected waves from the middle of the transmission line: in the experimental setup, the line was not homogeneous, as can be deduced from the additional peaks we received.

Finally, we present the comparison of the theoretical and empirical derivatives given in Table 3 and Figure 33. The timing of the peak derivatives seemed to fit much better the theoretical curve, and the location errors were much smaller. As noted previously, processing may improve the accuracy drastically.

**Table 3.** Distance calculations from the signal derivatives and respective location errors.


**Figure 33.** Comparison between the theoretical derivative and smoothed scope channel derivative.

#### **7. Synchronization between Sensors**

In order to take full advantage of the accuracy of the current method (see Table 4 and [2–4,31–33]) proper synchronization between sensors is required. Indeed, before measuring a transient phenomenon [34], an accurate method for measuring it must be chosen [35]. According to a broad literary review of a shelf product that will be used in the final device for synchronization between the measurements of the sensors, it was found that the White Rabbit Precision Time Protocol (PTP) was suitable for robust sub-nanosecond synchronization [36]. For a description of the characteristics of this technology, see [37–39].

**Table 4.** Comparison of fault location accuracy methods. DSE—distribution state estimation algorithm. SMT—synchronized measurement technology.


**Table 4.** *Cont.*


#### **8. Conclusions and Summary**

In the framework of the current research, a propagation of a short signal in a two-wire cable was investigated. It was shown that the short can be detected either by voltage or current measurements using the voltage/current first or second derivatives. The short can be detected either at the source or the load side. It was also shown that using bifurcations and reflection, the amount of detectors may be reduced. In order to achieve a high level of accuracy regarding the short's location, the inter-sampling duration should be of the nanosecond order (GHz sampling frequency). Of course, if there is no significant slope over a predetermined number of samples (say 1000 samples), there is no need to save them. Hence, the samples may be written as a moving window to some buffer register and deleted if the gradient is not significant. We also studied the phenomena of the dispersion of the short signal and determined in what cases it was significant.

Our method was based on the idea that in any system information even in the form of an electromagnetic wave will advance from one side of the system to the other in a fast, but finite velocity *v* stratifying *v* < *c*, where *c* is the speed of light in a vacuum. When considering a steady-state, we may neglect the propagation phenomena and employ lumped models; however, this is not applicable for short durations, as considered here.

The accuracy was significantly better in the retardation approach than in various methods mentioned in previous work. In Table 4, the accuracy of the different methods is compared.

It is expected that in the future, better wave sampling techniques and devices will be developed, as well as better processing methodologies, thus improving accuracy.

As the temporal difference between the fault signal arrivals and the width of the signal (see for example Figure A37) are much less by many orders of magnitude than the period of the AC voltage, one can assume that for all practical purposes, the AC signal is constant. Hence, we expect an AC experiment to yield similar results.

The above system description was derived for an electrical transmission line as the wave behavior is well known and there is considerable expertise in making the calculations; however, the same holds true for optical fibers and optical reflections, as well as for pipes, such as water, gas, or oil pipes, for which one can use acoustic echoes. The calculations for the fault's location are the same, although the propagation rates are different in the acoustic case. In the optical case, the equation *v* = *<sup>c</sup> <sup>n</sup>* still holds true. In both cases, underground pipes and underground fiber optic cables can be damaged at hard-to-reach locations, and an accurate determination of the fault's location is helpful in knowing where to start digging.

**Author Contributions:** Conceptualization, A.Y. and Y.P.; methodology, A.Y. and Y.P.; software, A.Y. and M.S.; validation, A.Y. and Y.P.; formal analysis, A.Y., Y.P. and M.S.; investigation, A.Y., Y.P. and M.S.; resources, A.Y. and Y.P.; data curation, M.S.; writing—original draft preparation, M.N.; writing—review and editing, A.Y.; visualization, A.Y., Y.P. and M.S.; supervision, A.Y. and Y.P.; project administration, A.Y. and Y.P. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research received no external funding.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** Not applicable.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **Appendix A. The Lumped Circuit Model**

The schematic description of the short circuit is presented in Figure A1.

**Figure A1.** Transmission line with a short.

This is modeled in Figure A2.

**Figure A2.** Short circuit example.

The parts of the transmission line before and after the short circuit are considered as a resistor and inductor connected in series. In order to mathematically analyze this, we used the Kirchhoff voltage law and Ohm's law:

$$\begin{array}{l} V\_{in}(t) = R\_1 I\_1(t) + L\_1 \frac{dI\_1(t)}{dt} + V\_S(t) \\ V\_S(t) = R\_2 I\_2(t) + L\_2 \frac{dI\_2(t)}{dt} + V\_{out}(t) \\ V\_{out}(t) = Z I\_2(t) \end{array} \tag{A1}$$

in which *Vin* is the source voltage, *I*<sup>1</sup> is the source current, *VS* is the short voltage, *I*<sup>2</sup> is the load current, and *Vout* is the load voltage. *R*<sup>1</sup> and *L*<sup>1</sup> are the resistance and inductance before the short, and *R*<sup>2</sup> and *L*<sup>2</sup> are the resistance and inductance after the short, while *Z* is the load impedance.

#### *Appendix A.1. The Case of Resistive Impedance*

In the first step, we ignored the inductance for mathematical simplicity. We also noticed that by Ohm's law:

$$V\_S(t) = R\_S(t)I\_S(t)\tag{A2}$$

where *RS*(*t*) is the time-dependent short resistance and *IS*(*t*) is the current flowing through the short. According to Kirchhoff's current law:

$$I\_{\mathbb{S}}(t) = I\_1(t) - I\_2(t) \tag{A3}$$

Thus, the currents in this case can be calculated algebraically as follows:

$$\begin{array}{l} I\_{1}(t) = \frac{Z + R\_{2} + R\_{S}(t)}{R\_{1} \cdot [Z + R\_{2} + R\_{S}(t)] + R\_{S}(t) \cdot (Z + R\_{2})} \cdot V\_{in}(t) \\\ I\_{2}(t) = \frac{R\_{S}(t)}{R\_{1} \cdot [Z + R\_{2} + R\_{S}(t)] + R\_{S}(t) \cdot (Z + R\_{2})} \cdot V\_{in}(t) \\\ I\_{S}(t) = \frac{Z + R\_{2}}{R\_{1} \cdot [Z + R\_{2} + R\_{S}(t)] + R\_{S}(t) \cdot (Z + R\_{2})} \cdot V\_{in}(t) \end{array} \tag{A4}$$

In the current model, the transmission line was a two-wire copper cable; each wire has a diameter *d*, and the distance between them is *D*; the cable is depicted in Figure A3. The total cable length is *l*. The values used for the demonstration are given in Table A1.

**Figure A3.** Cable geometry for the demonstration.

**Table A1.** Two-wire cable parameters.


The surface resistance in ohms (Ω) may be written as follows [29]:

$$R\_{Surface} = \sqrt{\frac{\omega \mu\_c}{2\sigma\_c}} = \sqrt{\frac{\pi f \mu\_c}{\sigma\_c}}\tag{A5}$$

In the above, *ω* is the angular frequency, *f* is the frequency, *μ<sup>c</sup>* is the magnetic permeability of the material, and *σ<sup>c</sup>* is the conductivity. Hence, the resistance per unit length [Ω/m] can be written as:

$$R = 2\frac{R\_{surface}}{2\pi r\_2^4} = 2\frac{R\_{surface}}{\pi d} \tag{A6}$$

The values used for the cable description appear in Table A2.

**Table A2.** Two-wire cable resistance.


We noticed that the value of *f* = 50 Hz used above is typical for many power lines. However, as the typical duration of the short is miniscule, the signal generated by the short will include a broad band of frequencies, each suffering a different impedance. This is dealt with in a later part of this paper. However, here, we assumed for simplicity that the resistance is constant.

The short circuit appears at distance *l*<sup>1</sup> from the input. The short-circuit *RS*(*t*) resistance is shown in Figure A3. The short is described by a time-dependent resistance, which was assumed to behave exponentially:

$$R\_S(t) = R\_{S0} e^{-\frac{t}{\frac{\pi}{4}}}.\tag{A7}$$

The initial resistance *RS*(0) = *RS*<sup>0</sup> was assumed to be very large and represents the region's air resistance. However, at time *t* = 0, a short is initiated, causing an exponential decrease in the short resistance at a typical duration of *τ<sup>S</sup>* = 10–100 ns, which depends on the conditions and geometry of the short-circuit region. The short-circuit parameters are concentrated in Table A3.


**Table A3.** Short-circuit parameters.

Thus, the current flows through the short instead of the load, causing a decrease in the load current. Moreover, since the overall impedance of the circuit decreases and is now dominated by the impedance of the short, the current at the source becomes much higher.

The transmission line resistances and the load impedance are described in Table A4.


**Table A4.** Transmission line resistance and load impedance.

The input voltage was assumed to be of the form:

$$V\_{in}(t) = A\_0 \cos(\omega\_0 t),\tag{A8}$$

where *A*<sup>0</sup> = 220 [V], *ω*<sup>0</sup> = 2*π f*<sup>0</sup> = 100*π* rad/s. We shall now present the calculation results.

#### Appendix A.1.1. Current

The source current just before the short is depicted in Figure A5 and after the short is depicted in Figure A6.

**Figure A5.** Source current before the short.

Hence, the current at the source is a highly sensitive indicator of the occurrence of a short. To avoid storing unnecessary data and for precise timing of the short's occurrence, one can look at the source current derivative (Figure A7); this has a distinctive pulse shape. Hence, by taking the derivative of the signal and by fixing a high detection threshold, one can avoid recording unnecessary data.

On the load side, the current vanishes after the short occurs (Figure A8); hence, the load current is also an excellent indicator of the short's occurrence.

**Figure A8.** Load current.

Again, we see that on the load side, the current behavior allows for identification of the short by taking the current derivative (Figure A9). This method allows precise timing with the need to store a small amount of data, as indicated above.

**Figure A9.** Load current derivative.

#### Appendix A.1.2. Voltage

The short circuit pulse may also be detected by the voltage measurement. For example, the voltage measured at half the distance between the source and the short will yield a voltage *V*<sup>1</sup> as follows:

$$V\_1(t) = V\_{in}(t) - \frac{1}{2}R\_1I\_1(t)\tag{A9}$$

This voltage is depicted in Figure A10.

**Figure A10.** Voltage at half the distance between the source and the short.

Again, the distinctive pulse shape of the voltage derivative (Figure A11) is apparent with the same advantage mentioned before.

**Figure A11.** Voltage derivative at half the distance between the source and the short.

The voltage at the short vanishes (Figure A12), since the resistance approaches zero during the short's creation, providing the same behavior, which allows the pulse form in the voltage derivative (Figure A13).

**Figure A13.** Voltage derivative at the short.

Similarly, the voltage *V*<sup>2</sup> at half the distance between the short and the load may be measured (Figure A14), and the pulse may be detected using the voltage derivative (Figure A15).

$$V\_2(t) = V\_s(t) - \frac{1}{2} R\_2 I\_2(t) \tag{A10}$$

**Figure A14.** Voltage at half the distance between the short and the load.

**Figure A15.** Voltage derivative at half the distance between the short and the load.

Summarizing the results of our first model, we saw that the current and voltage measurements enabled the short's pulse detection, indicating the short's occurrence. Likewise, it was shown that detection was possible both at the source and the load side. In order to detect the pulse, a resolution of the *τ<sup>S</sup>* order is needed. In the current model, the inductance was neglected, leading to a simplified description; in the next section, we will look at the case were induction is taken into account, leading to a somewhat more complex mathematical analysis. Moreover, in a lumped model, there is no pulse propagation along the transmission line, and for this purpose, we introduce a distributed model later in this paper.

#### *Appendix A.2. The Case of Resistive and Inductive Impedance*

In this model, the transmission line inductance is no longer neglected as in the previous section. Therefore, the equations given in (A1) become coupled differential equations that can only be solved numerically. The two-wire cable induction can be calculated and is shown in Table A5.


**Table A5.** Transmission line inductance.

The current in the circuit before the short occurs can be calculated analytically and is given as follows:

$$I\_{10}(t) = I\_{20}(t) = \frac{\mathbf{A}\_0 \cdot \mathbf{A}\_t}{\mathbf{Z} + \mathbf{R}\_\Gamma} \cdot \cos[\omega \cdot \mathbf{t} + \varphi\_\mathbf{t}] \tag{A11}$$

where: *At* <sup>≡</sup> <sup>1</sup> <sup>1</sup>+(*ω*·*τp*) <sup>2</sup> , *<sup>ϕ</sup><sup>t</sup>* ≡ −arctan[*<sup>ω</sup>* · *<sup>τ</sup>p*], *<sup>τ</sup><sup>p</sup>* <sup>≡</sup> LT <sup>Z</sup> . This current is depicted in Figure A16.

We now study the numerical solutions of Equation (A1) given the above initial form.

#### Appendix A.2.1. The Current

The source current is demonstrated in Figures A17 (right after the short) and A18 (a long time after the short).

**Figure A17.** Source current right after the short.

**Figure A18.** Source current a long time after the short.

**Figure A19.** The source current derivative.

In the previous model, the derivative had a pulse shape. In the current model, the first derivative did not exhibit a pulse shape (Figure A19); however, the second derivative (Figure A20) did exhibit a pulse shape with all the benefits mentioned previously.

**Figure A20.** The source current second derivative.

Current measurements on the load side also provide the short pulse detection ability. The load current is shown in Figures A21 (right after the short) and A22 (a long time after the short). Here, the current decay is evident.

**Figure A21.** Load current (right after the short).

**Figure A22.** Load current (after some time).

The current's first and second derivatives are shown in Figures A23 and A24, respectively.

**Figure A23.** The load current derivative.

**Figure A24.** The load current second derivative.

We see that the short may be detected and accurately timed by the current's second derivative, measured at either the source or the load side. Next, we investigated the current at the short itself. It is obvious that it is zero before the short happens, after which it grows linearly (Figure A25). After some time, the short current reaches the characteristic source current values (Figure A26).

**Figure A25.** Short current (right after the short).

**Figure A26.** Steady-state short current.

#### Appendix A.2.2. The Voltage

The short-circuit pulse may also be detected by the voltage measurement between the source and the short. If the voltage is measured at half a distance, due to a high short current, the voltage will be:

$$V\_1(t) = V\_{in}(t) - \frac{1}{2}R\_1I\_1(t) - \frac{1}{2}L\_1\frac{dI\_1(t)}{dt} \tag{A12}$$

The voltage and its derivative are shown in Figures A27 and A28, respectively. We deduced that for the voltage case, a first derivative will suffice for the short location even when inductance is not neglected.

**Figure A27.** Voltage at half the distance between the source and the short.

**Figure A28.** Voltage derivative at half the distance between the source and the short.

Figures A29 and A30 describe the voltage and its derivative at the short itself. We see that the voltage difference at the short when its resistivity goes to zero is also zero, and the pulse behavior of the voltage derivative is depicted.

**Figure A29.** The short voltage.

**Figure A30.** The short voltage derivative.

Analogous results may be obtained if the voltage is measured at the load side, even if the measurement is not at the load itself. For example, for half the distance voltage measurement, one obtains:

$$V\_2(t) = V\_s(t) - \frac{1}{2}R\_2I\_2(t) - \frac{1}{2}L\_2\frac{dI\_2(t)}{dt} \tag{A13}$$

Figures A31 and A32 show the voltage at half the distance between the short and the load. The voltage a brief duration after the short has formed is depicted in Figure A31, and a longer duration of the same is depicted in Figure A32.

**Figure A31.** Voltage at half the distance between the short and the load (right after).

**Figure A32.** Voltage at half the distance between the short and the load (after some time).

The voltage derivative displays a pulse behavior (Figure A33), and thus, in this case, a first derivative will suffice and a second derivative is not needed.

**Figure A33.** Voltage derivative at half the distance between the short and the load.

Finally, the load voltage is described, which is proportional to the load current (see also Equation (A1)):

$$V\_{out}(t) = Z \cdot I\_2(t) \tag{A14}$$

The load voltages, after a brief duration since the short's occurrence and later, are shown in Figures A34 and A35, respectively.

**Figure A34.** Load voltage (right after the short).

**Figure A35.** Load voltage (after some time).

The first and the second load voltage derivatives are shown in Figures A36 and A37. In this case, the desirable pulse shape was obtained for the second derivative.

**Figure A36.** Load voltage derivative.

**Figure A37.** Load voltage second derivative.

#### **Appendix B. Errors Received from the Smoothing Voltage and Derivative Smoothing Voltage Window**


**Figure A38.** Load voltage second derivative.

#### **References**


## *Article* **Application of Novel AC–AC Matrix VFD for Power Factor Improvement in Conventional AC–DC–AC VFD-Loaded Power Distribution Lines**

**Gytis Petrauskas 1,\*, Gytis Svinkunas 2, Audrius Jonaitis <sup>2</sup> and Andreas Giannakis <sup>3</sup>**


**Abstract:** In this study, an innovative approach to matrix-converter-based AC—AC variable frequency drives (VFDs) is introduced. The possibility of using AC–AC matrix VFDs for reactive power compensation in conventional AC–DC–AC VFD-loaded power distribution lines is investigated. It is found that the interaction of a large number of conventional AC–DC–AC VFDs with a conventional capacitor-based local compensation device leads to overcompensation in 0.4 kV power distribution lines. This is due to the fact that the conventional compensation device is designed to compensate the lagging reactive power produced by inductive loads, such as AC motors. This highlights the demand for the compensation of leading reactive power that is not predicted by the designer. To solve this problem, the modification of a certain number of previously installed VFDs by replacing their conventional AC–DC–AC converters with AC–AC matrix converters is proposed. This can lead to improvements in the power factor in 0.4 kV power distribution lines. In this study, the range of reactive power produced by conventional AC–DC–AC VFDs was determined mathematically, by simulation, and experimentally. The range of reactive power produced by the novel AC–AC matrix VFD was also determined. On that basis, the number of VFDs to be modified is defined to keep the power factor close to unity.

**Keywords:** matrix converter; space vector modulation; power factor; variable frequency drive

#### **1. Introduction**

Power generation and transmission are complex processes that require the interconnected operation of the components of the power system. The reactive power is one of the main components in the system. Loads such as electric motors require reactive power for their operation. To improve the performance of the AC power systems, this reactive power has to be managed. This is known as reactive power compensation [1].

Typically, the current in old-fashioned power distribution lines (PDL) lags behind voltage, because of inductive loads such as motors. Local reactive power compensation devices are usually designed to compensate the lagging reactive power [2].

The evolution of variable frequency drive (VFD) technology has changed the type of reactive power in 0.4 kV PDL. VFDs are finding increasing applications in various industrial and infrastructure sectors. The global VFD market size is expected to be 31.3 billion USD by 2025, from an estimated 19.2 billion USD in 2020, rising at a market growth of 6% for the mentioned forecast period.

A typical induction motor connected directly to a power distribution line is a lagging reactive power source. When connecting this motor via an AC–DC–AC frequency converter,

**Citation:** Petrauskas, G.; Svinkunas, G.; Jonaitis, A.; Giannakis, A. Application of Novel AC–AC Matrix VFD for Power Factor Improvement in Conventional AC–DC–AC VFD-Loaded Power Distribution Lines. *Electronics* **2022**, *11*, 997. https://doi.org/10.3390/ electronics11070997

Academic Editor: Giampaolo Buticchi

Received: 14 February 2022 Accepted: 22 March 2022 Published: 23 March 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

a conventional VFD is formed. This VFD, unlike the induction motor, produces the leading reactive power. Data on the reactive power produced by VFDs obtained experimentally are given below. Reactive power compensators, traditionally designed to compensate the inductive (lagging) reactive power, are not capable of compensating the leading reactive power produced by the VFD. It carries financial losses. Companies that are unable to compensate the VFD-produced reactive power pay fines. Some studies have suggested solutions to this problem. The authors of [3] proposed to compensate the reactive power using reactive elements. The authors of [4] defined power quality coefficients that determine the distortion caused by variable-speed asynchronous electric drives. The authors of [5] suggested the use of dynamic reactive power compensation equipment.

Recently, VFDs based on a novel matrix converter (MC) are becoming more widespread in buildings and industry. With the development of semiconductor technologies, the popularity of MC is constantly increasing. In the AC–AC matrix VFD, indirect space vector modulation (ISVM) is the most common way to control converter switches. Using this control method, the MC is virtually divided into two parts. The first part is the current source rectifier (CSR). The second part is the voltage source inverter (VSI). This division makes it possible to control the current displacement angle independently of the voltage on the motor side. Such a VFD connected to the PDL can control the reactive power at the connection point. With regard to the method of control mentioned above, the MC-based induction motor VFD has the ability to exchange both leading and lagging reactive power with the connected power distribution line. This means that the AC–AC matrix VFD can be used for conventional AC–AC–AC VFD-produced reactive power compensation. It is, therefore, proposed to replace the electronic equipment of one of the conventional VFDs installed in a commercial or industrial building. Instead of three stages (diode supply-side rectifier, intermediate DC circuit, and inverter), nine bidirectional electronic switches are installed, leaving the VFD induction motor the same. In this way, a PDL power factor close to unity can be achieved.

Some authors of the reviewed publications suggested using ISVM-controlled MC for reactive power compensation. The authors of [6] suggested the use of a permanent magnet machine powered by a MC as the compensation device. The authors of [7] proposed to connect the AC–AC matrix VFD to the PDL, thus compensating for the reactive power produced by light-emitting diode light sources. The authors of [8] proposed using an MC in combination with a transformer for power factor control. The authors of [9,10] presented a modulation strategy allowing the expansion of the MC reactive power range. The authors of [11] suggested the use of AC–AC matrix VFDs for voltage sag impact reduction. The only study that considered the reactive power in the induction motor MC VFD was [12]. However, the authors of this publication only proposed a control strategy that provides current control and a unity power factor. They did not measure the ability to compensate for the reactive power produced by other sources, such as conventional AC–DC–AC VFDs. Therefore, a comprehensive study of MC-based induction motor VFDs is needed to determine the range of reactive power compensation they provide before they can be put into practical application. The number of conventional AC–DC–AC VFDs whose reactive power can be compensated for by a single AC–AC matrix VFD must be determined. Furthermore, the effect of motor load torque and rotor speed on the reactive power of conventional AC–DC–AC VFDs must be investigated.

#### **2. Overcompensation Problem in Current Power Distribution Lines**

Typically, the current in conventional PDLs lags behind voltage, because of inductive loads such as AC motors (Figure 1a).

However, currently, as shown in Figure 1b, more and more AC motors are powered by AC–DC–AC frequency converters. One component of the conventional VFD directly connected to the PDL is the diode rectifier. As shown in Figure 2, another large and sensitive element is the electrolytic capacitor. The value of this capacitor is usually designed as 85 μF/kW. The range of voltage variation in such a case is 5–10% of the nominal voltage.

**Figure 1.** The loads and compensation devices of a 0.4 kV PDL: (**a**) conventional load equipment; (**b**) current load equipment (causes overcompensation).

#### *2.1. Theoratical Analysis of the Reactive Power Generated by Diode Rectifier Supply-Side Variable Frequency Drive*

The reactive power of such equipment directly depends on the voltage at the power distribution line connection point and the current of the diode rectifier (Figure 2).

**Figure 2.** Time diagrams of the voltage and current of single-phase diode rectifier supply-side VFD.

The input current of the AC–DC device, due to the large number of harmonics, is quite complex and can be described by the following Equation (1) [7]:

$$I\_{IN}(t) = I\_0 + I\_1 \sin(\omega t + \varphi\_1) + I\_2 \sin(\omega t + \varphi\_2) \tag{1}$$

The consumption or generation of reactive power depends on *I*1*sin*(*ωt* + *ϕ*1). Because of this, it must be expressed in a Fourier series, and *ϕ*<sup>1</sup> must be determined as follows:

$$\tan \varphi\_1 = \frac{I\_1''}{I\_1'} = \frac{(\pi - 2\theta - \sin 2\theta)}{(1 + \cos 2\theta)}.\tag{2}$$

In the case of *θ*<sup>1</sup> = 64◦, *ϕ*<sup>1</sup> = 19.1◦ when *k*<sup>V</sup> = 10%, tan *ϕ*<sup>1</sup> = 0.34. In the case of *θ*<sup>2</sup> = 72◦, *ϕ*<sup>2</sup> = 16.1◦ when *k*<sup>V</sup> = 5%, tan *ϕ*<sup>2</sup> = 0.28. These are the minimum and maximum limits of the current displacement angle. Since *ϕ*<sup>1</sup> > 0 and *ϕ*<sup>2</sup> > 0, it can be stated that the conventional AC–DC–AC VFD injects some amount of the leading reactive power into the PDL. It injects 0.28–0.34 kVar in the case of powering a 1 kW load.

For more powerful VFDs, a three-phase diode rectifier supply is used (Figure 3). An equation for the expression of the reactive power on the forward-conducting angle of the diodes can be derived for this rectifier.

**Figure 3.** Time diagrams of the voltage and current of three-phase diode rectifier supply-side VFD: (**a**) pure resistor load; (**b**) conventional VFD.

The voltage pulsations and current of diode rectifier-based devices can be described by the following common equations:

$$V\_A = V\_m \sin \omega t\_\prime \tag{3}$$

$$
\dot{q}\_{IN} \approx \mathbb{C} \frac{dV\_A}{dt} = \mathbb{C} \, V\_m \, \omega \, \cos \omega t. \tag{4}
$$

$$
\Delta V\_{\text{PULS}} = V\_{\text{MAX}} - V\_{\text{MIN}\prime} \tag{5}
$$

$$k\_V = \frac{\Delta V\_{PLL}}{V\_{MAX}}.\tag{6}$$

According to the technical requirements, the voltage pulsation *k*<sup>V</sup> on the DC capacitor is in the range of 5–10%. According to this, angle αON determines the moment forwardconduction of the VFD's supply-side diode rectifier.

$$\begin{array}{ll} V\_{\rm D\overline{C}} = & V\_A - V\_B = V\_m \sin \omega t - V\_m \sin(\omega t - 120^\circ) = 2 \cos \frac{\omega t + (\omega t - 120^\circ)}{2} \times \sin \frac{120^\circ}{2} = \\ & 2 \cos(\omega t - 60^\circ) \times \left(\frac{\sqrt{3}}{2}\right) = \sqrt{3} \cos(\omega t - 60^\circ) = \sqrt{3} \sin(\omega t + 30^\circ). \end{array} \tag{7}$$

The maximum value is obtained when *ωt* = 60◦ or 120◦, where *sin* (60◦ + 30◦ − *αON*) = 0.9–0.95. Therefore,

$$\mathfrak{a}\_{ON} = 26^{\circ}, \text{ at } k\_V = 10\%;$$

$$\mathfrak{a}\_{ON} = 18^{\circ}, \text{ at } k\_V = 5\%;$$

$$\mathfrak{a}\_{ON} = 13^{\circ}, \text{ at } k\_V = 2, 5\%.$$

The type of reactive power (leading or lagging) is determined by the component *i*<sup>1</sup> = *I*1*msin*(*ωt* + *ϕ*1) in the Fourier series (Equation (1)).

$$I\_{1}^{\prime} = \frac{1}{\pi} \int\_{60^{\circ} - \mathfrak{a}\_{\text{ON}}}^{60^{\circ}} \cos(\omega t + 30^{\circ}) \sin \omega t \, d\omega t + \frac{1}{\pi} \int\_{120^{\circ} - \mathfrak{a}\_{\text{ON}}}^{120^{\circ}} \cos(\omega t - 30^{\circ}) \sin \omega t \, d\omega t + \frac{1}{\pi} \int\_{240^{\circ} - \mathfrak{a}\_{\text{ON}}}^{300^{\circ}} \cos(\omega t - 30^{\circ}) \sin \omega t \, d\omega t.$$

$$\frac{1}{\pi} = \frac{1}{\pi} \int\_{60^\circ - \mathfrak{a}\_{\text{ON}}}^{60^\circ} \cos(\omega t + 30^\circ) \cos x dt \omega t + \frac{1}{\pi} \int\_{120^\circ - \mathfrak{a}\_{\text{ON}}}^{120^\circ} \cos \left(\omega t + 30^\circ \right) \cos x dt \omega t + \frac{1}{\pi} \int\_{300^\circ - \mathfrak{a}\_{\text{ON}}}^{300^\circ} \cos \left(\omega t - 30^\circ \right) \cos x dt \omega t.$$

$$\sigma\_1' = \frac{1}{2\pi} \left[ \sqrt{3} + \cos(150^\circ - 2a\_{ON}) - \cos(30^\circ - 2a\_{ON}) \right]. \tag{10}$$

$$I\_1'' = \frac{1}{2\pi} \left[ \frac{4\sqrt{3}}{2} - \sin(150^\circ - 2a\_{\rm ON}) \right. \\ \left. - \sin(210^\circ - 2a\_{\rm ON}) \right] \tag{11}$$

$$\tan\varphi\_1 = \frac{\frac{1}{2\pi}\left(2\sqrt{3}a\_{ON} - \sin(150^\circ - 2a\_{ON}) + \sin(30^\circ - 2a\_{ON})\right)}{\frac{1}{2\pi}\left(\sqrt{3} - \cos(150^\circ - 2a\_{ON}) - \cos(30^\circ - 2a\_{ON})\right)}.\tag{12}$$

According to Equation (12),

*I*

$$\begin{aligned} \varkappa\_{ON} &= 13^{\circ}, \; k\_V = 2, 5\%, \; \varrho\_1 = 8.86^{\circ}, \; \tan \varrho\_1 = 0.152, \\\varkappa\_{ON} &= 18^{\circ}, \; k\_V = 5\%, \; \varrho\_1 = 11.98^{\circ}, \; \tan \varrho\_1 = 0.22, \\\varkappa\_{ON} &= 26^{\circ}, \; k\_V = 10\%, \; \varrho\_1 = 17.27^{\circ}, \; \tan \varrho\_1 = 0.311. \end{aligned}$$

The results of the calculation show that, at the same pulsation level, the three-phase rectifier generates less reactive power than the single-phase rectifier.

#### *2.2. Experiemntal Analysis of the Reactive Power Generated by Diode Rectifier Supply-Side Ariable Frequency Drive*

The experimental analysis of the reactive power in the VFD loaded PDL was performed with a METREL MI 2892 power quality analyzer. That instrument records all measurement (Classic and Modern), regardless of selected method. This device complies with the measurement methods defined in the IEEE 1459 standard. The old measurement methods were applicable when currents and voltages were close to sinusoidal ones. However, they are not suitable for modern measurements when we have power electronics equipment such as VFD representing a nonlinear load for industrial and commercial PDL. The methodology used in this study measures the fundamental and nonfundamental components separately, as shown in Figure 4.

The experimentally obtained results of power analysis are presented in Table 1 (singlephase supply AC-DC-AC VFD) and in Table 2 (three-phase supply AC-DC-AC VFD). The following power distribution line voltage parameters were investigated:


**Figure 4.** The power management organization according to the IEEE1459.

**Table 1.** Power components at the point of connection of Siemens Micromaster 420 single-phase diode rectifier supply-side VFD to the PDL, keeping motor load torque constant.


**Table 2.** Power components at the point of connection of Rockwell Automation Power Flex 70 threephase diode rectifier supply-side VFD to the PDL, keeping motor load torque constant.


The forward-conducting and reverse-blocking angles of the VFD's supply-side diode were determined from the experimental voltage and current time diagrams presented in Figure 5. These data are consistent with the theoretical assumptions (Figure 2) and with the data from the mathematical calculations performed according to Equation (2). According to the experimental data, the forward-conducting angle was 72.6◦, leading to the calculation of tan(*ϕ*) = 0.28. A similar result can be obtained from the ratio of the reactive power of fundamental harmonics to the active power of fundamental harmonics measured experimentally using a power quality analyzer: tan(*ϕ*) = *Q*VFund/*P*Fund = 17.6/67.4 = 0.26.

**Figure 5.** Current and voltage time diagrams at the point of connection of Siemens Micromaster 420 single-phase diode rectifier supply-side VFD to the PDL, with a motor supply voltage frequency of 50 Hz.

The forward-conducting and reverse-blocking angles of the VFD's supply-side diode were determined from the experimental voltage and current time diagrams presented in Figure 6. These data confirm the theoretical assumptions presented in Figure 3. These data were also compared with the data of the mathematical calculations performed according to Equation (12). A similar result can be obtained from the ratio of the reactive power of fundamental harmonics to the active power of fundamental harmonics measured experimentally using a power quality analyzer: tan(ϕ) = *Q*VFund/*P*Fund = 108/522 = 0.20. Thus, the ratio is higher than the theoretical one.

**Figure 6.** Current and voltage time diagrams at the point of connection of Rockwell Automation PowerFlex 70 three-phase diode rectifier supply-side VFD to the PDL, with a motor supply voltage frequency of 50 Hz.

The reactive power produced by AC–DC–AC VFDs cannot be compensated by using a conventional capacitor-based local compensation device. In this case, a universal compensation device is required, which has the ability to compensate for both types of reactive power: leading and lagging.

Inductive reactors designed to reduce harmonic distortion can perform the function of compensating the reactive power produced by VFDs. However, this method of compensation has significant drawbacks. The first disadvantage is the cost of compensation equipment due to the high cost of ferrous metals. Another drawback is the high energy loss. A third disadvantage is the high weight and dimensions of the compensation equipment. These drawbacks are evident in Table 3, which presents the data for mass-produced reactive power compensation reactors.

The use of an induction motor powered by an MC as the universal compensation device was researched. Depending on the structure of the converter and the specific controls, it can be said that AC–AC matrix VFDs may be suitable for both leading and lagging reactive power compensation.


**Table 3.** Inductive reactors of Schneider electric designed for 400 V, 50 Hz PDL.

#### **3. Special Features of the AC–AC Matrix VFD**

The researched compensation device consisted of an MC, whose input was connected to the PDL and powered the induction motor (Figure 7). The MC used the forced switching of nine bidirectional switches. These nine switches generated the supply voltage to the motor stator windings of the required frequency. Unlike conventional AC–DC–AC VFDs, the AC–AC matrix VFD contains no capacitors. These nine bidirectional switches created combinations of 27 active, passive, and zero vectors, as shown in Table 4.

**Figure 7.** Functional diagram of MC-based induction motor VFD.

**Table 4.** Active combinations created by nine bidirectional switches.


Using the ISVM control method, the required stator winding voltage and PDL current were generated from the active and zero vectors. Figure 8 shows the active vectors produced from the previously presented combinations.

**Figure 8.** Graphics of the active vectors presented in Table 4: (**a**) graphic of the motor stator windings voltage vectors; (**b**) graphic of the PDL current vectors.

The motor stator winding voltage and PDL current are formed from two certain sector vectors. The frequency of MC motor supply voltage is determined by the angle *Q*SC, and the current displacement at the connection to the PDL point is determined by the angle *Q*SV [7].

$$Q\_{\mathbb{S}\mathbb{C}} = (\omega\_{\text{i}}t - q\_{\text{in}}) + \mathfrak{A}0^{\circ},\tag{13}$$

$$- \Re 0^{\circ} \le \omega\_i t - \varrho\_{in} \le + \Re 0^{\circ},\tag{14}$$

where *t* is the time for synchronization with the PDL frequency, and *ϕin* is the current displacement angle.

#### **4. Application of the AC–AC Matrix VFD as the Reactive Power Compensation Device**

To improve the power factor in current 0.4 kV PDLs, it is proposed to replace some of the conventional AC–DC–AC VFDs with the novel AC–AC matrix VFD, as presented in Figure 9.

**Figure 9.** The structure of researched system.

As described above, the main difference between conventional AC–DC–AC VFDs and the AC–AC matrix VFD is related to electronic power circuits and control. The conventional AC–DC–AC VFD power circuits consist of a diode supply-side rectifier, an intermediate DC circuit, and an inverter. The AC–AC matrix VFD power circuits consist of nine bidirectional electronic switches based on IGBT. As shown by the theoretical calculations, initial experimental study, and initial simulation in Matlab/Simulink, the conventional AC–DC–AC VFD produces leading reactive power at the point of connection to the PDL. Moreover, theoretical calculations and initial simulations in Matlab/Simulink showed that the AC–AC matrix VFD has the ability to directly control the reactive power produced at the point of connection to the PDL. When these VFDs are connected to the same PDL, the matrix VFD must compensate for the reactive power produced by the conventional AC–DC–AC VFD. It is, therefore, proposed to replace the electronic equipment of one of the conventional VFDs installed in a commercial or industrial building. Instead of three stages (diode supply-side rectifier, intermediate DC circuit, and inverter), nine bidirectional electronic switches are installed, leaving the VFD induction motor the same. In this way, a PDL power factor close to unity can be achieved. By using the AC–AC matrix VFD, the transfer of active power to the motor and the reactive power compensation are performed simultaneously. A Matlab/Simulink simulation study was performed to determine the reactive power compensation range of the system shown in Figure 9.

The input current and motor supply voltage of the MC can be described by the following equations [13]:

$$I\_{IN} = \frac{\sqrt{3}}{2} \ I\_{OUT} \ m \cos q\_{OUT} \tag{15}$$

$$V\_{OUT} = \frac{\sqrt{3}}{2} \; V\_{IN} \; m \cos \varphi\_{IN\prime} \tag{16}$$

where *IIN* is the MC input current, *VOUT* is the MC motor supply voltage, *m* is the modulation index, *ϕIN* is the input displacement angle, and *ϕOUT* is the motor supply displacement angle.

The AC–AC matrix VFD electronic switches were simulated using standard lossless Matlab/Simulink blocks. On the basis of Equations (15) and (16), the power equation of the AC–AC matrix VFD was derived as follows:

$$P\_{IN} = \frac{3}{2} V\_{\text{PDL}} I\_{IN} \cos \varphi\_{IN} = P\_{\text{OUT}} = \frac{3}{2} V\_{\text{OUT}} I\_{\text{OUT}} \cos \varphi\_{\text{OUT}} \tag{17}$$

where *VPDL* is the voltage of the PDL, and *fPDL* is the frequency of the PDL.

From Equation (15), it can be seen that an increase in the induction motor winding current displacement angle *ϕOUT* causes a decrease in PDL branch current *IIN*. From Equation (16), it can be seen that an increase in the PDL current displacement angle *ϕIN* causes a decrease in induction motor winding voltage *VOUT*.

According to Equation (17), it can be seen that the active power of the AC–AC matrix VFD must be a constant value, thereby ensuring the operation of the powered induction motor. To ensure constant *POUT* in the case of variable cos *ϕIN*, the motor supply voltage *VOUT* must be regulated within a certain range. To achieve this, constant *POUT* can be maintained during the control of the modulation index *m* (0–1).

For application of the AC–AC matrix VFD as the reactive power compensation device, the lower point of *VOUT* at induction motor stator windings was determined.

$$V\_{OUT} = \frac{V\_{IN}}{\sqrt{3}}.\tag{18}$$

The voltage was reduced to extend the modulation limits. To reduce voltage, the stator windings have to be connected in a delta arrangement (Δ).

The voltage ratio of the induction motor to ensure reactive power compensation is as follows:

$$\frac{V\_{OUT}}{V\_{PDL}} = \frac{1}{\sqrt{3}} = 0.58.\tag{19}$$

According to Equation (16),

$$\frac{\sqrt{3}}{2}\,\,m\cos q\_{IN} = 0.58\,,\tag{20}$$

$$
\hbar m \cos \varphi\_{IN} = 0.67.\tag{21}
$$

The following equations determine the limits within which m and *ϕIN* vary:

$$0.67 < m < 1,\tag{22}$$

$$0 < \wp\_{IN} < 48^{\circ}.\tag{23}$$

$$0 < \tan \varrho\_{IN} < 1.1.\tag{24}$$

Equation (21) is valid only if the AC–AC matrix VFD motor supply voltage frequency corresponds to the PDL voltage frequency. In the event that the MC motor supply voltage frequency is not constant, one possible condition is

$$\frac{V\_{OUTf}}{f\_{OUT}} = \text{const.}\tag{25}$$

In the case of a VFD load with constant torque variation, the following equations apply:

$$V\_{outf} = \frac{f\_{OUT} \cdot V\_{OUT}}{f\_{PDL}},\tag{26}$$

$$\frac{f\_{\text{OUT}} \cdot V\_{\text{OUT}}}{f\_{\text{PDL}}} = \frac{\sqrt{3}}{2} \,\, V\_{\text{IN}} \,\, m \cos q\_{\text{IN}\_{\text{V}}} \tag{27}$$

$$
\varepsilon m \cos \varphi\_{IN} = 0.6 \mathcal{T} \times \frac{f\_{\text{OUT}}}{f\_{\text{PDL}}}.\tag{28}
$$

Equation (28) shows that the ability to adjust the angle increases if the motor operating frequency *f OUT* is lower than the frequency of the power distribution line. In the case of an AC–AC matrix VFD load with squared torque variation, the following equations apply:

$$V\_{outf} = V\_{OUT} \left(\frac{f\_{OUT}}{f\_{PDL}}\right)^2,\tag{29}$$

$$m \cos q\_{IN} = 0.67 \times \left(\frac{f\_{OUT}}{f\_{PDL}}\right)^2. \tag{30}$$

As shown in Equation (30), it is possible to further adjust the angle *ϕIN* under squared torque load. However, the reactive power is determined not only by the angle *ϕIN*, but also by the active power *POUT* of the AC–AC matrix VFD. As the active power decreases, the reactive power also decreases, unless this is compensated for by an increase in allowable compensation angle *ϕIN*. Assuming that the AC–AC matrix VFD motor is always loaded at the maximum allowable torque, when the AC–AC matrix VFD operating frequency is varied, the motor current remains at the maximum permissible *IOUT*.

$$P\_{\rm OUT} \sim \frac{f\_{\rm OUT}}{f\_{\rm PDL}} V\_{\rm OUT} I\_{\rm OUT}.\tag{31}$$

Keeping the active power at a nominal speed of 100%, the reactive power of the AC–AC matrix VFD at variable speed was calculated. On the basis of Equations (28) and (30), the compensation angles *ϕIN* were calculated. The tan*ϕIN* and the reactive power *Q* required for compensation were calculated on the basis of the compensation angles.

The calculation results presented in Figure 10 show that, as the frequency of the AC–AC matrix VFD decreases, the reactive power increases. Thus, a decrease in the operating frequency of the VFD increases the possibility of reactive power compensation. Reactive power compensation is available over the entire operating frequency range of the AC–AC matrix VFD.

**Figure 10.** Relative active and reactive power at the point of AC–AC matrix VFD connection to the PDL as a function of the VFD operating frequency in the cases of VFD load with constant torque and squared torque variation.

#### *4.1. Structure of the Matlab/Simulink Model for Simulating the AC–AC Matrix VFD*

The Matlab/Simulink models of the reactive power compensation systems consisted of three pieces (Figure 11).

**Figure 11.** Structure of the AC–AC matrix VFD Matlab/Simulink model.

The first part consisted of PDL simulation blocks that simulated 10/0.4 kV transformer and PDL cables using the following standard Matlab/Simulink blocks: ideal sinusoidal AC voltage source and three-phase series RLC branch.

The second part consisted of Matlab/Simulink blocks for simulating MC power circuits (Figure 12) using standard blocks simulating an IGBT device in parallel with a series RC snubber. In the second part, space vector modulation control modules were also attached [14]. Subsystems running Park and Clarke transformations were used for this purpose. The sector separation subsystem was implemented using standard Matlab/Simulink logic and comparison blocks.

The third part consisted of Matlab/Simulink blocks for simulating the MC-powered induction motor according to an equivalent diagram of the induction motor [15] using standard blocks simulating a three-phase series RL branch.

For recording the active and reactive power data, the PLL-driven, positive-sequence block was used to record the positive-sequence active power P (W) and reactive power Q (var) of a periodic set of voltages and currents.

**Figure 12.** Structural diagram of the nine ideal bidirectional switches in Matlab/Simulink model.

#### *4.2. Structure of the Matlab/Simulink Model for Simulating the Conventional AC–DC–AC VFD*

The Matlab/Simulink model of the conventional AC-DC-AC VFD consisted of four parts. The first part of this model used a standard Matlab/Simulink block to simulate the full-bridge three-phase diode rectifier connected to the PDL using a universal bridge mask Matlab/Simulink block, in which the "power electronic device—diode" settings were applied. The second part implemented the capacitor bank of the DC circuit using a parallel RLC branch Matlab/Simulink block, in which the "branch type—C" settings were applied. The third part consisted of a Matlab/Simulink block implementing an IGBT full-bridge three-phase inverter using a universal bridge mask Matlab/Simulink block, in which the "power electronic device—IGBT/diode" settings were applied. The "PWM generator 2 level" block was also used to control the inverter. The fourth part consisted of Matlab/Simulink blocks for simulating the AC–DC–AC powered induction motor according to an equivalent diagram of the induction motor using standard blocks simulating a three-phase series RL branch.

#### *4.3. Reactive Power Compensation Limits of the AC–AC Matrix VFD*

The reactive power produced by the MC-based VFD depends directly on the current displacement angle at the point of connection to the PDL. This compensation range was determined by way of Matlab/Simulink simulations. The values of reactive power were determined by keeping the real power transferred to the induction motor constant. As a result, changes in real power caused by current displacement angle changes (rectifier stage) were compensated for by voltage modulation index correction (inverter stage).

These ranges of reactive power compensation are quite wide because an extension of these limits was applied. While the VFD's MC was connected to a 400 V line-to-line PDL, the induction motor windings were connected in a "delta" arrangement and powered by 230 V line-to-line voltage. This enabled changing the ISVM modulation index within a wider range. Consequently, at a displacement angle of zero, the modulation index was significantly reduced. However, when the displacement angle increased, there was a much wider voltage correction range due to the delta connection.

The simulation results presented in Figure 13 clearly show that, using the MC-based VFD, the reactive power can be compensated for in both directions (leading and lagging), depending on the current displacement angle.

**Figure 13.** The reactive power compensation ranges of the 15 kW MC-based VFD connected to 0.4 kV PDL.

The simulation results presented in Figure 13 show that the possible displacement angles ranged from −44◦ to +47◦. MC-based VFD control in this angle range allowed the real power transferred to the motor to be kept constant. For the 15 kW induction motor, the reactive power produced at these displacement angles varied from the leading 14.7 kVar to the lagging 15.7 kVar. Increasing the displacement angle above this specified range led to a decrease in the voltage at the induction motor stator windings and a decrease in the real power transferred to the induction motor.

As mentioned previously, the voltage drop due to the displacement angle change has to be recovered by increasing the value of the modulation index. Upon reaching the limits determined by the displacement angle specified range, the modulation index reaches its maximum value (shown in Table 5) and cannot recover a voltage drop caused by a further increase in the current displacement angle.

**Table 5.** Reactive power at the point of the VFD connection to the PDL.


These simulation results were confirmed by mathematical calculation according to Equation (21). The influence of the indirect space vector modulation control method was mathematically evaluated. The modulation index calculated to compensate for the voltage drop across the delta-connected induction motor windings was calculated using Equation (21) as presented in Figure 14.

**Figure 14.** ISVM modulation index for voltage drop recovery.

#### *4.4. Compensation of Reactive Power Produced by Conventional AC–DC–AC Variable Frequency Drives*

In order to evaluate the ability of the AC–AC matrix VFD to compensate the reactive power produced by conventional AC–DC–AC VFDs and keep the power factor close to unity, a Matlab/Simulink model was used. As shown in Figure 15, the model included a 0.4 kV PDL branch to which one AC–AC matrix VFD and a number of conventional AC–DC–AC VFDs were connected. The 15 kW induction motors were powered by the MC converter and by conventional AC–DC–AC frequency converters.

**Figure 15.** The researched system for conventional AC–DC–AC VFD reactive power compensation.

In the course of the study, the number of conventional AC–DC–AC VFDs was varied from one to seven. To compensate the leading reactive power in the PDL produced by the conventional AC–DC–AC VFDs, the current displacement angle of the AC–AC matrix VFD was regulated within the permissible limits.

As mentioned above, an increase in the current displacement angle caused a decrease in the voltage of the MC-powered induction motor stator winding and a decrease in transferred active power. This is directly related to ISVM control, which is applied as the main control strategy for AC–AC matrix VFDs. To recover this decrease, the modulation index was increased. This allowed the active power that was transferred to the induction motor by the MC constant to be maintained. However, the Matlab/Simulink simulation shows that the limits for the MC motor supply voltage recovery by the modulation index were not wide enough. As shown in Table 5, the current displacement angle and modulation index of the ISVM had to be significantly increased as the number of conventional AC–DC–AC

VFDs increased. When connecting more than six conventional AC–DC–AC VFDs, the modulation index had to be increased to the maximum allowed value. The unchanged active power transferred to the induction motor was maintained. However, under such conditions, the AC–AC matrix VFD could no longer fully compensate for the reactive power and maintain the unity power factor. Therefore, it can be argued that an ISVM-controlled AC–AC matrix VFD can only compensate for the reactive power produced by up to six conventional AC–DC–AC VFDs.

The relationship between the reactive power produced by the AC–DC–AC VFD at the point of VFD connection to the PDL and the motor load torque was investigated using the Matlab/Simulink simulation. This relationship was formed at different motor stator winding voltage frequencies and different rotor speeds. The simulation results are shown in Figure 16. Accordingly, it can be stated that VFD produces leading reactive power with varying motor load torque and rotor speed. The value of this reactive power depends directly on the motor load torque and rotor speed. This assumes that the proportions between the number of novel AC–AC matrix VFDs connected to the PDL and the number of conventional AC–DC–AC VFDs will remain similar to those described in Table 5 to maintain the power factor close to unity with varying motor load torque and rotor speed.

**Figure 16.** The reactive power at the point of single AC–DC–AC VFD connection to the PDL as a function of motor load torque.

#### **5. Discussion**

The idea to conduct this study arose from the observation of reactive power compensation problems in large building PDLs. It was observed that the interaction of a number of conventional AC–DC–AC VFDs with a conventional capacitor-based local compensation device leads to overcompensation in the 0.4 kV PDLs of the Kaunas Arena building. Capacitive reactive power compensators are installed in this building. This is due to the fact that conventional compensation devices are designed to compensate for the lagging reactive power produced by inductive loads, such as AC motors. This highlighted the demand for the compensation of capacitive reactive power that is not predicted by the designer.

Theoretical calculations show that a conventional AC–DC–AC VFD generates leading reactive power equal to about 30% of real power. Experimental studies confirmed this. This leading reactive power is produced by both single-phase and three-phase supply AC–DC–AC VFDs. Thus, this study is relevant and timely, as confirmed by the example provided above.

Energy companies have proposed installing large quantities of inductive reactors for power factor improvement. First of all, this is not ecologically acceptable due to the high consumption of nonferrous metals. Another shortcoming would be a significant financial cost for the company operating the Kaunas Arena building. The use of AC–AC matrix VFDs would avoid both of these disadvantages.

An AC–AC matrix VFD operating as the reactive power compensation device has another obvious advantage over capacitor-based compensation devices, namely there is no need to use large capacitors. This is an advantage in terms of volume and reliability.

Another important application of the AC–AC matrix VFD is the voltage regulation of the distribution grid. Due to the rapidly evolving solar energy, the distribution grid faces the problem of voltage fluctuations, which can be solved by using the AC–AC matrix VFD as a static reactive power compensator. A particularly important feature of this compensator is that it can generate both lagging and leading power. Future studies will investigate the application possibilities of AC–AC matrix VFD bidirectional reactive power in detail.

#### **6. Conclusions**

Due to its specific properties, a conventional AC–DC–AC VFD generates leading reactive power. From a technical point of view, this reactive power can be compensated for by induction reactors. However, the high cost, weight, and dimensions of these reactors make this method of compensation unusable. As a result, it was proposed to replace a certain number of conventional AC–DC–AC VFDs with AC–AC matrix VFDs. Studies have shown that, in this way, it is possible to bring the power factor closer to unity.

The application of indirect space vector modulation provides an opportunity to control the current displacement angle of the MC independently from the voltage of the PDL. As a result, the AC–AC matrix VFD can be applied for reactive power compensation. It was determined that the AC–AC matrix VFD can provide the appropriate amount of both leading and lagging reactive power. This feature assumes the application of this AC–AC matrix VFD as the reactive power compensation device.

An increase in the current displacement angle causes a decrease in the voltage of the stator windings and active power transferred to the induction motor. To recover this voltage decrease, the modulation index of the ISVM has to be increased. The determined applicable displacement angle ranges from −44◦ to +47◦. To maintain constant power transfer to the motor, the range of the current displacement must not exceed the determined range.

The AC–AC matrix VFD has the ability to compensate for the reactive power produced by conventional AC–DC–AC VFDs that capacitor-based local reactive power compensation devices cannot compensate for. A single AC–AC matrix VFD has the ability to compensate for the reactive power produced by six conventional AC–DC–AC VFDs with the same nominal power.

The compensation power value of the innovative AC–AC matrix VFD is independent from the drive load and frequency. This AC–AC matrix VFD can perform reactive power compensation, even when the VFD operation mode changes.

**Author Contributions:** Conceptualization, G.P.; methodology, G.S.; software, G.P.; validation, G.S. and G.P.; formal analysis, G.S.; investigation, G.S. and G.P.; resources, G.P., G.S. and A.J.; data curation, G.S.; writing—original draft preparation, G.P. and G.S.; writing—review and editing, A.J. and A.G.; visualization, G.P.; project administration, A.J.; funding acquisition, A.J. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was supported by the European Economic Area (EEA) and Norway Financial Mechanism 2014–2021 under Grant EMP474.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


### *Article* **A Fault Detection Method of IGBT Bond Wire Fatigue Based on the Reduction of Measured Heatsink Thermal Resistance**

**Dan Luo 1, Minyou Chen 1, Wei Lai 1,\*, Hongjian Xia 1, Zhenyu Deng 2, Zhi Wang <sup>1</sup> and Kai Yu <sup>3</sup>**


**Abstract:** Bond wire lift-off is one of the major failure mechanisms in the insulated gate bipolar transistor (IGBT) modules. Detecting the fault of bond wires is important to avoid the open-circuit fault of IGBT to ensure the reliable operation of power converters. In this paper, we propose a novel bond wire fatigue detection method for IGBT, which could be used in normal working conditions. Firstly, we investigated the dependence of bond wire fatigue on heatsink thermal resistance. An aging rate K was proposed to compare the measured thermal resistance with the initial value, which could indicate the bond wire fatigue. Then, this proposed method was verified by simulation and experimental results under different current levels. Finally, a power cycling test was used to show the aging process of the IGBT module, which shows the feasibility of proposed method.

**Keywords:** IGBT; bond wire fatigue; Heatsink thermal resistance; fault detection; heat flow

#### **1. Introduction**

Power converters are widely used with the rapid development of renewable energy [1]. As the key component of power converters, insulated gate bipolar transistors (IGBTs) are the most adopted power devices [2] according to the demand for operational reliability, energy efficiency, and cost competitiveness.

Figure 1 shows the structure of wire-bonded IGBT, which consists of several layers of different materials. IGBT die is soldered on the direct-bonded copper (DBC) plate, and the DBC plate is soldered on the baseplate. The silicon IGBT die is connected to the substrate by several paralleled aluminum bond wires. As a result of physical limits, a coefficient of thermal expansion (CTE) mismatch occurs between silicon die and aluminum bond wires, causing swelling stress and shrinkage stress during power cycling and finally leading to the bond wire lift-off [3]. Bond wire lift-off is one of the domain failure mechanisms of the IGBT module [4], and it usually appears in the last 10% of the remaining life stage of the module. High-junction temperature fluctuations [5] and high-frequency operation [6] will also accelerate the aging of bond wires. The failure of bond wires in IGBT will easily lead to open-circuit faults and cause damage to the whole system [7]. Consequently, the reliability of bond wires is important for the IGBT module.

The fault detection method could obtain the state of the device, which is important to ensure the safe operation of power converters. Many bond wire failure detection methods have been proposed in recent studies. J. Lehmann [8] presented a modified DCB layout in an IGBT module to measure the fatigue of bond wires. This method needs to change the structure of the IGBT module to set the auxiliary circuit inside. H. Shiratsuchi [9] and H. Tomonaga [10] proposed to monitor IGBT current distribution by the magnetic field, which could be used to show the status of bond wires [11]. These sensors need

**Citation:** Luo, D.; Chen, M.; Lai, W.; Xia, H.; Deng, Z.; Wang, Z.; Yu, K. A Fault Detection Method of IGBT Bond Wire Fatigue Based on the Reduction of Measured Heatsink Thermal Resistance. *Electronics* **2022**, *11*, 1021. https://doi.org/10.3390/ electronics11071021

Academic Editor: Hamid Reza Karimi

Received: 9 March 2022 Accepted: 23 March 2022 Published: 24 March 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

to be integrated into the module to measure the magnetic field. Such methods are capable of detecting the bond wire fatigue; however, the invasive modifications or sensors would bring unpredictable reliability issues to the power module itself. To overcome such challenges, non-invasive detection methods are also proposed. The fatigue of bond wires changes the electrical gate charge circuit, which finally affects the switching process. Hence, these parameters have been used by several researchers to indicate the fault of bond wires, such as gate current [12], charging time [13], transconductance [14], and stray inductance [15]. Although those methods are non-invasive and only gate voltage needs to be measured, the sensitivity and accuracy of the measured results could be easily affected by the high sampling frequency and resolution of gate signal [16]. The on-state voltage of IGBT is independent of the junction temperature at the inflection point, which has a zero-temperature characteristic. Hence, U. Choi [17], A. Singh [18], and M. Du [19] used the conduct voltage at the inflected point with special gate voltage to measure bond wire lift-off, while P. Sun [20] measured the short-current at special gate voltage. Although these methods showed adequate sensitivity to detect the bond wire fault irrespective of the junction temperature, they could only be used at abnormal working conditions. In general, the weaknesses of those detection methods lead to an increase in costs and complexity in normal operations. Therefore, a more convenient detection method is still needed to reflect the health status of bond wires in IGBT modules in normal working conditions.

To address this challenge, a novel method is proposed in this paper to detect the bond wire fatigue based on the heatsink thermal resistance decrement, which could be used in normal conditions. Two aspects are demonstrated as follows. (1) The effect of IGBT bond wire lift-off on heatsink thermal resistance measurement is presented. The measured results decrease due to the heat flow of bond wires. (2) A fault detection method based on the reduction in measured heatsink thermal resistance is proposed. In this method, the fault of bond wires is indicated after a decrease in measured results of heatsink thermal resistance, which is independent of the working conditions. By these means, the fault of bond wires could be conveniently detected to avoid open-circuit fault in normal conditions.

The rest of this paper is organized as follows. Our detection method is proposed in Section 2. A multi-physics field FEM model is established to analyze the effect of bond wire lift-off in Section 3. The experimental results verify this method in Section 4. A power cycling test is used to show the aging process in Section 5. Section 6 concludes this paper.

#### **2. Failure Mechanism and Detection Method**

#### *2.1. Effect of Bond Wire Lift-Off on Heatsink Thermal Resistance Measurement*

Power loss of die *P*<sup>D</sup> is far greater than bond wires *P*WB in a healthy module [17]; hence, IGBT die is the major heat source in the IGBT module *P*loss, while the power loss of bond wires is nearly negligible (Equation (1)). The heat mainly concentrates under die and transfers through each layer to the baseplate, and dissipates to the ambient temperature by the heatsink, as shown in Figure 2a.

$$P\_{\rm loss} = P\_{\rm D} + P\_{\rm WB} \stackrel{P\_{\rm D} \gg P\_{\rm WB}}{\approx} P\_{\rm D} \tag{1}$$

**Figure 2.** (**a**) Heat flow in healthy module. (**b**) Thermal network of healthy module.

The case temperature *T*<sup>C</sup> rises when the power loss *P*loss flows through the heatsink to ambient *T*A, which is related to the equivalent thermal resistance of heatsink *Z*E\_HS, as in Equation (2).

$$T\_{\mathbb{C}} = P\_{\text{loss}} \cdot Z\_{\text{E\\_HS}} + T\_{\text{A}} = P\_{\text{D}} \cdot Z\_{\text{E\\_HS}} + T\_{\text{A}} \tag{2}$$

The thermal network in the healthy module is shown in Figure 2b. The power loss of die transfers through the IGBT module *Z*JC and heatsink *Z*HS to the ambient. Hence, the measured thermal resistance of heatsink could be obtained based on (3), which equals the theoretical value of equivalent thermal resistance of heatsink *Z*E\_HS on the case point.

$$Z\_{\rm E\\_HS} = \frac{T\_{\rm C} - T\_{\rm A}}{P\_{\rm loss}} = Z\_{\rm HS} \tag{3}$$

However, the total resistance of parallel bond wires increases after bond wire liftoff [21] which leads to a power loss increase in the remaining bond wires *P*WB [20], as in Equation (4), where *R*WB is the resistance of a single bond wire, *I*<sup>C</sup> is the conduction current, *N*wire is the number of total bond wires, and *N*fail is the number of broken wires.

$$P\_{\rm WB} = I\_{\rm C}^2 \cdot R\_{\rm WB} / \left( N\_{\rm wires} - N\_{\rm fail} \right) \tag{4}$$

Our previous study [22,23] proposes that the heat flow of bond wires is different from the die, which transfers to both the die side and the emitter side at the same time, as in Figure 3a. Hence, the power loss of bond wires could be divided into two parts based on the direction of heat flow, which transfers through the die side *P*WB\_D and emitter side *P*WB\_E, as in Equation (5).

$$P\_{\rm WB} = P\_{\rm WB\\_D} + P\_{\rm WB\\_E} \tag{5}$$

**Figure 3.** (**a**) Heat flow after bond wire lift-off. (**b**) Thermal network of IGBT module after wire lift-off.

Only *P*WB\_D transfers through die to the case point and dissipates to ambient temperature by heatsink with die power loss. This power loss *P* loss on case point finally causes a temperature rise on the heatsink *T* C, as in Equations (6) and (7).

$$P\_{\text{loss}}' = P\_\text{D} + P\_{\text{WB\\_D}} \tag{6}$$

$$T'\_{\mathbb{C}} = P'\_{\text{loss}} \cdot Z\_{\mathbb{E}\text{-HS}} + T\_{\text{A}} = (P\_{\text{D}} + P\_{\text{WB\\_D}}) \cdot Z\_{\mathbb{E}\text{-HS}} + T\_{\text{A}} \tag{7}$$

The thermal network after bond wire lift-off is shown in Figure 3b. The thermal resistance of the module and equivalent thermal resistance of heatsink stay the same after bond wire lift-off; only part of the bond wire power loss transfers through the die to the heatsink.

Previous research [24,25] proposed that the heat flow in the IGBT module is only affected by the structure after solder fatigue. Although the power loss of bond wires increases, the heat flow stays the same after lift-off due to the same structure. Hence, the equivalent thermal resistance of heatsink on the case point could be calculated based on the same Equation as (3) as in Equation (8).

$$Z\_{\rm E\\_HS} = \frac{\left(T\_{\rm C}^{\prime} - T\_{\rm A}\right)}{P\_{\rm D} + P\_{\rm WB\\_D}}\tag{8}$$

Although the power loss of die *P*<sup>D</sup> and part of the bond wire power loss *P*WB\_D transfer through the die to the heatsink, the power loss of the whole IGBT module *P*IGBT is measured as the calculated power loss, which is different from the theoretical power loss *P* loss on the case point, as shown in Figure 4. Hence, using the power loss of the whole module will overestimate the power loss on the case point, which is higher than the theoretical power loss *P* loss, as in Equation (9).

$$P\_{\rm KGBT} = P\_{\rm D} + P\_{\rm WB} = P\_{\rm D} + P\_{\rm WB\\_D} + P\_{\rm WB\\_E} = P\_{\rm loss}^{\prime} + P\_{\rm WB\\_E} \tag{9}$$

**Figure 4.** Power loss of IGBT module.

Using the overestimated power loss to calculate the thermal resistance of heatsink will underestimate the measured thermal resistance of heatsink *Z*M\_HS on the case point after bond wire lift-off, as in Equation (10).

$$Z\_{\rm M\\_HS} = \frac{T\_{\rm C}^{\prime} - T\_{\rm A}}{P\_{\rm D} + P\_{\rm W\mathcal{B}}} = \frac{(P\_{\rm D} + P\_{\rm W\mathcal{B}\\_D}) \cdot Z\_{\rm E\\_HS}}{P\_{\rm D} + P\_{\rm W\mathcal{B}\\_D} + P\_{\rm W\mathcal{B}\\_E}} < \frac{(P\_{\rm D} + P\_{\rm W\mathcal{B}\\_D}) \cdot Z\_{\rm E\\_HS}}{P\_{\rm D} + P\_{\rm W\mathcal{B}\\_D}} = Z\_{\rm E\\_HS} \tag{10}$$

#### *2.2. Fault Detection Method of IGBT Bond Wire Fatigue Based on Heatsink Thermal Resistance*

Both solder fatigue and bond wire lift-off will lead to increases in on-state voltage *V*CE, power loss *P*loss, junction temperature *T*J, and case temperature *T*C. The thermal impedance of the heatsink increases slightly [25] or remains the same [26] after solder fatigue. However, we propose that, unlike the healthy and solder fatigue modules, the measured heatsink thermal resistance would decrease after bond wire lift-off, as shown in Table 1. Hence, using the decrement in heatsink thermal resistance can easily distinguish the bond wire lift-off from the healthy module and solder fatigue module. To determine the status of bond wires, a method based on the reduction in heatsink thermal resistance is presented.

**Table 1.** Different performance of healthy and fatigue modules.


The initial thermal resistance of heatsink *Z*HS\_initial is measured through the power loss of the IGBT module *P*IGBT and the temperature difference Δ*T*CA between case and ambient temperature on the case point, as in Equation (11). The *Z*HS\_initial is set as the reference value of the healthy module.

$$Z\_{\rm HS\\_initial} = \frac{\Delta T\_{\rm CA}}{P\_{\rm IGBT}}\tag{11}$$

The compared heatsink thermal resistance *Z*HS\_K is measured at the same current level with new power loss *P* IGBT and temperature difference Δ*T* CA, as in Equation (12).

$$Z\_{\rm HS\\_K} = \frac{\Delta T\_{\rm CA}^{\prime}}{P\_{\rm IGBT}^{\prime}} \tag{12}$$

The aging ratio *K* is defined to detect bond wire fatigue as in Equation (13), which is solely related to the difference between power loss of the whole module and theoretical power loss on the case point.

$$K = \frac{Z\_{\text{HS\\_K}} - Z\_{\text{HS\\_initial}}}{Z\_{\text{HS\\_initial}}} \cdot 100\% \tag{13}$$

The value of *K* decreases after bond wire lift-off. The number of remaining bond wires will be updated after *K* decreases. The aged IGBT should be replaced to avoid open-circuit failure when the critical failure is reached. The flowchart of the proposed method is shown in Figure 5.

**Figure 5.** Flowchart of the fault detection method of bond wires.

The proposed method is capable of monitoring the bond wire lift-off by measuring the decrement in heatsink thermal resistance. This decrement occurs in the IGBT operation due to the different heat spreading paths of bond wires. The key advantage of this method is that the thermal resistance of the heatsink is measured independent of working conditions, and does not depend on the current, die temperature, or solder fatigue.

#### **3. Simulation Validation**

#### *3.1. Electro-Thermal Modeling for IGBT Module*

A multi-physics field finite element method (FEM) model was established based on a 1200 V/50 silicon IGBT module (STARPOWER, Jiaxing, China, GD50HFL120C1). The unpacked power module free of gel is shown in Figure 6a. The geometry of the IGBT layout was supplied by the power module manufacture STARPOWER, shown in Figure 6b. The FEM model is tested with and without bond wires removed. The simulation module is used to show the mechanisms of heat transfer after bond wire lift-off.

**Figure 6.** (**a**) IGBT module GD50HFL120C1. (**b**) Dimensions of GD50HFL120C1.

The bond wires of diode and gate have been removed in the FEM model. The structure and boundaries of the FEM model are shown in Figure 7a. The boundary conditions are set as follows. The ambient temperature is set at 20 ◦C. All of the boundaries' conditions are set as electric insulation in the physical field of electric currents, except a DC source with a high potential on the collector side and ground potential on the emitter side. A convection coefficient of 3000 W/m2·K is defined on the bottom surface of the baseplate to simulate a wind-cooling heatsink; the rest of the surfaces are set as 12.5 W/m2·K for free convection air in the physical field of heat transfer in solids. The physical fields of heat transfer in solids and electric currents are defined as the source and destination in the multi-physics field of temperature coupling, respectively. All domains are used in electromagnetic heat source and boundary electromagnetic heat source, where the electric currents are set as the electromagnetic source and heat transfer in solids is set as the heat transfer source.

**Figure 7.** (**a**) FEM model; (**b**) meshed IGBT module; (**c**) mesh of baseplate.

The meshed model is shown in Figure 7b, which consists of 1,152,643 domain elements, 216,192 boundary elements, and 7236 edge elements. To study the effect of bond wire lift-off on the thermal resistance measurement, the bottom of the baseplate layer meshed with more free triangular distribution than other areas as in Figure 7c, which consist of 164,632 boundary elements and 1619 edge elements.

The material properties of the FEM model are shown in Table 2. The conduct characteristic of IGBT die *r*die is temperature-dependent in different current levels. Hence, the electrical conductivity of die *σ*die could be obtained based on the die temperature [27], where *l* and *A* are the height and conduct area of IGBT die as in Equations (14) and (15).

$$r\_{\rm die} = \frac{V\_{\rm CE\\_25}}{I\_{\rm C}} + \frac{V\_{\rm CE\\_150} - V\_{\rm CE\\_25}}{I\_{\rm C}(150 - 25)}(T\_{\rm I} - 25) \tag{14}$$

$$
\sigma\_{\text{die}} = \frac{1}{r\_{\text{die}}} \cdot \frac{l}{A} \tag{15}
$$


**Table 2.** Material properties of the FEM model.

This IGBT die shows different temperature characteristics under each current condition, with a negative temperature coefficient (NTC) at 10 A, a zero temperature coefficient (ZTC) at 20 A, and a positive temperature coefficient (PTC) at 30 A and 40 A, as shown in Figure 8a. The decrement in the measured heatsink thermal resistance is determined by the fatigue of bond wires, which is not affected by the conducted current. Hence, the simulation will be tested under each current level. The case temperature is measured by the point below the center of the die on the baseplate, as in Figure 8b.

**Figure 8.** (**a**) Temperature characteristics of IGBT electrical conductivity under different current levels; (**b**) case temperature measure point.

#### *3.2. FEM Results*

Figure 9a shows the power loss after bond wires are removed under different current conditions, where the dashed columns are die power loss and solid columns are bond wire power loss. The power loss of the whole module increases due to the bond wire power loss after lift-off. The power loss of the die stays almost the same, while the power loss of the bond wires significantly increases after lift-off. The power loss of bond wires rises from 0.19 W to 0.79 W at 10 A, while the die power loss stays at 11.16 W. The higher current shows a higher power loss increase in wires, which rises from 3.1 W to 12.6 W at 40 A, while the die power loss remains at 69 W. The case temperature variation is shown in Figure 9b, which shows a slight rise after bond wires are removed due to the increased power loss.

**Figure 9.** FEM results. (**a**) Power loss of IGBT module; (**b**) case temperature at case point.

Not only the power loss but also the proportion of bond wires to total power loss increase after bond wire lift-off, as shown in Table 3. The proportion of bond wires in total power loss rises after lift-off, increasing from 1.7% to 6.59% at 10 A, 2.83% to 10.59% at 20 A, 3.65% to 13.34% at 30 A, and 4.3% to 15.42% at 40 A. The proportion of bond wire power loss to whole power loss of the IGBT module changed obviously after lift-off at a larger current due to the lower on-state resistance of IGBT die.

**Table 3.** Proportion of bond wire power loss in total loss.


The measured thermal resistances of heatsink after bond wires were removed are shown in Figure 10a. Although the thermal resistances show different initial values at each current level due to the spreading of thermal resistance [28], they all decrease after bond wires are removed. The thermal resistance decreases from 0.357, 7 K/W to 0.353, 2 K/W at 10 A, 0.357, 3 K/W to 0.350, 1 K/W at 20 A, 0.357, 1 K/W to 0.348, 0 K/W at 30 A, and 0.356, 9 K/W to 0.346, 3 K/W at 40 A after bond wires are removed.

The aging ratio *K* of simulation results are shown in Figure 10b. Although the aging ratio shows similar values in each current level, the decrement is more significant at a higher current. The value of *K* reaches 1.27%, 2.02% 2.56%, and 2.96% at each current level with one bond wire remaining. According to the results, the value of *K* decreases after bond wire lift-off. Hence, the decrement in *K* could indicate the fatigue of bond wires to avoid an open circuit.

The heat flow in the IGBT module before and after bond wires are removed is shown in Figure 11. The distribution of heat flow is mainly concentrated under the die before bond wires are removed, while the heat flow of bond wires is nearly negligible. Although the heat flow under the chip stays nearly the same after bond wire lift-off (blue lines), the heat flow of bond wires changes. Bond wire fatigue leads to a rise in bond wire power loss, and heat mainly concentrates in the die side and emitter side. This increase in the heat flow in the emitter side shows that part of the bond wire power loss did not transfer through the die side (red lines). Hence, using the power loss of the whole module to calculate the heatsink thermal resistance will underestimate the result.

**Figure 10.** FEM results. (**a**) Heatsink thermal resistance *Z*M\_HS; (**b**) aging ratio *K*.

**Figure 11.** Heat flow in IGBT module after bond wires are removed.

#### **4. Experimental Validation**

#### *4.1. Test Bench Setup*

The main electrical circuit for the test is shown in Figure 12a. The gate voltage was set at 15 V to control the IGBT. A DC source, which varied from 10 A to 40 A with 10 A intervals, was used to emulate the different operating conditions. The collector–emitter voltage was measured by oscilloscopes.

The test environment is shown in Figure 12b. The case temperature was measured from the thermocouple data logger (PICO, Cambridgeshire, UK, TC08). A fan-cooled heatsink (GD Rectifiers, West Sussex, UK, PS260/xxF(6)) was set as the air-cooling heatsink to be tested. Two graves were incised on top of the heatsink to place the thermal couples. The case temperature was measured by the thermal couple, as shown in Figure 12c. A thermal pad was attached to the module baseplate to reduce the air gap between the heatsink and IGBT. To emulate the aging of bond wires, the thermal resistance of heatsink was measured with different bond wires removed. The temperature curve of the case point on heatsink at 30 A is shown in Figure 12d, where the blue solid line is the case temperature, the black dashed line is the ambient temperature, and the red dashed line is the steady temperature of the case point. The forced air-cooling heatsink reaches its steady state after 500 s. Hence, the power loss and case temperature are measured after 10 min until reaching thermal steady state in each test.

**Figure 12.** Test bench: (**a**) main electrical circuit; (**b**) test environment; (**c**) thermal couples on heatsink; (**d**) temperature curve of case point on heatsink at 30 A.

#### *4.2. Experimental Results Analysis*

The experiment results show that the aging of bond wires finally leads to a rise in the power loss of the IGBT module; the module fuses at 40 A with one bond wire remaining, as in Figure 13a. The power loss shows a small rise after bond wire lift-off at the smaller current, which increases more significantly at a higher current level. These increased power losses finally lead to a rise in the temperature at case point, as shown in Figure 13b. The experimental results show that the increase in case temperature is more significant at a higher current, while the variation is small at 10 A due to its low power loss.

The measured heatsink thermal resistances are shown in Figure 13c. Although the initial measured thermal resistance is different for each current level due to the thermal spreading resistance, they all show a decreasing trend after bond wires are removed. The measured thermal resistance decreases from 0.4427 K/W to 0.3960 K/W at 10 A, 0.3803 K/W to 0.3657 K/W at 20 A, and 0.3729 K/W to 0.3548 K/W at 30 A after three bond wires are removed. Although this module fused at 40 A with one wire remaining, it still decreases from 0.3609 K/W to 0.3568 K/W with two wires removed.

Figure 13d illustrates that the value of *K* shows similar decreasing trends at higher currents, and shows a large decrement at 10 A. The aging rate *K* is only dependent on the heat flow of bond wires, which are free of operating conditions. Hence, *K* can be used to detect the fault of bond wires to avoid the open circuit.

**Figure 13.** Experimental results: (**a**) power loss of IGBT module; (**b**) case temperature; (**c**) heatsink thermal resistance *ZM\_HS*; (**d**) aging ratio *K*.

#### *4.3. Discussion*

The comparison of bond wire fault detection method is discussed in Table 4. As a non-invasive detection method, the proposed method does not need to change the structure of the IGBT module, which could be used in normal conditions. The case temperature and power loss are easier to measure than the gate signal during operation. Hence, these advantages could help maintain the power converter to avoid an open circuit. However, there are still some problems during measurement.

As previously mentioned, the thermal resistance of heatsink decreases after bond wires are removed. Although the *K* shows a similar reduction at all current levels in the simulation, it shows an anomalous reduction at 10 A in the experimental results. This strange performance is caused by the measurement of the case temperature.

JESD51-1 [29] proposed to measure an accurate thermal resistance with at least a 20 ◦C temperature rise on-die, because the high power loss of die could make the detection of the case temperature more accurate. The increased power loss after bond wires are removed is shown in Figure 14. The experimental results show that power loss significantly increases at higher current levels after bond wires are removed, while the increased power loss at 10 A is far smaller than other current levels.

The small increase in power loss at 10 A makes it difficult to detect the variation in case temperature after lift-off, which causes a small change in the case temperature of less than 0.1 ◦C. These small changes in the case temperature lead to inaccurate measured results, shown in Figure 13d. The low power loss makes it difficult to detect the case temperature variation after bond wires are removed at a low current, while this is easier to detect at a higher current. Thus, it is important to ensure the sensitivity of the case temperature detection method to provide accurate measurement results, which would be better to use in higher current working conditions.

**Table 4.** Comparisons of bond wire fault detection.


**Figure 14.** The growth of the IGBT module's power loss after bond wires are removed.

#### **5. Thermal Resistance Measurement of Heatsink in Power Cycling**

To verify the detection method proposed in this paper, a power cycling test is used to simulate the power converter. The power cycling circuit is shown in Figure 15. A singlephase full-bridge is built based on Ref. [30], which could generate a high-temperature swing with low power loss due to the inductive load. The power cycling circuit is shown

in Figure 16. The full-bridge is composed of IGBT1, IGBT2, IGBT3, and the device under test (DUT). The *V*CE is measured by the *V*CE measurement circuit. A small current source (100 mA) is used to measure the junction temperature of IGBT by the *V*CE measurement circuit with the Temperature-Sensitive Parameter (TSEP) method. The auxiliary IGBT is used to block the branch of DUT during junction temperature measurement.

The test bench is shown in Figure 16. To show the feasibility of the proposed method, a different IGBT module (Semikron, Zhuhai, China, SKM50GB12T4) was used for this experiment. The DC source was set at 50 V and a 0.02 mH inductor was used as the load. The gate source and clamp source supply the gate driver and *V*CE measurement circuit. The IGBT was controlled by DSP. All of the data were collected by the NI DAQ. The control signal and acquisition signal were processed by LabVIEW on computer. The IGBT was placed on the cold plate and cooled by the chiller. The DUT was tested with a temperature variation of 83.2 ◦C and mean die temperature of 93.3 ◦C. The working frequency and switching frequency were 0.03 Hz and 6 k Hz, respectively.

The DUT failed after 56,879 cycles. The open package of the failed IGBT module is shown in Figure 17a. There are five failed wires on the chip with one wire remaining in Figure 17b.

**Figure 15.** Power cycling circuit.

**Figure 16.** Test bench.

Previous research proposed that the thermal resistance will decrease after bond wires failed [23], which is shown in Figure 18a, where the brown wave is normalized conduct voltage and the blue wave is normalized measured thermal resistance of the IGBT module. The measured thermal resistance of the IGBT module could be measured in this test due to the special custom circuit test circuit; however, it is nearly impossible to measure the thermal resistance of the module during operation in a normal power converter. Although the measured thermal resistance of heatsink seems to show a notable change during cycling, it shows a significant decrease after bond wires fault, which is shown in Figure 18b, where the brown wave is normalized conduct voltage and the blue wave is normalized measured thermal resistance of heatsink.

(**a**) (**b**)

**Figure 17.** Cycling results of IGBT module SKM50GB12T4: (**a**) whole module; (**b**) failed wires.

**Figure 18.** Normalized measured results of (**a**) IGBT module and (**b**) heatsink.

All in all, these results show that the measured thermal resistance of heatsink is easy to obtain to indicate the bond wire fault of IGBT modules, which might be helpful for the condition monitoring of power converters.

#### **6. Conclusions**

We proposed a novel method to detect bond wire fatigue by the decrement in measured heatsink thermal resistance. The advantage of this method is that it is not necessary to detect junction temperature, and thus, it could be used in normal working conditions. A multi-physics field FEM model was established to validate this method. The simulation results show that the heat flow changes after bond wire lift-off, which overestimates the calculated power loss and underestimates the measured heatsink thermal. Hence, the decrement in measured thermal resistance of heatsink could be used to detect the fatigue of bond wires. This method was verified by our experimental results. A power cycling

test was used to show the variation in measured thermal resistance of heatsink during the aging process of the IGBT module, which verified the fault detection method.

The scope of this paper is monitoring the fatigue of bond wires under normal operation conditions, which could provide information for health management to avoid open-circuit faults. However, it is still difficult to measure the state of IGBT in the power converter. In future work, this method will be further studied to be integrated into a real power converter, which could help to ensure the reliable operation of the converter.

**Author Contributions:** Conceptualization, methodology, validation, and writing—original draft preparation, D.L.; writing—review and editing, W.L., H.X. and Z.D.; supervision, W.L. and M.C.; funding acquisition, K.Y.; validation, Z.W. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was supported by the Shanxi Provincial Department of Science and Technology unveiled the bidding project (20201101017); the National Key Research and Development Program of China (grant numbers 2018YFB0905800); the National Natural Science Foundation of China (grant numbers 51707024); the Fundamental Research Funds for the Central Universities Project (no. 2020CDJQY-A026); and the National "111" Project (B08036).

**Data Availability Statement:** The data presented in this study are available on request from the corresponding author.

**Acknowledgments:** The authors would like to thank Li Ran, Ruizhu Wu, Borong Hu, and Xuan Guo at the University of Warwick for the help and advice.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


### *Article* **Fault Diagnosis Method of Six-Phase Permanent Magnet Synchronous Motor Based on Vector Space Decoupling**

**Hanying Gao \*, Jie Guo, Zengquan Hou, Bangping Zhang and Yao Dong**

School of Electrical and Electronic Engineering, Harbin University of Science and Technology, Harbin 150080, China; 1603011307@stu.hrbust.edu.cn (J.G.); 1920310189@stu.hrbust.edu.cn (Z.H.); zbp123456@163.com (B.Z.); a1090897186@163.com (Y.D.)

**\*** Correspondence: ghy@hrbust.edu.cn; Tel.: +86-137-9666-8369

**Abstract:** Compared with the three-phase motor, the six-phase motor has lower torque ripple and higher fault tolerance performance, which makes it widely used in aviation, ships, industrial manufacturing, and other application fields. However, the probability of failure of the polyphase motor system increases with the increase in the number of phases. In order to deal with the open phase fault and power switch fault of the six-phase inverter, a fault diagnosis method for the six-phase inverter based on vector space decoupling (VSD) is proposed. The open phase fault index is first determined according to the VSD decoupling inverse transform and the current constraints. The fault index is then optimized from the perspective of preventing misdiagnosis and improving reliability, and the open phase fault can be diagnosed in one fundamental cycle. In addition, the current trajectory of harmonic plane after switch fault is analyzed, and the back propagation (BP) neural network is used to identify the harmonic plane current trajectory of different types of switch fault. Finally, the correctness and feasibility of the proposed fault diagnosis method are verified by simulations and experiments. The obtained results demonstrate that the proposed method can quickly and accurately locate the open phase fault and switch fault without additional hardware. The proposed method is simple, efficient, and robust.

**Keywords:** six-phase permanent magnet synchronous motor (PMSM); inverter fault diagnosis; neural network; open circuit fault; power switch failure

#### **1. Introduction**

The polyphase permanent magnet synchronous motor has its unique advantages in improving power, restraining torque ripple, and fault-tolerant control. It is suitable for ships [1], aerospace [2], energy utilization [3], rail transit [4], and other application domains with high-reliability requirements. However, compared with the three-phase motor, the number of power devices and sensors in the driving system of the polyphase motor is also doubled. In the case of failure, it will threaten personal safety or lead to system collapse. Therefore, it is necessary to detect and diagnose the different operating parameters in the early stage of system fault.

In the polyphase motor drive system, the inverter switch failure and phase failure rate are the highest [5]. The fault diagnosis technology can instantly and accurately locate the fault location of the motor drive system and provide key information for maintenance and repair. In addition, it provides an accurate basis for the selection of the subsequent fault-tolerant control technology of the polyphase motor. Therefore, a fast, stable, and accurate fault diagnosis method for polyphase motor drive systems is crucial.

Three main fault diagnosis methods for motor drive systems exist: model-based [6–8], knowledge-based [9,10], and signal-based [11]. In [12], the related terms of DC side voltage and current of inverter are modeled and analyzed, and the residual evaluation function of DC side voltage is constructed to diagnose the fault of switch. A phase current observer

**Citation:** Gao, H.; Guo, J.; Hou, Z.; Zhang, B.; Dong, Y. Fault Diagnosis Method of Six-Phase Permanent Magnet Synchronous Motor Based on Vector Space Decoupling. *Electronics* **2022**, *11*, 1229. https://doi.org/ 10.3390/electronics11081229

Academic Editor: Ahmed Abu-Siada

Received: 21 March 2022 Accepted: 7 April 2022 Published: 13 April 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

is designed to convert the phase current error into coordinates to obtain the fault vector angle, so as to locate the switch fault [13]. A current interval sliding mode observer is designed to improve the prediction process of the phase current [14]. The performance of the model-based fault diagnosis method highly depends on the model's accuracy. The changes in the motor parameters and operating conditions will also have a certain impact on the diagnosis accuracy.

In the knowledge-based diagnosis method, the main neural network algorithm and auxiliary neural network are used to analyze the amplitude-frequency characteristics of DC bus voltage harmonics and diagnose the fault of the three-level inverter power device [15]. In [16], the intermittent faults of power equipment are studied, and the fault levels under different fault conditions are classified by using fuzzy theory. In [17], a new method is mentioned to diagnose the fault of a wind turbine by developing a knowledge base to simulate the thinking mode of experts. This method has a high computational load, and low real-time performance, and it is difficult to implement.

The fault diagnosis based on signals can be divided into voltage and current methods. The typical shape of the fault track is matched by calculating the distance from the harmonic plane current track to the centroid [18]. This algorithm is complex and requires a lot of calculations. In [19], a new method is mentioned to decompose and reconstruct the voltage signal by using wavelet packets. It also uses the characteristic frequency related to the fault signal in its power spectrum to judge the open circuit fault type of the switch. In [20], by analyzing the frequency and angle of each current vector, whether the power switch of the three-phase inverter fails can be judged. In [21], the sampled current is decomposed using the wavelet transform and transformed by coordinate, and the fault trajectory is diagnosed using the support vector machine.

In this paper, a fault diagnosis method based on VSD is proposed for phase failure and power switch failure. The phase failure index is first determined according to the VSD transformation and phase failure constraints. A series of fault indexes are then optimized in order to improve the diagnosis reliability. Afterward, the switch fault is diagnosed as the characteristic signal by analyzing the current trajectories of harmonic planes after VSD transformation. Finally, considering the 10 kW double Y-phase shifted 30◦ six-phase PMSM, the correctness of the diagnosis algorithm is verified by simulations and experiments.

#### **2. Mathematical Model of the Six-Phase Permanent Magnet Synchronous Motor**

The six-phase PMSM drive system is mainly composed of a six-phase voltage source inverter (VSI). Its topology is shown in Figure 1. Note that N1 and N2 are the neutral points of the two windings.

**Figure 1.** Topology of the six-phase inverter with neutral isolation.

The six-phase PMSM is a nonlinear and strongly coupled system. Therefore, an appropriate decoupling transformation is required to simplify the analysis. In addition, the VSD

decoupling method, which is more suitable for polyphase motors, can control the harmonic component. The vector space decoupling matrix is given by:

$$\mathbf{C}\_{6s} = \frac{1}{\sqrt{3}} \begin{bmatrix} 1 & -\frac{1}{2} & -\frac{1}{2} & \frac{\sqrt{3}}{2} & -\frac{\sqrt{3}}{2} & 0\\ 0 & \frac{\sqrt{3}}{2} & -\frac{\sqrt{3}}{2} & \frac{1}{2} & \frac{1}{2} & -1\\ 1 & -\frac{1}{2} & -\frac{1}{2} & -\frac{\sqrt{3}}{2} & \frac{\sqrt{3}}{2} & 0\\ 0 & -\frac{\sqrt{3}}{2} & \frac{\sqrt{3}}{2} & \frac{1}{2} & \frac{1}{2} & -1\\ 1 & 1 & 1 & 0 & 0 & 0\\ 0 & 0 & 0 & 1 & 1 & 1 \end{bmatrix} \tag{1}$$

In this matrix, the first two rows of variables correspond to the *α-β* subspace, the middle two rows correspond to the *z*1-*z*<sup>2</sup> subspace, and the last two rows correspond to the *o*1-*o*<sup>2</sup> zero sequence. The conversion of electromechanical energy is only related to *α-β*.

The rotation coordinate transformation is expressed as:

$$\mathbf{C}\_{6\text{s}/6\text{r}} = \begin{bmatrix} \cos\theta & \sin\theta & 0\\ -\sin\theta & \cos\theta & 0\\ 0 & 0 & \mathbf{I}\_4 \end{bmatrix} \tag{2}$$

where I4 is a fourth-order unit matrix. The motor mathematical model after VSD transformation is detailed in the sequel.

The magnetic flux equation is:

$$
\begin{bmatrix} \psi\_d \\ \psi\_q \end{bmatrix} = \begin{bmatrix} L\_d & 0 \\ 0 & L\_q \end{bmatrix} \begin{bmatrix} i\_d \\ i\_q \end{bmatrix} + \psi\_f \begin{bmatrix} 1 \\ 0 \end{bmatrix} \tag{3}
$$

where *Ld* and *Lq*, *id* and *iq*, *ψ<sup>d</sup>* and *ψ<sup>q</sup>* are the inductance, current, and stator flux of the direct axis and quadrature axis, respectively.

The voltage equation is:

$$
\begin{bmatrix} u\_d \\ u\_q \end{bmatrix} = \begin{bmatrix} R & 0 \\ 0 & R \end{bmatrix} \begin{bmatrix} i\_d \\ i\_q \end{bmatrix} + \frac{\mathbf{d}}{\mathbf{d}t} \begin{bmatrix} \psi\_d \\ \psi\_q \end{bmatrix} + \omega\_\mathbf{e} \begin{bmatrix} -\psi\_\mathbf{q} \\ \psi\_d \end{bmatrix} \tag{4}
$$

where *ud* and *uq* are the stator voltages of the direct axis and quadrature axis, respectively. The electromagnetic torque equation is:

$$T\_{\mathbf{e}} = \Im p \left[ \psi\_f i\_q + (L\_d - L\_q) i\_d i\_q \right] \tag{5}$$

where *T*<sup>e</sup> and *ψ<sup>f</sup>* are the electromagnetic torque and permanent magnet flux linkage, respectively.

The equation of motion is:

$$T\_\mathbf{e} - T\_\mathbf{L} - B\omega\_\mathbf{m} = J \frac{\mathbf{d}\omega\_\mathbf{m}}{\mathbf{d}t} \tag{6}$$

where *T*L, *B*, *ω*m, and *J* are load torque, damping coefficient, mechanical angular velocity, and moment of inertia, respectively.

#### **3. Open Phase Fault Diagnosis Strategy**

After VSD transformation, the property of the *α-β* plane variable is similar to that of the three-phase motor, while the *z*1-*z*<sup>2</sup> plane is a unique property of the six-phase PMSM [22]. Simultaneously, the change of the *z*1-*z*<sup>2</sup> component during inverter fault is explored, which can be used for inverter fault diagnosis.

#### *3.1. Calculation of the Phase Failure Index*

In the normal state, the fundamental subspace current *iα*, *i<sup>β</sup>* in the VSD static coordinate system is obtained by decoupling transformation of the six-phase stator current:

$$i\_a = i\_a - \frac{1}{2}i\_b - \frac{1}{2}i\_c + \frac{\sqrt{3}}{2}i\_d - \frac{\sqrt{3}}{2}i\_c \tag{7}$$

$$i\_{\beta} = \frac{\sqrt{3}}{2}i\_b - \frac{\sqrt{3}}{2}i\_c + \frac{1}{2}i\_d + \frac{1}{2}i\_c - i\_f \tag{8}$$

Substituting the six-phase stator current of the motor during normal operation into Equations (7) and (8), the following is obtained:

$$\begin{cases} i\_{\rm at} = I\_{\rm m} \sin(\theta) - \frac{1}{2} I\_{\rm m} \sin(\theta - \frac{2\pi}{3}) - \frac{1}{2} I\_{\rm m} \sin(\theta + \frac{2\pi}{3}) + \frac{\sqrt{5}}{2} I\_{\rm m} \sin(\theta - \frac{\pi}{6}) - \frac{\sqrt{5}}{2} I\_{\rm m} \sin(\theta - \frac{5\pi}{6}) = 3 I\_{\rm m} \sin(\theta) \\\ i\_{\rm \phi} = \frac{\sqrt{5}}{2} I\_{\rm m} \sin(\theta - \frac{2\pi}{3}) - \frac{\sqrt{5}}{2} I\_{\rm m} \sin(\theta + \frac{2\pi}{3}) + \frac{1}{2} I\_{\rm m} \sin(\theta - \frac{\pi}{6}) + \frac{1}{2} I\_{\rm m} \sin(\theta - \frac{5\pi}{6}) - I\_{\rm m} \sin(\theta + \frac{\pi}{6}) = 3 I\_{\rm m} \cos(\theta) \end{cases} \tag{9}$$

Similarly, the current relationship in the harmonic subplane can be obtained:

$$\begin{cases} \dot{i}\_x = \dot{i}\_a - \frac{1}{2}\dot{i}\_b - \frac{1}{2}\dot{i}\_c - \frac{\sqrt{3}}{2}\dot{i}\_d + \frac{\sqrt{3}}{2}\dot{i}\_c\\ \dot{i}\_y = -\frac{\sqrt{3}}{2}\dot{i}\_b + \frac{\sqrt{3}}{2}\dot{i}\_c + \frac{1}{2}\dot{i}\_d + \frac{1}{2}\dot{i}\_c - \dot{i}\_f \end{cases} \tag{10}$$

Substituting the six-phase stator current of the motor during normal operation into Equation (10) results in:

$$\begin{cases} \ i\_x = 0\\ \ i\_y = 0 \end{cases} \tag{11}$$

It can be deduced from this analysis that the output electromagnetic torque of the motor is mainly provided by the fundamental subspace current components *i<sup>α</sup>* and *iβ*. In the normal state, the current *iz*1, *iz*<sup>2</sup> of the harmonic subplane is null. The currents *iα*,*i<sup>β</sup>* and *iz*1,*iz*<sup>2</sup> after VSD decoupling transformation are shown in Figure 2. The fundamental subspace is circular in the steady-state current *iα*,*iβ*. The harmonic subspace current *iz*1,*iz*<sup>2</sup> is the point at the origin, which is coherent with the theoretical calculation results.

**Figure 2.** *α-β* and *z*1-*z*<sup>2</sup> plane current waveform during normal operation: (**a**) *α-β* plane current waveform in case of normal operation; (**b**) *z*1-*z*<sup>2</sup> plane current waveform in case of normal operation.

By inverting the normal VSD transformation, the following is obtained:

$$
\begin{bmatrix} i\_a \\ i\_b \\ i\_c \\ i\_d \\ i\_e \\ i\_f \end{bmatrix} = \frac{1}{\sqrt{3}} \begin{bmatrix} 1 & 0 & 1 & 0 & 1 & 0 \\ -\frac{1}{2} & \frac{\sqrt{3}}{2} & -\frac{1}{2} & -\frac{\sqrt{3}}{2} & 1 & 0 \\ -\frac{1}{2} & -\frac{\sqrt{3}}{2} & -\frac{1}{2} & \frac{\sqrt{3}}{2} & 1 & 0 \\ \frac{\sqrt{3}}{2} & \frac{1}{2} & -\frac{\sqrt{3}}{2} & \frac{1}{2} & 0 & 1 \\ -\frac{\sqrt{3}}{2} & \frac{1}{2} & \frac{\sqrt{3}}{2} & 0 & 0 & 1 \\ 0 & -1 & 0 & -1 & 0 & 1 \end{bmatrix} \begin{bmatrix} i\_a \\ i\_{\beta} \\ i\_{z1} \\ i\_{z2} \\ i\_{\phi 1} \\ i\_{\phi 2} \end{bmatrix} \tag{12}
$$

When a phase failure occurs, it can be seen from Equation (12) that the fundamental and harmonic plane currents have a certain relationship. It is assumed that the phase failure of phase *a* winding occurs. That is, when the constraint condition is *ia* = 0, the first row of the VSD inverse matrix (cf. Equation (12)) is multiplied by the plane current in order to obtain *i<sup>α</sup>* + *iz*<sup>1</sup> = 0. When the motor is in normal operation, the harmonic current is *iz*<sup>1</sup> = 0. In summary, the open circuit fault index F*a* can be computed as:

$$\mathbf{F}\_{\mathfrak{a}} = -\frac{\dot{i}\_{z1}}{\dot{i}\_{\mathfrak{a}}} \tag{13}$$

Similarly, the open-circuit fault index of six-phases (cf. Equation (14)) can be obtained:

$$\begin{cases} \mathbf{F}\_{d} = -\frac{i\_{z1}}{i\_{a}} \\ \mathbf{F}\_{b} = \frac{i\_{z1}}{-i\_{a} + \sqrt{3}i\_{\beta} - \sqrt{3}i\_{z2}} \\ \mathbf{F}\_{c} = \frac{i\_{z1}}{-i\_{d} - \sqrt{3}i\_{\beta} + \sqrt{3}i\_{z2}} \\ \mathbf{F}\_{d} = \frac{i\_{z1}}{i\_{d} + 1/\sqrt{3}i\_{\beta} + 1/\sqrt{3}i\_{z2}} \\ \mathbf{F}\_{c} = \frac{i\_{z1}}{i\_{d} - 1/\sqrt{3}i\_{\beta} - 1/\sqrt{3}i\_{z2}} \\ \mathbf{F}\_{f} = -\frac{i\_{z2}}{i\_{\beta}} \end{cases} \tag{14}$$

The numerator of this fault index is the harmonic plane current. Due to the fact that the harmonic plane current component is null in the normal state, the fault index is always kept null during the normal operation of the motor. When a phase fault occurs, the fault index of the phase rises 1, so as to distinguish the normal operation and inverter phase fault.

#### *3.2. Optimization Scheme of the Winding Open Circuit Fault Index*

In the case where only the fault index F*n* (*n* = *a*,*b*,*c*,*d*,*e*,*f*) is used, because the denominator of the fault indicator is too small near the zero-crossing area, a spike pulse will appear, which may lead to misdiagnosis. Therefore, the fault index F*<sup>n</sup>* should be improved and optimized. The optimization process is illustrated in Figure 3.

**Figure 3.** Fault index optimization process of disconnected phase.

The fault index F*<sup>n</sup>* is first subjected to peak pulse processing using Equation (15), in order to obtain the first fault index E1 *n* :

$$\begin{cases} \text{ E}\_{n}^{1} = 0 \text{ / } |\text{F}\_{n \text{dco}}| \le \Delta\\ \text{ E}\_{n}^{1} = \text{F}\_{n \text{\prime}} \left| \text{F}\_{n \text{dco}} \right| > \Delta \end{cases} \tag{15}$$

where F*ndeo* is the denominator value of fault index F*<sup>n</sup>* and Δ is the threshold value of the zero-crossing area width. This value cannot be too large, in order to ensure the diagnosis speed. The specific value is determined according to the experiment. In this paper, Δ is set to 0.1.

The fault index after peak pulse processing is then filtered using Equation (16) in order to obtain the second fault index E2 *n*:

$$\begin{cases} \mathcal{E}\_n^2 = \mathcal{E}\_{n'}^1 \left( 1 - \delta \le \mathcal{E}\_n^1 \le 1 + \delta \right) \\\mathcal{E}\_n^2 = 0 \quad \left( 1 + \delta \le \mathcal{E}\_n^1 \& \mathcal{E}\_n^1 \le 1 - \delta \right) \end{cases} \tag{16}$$

where *δ* is the width of the filter band, which is used to filter out the unnecessary interference while not affecting the subsequent processing. The recommended value range of *δ* is [0.1–0.3]. In this paper, it is set to 0.1.

The processed fault index will be set to 1 after the fault occurs. However, the fault index will be set to zero in the zero-crossing area, due to the processing of the zero-crossing spike pulse. Therefore, it is necessary to integrate the fault index according to Equation (17) in order to obtain the third fault index E3 *n*:

$$\mathbf{E}\_n^3 = \frac{1}{\mathbf{T}\_\mathbf{v}} \int\_0^{\mathbf{T}\_\mathbf{v}} \mathbf{E}\_n^2(t) \mathbf{d}t \tag{17}$$

$$\mathbf{T\_v = \tau \ast \mathbf{T\_s}(\tau \le 1)}\tag{18}$$

where Ts is the periodic value of the current fundamental wave. The larger the value of *τ*, the slower the diagnosis speed, but the higher the diagnosis accuracy. On the contrary, the smaller the value of *τ*, the faster the diagnosis speed, but the smaller the diagnosis accuracy. In this paper, *τ* is set to 0.6, in order to ensure the diagnosis accuracy and rapidity. The traditional integration consists in integrating the fault indicators of the whole cycle, which will prolong the fault diagnosis time and reduce the diagnosis efficiency. Selecting Tv Equation (18) can speed up the detection speed.

Finally, the third fault index E3 *<sup>n</sup>* is compared with the threshold in order to obtain the improved fault index OPF*n*:

$$\begin{cases} \text{OPT}\_{\text{n}} = 1, \, \text{E}\_{\text{n}}^{3} > \text{G}\_{th} \\ \text{OPT}\_{\text{n}} = 0, \, \text{E}\_{\text{n}}^{3} < \text{G}\_{th} \end{cases} \tag{19}$$

where G*th* is the judgment threshold selected between 0 and 1. If the value of G*th* is too large, the diagnosis speed will slow down. Because these steps have a negative integration link to suppress the fluctuation of fault indicators, the value can be appropriately reduced, and G*th* can have a value between 0.1 and 0.3.

It can be deduced that using the constraint condition that the fault phase current is null after the phase failure, combined with the vector space decoupled VSD inverse matrix, the fault index of the phase failure is derived. This can diagnose and locate 15 types of phase faults of the inverter, including 6 types of single-phase faults and 9 types of two-phase faults of different windings.

#### **4. Power Switch Fault Diagnosis Strategy**

Several types of power switch faults exist. They mainly include the short circuit and open circuit faults. The short circuit fault has a short duration and is difficult to detect. For further treatment, the short circuit fault is changed into open an circuit fault by a fuse device. The open-circuit faults are mostly single-switch and two-switch faults. The fault of two switches on the same bridge arm can be treated as open phase fault. Therefore, this paper only tackles the open circuit fault of a single switch and two switches on different bridge arms.

#### *4.1. Harmonic Plane Current Fault Trace Analysis*

Figure 4 shows the current waveform of the *z*1-*z*<sup>2</sup> plane when different switches fail after VSD conversion of the six-phase stator current. When T1 fails, the current trajectory of the *z*1-*z*<sup>2</sup> plane points to the negative half of the *z*<sup>1</sup> axis. When T1 and T2 fail, the current trajectories of *iz*<sup>1</sup> and *iz*<sup>2</sup> are fan-shaped. Similarly, when other switches fail, they also have these trajectory characteristics.

**Figure 4.** *z*1-*z*<sup>2</sup> plane current in case of different power switch faults; (**a**) *z*1-*z*<sup>2</sup> plane current waveform in case of T1 fault; (**b**) *z*1-*z*<sup>2</sup> plane current waveform in case of T1 and T2 faults.

The reference direction of the current vector during each phase fault can be expressed as:

$$\text{dn} - \text{ref} = \arctan(\frac{\text{A}\_{z2}}{\text{A}\_{z1}}) \begin{cases} \pi - (k - 1)\frac{\pi}{6}, f\_n \le 1\\ -(k - 1)\frac{\pi}{6}, f\_n \ge 0 \end{cases} \tag{20}$$

where A*z*<sup>1</sup> and A*z*<sup>2</sup> represent the amplitude of harmonic currents *iz*<sup>1</sup> and *iz*2, respectively. *n* represents the *a*,*b*,*c*,*d*,*e*,*f* phase, while the fault phase corresponding to *k* = 1, 5, −3, −4, 6, 4 is *a*,*b*,*c*,*d*,*e*,*f*, respectively. The fault current vector turns counterclockwise by angle dn-ref from the *<sup>x</sup>* axis. *fn*(*t*) = 0 <sup>T</sup> <sup>0</sup> *indt* is the average value of fault current in a current cycle.

It can be deduced that in the case of a single-switch or two-switch open-circuit fault of the inverter, the current trajectory in the harmonic *iz*<sup>1</sup> and *iz*<sup>2</sup> planes regularly changes. The current vector trajectory profile under single-switch and multi-switch faults can be developed using the current values in the *iz*<sup>1</sup> and *iz*<sup>2</sup> harmonic planes, as shown in Figures 5 and 6.

**Figure 5.** Reference direction of *iz*<sup>1</sup> and *iz*<sup>2</sup> current trace in the case of a single switch failure.

According to the different reference directions of the current track under the *z*1-*z*<sup>2</sup> plane fault, the intelligent algorithm has the characteristics of strong analysis ability and several diagnosis types. Therefore, the neural network algorithm is used for fault diagnosis based on the characteristics of fault current trajectory.

In order to distinguish the fault types and improve the diagnosis efficiency, different fault types should be classified and coded. The 12 bit binary number F1F2F3F4F5F6F7F8F9F10F11F12 is used to encode the single-switch and two-switch faults of the six-phase inverter. When all the bits are equal to 1, the switch has an open-circuit fault. On the contrary, when all the

bits are 0, the switch has no fault. Note that there are 36 fault conditions. The specific fault types are shown in Table 1.

**Figure 6.** Reference direction of *iz*<sup>1</sup> and *iz*<sup>2</sup> current trace, in the case of two-power-switch faults. **Table 1.** Fault type code.


#### *4.2. Principle and Algorithm of BP Neural Network*

The neural network is a nonlinear system. Each neuron can output a signal according to the input layer signal and activation function. In addition, a large number of neurons can jointly form a highly nonlinear system [23]. Figure 7 presents a representative neuron structure model.

**Figure 7.** Single neuron structure.

In the latter, *x*1,*x*2,*x*<sup>3</sup> ... *xn* is the input parameter, *Wk*1, *Wk*2, *Wk*<sup>3</sup> ... *Wk*(*n*−1), *Wkn* represents the weight of each parameter, *θ<sup>i</sup>* denotes the threshold, *f*(·) s the activation function, and *yi* represents the neuron output. The relationship between each variable is given by:

$$\begin{cases} \ u\_i = \sum\_{j=1}^n w\_{ij} \mathbf{x}\_j \\\ v\_i = u\_i + \theta \end{cases} \tag{21}$$

The output *yi* of the neuron is expressed as:

$$y\_i = f\left(\sum\_{j=1}^n w\_{ij}\mathbf{x}\_j + \theta\_i\right) \tag{22}$$

The structure of the BP neural network is shown in Figure 8. Due to the gradient descent method, the training can fall into the local minimum, which leads to the inability of effective training [24]. Therefore, this paper uses the Levenbrg–Marquardt algorithm based on the combination of the gradient method and Newton method, in order to optimize the BP neural network. This method has less iterations and a fast iteration speed. Therefore, it can approach the optimal weight faster in order to complete the training.

**Figure 8.** Neural network structure model.

Considering that the residual of the output layer is γ(*x*), which has a nonlinear relationship with *x*, the iterative formula of the Gauss Newton method is given by:

$$\begin{cases} \begin{aligned} \mathbf{x}\_{k+1} &= \mathbf{x}\_k + \Delta \mathbf{x}\_{\mathcal{S}^n} \\ \mathbf{x}\_{k+1} &= \mathbf{x}\_k - H^{-1} \nabla f \end{aligned} \end{cases} \tag{23}$$

where ∇*f* and *H* are respectively the gradient and Hessian matrix of γ(*x*) given by:

$$\begin{aligned} \nabla f &= 2f\_r^T r = 2\sum\_{i=1}^m r\_i \frac{\delta r\_i}{\delta x\_i} \\ H\_{jk} = 2f\_r^T f\_r &= 2\sum\_{i=1}^m \left(\frac{\delta r\_i}{\delta x\_j} \frac{\delta r\_i}{\delta x\_k} + r\_i \frac{\partial^2 r\_i}{\partial x\_j \partial x\_k}\right) \end{aligned} \tag{24}$$

and therefore:

$$
\Delta \mathbf{x}\_{\mathbb{S}^n} = -\left(\boldsymbol{J}\_r^T \boldsymbol{J}\_r\right)^{-1} \boldsymbol{J}\_r^T \boldsymbol{r} \tag{25}
$$

The Levenbrg–Marquardt algorithm improves the iteration step size:

$$y\_i = f\left(\sum\_{j=1}^n w\_{ij} x\_j + \theta\_i\right) \tag{26}$$

where I is the identity matrix and *μ* represents the damping factor usually having a value range of [10−8, 1], which ensures that *J<sup>T</sup> <sup>r</sup> Jr*+*μ*I is a positive definite matrix and that the iteration is in the downward direction.

Before using the neural network diagnosis, the relevant parameters of the neural network should be set according to the needs, the Sigmoid function should be selected as the activation function, the three-layer neural network should be used for training, and the other parameters should be set by default.

#### **5. Simulation Analysis**

#### *5.1. Simulation Analysis of Winding Open-Circuit Fault*

In order to verify the proposed fault diagnosis algorithm, a six-phase motor simulation model is built, which is mainly composed of a rectifier, controller, inverter, and motor. The motor parameters are: rated output power P = 10 kW, rated voltage U = 311 V, rated current I = 20 A, rated speed N = 1500 r/min, rated torque T = 60 N·m, pole pair p = 5, quadrature axis and direct axis inductance Ld = Lq = 8.5 mH, and power factor = 0.9.

The current waveform obtained by increasing and decreasing load and disturbance under normal conditions of the motor is shown in Figure 9. After the motor speed is increased, the load is set to 30 N·m and runs stably at 500 r/min. The six-phase stator current waveform is balanced and the sinusoidal degree is satisfactory. When the load of the motor suddenly changes to 45 N·m at 0.2 s, the current amplitude rapidly increases and runs in a stable state. When the load decreases to 40 N·m at 0.4 s, the current decreases. When the interference is added at 0.6 s, the motor current slightly increases and then decreases to the stable state.

**Figure 9.** Current waveform of load and disturbance during normal operation.

The fault index waveform corresponding to this case is shown in Figure 10. The fault index of the six-phase open circuit is null. In addition, there is no rise when the motor stably operates, suddenly increases or decreases load, and suddenly adds disturbance. The fault index has no false diagnosis under different conditions without fault, which proves that the diagnosis method has a good robustness.

**Figure 10.** Fault indicators under normal operation load and disturbance.

The current waveform of the open-circuit fault of phase *a* at 0.3 s is shown in Figure 11. The load torque is 30 N·m, and the phase failure of phase *a* occurs at 0.3 s. The phase *a* current becomes zero after 0.3 s. Among the remaining four-phase currents, phase *b* and phase *c* have the same amplitude and complementary waveforms, and the waveform amplitude and phase of phase *d*, *e* and *f* change to varying degrees.

**Figure 11.** Phase *a* current waveform of open-circuit fault in 0.3 s.

The fault index waveform under these conditions is shown in Figure 12. After 0.3 s, the phase *a* fault index rises to 1 and the fault indexes of other phases do not change.

**Figure 12.** Phase *a* fault indicator waveform when open fault occurs within 0.3 s.

The current waveform of the open-circuit fault of phase *a* and phase *d* at 0.3 s and 0.5 s is shown in Figure 13. The load torque is 30 N·m, the phase failure of phase *a* and phase *d* occurs at 0.3 s and 0.5 s, respectively. The phase *a* current becomes zero after 0.3 s and the phase *d* current also becomes zero after 0.5 s.

**Figure 13.** Current waveforms of phase *a* and phase *d* at 0.3 s and 0.5 s open-circuit fault, respectively.

The fault index waveform under these conditions is shown in Figure 14. After 0.3 s, the phase *a* fault index rises to 1, and the phase *d* fault index rapidly rises to 1 within the second half cycle of 0.5 s, so as to accurately locate the two-phase open-circuit fault.

**Figure 14.** Fault index waveforms of phase *a* and phase *d* at 0.3 s and 0.5 s open-circuit fault, respectively.

The current waveform of the open-circuit fault of phase *a* and phase *f* at 0.3 s and 0.5 s is shown in Figure 15. The load torque is 30 N·m, the phase failure of phase *a* and phase *f* occurs at 0.3 s and 0.5 s, respectively. The phase *a* current becomes zero after 0.3 s and the phase *f* current also becomes zero after 0.5 s. Among the remaining four-phase currents, phase *b* and phase *c* have the same amplitude and opposite phase. Similarly, phase *d* and phase *e* have the same amplitude and opposite phase.

**Figure 15.** Current waveforms of phase *a* and phase *f* at 0.3 s and 0.5 s open-circuit fault, respectively.

The fault index waveform under these conditions is shown in Figure 16. After 0.3 s, the phase *a* fault index rises to 1, and the phase *f* fault index rapidly rises to 1 within the second half cycle of 0.5 s, so as to accurately locate the two-phase open-circuit fault.

**Figure 16.** Fault index waveforms of phase *a* and phase *f* at 0.3 s and 0.5 s open-circuit fault, respectively.

#### *5.2. Switch Fault Simulation*

Figure 17 shows the harmonic plane current trajectories obtained by simulation in the case of 12 single-switch faults. It can be observed that the fault trajectories of the 12 switches of the six-phase VSI inverter are consistent with the theory.

**Figure 17.** *z*1-*z*<sup>2</sup> harmonic plane current trace in case of single-switch fault.

Figure 18 illustrates the harmonic plane current trajectories obtained by simulation, in the case of 24 types of two-switch faults. The harmonic plane current trajectories are fan-shaped patterns with different center angles in the case of two-switch faults, that are used as characteristic signals for fault diagnosis.

**Figure 18.** *z*1-*z*<sup>2</sup> harmonic plane current trace in case of two-switch fault.

Figure 19 presents the training model of the neural network. The current vector characteristic trajectories of single-switch fault and two-switch fault, are used as samples for training. The hidden layer neuron is 9, the expected error is 0.001, and the maximum number of iterations is 1000. The Newff function is used for training and the Sigmoid function is used as the activation function. The feedback process of the optimization error is performed using the L–M algorithm.


**Figure 19.** Neural network training model.

Figure 20 shows the training error convergence curve of the neural network. The neural network optimized using the L–M algorithm has a high convergence speed. When the training is completed 14 times, the mean square error is 7.6208 × <sup>10</sup><sup>−</sup>4, which meets the error requirements.

**Figure 20.** Error convergence curve of neural network.

The coincidence degree between the error regression curve and the expected curve shown in Figure 21 is high. This proves that the neural network has good fitting and classification ability for different fault current trajectories.

**Figure 21.** Regression curve of neural network training error.

The diagnosis results of the neural network are shown in Table 2. It can be seen that the trained network can identify the single-switch and two-switch faults. The error between the output value of 12 neurons in the output layer and the coding value of the fault type is very small, which leads to an accurate diagnosis.


**Table 2.** Neural network diagnosis results.


**Table 2.** *Cont.*






**Table 2.** *Cont.*

#### **6. Experimental Verification**

Figure 22 shows the overall block diagram of the six-phase PMSM control system, which provides the required DC bus voltage for the inverter after rectification by a threephase uncontrolled rectifier bridge. The DSP-28335 chip outputs the IGBT driving waveform. The resolver and current hall sensor detect the position and phase current of the motor rotor. The Labview host computer platform can receive the motor running state and fault index waveform in DSP in real time.

,\*%7

**Figure 22.** Overall block diagram of the six-phase PMSM control system.

In order to verify the proposed fault diagnosis algorithm, a six-phase motor experimental platform based on DSP is built. The experimental platform is shown in Figure 23. It is mainly composed of a rectifier, controller, inverter, and motor. The motor parameters are: rated output power P = 10 kW, rated voltage U = 311 V, rated current I = 20 A, rated speed N = 1500 r/min, rated torque T = 60 N·m, pole pair p = 5, quadrature axis and straight axis inductor Ld = Lq = 8.5 mH, and power factor = 0.94.

**Figure 23.** Experimental platform of the six-phase motor control system.

Figure 24 shows the phase current waveform when the motor is running at 500 r/min. The current is observed by collecting the voltage at the two ends of the sampling resistance. The voltage value is 100 mV, which corresponds to a current value of 2 A. The amplitudes of the phase currents are equal with a high sinusoidal degree. The current waveforms of phase *a*, *b*, and *d* under the same conditions are shown in Figure 24a. The phase difference between phase *d* current and phase *a* current is 30 degrees. The waveform of the motor is smooth and sinusoidal during normal operation.

**Figure 24.** Waveform of motor under stable operation at 500 r/min: (**a**) current waveform of phase *a*, *b*, and *c*; (**b**) current waveform of phase *a*, *b*, and *d*.

Figure 25 shows the motor speed and six-phase current waveform under sudden load. When the motor speed increases from 400 r/min to 500 r/min in Figure 25a, the actual motor speed gradually increases in the form of the slope with the given speed; the transition is gentle and the overshoot is small in the process of speed increase. In Figure 25b, the amplitude of the motor phase current gradually increases during loading, and the dynamic adjustment process is smooth and stable.

Figure 26 shows the motor speed and the six-phase current waveform during sudden load reduction. When the motor decelerates from 500 r/min to 400 r/min in Figure 26a, the actual motor speed gradually decreases in the form of the slope with the given speed. The transition is smooth and the overshoot is small during deceleration. In Figure 26b, the

amplitude of the motor phase current gradually decreases during load reduction, and the dynamic regulation process is smooth and stable.

&

**Figure 25.** Waveform of the motor under sudden load: (**a**) speed waveform; (**b**) current waveform of the six-phase motor.

**Figure 26.** Waveform of the motor under sudden load: (**a**) speed waveform; (**b**) current waveform of the six-phase motor.

Figure 27 shows the fault index waveform of the motor during stable operation and sudden load increase and decrease. During stable operation and sudden load increase and decrease in the motor, the values of the six-phase open phase fault index are zero, and there is no change. The fault index has no misdiagnosis under fault-free operation, which proves that it has good robustness.

**Figure 27.** Fault index waveform under stable operation at 500 r/min.

Figure 28 presents the phase current and fault index waveform of motor phase *a* in the case of phase failure. Figure 28a presents the current waveform before and after the fault, in which the blue, black, and green lines respectively represent the current waveform of phase *a*, *b*, and *c* of the motor. After the phase failure of phase *a*, the current value of this phase drops to zero, the current amplitude of phase *b* and *c* becomes almost twice the original one, and the phase positions are complementary. Figure 28b illustrates the waveform of the fault phase current and fault index. After the phase failure of phase *a*, the phase failure index Ea of phase *a* increases to a high level after 32 ms, and the optimized fault index has no obvious burr and peak pulse. Therefore, the fault diagnosis and early warning can be performed in a short time.

**Figure 28.** Phase current and fault index waveform in case of phase failure of phase *a*: (**a**) fault current waveform; (**b**) fault phase current and fault index waveform.

Figure 29 shows the fault index waveform of the six-phase disconnection when the *a* phase disconnection fault occurs. After the fault occurs, only the fault index Ea of phase *a* rises to 1, while the fault indexes of the other phases do not change, and there is no misdiagnosis.

**Figure 29.** Fault index waveform in case of phase failure of phase *a*.

The phase current and fault index waveform of phase *a* and phase *d* of the motor with phase failure, are shown in Figure 30. The blue, black, and green lines shown in Figure 30a represent the current waveforms of motor phases *a*, *b*, and *d*, respectively. After the phase failure of phase *a* and *d*, the corresponding phase current value drops to zero, and the amplitude of the phase *b* current increases. The six-phase failure index waveform of phase *a* and phase *d* is shown in Figure 31. Before the phase failure occurs, the sixphase failure index remains null. After the failure occurs, the failure indexes Ea and Ed of phase *a* and phase *d* rise to 1, while the other four-phase failure indexes remain null without misdiagnosis.

Figure 32 shows the phase current and fault index waveform of phase failure of phase *a* and phase *f*. The blue, black, and green lines shown in Figure 32a represent the current waveforms of motor phases *a*, *b*, and *f*, respectively. A phase failure occurs in phase *a* and phase *f*, and the current value drops to zero. After the failure of phase *a* and phase *f*, their failure indexes Ea and Ef jump to the high level after 22 ms and 24 ms, respectively. These situations show that the proposed open phase fault diagnosis method has a high diagnosis speed, and can accurately locate the fault phase position.

**Figure 30.** Phase current and fault index waveform in case of phase failure of phase *a* and phase *d*: (**a**) fault current waveform; (**b**) fault phase current and fault index waveform.

**Figure 31.** Fault index waveform in case of phase failure of phase *a* and phase *d*.

**Figure 32.** Phase current and fault index waveform in case of phase failure of phase *a* and phase *f*: (**a**) fault current waveform; (**b**) fault phase current and fault index waveform.

The six-phase failure index waveform of phase *a* and phase *f* is shown in Figure 33. During normal operation, the failure indexes of the two phases are 0. After phase *a* and phase *f* fail, their failure indexes Ea and Ef rise to 1, and the failure indexes of the other phases do not change. It can then be deduced that the fault index of each phase can accurately locate the position of the fault phase. In addition, the diagnosis results are accurate, and there will be no false diagnosis. Finally, the experimental results are coherent with the theoretical analysis, which verifies the correctness and efficiency of the proposed diagnosis algorithm.

**Figure 33.** Fault index waveform in case of phase failure of phase *a* and phase *f*.

#### **7. Conclusions**

This paper proposed a fault diagnosis method based on vector space decoupling (VSD). The open phase fault index is derived according to the VSD inverse transformation and the current constraints after the fault. The fault index is optimized in order to prevent misdiagnosis and improve reliability. The diagnosis of a single-phase and double-phase fault can be performed in one fundamental cycle. In addition, by considering the unique harmonic plane current track after VSD transformation as the characteristic signal, a neural network is used to identify different fault current tracks, in order to diagnose the switch fault. The simulation and experimental results show that the proposed scheme has a high detection speed, ability to deal with several fault types, and good robustness. Finally, the proposed approach can accurately locate the winding open-circuit fault and power switch fault, which can be used for inverter open-circuit fault diagnosis and provides a basis for maintenance personnel.

**Author Contributions:** Conceptualization, H.G.; formal analysis, H.G. and J.G.; data curation, Z.H. and J.G.; writing—review and editing, B.Z. and Y.D. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research work was funded by the National Natural Science Foundation of China grant number 51177031.

**Data Availability Statement:** The data presented in this study are available on request from the corresponding author.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


### *Article* **Analysis and Operation of a High DC-AC Gain 3-***φ* **Capacitor Clamped Boost Inverter**

**Dogga Raveendhra 1,\*, Poojitha Rajana 2, Beeramangalla Lakshminarasaiah Narasimharaju 3, Yaramasu Suri Babu 4, Eugen Rusu 5,\* and Hady Habib Fayek <sup>6</sup>**


**Abstract:** This article introduces a three-phase capacitor clamped inverter with inherent boost capability by relocating the filter components from the AC side to the configuration's midpoint. This topology has several distinguishing characteristics, including: (a) low component count; (b) high DC-AC gain; (c) decreased capacitor voltage stresses; (d) improved power quality (extremely low voltage and current THDs) without the use of an AC-side filter; and (e) decreased voltage stresses on power semiconductor devices. Simulations were carried out on the MATLAB Simulink platform, and results under steady-state conditions, load and reference change conditions, and phase sequence change conditions, along with THD profiles, are presented. This inverter's performance was compared to that of similar converters with intrinsic gain. A 1200 W experimental prototype was built to demonstrate the system's feasibility and benefits. When compared to existing topologies, simulation and experimental results indicate that the proposed inverter provides superior high gain, smooth control, low stress, and a long life time.

**Keywords:** step up inverter; single stage inverter; capacitor clamped inverter; high-gain converter; DC–AC power converter

#### **1. Introduction**

To overcome the disadvantages of the traditional inverters, such as voltage sources and current source inverters, the ZSI/qZSI [1,2] is widely accepted for various applications. The ZSI/qZSI offers a voltage step-up/down function in single-stage power conversion without requiring additional power processing stage, as shown in Figure 1a, and its application in an electric vehicle is depicted in Figure 1b. Moreover, ZSI/qZSI's reliability is high because shoot-through is an integral part of the operation. The study of these converters has mainly focused on control techniques [3–5], applications [6], and PWM schemes [7,8].

In addition, various power electronics topologies have been proposed in the literature to meet the different objectives, such as reducing the number of switches, reducing the passive component count, and increasing the voltage gain and voltage stresses on the switches/capacitors. The SBI [9] is one such topology that was introduced to decrease the number of passive components (one inductor and one capacitor) in comparison to the ZSI/qZSI by having one additional switch. Although the SBI can perform voltage step-up or step-down in a single stage, its voltage gain is significantly less than that of

**Citation:** Raveendhra, D.; Rajana, P.; Narasimharaju, B.L.; Babu, Y.S.; Rusu, E.; Fayek, H.H. Analysis and Operation of a High DC-AC Gain 3-*φ* Capacitor Clamped Boost Inverter. *Energies* **2022**, *15*, 2955. https:// doi.org/10.3390/en15082955

Academic Editors: Nicu Bizon and Adolfo Dannier

Received: 21 February 2022 Accepted: 13 April 2022 Published: 18 April 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

impedance source converters such as the ZSI/qZSI (1-D). To enhance the source current profile and voltage gain, a group of qSBIs was reported in [10,11]. These included dc-link and embedded-type qSBIs, in addition to current-fed SBIs. However, the embedded-type qZSI necessitates the use of two distinct DC sources, which is undesirable. The qSBI has similar characteristics to the qZSI, except that the shoot-through mode is used for voltage boosting. A comprehensive comparison of the qSBI and qZSI was described [12]. However, the shootthrough duty cycle in these topologies cannot exceed (1–M), where M is the modulation index, thereby limiting the voltage gain in all of the above-mentioned topologies. To achieve the desired output voltage with a high voltage gain and good power quality, a high-duty cycle must be used, lowering M. The lower the value of M, the lower the overall DC-AC conversion gain and the higher the output harmonics. Either the M or the B.F. can be increased to increase the overall DC-AC gain. Numerous PWM techniques have been proposed for modifying the modulating waves, and it has been demonstrated that PWM schemes can only slightly increase M [7]. Numerous high-gain inverter circuits with and without a galvanic isolation transformer have been proposed [13–25] to increase the boost factor in impedance source converters. Transformer-based ZSIs have been introduced [13,14]. However, the transformer's leakage inductance results in voltage spikes at the DC-bus. To achieve a high voltage gain, transformerless ZSIs with additional passive components, such as inductors, capacitors, and diodes, have been proposed [15–25]. They have been labelled L-ZSI [15], SL-ZSI [16], SL-qZSI [17], EB-ZSI [18], DA-qZSI [19], CA-qZS [20], and EB-qZSI [21], and by incorporating switched-inductor, switched-capacitor, and hybrid switched-capacitor/switched-inductor designs, high boosting factors can be achieved. The addition of passive elements and power electronic components, on contrast, increases the converter's cost, size, volume, losses, and weight [24,25].

**Figure 1.** (**a**) Classical impedance source converters and (**b**) their applications in EV.

For single-phase and three-phase applications, the aforementioned topologies have been proposed. A simple single-phase HB ZSI with reduced capacitor voltage stress was described in [26]. Although this topology is straightforward and compact, it has a low boost factor. In [27], an HB-SBI with discontinuous input current was introduced to increase the gain of the inverter. To address the shortcomings of the HB-SBI, [28] proposed the HB-qSBI. The overall voltage gain is low in all of these half-bridge topologies [26–28]. By comparison, in the SL-ZSI [16], SL-qZSI [17], EB-ZSI [18], DA-qZSI [19], CA-qZSI [20], and EB-qZSI [21] topologies, the voltage stresses on the capacitors are greater, and these topologies employ a greater number of capacitors. The capacitor voltage is typically greater than the input voltage in order to perform the impedance-source stage's voltage boost function. As a result, high-voltage Z capacitors must be used, potentially adding volume and cost to the system. Because of the strong probability of capacitor failure during the field operation of power electronic converters [29], and the stringent reliability restrictions imposed by the

aerospace, automotive, defense, space, and energy industries, stresses and use of capacitors must be reduced to improve inverter reliability [30].

Overall, all of the mentioned topologies have common issues, such as the requirement for capacitors having a high voltage rating (greater than supply), common mode voltages, PWM-natured voltages after the inverter switching leg, and a higher component count when achieving a boosted DC-AC gain in a single stage manner. To address these issues, the capacitor clamped boost inverter with high voltage gain was introduced [31], which disperses the X-shaped passive components of the impedance source inverter rather than concentrating them in one location (between the input and inverter switching network in impedance source inverters). The passive components are distributed evenly between the input and output ports on each leg. However, ref. [31] does not deal with detailed steady-state analysis. Hence, in this study, a detailed analysis in various modes based on the inductor current *iL* bands (upper (*iLmax*) and lower bands (*iLmin*)) was conducted. Based on the upper and lower band values, the operation was divided into three zones in this study. Based on the aforementioned zones, the operation of the converter was further divided into two cases: *case-I* (*zone-1* and *zone-3*) and *case-II* (*zone-2*). In addition, this manuscript includes capacitor voltage profiles and capacitor life time calculations. This paper also discusses the design of a sliding mode controller for the CCBI to track the required voltages and currents to fulfil the specified load characteristics. Also shown are the CCBI's performance under load, reference, and phase sequence change conditions, and its THD profiles. In addition, the performance of this inverter for non-linear loads was also examined. The operating principles, steady-state analysis of various cases, differential modulation technique, capacitor voltage profiles, capacitor life time calculations, and sliding mode controller for the CCBI are presented in Section II. Simulation results and a discussion of the results under steady-state conditions, load and reference change, and phase sequence change conditions, along with THD profiles, are discussed in Section III. A performance investigation of this inverter for non-linear loads is also presented. In the same section, comparative analysis of the proposed inverter with existing similar converters is also presented, along with experimental verification. Section IV presents the conclusions.

#### **2. Operation of the CCBI**

The proposed inverter, depicted in Figure 2a, includes six switches, three small inductors, and three capacitors. Because of the time-varying duty cycle, the intrinsic boost feature of this proposed inverter provides flexibility for grid-connected and stand-alone applications, for a large range of AC output voltages, which are even higher than the DC voltage. This capability is not accessible in standard VSIs, where the DC input voltage is always greater than the AC output voltage [11]. The following offers an analysis of the converter in various modes, a differential modulation scheme, capacitor voltage profiles, a life time analysis, and a sliding mode controller.

#### *2.1. Analysis of Converter*

The operation of the converter shown in Figure 2a is explained with the help of a single-phase equivalent circuit, which is shown in Figure 2b. The equivalent circuit contains one leg (phase-A) along with considerations of the effect of other phases. Boost inverter upper switches are represented with odd numbers, whereas lower switches are represented with even numbers, and these switches operate in a complementary manner. Every inverter leg contains one inductor, one capacitor, and two switches. Analysis of the boost inverter is explained via mathematical modeling.

For one cycle (*0* < *t* < *T*) of load current (*iLoad*), the average value of the inductor current (*iL*) is positive and negative for the periods (0 < *t* < *T*/2) and (*T*/2 < *t* < *T*) respectively, which is shown in Figure 3, where *T* = 1/*f*. It can be observed that *iL* is oscillating at the switching frequency of *fs* between two bands, namely, the upper band (*iLmax*) and the lower band (*iLmin*). During the positive half cycle, the upper band is always positive. However, the lower band current value is negative in *zone-1* (*0* < *t* < *Ta*) and *zone-3* (*T*/2 − *Ta* < *t* < *T/2*),

whereas it is positive in *zone-2* (*Ta* < *t* < *T*/2 − *Ta*). Here, *Ta* is the time when *zone-1* comes to an end.

**Figure 2.** (**a**) Proposed converter; (**b**) single-phase equivalent circuit.

**Figure 3.** (**a**) Gate signals of S1 and S2 and inductor current for positive half cycle; inductor current in one switching cycle of (**b**) *zone-1*, (**c**) *zone-2*, and (**d**) *zone-3*.

Based on the aforementioned zones, the operation of converter is divided into two cases, *case-I* (*zone-1* and *zone-3*) and *case-II* (*zone-2*) as shown in Figure 3. To simplify the analysis further, only one switching sample is considered of N (*=fs*/*f*) samples, and the detailed description of both cases is given below.

*case-I (zone-1 and zone-3):* It is interesting to note that, in this case, all the semiconductor devices sequentially (*D*2, *S*2, *D*1, and *S*1) participate in one switching sample of *G*2, which is shown in Figure 4. Based on the conduction of these switching devices, the operation of the circuit in this case is further classified into four modes, and its equivalent circuit in each mode is shown in Figure 4. The operation of the inverter in various modes for *case-I* is explained below.

**Figure 4.** Equivalent circuit in various modes: (**a**) *Mode-1*; (**b**) *Mode-2*; (**c**) *Mode-3*; (**d**) *Mode-4*;

*Mode-1 (0* < *t* < *t1):* This mode starts when the gate signal is applied to the lower switch *S*2. However, *S*<sup>2</sup> cannot be turned on instantly due to the fact that the inductor does not allow the sudden change in current, as it is has a negative value in the previous mode. This leads the diode *D*<sup>1</sup> to be turned on and provide a path for a negative inductor current, as shown in Figure 4a.

This *iL* increases linearly in the presence of a positive supply voltage, as shown in Figure 5, and its current equation can be written as:

$$i\_L(t) = \frac{V\_{in}}{L}(t - T\_o) + i\_L(T\_o) \tag{1}$$

**Figure 5.** Waveforms during *case-I*.

This mode ends at *t* = *t*1, where *iL* becomes zero and diode *D*<sup>2</sup> turns off. The time duration of this *Mode-1* can be calculated as:

$$t\_1 = L \frac{i\_L(T\_o)}{V\_{in}} + T\_o \tag{2}$$

*Mode-2 (t1* < *t* < *t2):* This mode starts at *t* = *t*<sup>1</sup> when S2 comes into conduction. In the presence of a positive supply voltage (*Vin*) across the inductor, its current is increases linearly from 0 to *ILmax*, as shown in Figure 6, and its equation can be written as:

$$
\dot{u}\_L(t) = \frac{V\_{in}}{L}(t - t\_1) \tag{3}
$$

This mode ends at *t* = *t*2, when the switching pulse for *S2* is removed and the time duration of this mode can be evaluated as:

$$t\_2 - t\_1 = DT - t\_1 \tag{4}$$

*Mode-3 (Ton* < *t* < *t3):* This mode starts when the gate signal is given to switch *S1*. From the previous state, it is clear that the initial inductor current is positive (*ILmax*), which brings diode *D*<sup>1</sup> to conduction, even in the presence of firing pulses at *G*1, as shown in Figure 6. During this period, a negative voltage (*Vin* − *VAO*) appears across the inductor, which leads to the decrement of the inductor current with a negative slope of (*Vin* − *VAO*)/*L*, which can be expressed as:

$$i\_L(t) = \frac{V\_{in} - V\_{AO}}{L}(t - t\_2) + i\_L(t\_2) \tag{5}$$

**Figure 6.** Waveforms during *case-II*.

This mode ends at *t* = *t*3, when *iL* reaches zero and forces the diode to be turned off. The duration of this mode can be determined as:

$$t\_3 - DT = \frac{L\dot{t}\_L(t\_2)}{V\_{AO} - V\_{in}}\tag{6}$$

*Mode-4 (t3* < *t* < *T):* The zero-initial current of the inductor and the presence of the switching pulse brings *S1* to conduction mode. Now, the inductor discharges in the presence of a negative voltage (*Vin* − *VAO*) and, hence, the inductor current is decreased to a specific negative value (*ILmin*). This negative inductor current is the initial current for *Mode-1*. The expression for the inductor current is given as:

$$i\_L(t) = \frac{V\_{in} - V\_{AO}}{L}(t - t\_3) \tag{7}$$

This mode ends with the removal of the gate pulse of *S1* and the duration of this mode can be calculated as *t*<sup>4</sup> − *t*<sup>3</sup> = *T* − *t*3.

The same cycle of operation repeats until *t* = *Ta*. The inductor voltage balance equation during *case-I* can be written as:

$$\begin{array}{l}V\_{in}d\_{Ak}T\_s = (V\_{AO} - V\_{in})(1 - d\_{Ak})T\_s\\ \Rightarrow V\_{AO} = \frac{V\_{in}}{1 - d\_{Ak}}\end{array} \tag{8}$$

where *dAk* is the duty cycle at the '*k*th' switching sample of switch S2 of phase A. Waveforms during this case shown in Figure 5. As *dA* is a time-varying value, and when *d* > *da* at *t* = *Ta*, *case-I* ends.

*case-II (Ta* < *t* < *T/2* − *Ta):* This is the special case where *Mode-2* and *Mode-3* operations of *case-I* only take place as there is no negative value of *iLmin* and the remaining two cases are absent. In this case, only two semiconductor switches take active participation in conversion, namely, *S2* and *D1*, whereas the remaining two are in an idle state. Hence, two modes are sufficient to explain the operation; waveforms during this case are shown in Figure 6. It can be observed from the characteristics presented in Figures 5 and 6 that *case-II* is a special case of *case-I*, where only two modes (*Mode-2* and *Mode-3*) are presented during operation. Waveforms of lower switch gate pulses, inductor current, upper and lower diode and switch currents, coupled capacitor current, and input current are presented in Figure 6 respectively. A detailed explanation is presented below.

*Mode-1(Ta* < *t* < *t5):* This mode starts at *t* = *Ta*, at which instant firing pulses (*G*2) are given to *S2*. Due to a positive initial inductor current and the presence of *G*2, switch *S*<sup>2</sup> is turned on. In the presence of a positive voltage across the inductor, it is charged to a specific value, which can be expressed as:

$$i\_L(t) = \frac{V\_{in}}{L}(t - T\_p) + i\_L(T\_p) \tag{9}$$

This mode ends at *t* = *t*<sup>5</sup> when firing pulses are removed from *G2*.

*Mode-1 (t5* < *t* < *t6):* This mode of operation starts when pulses are given to *S1*. Although pulses are presented at *S*1, it cannot be turned on due to the positive initial current in the inductor. This turns on diode *D*1. Now, the negative voltage across the inductor causes a decrement in the current with the negative slope of (*Vin* − *VAO*)/*L*, which can be expressed as:

$$\dot{\iota}\_L(t) = \frac{V\_{\rm in} - V\_{AO}}{L}(t - T\_{\rm onb}) + \dot{\iota}\_L(T\_{\rm onb}) \tag{10}$$

This mode ends at *t* = *t6* when firing pulses are removed from *S*1. A similar operation (*Mode-1* and *Mode-2*) continues for several switching cycles until *(T*/2 − *Ta*). The voltage balance equation of the inductor obeys Equation (8), as discussed in *case-I*. Furthermore, the similarly boosted inverter operates in a negative half cycle, with the major role of *S1, D2* in *T*/2 to *(T*/2 + *Ta)*, and (*T* − *Ta*) to *T*, in addition to *D*1, *S*1, *D*2, and *S*<sup>2</sup> during (*T*/2 + *Ta*) to (*T* − *Ta*).

#### *2.2. Differential Modulation Technique for Three-Phase Boost Inverter*

As shown in (8), once the duty cycle becomes zero, *VAO* = *Vin*; this shows that this converter outputs a dc bias voltage in relation to the negative supply terminal. The primary goal of this study was to generate three-phase sinusoidal voltages across the load terminals of Figure 2a. Based on the gain of this boost inverter, we assume these voltages are modulated with the following duty cycles (*dA*, *dB*, and *dC*) as follows [13]:

$$\begin{array}{l} V\_{AO} = \frac{V\_{dc}}{1 - d\_A} = V\_{in} + A + A \sin \omega t\\ V\_{BO} = \frac{V\_{dc}}{1 - d\_B} = V\_{dc} + A + A \sin(\omega t - 120^{\circ})\\ V\_{CO} = \frac{V\_{dc}}{1 - d\_C} = V\_{dc} + A + A \sin(\omega t - 240^{\circ}) \end{array} \tag{11}$$

where *dA*, *dB*, and *dC* are the duty cycles of the *A*, *B*, and *C* phases, respectively, *Vin* is the bias DC voltage of the boost inverter (i.e., supply voltage), and A is the sinusoidal voltage amplitude. It should be noted that the CCBI one-leg voltage with regard to the negative terminal of a source (*VAO*, *VBO*, *VCO*) always has the same sign as *Vin*; thus, *(VAO*)*DC* must be added to maintain this necessary condition:

$$\begin{Bmatrix} V\_{AO}(t) = (V\_{AO})\_{DC} + (V\_{AO})\_{AC} \sin wt\\ V\_{BO}(t) = (V\_{BO})\_{DC} + (V\_{BO})\_{AC} \sin wt\\ V\_{CO}(t) = (V\_{CO})\_{DC} + (V\_{CO})\_{AC} \sin wt \end{Bmatrix} \tag{12}$$

Here

$$(V\_{dc} + \mathbf{A} = (V\_{AO})\_{DC} = (V\_{BO})\_{DC} = (V\_{CO})\_{DC} \& |V\_{AO}|\_{AC} = |V\_{BO}|\_{AC} = |V\_{CO}|\_{AC} \tag{13}$$

From the 1 − *φ* equivalent model of the 3 − *φ* boost inverter, as shown in Figure 2b, the phase voltage *VAN* applied to *RL* of the 3 − *φ* system can be obtained as [2]:

$$V\_{AN} = \frac{2}{3} \left[ V\_{A0} - \frac{1}{2} (V\_{\text{BO}} + V\_{\text{CO}}) \right] \tag{14}$$

The first term in (14) is the voltage *VAO* produced by the same phase of the boost converter, whereas the second and third terms account for the influence of the other two phases. It can be understood that the phase voltage of the load is a function of all of the three phases' leg voltages (*VAO*, *VBO*, and *VCO*), and for the particular load phase voltage, the other phases' leg voltages' combined effort can be grouped as:

$$V\_{cq} = \frac{1}{2}(V\_{\rm BO} + V\_{\rm CO})\tag{15}$$

The difference in *VANVeq* should also cause the same phase current in the 1 − *φ* model, so an equivalent resistance can be introduced, as mentioned below:

$$R\_{eq} = \frac{3}{2} R\_L \tag{16}$$

From Equations (12) and (14):

$$\begin{array}{ll} V\_{AN} &= \frac{2}{3} \left\{ \left[ \left( V\_{AO} \right)\_{DC} + \left( V\_{AO} \right)\_{DC} \sin \omega t \right] \\ &- \frac{1}{2} \left[ \left( V\_{BO} \right)\_{DC} + \left( V\_{BO} \right)\_{DC} \sin(\omega t - 120) \right. \\ &+ \left( V\_{CO} \right)\_{DC} + \left( V\_{CO} \right)\_{DC} \sin(\omega t - 240) \right] \right\} \\ \Rightarrow & V\_{AN} = \left( V\_{AO} \right)\_{AC} \sin \omega t \end{array} \tag{17}$$

In a similar way, *VBN* and *VCN* have a 120◦ phase shift at the load terminals. Therefore, the phase-to-neutral voltages at the load are:

$$\begin{array}{l} V\_{AN} = \left( V\_{AO} \right)\_{\mathcal{AC}} \sin \omega t\\ V\_{BN} = \left( V\_{AO} \right)\_{\mathcal{AC}} \sin(\omega t - 120^{\circ})\\ V\_{CN} = \left( V\_{AO} \right)\_{\mathcal{AC}} \sin(\omega t - 240^{\circ}) \end{array} \tag{18}$$

These ideal outcomes can be achieved by calculating the three-phase duty cycles using:

$$\begin{cases} D\_A(t) = 1 - \frac{V\_{in}}{(V\_{AO})\_{DC} + (V\_{AO})\_{AC} \sin wt}{V\_{in}}\\ D\_B(t) = 1 - \frac{V\_{in}}{(V\_{BO})\_{DC} + (V\_{IO})\_{AC} \sin (wt - 120^\circ)}{V\_{in}}\\ D\_C(t) = 1 - \frac{V\_{in}}{(V\_{CO})\_{DC} + (V\_{CO})\_{AC} \sin (wt - 240^\circ)} \end{cases} \tag{19}$$

#### *2.3. Capacitor Voltage Profile*

One of the main objectives of this study was to reduce the capacitor peak voltages, which can be calculated for the CCBI as follows:

$$\begin{array}{l} V\_{\text{CA}} = \left( V\_{\text{AO}} \right)\_{\text{DC}} + \left( V\_{\text{AO}} \right)\_{\text{AC}} \sin \omega t - V\_{\text{in}} \\ \Rightarrow V\_{\text{CA}} = \left( V\_{\text{CO}} \right)\_{\text{DC}} + \left( V\_{\text{CO}} \right)\_{\text{AC}} \sin \omega t \end{array} \tag{20}$$

Here (*VCO*) *DC* = (*VAO*) *DC* − *Vin*, and can be calculated as:

$$\begin{aligned} \left(\left(V\_{\text{CO}}\right)\_{\text{DC}} = \left(V\_{\text{AO}}\right)\_{\text{DC}} - V\_{\text{in}}\\ \Rightarrow \left(V\_{\text{CO}}\right)\_{\text{DC}} = \begin{pmatrix} \frac{D}{1 - D} \\ \frac{1 - D}{1 - D} \end{pmatrix} V\_{\text{in}} \end{aligned} \tag{21}$$

Whereas in case of other topologies, the capacitor voltages are higher due to the requirement of a higher dc link voltage for the required DC-AC conversion. Capacitor voltage profiles for the DC-AC conversion of 1 to 1.8 in the proposed case and other similar impedance source inverters are shown in Figure 7, which depicts the reduction in voltage stress on the capacitor.

**Figure 7.** Capacitor voltage profiles.

#### *2.4. Life Time Calculation for Capacitor*

To examine the life time benchmarks of different capacitor solutions and online condition monitoring, life models are used. Generally, the life time of the capacitors is greatly influenced by two factors, namely, voltage stress and temperature. The most extensively accepted empirical model for capacitor life is:

$$\tau = \tau\_0 \times \left(\frac{V}{V\_o}\right)^{-n} \times \exp\left[\left(\frac{E\_a}{K\_B}\right)\left(\frac{1}{\theta} - \frac{1}{\theta\_0}\right)\right] \tag{22}$$

where *τ* is the life time under use conditions, *τ<sup>o</sup>* is the life time under test conditions, *V* is the voltage at use conditions, and *V0* is the voltage at test conditions. *θ* and *θ*<sup>0</sup> are the temperature (Kelvin) at use and test conditions, respectively. *Ea* is the activation energy, *KB* is Boltzmann's constant (8.62 × <sup>10</sup>−<sup>5</sup> eV/K), and n is the voltage stress exponent.

From (22), it is clear that Ea and n are the key parameters to determine the life time; its values were found to be 1.19 and 2.46 for high dielectric constant ceramic, and 1.3–1.5 and 1.5–7 for MLC-Caps.

For Al-Caps and film capacitors, a simplified model from (22) is popularly applied as follows [14]:

$$
\pi = \pi\_o \times \left(\frac{V}{V\_o}\right)^{-n} \times 2^{\frac{\theta\_0 - \theta}{10}} \tag{23}
$$

#### *2.5. Sliding Mode Controller*

When a sliding mode controller is adopted, the system performs effectively in both steady-state and dynamic operations. Although more complicated control approaches, such as THD, can increase system performance, the observed results look satisfactory in many circumstances of practical importance, while the basic controller lowers system cost. An experimental prototype was created, and the experimental findings show that the converter is capable of step-up [2].

The following reasonable assumptions must be considered when designing the sliding mode controller for the proposed converter: power switches that are ideal, converters that operate at high switching frequencies, and power supplies that are free of sinusoidal ripple. Each phase of the proposed converter has two state variables. The sliding surface equation of state space in a three-phase system is expressed as:

$$\begin{array}{l} s\_1(i\_{La}, v\_d) = K\_{a1}\varepsilon\_{a1} + K\_{a2}\varepsilon\_{a2} = 0\\ s\_2(i\_{Lb}, v\_b) = K\_{b1}\varepsilon\_{b1} + K\_{b2}\varepsilon\_{b2} = 0\\ s\_3(i\_{Lc}, v\_c) = K\_{c1}\varepsilon\_{c1} + K\_{c2}\varepsilon\_{c2} = 0 \end{array} \tag{24}$$

where:

$$
\begin{bmatrix} \varepsilon\_{d1} \\ \varepsilon\_{b1} \\ \varepsilon\_{b1} \end{bmatrix} = \begin{bmatrix} i\_{la} \\ i\_{lb} \\ i\_{lc} \end{bmatrix} - \begin{bmatrix} i\_{la\_{ref}} \\ i\_{lb\_{ref}} \\ i\_{lc\_{ref}} \end{bmatrix} \otimes \begin{bmatrix} \varepsilon\_{d2} \\ \varepsilon\_{b2} \\ \varepsilon\_{c2} \end{bmatrix} = \begin{bmatrix} \upsilon\_a \\ \upsilon\_b \\ \upsilon\_c \end{bmatrix} - \begin{bmatrix} \upsilon\_{a\_{ref}} \\ \upsilon\_{b\_{ref}} \\ \upsilon\_{c\_{ref}} \end{bmatrix} \tag{25}
$$

In sliding mode control theory, sensing of all state variables is required to generate the proper control signals and obtain the required AC supply. The generation of the inductor current reference is difficult to assess because it is dependent on several factors, such as supply voltage, load demand, and load voltage. As a result, *iL*-*iLref* can be generated directly from the high frequency component of the inductor current feedback signal, which must be removed due to the control strategy by designing a suitable high pass filter. The addition of a high pass filter increases system order and has the potential to change system dynamics. To overcome this issue, the selected values of the CCBI's switching frequency were higher than the filter cut-off frequency. The trajectory of the sliding surface for this design is shown in Figure 8.

**Figure 8.** Trajectory of the sliding surface.

#### **3. Results and Discussions**

The proposed 3 − *φ* CCBI, as shown in Figure 9, was successfully assessed by means of both simulations and prototype-based hardware results. Simulations were carried out using the MATLAB Simulink environment, and the parameters considered for the simulations are summarized in Table 1, as shown below.

**Figure 9.** Complete system diagram of the hardware setup.

**Table 1.** Electrical parameters of the system.


The following results were acquired at the average switching frequency (*Fs*) equal to 10 kHz. A sliding mode controller was used to achieve good dynamic response, high robustness, and noise-free response while tracking the required 3 − *φ* AC from DC supply. System state variables were continuously monitored and controlled near to a zero error response with the hysteresis band = 0.3, filter constant = 0.01, *K*<sup>1</sup> = 0.304, and *K*<sup>2</sup> = 0.2. System performance was evaluated in both a steady state and transient states while feeding power to different types of loads (linear and nonlinear) under different test conditions. 3 − *φ* Phase voltages, line voltages, and load currents obtained from this inverter are shown in Figures 10–12, respectively. From these results, it can be clearly seen that the input low-level DC supply was successfully converted to ideal sinusoidal three-phase AC power.

**Figure 10.** Phase voltage of the inverter during steady-state conditions.

**Figure 11.** Line voltages of the inverter during steady-state conditions.

**Figure 12.** Load currents of the inverter during steady-state conditions.

In the boost inverter topology, at least one capacitor is placed in every leg of the respective phase of the converter for the boosting operation. The negative terminals of each of the three capacitors of the three-phase inverter are connected to a common point in this topology, and these are also shown in Figure 13. With reference to this point, the common mode capacitor voltage (*CMMCV*) is defined as the average of all of the three capacitor voltages (*VAO*, *VBO*, and *VCO*) and is shown in Figure 14. In Figure 14, the conventional CMMCV is calculated for the topology proposed by Cecati and compared with the proposed topology. Figure 14 shows that the CMMCV across all of the three capacitors is greatly reduced by the proposed scheme, due to the fact that the individual capacitor voltage is also lower than that of the conventional topology. Figures 15 and 16 were captured for the critical evaluation of the harmonic content contained at the output. These results show the THD waveforms of phase voltage, line voltage, and load current, respectively; from these results, it can be clearly understood that this inverter offers good quality of AC output without any lowest order harmonics (<3% of fundamental) for resistive load. All of the harmonic quantities are lower than 1.5% of the fundamental.

**Figure 13.** Capacitor voltages of the inverter during steady-state conditions.

**Figure 14.** Common mode capacitor voltages.

**Figure 15.** THD waveform of line voltage.

**Figure 16.** THD waveform of load current.

In order to assess the dynamic performance of the converter, sudden changes were incorporated during the operation of the converter at load (increased by 50% and decreased by 50%), and in the reference voltage (decreased by 50% and changed the phase by 180◦), and results were captured in each case for analysis. Figure 17 shows the current drawn by the 100% load (1.2 kW) from (0 to 0.04 s) and 50% load (0.6 kW) from (0.04 to 0.08 s), whereas Figure 18 depicts the opposite case of loading, i.e., 50% loading from (0 to 0.04 s) and 100% load from (0.04 to 0.08 s). Figure 19 was captured when the mode of operation is suddenly changed from active mode to regeneration mode at 0.04 s. Although the mode is changed from the active mode to the regeneration mode, the voltage amplitude remains constant, and its harmonics also remain the same. Figures 20–23 show the phase voltages, line voltages, load currents, and capacitor voltages observed when the reference voltage is suddenly changed from 100% to 50% at 0.04 s. Whenever the reference voltage is changed, the output voltage changes, and the current also changes accordingly for the resistive load. THD waveforms in the case in which the reference voltage is changed were captured after

the disturbance was settled, and are shown in Figures 23–25. These results (Figures 20–23) reveal that the CCBI with a sliding mode offers good dynamic response in stable operation, even for all kinds of disturbances, as discussed earlier.

**Figure 17.** Load current for a linear load with a step change in the load from 100 to 50%.

**Figure 18.** Load current for a linear load and a step change in the load from 100 to 50%.

**Figure 19.** Load current for the inversion mode of the load.

**Figure 20.** Phase voltages for a linear load and a step change in the reference load voltage from 100 to 50%.

**Figure 21.** Line voltages for a linear load and a step change in the reference load voltage from 100 to 50%.

**Figure 22.** Load currents for a linear load and a step change in the reference load voltage from 100 to 50%.

**Figure 23.** Capacitor voltages for a linear load and a step change in the reference load voltage from 100 to 50%.

**Figure 24.** Load voltage and load current for a linear load and a step change in the reference load voltage from 50%.

**Figure 25.** Load voltage and load current for a linear load and a step change in the reference load voltage from 100 to 33%.

For critical evaluation of the converter, the inverter output is fed to a nonlinear load (three-phase diode bridge rectifier with R Load of 255 Ω), and Figures 26–33 show the CCB inverter-fed diode bridge output currents and voltage, the diode bridge input line voltage and currents, the capacitor voltages of CCB and CMMCV, and the harmonic spectra of diode bridge input voltage and currents, respectively. Under steady-state mode, the diode bridge rectifier-fed resistive load absorbs the highly distorted current of 31.39% THD and voltage of 7.25% THD, as shown in Figures 32 and 33, respectively. All of the foregoing data show that the CCB inverter has good behavior, and particularly superior dynamic behavior, which is mostly due to the lower values of the boost capacitances and voltage across the capacitor. This performance is especially notable when compared to that of a current source inverter (CSI); whereas the proposed system employs three independent small inductors, the CSI employs only one large inductor, resulting in much poorer dynamic performance.

**Figure 26.** Non-linear load (diode bridge) output currents.

**Figure 27.** Non-linear load (diode bridge) output voltages.

**Figure 28.** Non-linear load (diode bridge) input voltages.

**Figure 29.** Non-linear load (diode bridge) input currents.

**Figure 30.** Capacitor voltages of the CCBI.

**Figure 31.** Common mode voltages of the CCBI.

**Figure 32.** CCBI voltage THD for the nonlinear (diode bridge) load.

**Figure 33.** CCBI current THD for the nonlinear (diode bridge) load.

*Comparison of the CCBI with ZSI:* For the same source and load, and required gain, ZSI is implemented with the shoot-through duty of 0.4091 and AC-side filter components of inductor Lf = 0.25 mH and capacitor Cf = 44 μH. Its load parameters, z-source capacitor voltages, and CMMV are presented in Figures 34–36.

**Figure 34.** Load voltage and current of ZSI.

**Figure 35.** Z-source capacitor voltages of ZSI.

**Figure 36.** Common mode voltages of ZSI.

From these results (Figures 21 and 34), it can be understood that peak voltages (956 V in the impedance source inverter and 910 V in the CCBI) and settling time to reach the steady state (0.065 s for the impedance source inverter and 0.021 s for the CCBI) are higher in the case of the impedance source inverter. The peak capacitor voltage is 1124 V in the case of the impedance source inverter, whereas it is 1056 V in the case of the CCBI. It can also be seen that CMMV in the case of the impedance source inverter has a PWM nature, as depicted in Figure 36, whereas it has a steady nature in the case of the CCBI, as depicted in Figure 14. Hence, it can be understood that the CCBI offers better performance for the single-stage power conversion.

In addition, in terms of the number of components, voltage and current THDs, capacitor voltage stresses, and boost factors, the performance of this inverter was compared to that of existing inverter topologies. Figures 37–40 provide these comparative characteristics. In comparison to other topologies, the implementation of the CCBI requires fewer components, as seen in Figure 37. As a result, the converter's cost, size, and volume are reduced. THD (both voltage and current) profiles of the proposed inverter, and the studied inverter topologies, were captured for comparative analysis. It is worth noting that, with the exception of the boost and CCBI topologies, AC filters are utilized on the AC side in all other topologies. The CCBI is able to deliver greater performance in terms of THDs even under these conditions, as seen in Figure 38.

**Figure 37.** Bar chart of no. of components used in different topologies.

**Figure 38.** THD values in different topologies.

**Figure 39.** Total capacitor stress in different topologies.

**Figure 40.** Boost factors in different topologies.

The total capacitor stresses in the CCBI are quite low as compared to other topologies, as shown in Figure 39. Because the capacitor is the most vulnerable component in an inverter in terms of reliability, reducing voltage stresses on the capacitor improves its reliability. As shown in Figure 40, the proposed converter is capable of providing superior gain than the existing topologies despite having fewer boosting factors. This function aids in the reduction in stresses on the inverter's capacitors and switches. Overall, the proposed inverters provide higher performance in terms of number of components, voltage and current THDs, capacitor voltage stresses, and boost factors, as evidenced by these comparative data.

*Experimentation Results:* For the experimental verifications, a laboratory-made test bench was developed, as illustrated in Figure 41. It consists mainly of six IRF460 MOSFETs (500 V, 16 A) driven by a TLP25-based optically isolated driver circuit, three EZPE50506MTA capacitors (15 μF), and three inductors (0.6 mH). Inductor currents and capacitor voltages are sensed by a TELCON-25 and AD202JN-based signal measurement and conditioning circuit.

**Figure 41.** Prototype of the boost inverter.

The quantities sensed by these sensor-based resistor networks are then applied to the corresponding multiplexer (HEF4052B) input terminals via filtering, amplifying, and biasing circuits. All of the sensed parameters are sent to the FPGA Spartan-3E kit via a multiplexer circuit. Two 2-channel multiplexers are used in time division multiplexing to independently process inductor currents and capacitor voltages. Inductor currents and capacitor voltages are time division multiplexed and processed on the FPGA kit's on-board ADC (LTC1407A). Internally, these signals are demultiplexed using VHDL code. Using demultiplexed inductor currents and capacitor voltages, a VHDL-programmed sliding mode controller generates gating pulses to the inverter.

This prototype was tested with a 150 V DC supply to demonstrate the proposed inverter's step-up capability, and the results were monitored in a closed-loop manner, with the control logic developed in an FPGA Sparta-3e XC3S500e board. The CCBI converts 150 V DC to three-phase AC with a peak voltage of 282 volts, 163.29 V (peak) phase voltage, and 4.89 A (peak) phase current. These conversion pole voltages are shown in Figure 42. Load currents are depicted in Figure 43. These findings show that the converter's performance is consistent with the simulation results. Simulation and hardware tests confirm that the inverter is performing proper DC-AC conversion.

**Figure 43.** Load current [1 A/div].

#### **4. Conclusions**

This research suggested and successfully validated a unique three-phase, step-up DC-AC converter for distributed power generation using both simulation and experimental data. This converter successfully demonstrated single-stage operation in the same way as any other impedance source converter. Both simulation and experimental results verified that the operating voltages across the capacitors are reduced, resulting in increased capacitor and converter reliability and longevity. In addition to the technology, this inverter offers a lower boosting factor for the necessary DC-AC conversion, thus requiring a lower dc link voltage. When compared to other impedance source converters for the same DC-AC conversion, this feature has a high side gate isolation voltage requirement. In this paper, detailed operations in various modes are presented, along with differential pulse width modulation and a sliding mode controller.

**Future work:** A performance investigation of the CCBI in electrical vehicle loads with different drive cycles, and in distributed power generation with different environmental conditions, can comprise the future scope of work.

**Author Contributions:** Writing—original draft and resources, D.R. and P.R.; conceptualisation, methodology, D.R. and P.R.; investigation, D.R., B.L.N. and Y.S.B.; review and editing, D.R., H.H.F. and E.R. All authors have read and agreed to the published version of the manuscript.

**Funding:** Unitatea Executiva Pentru Finantarea Invatamantului Superior a Cercetarii Dezvoltarii si Inovarii: PN-III-P4-ID-PCE-2020-0008.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** Not applicable.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **Nomenclature**


#### **References**


**Dong Yan, Lijun Hang \*, Yuanbin He, Zhen He and Pingliang Zeng**

College of Automation, Hangzhou Dianzi University, Hangzhou 310018, China; ayyzyd@163.com (D.Y.); yuanbinhe@hdu.edu.cn (Y.H.); hezhen\_hz@hdu.edu.cn (Z.H.); plzeng@hotmail.com (P.Z.)

**\*** Correspondence: ljhang@hdu.edu.cn

**Abstract:** The Gallium Nitride high electron mobility transistor (GaN HEMT) has been considered as a potential power semiconductor device for high switching speed and high power density application since its commercialization. Compared with the traditional Si transistors, GaN HEMT has faster switching speed and lower on-off loss. As a result, it is more sensitive to the nonlinear parameters due to the fast switching speed. The subsequent voltage and current overshooting will affect the efficiency and safety of the GaN HEMT and power electronic systems. In this paper, an accurate switching transient analytical model for GaN HEMT is proposed, which considers the effects of parasitic inductances, nonlinear junction capacitances and nonlinear transconductance. The model characteristic of turn-ON process and turn-OFF process is illustrated in detail, and the equivalent circuits are derived for each switching transition. The accuracy of the proposed model can be verified by comparing the predicted switching waveform and switching loss with that of the experimental results based on the double pulse test (DPT) circuit. Compared with the conventional model, the proposed model is more accurate and matches better with the experimental results than the conventional model. Finally, this model can be used for analyzing the influences of gate resistance, nonlinear junction capacitances, and parasitic inductances on switching transient waveform and refining calculation switching loss.

**Keywords:** GaN HEMT; switching transient analytical model; parasitic inductance; nonlinear junction capacitance; nonlinear transconductance; double pulse test

#### **1. Introduction**

GALLIUM NITRIDE (GaN) is a typical representative of the third generation wide band gap semiconductor materials and has a broad application prospect. In recent years, Gallium Nitride high electron mobility transistor (GaN HEMT) has been successfully applied to high frequency and high power density converters [1]. GaN HEMT can not only attain small conduction resistance, but also push the switching frequency to several megahertz when comparing with the state-of-the-art Si MOSFETs. Nevertheless, high frequency switching transient still brings some extra problems, such as voltage and current overshooting, and even instability. As a result, it is more sensitive to the nonlinear parameters because of high dv/dt and di/dt. Meanwhile, the subsequent switching process ringing will affect the efficiency and reliability of the GaN HEMT devices and power electronic systems [2]. In order to fully utilize the GaN HEMT, it is necessary to analyze the parameters' effects upon switching loss and the switching transient characteristic.

Generally, the switching transient of devices can be analyzed by experimental testing [3] or software simulation method [4]. However, these methods cannot give a definitive or analytical explanation of the influence mechanism of the nonlinear parameters in devices. Therefore, an accurate switching transient analytical model for estimating the switching loss and influence of nonlinear parameters is necessary.

The popular switching transient analytical model is the piecewise linear model [5]. However, the nonlinear parameters are not taken into account so that the calculated results

**Citation:** Yan, D.; Hang, L.; He, Y.; He, Z.; Zeng, P. An Accurate Switching Transient Analytical Model for GaN HEMT under the Influence of Nonlinear Parameters. *Energies* **2022**, *15*, 2966. https://doi.org/ 10.3390/en15082966

Academic Editor: Denis N. Sidorov

Received: 2 March 2022 Accepted: 14 April 2022 Published: 18 April 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

do not agree with the experimental results very well, especially in high frequency applications, since the switching transient and switching loss are not well evaluated. In study [6], a second-order analytical model is proposed. More comprehensive analytical models of Si MOSFETs are presented in [7–9]. These models consider the parasitic inductances and the nonlinear junction capacitances properly. On this basis, the authors of [10] apply the analysis model to develop the SiC MOSFET model, whereas, in some of the derivation, the parameter setting is idealistic. The nonlinear parameters' modeling results in [11] is too complex due to the numerical method or iterative calculations. In studies [12–14], the impact of nonlinear capacitance and nonlinear transconductance in SiC MOSFET is discussed, and a semi-physical semi-behavioral analytical model for switching transient of SiC MOSFET power module is proposed. However, these models are still not suitable for GaN HEMT devices, because GaN HEMT have no reverse recovery characteristics, and have smaller charge capacitance and parasitic inductance in contrast to Si MOSFET and SiC MOSFET [15].

In study [16], a switching loss model for GaN HEMT is proposed. The model considers the nonlinear junction capacitances as piecewise linear structure, so it still cannot precisely represent the nonlinear characteristics. In studies [17–19], the adopted interpolation method is used to fit nonlinear junction capacitances of GaN HEMT. However, this method has no specific mathematical expression and the results are too complex. In study [20], the package and PCB parasitic inductances, as well as the nonlinear capacitances are considered in the GaN HEMT model, but this model only includes the turn-ON process without switching loss calculation and parameter analysis. Some analytical models are proposed for cascode GaN HEMT [21,22]. These models cannot be directly applied to the GaN HEMT because of the different structure. Therefore, a more accurate switching transient analytical model for GaN HEMT is needed to explain the influence of nonlinear parameters and calculate the loss accurately. The main contributions of this paper are:


#### **2. Novel Analytical Model of GaN HEMT Device**

In order to test and evaluate the switching characteristics of GaN HEMT, a double pulse test (DPT) circuit with inductive load can be adopted as illustrated in Figure 1, where *Q* and *Q\_H* represent the lower switch and upper GaN HEMT device of the half bridge. In this paper, the GaN HEMT device of GS61004B produced by GaN systems company will be illustrated as an example. *Cgs*, *Cgd*, and *Cds* represent the capacitors of gate source, gate drain, and drain source, respectively. To simplify the circuit analysis, the parasitic inductance and package stray inductance are accounted into *Ld*, *Ls*, *Lg*. *Lloop* lumps all of the parasitic inductances and package stray inductances along the power loop. The GaN HEMT device does not contain a p-n diode, but the way they conduct in the reverse direction is similar to diodes because this channel is formed by turning on the two-dimensional electron gas (2DEG) in the device.

**Figure 1.** Circuit schematic of double pulse test bench.

In Figure 1, it is very important to determine the parasitic inductances and nonlinear parameters to obtain an accurate switching transient analytical model. Generally, the parasitic inductances can be acquired by Maxwell 3-D software and the nonlinear parameters can be obtained by the modeling method, such as the input capacitance *Ciss* = *Cgs* + *Cgd*, the output capacitance *Coss* = *Cds* + *Cgd*, and the reverse capacitance *Crss* = *Cgd*. *Ciss* and *Crss* can be fitted by simple piecewise linear equation due to their low degree of nonlinearity. However, *Coss* is a parameter that changes dramatically with the variation of *vds* at low voltage level, which is with high degree of nonlinearity, and is more difficult to be accurately modeled by the above methods. A nonlinear function tanh(*x*) will be introduced to represent *Coss* in this paper, as shown in Equation (1). This function can be used to approximate the *Coss* during switching process.

$$\tanh(\mathfrak{x}) = \frac{e^{\mathfrak{x}} - e^{-\mathfrak{x}}}{e^{\mathfrak{x}} + e^{-\mathfrak{x}}} \tag{1}$$

Based on tanh(*x*), a nonlinear function shown in Equation (2) is proposed to fitting the nonlinear characteristic of the *Coss* of GS61004B, which can model different changing rate of *Coss* when *vds* began to change in low voltage.

$$\mathcal{L}\_{\text{ess}} = \mathcal{L}\_{\text{owux}} (1 + \upsilon\_{\text{ds}} (1 + k\_1 (1 + \tanh(k\_2 \cdot \upsilon\_{\text{ds}} + k\_3))))^{k\_4} \tag{2}$$

where *Comax*, *k*1, *k*2, *k*3, and *k*<sup>4</sup> are the fitting parameters and are given in Table 1. This method has more accuracy modeling results. The modeling results *Coss* of GaN HEMT is verified in Figure 2a, and it can be concluded that the maximum error between the fitted data and extracted data from the datasheet is less than 3%. Furthermore, this model can also be applied to other different types of devices by adjusting the parameters.

**Figure 2.** Modeling results and datasheet: (**a**) Nonlinear capacitances; (**b**) Transfer characteristic curves.

Transconductance *gfs* describes the dynamic behavioral feature of *ich* when *vgs* changes. Using a single value of transconductance has a large opportunity to cause great errors. In this paper, the slope of the tangent line in the transfer characteristic curve is used to approximate the transconductance at the corresponding operation point. Thus, the equation of *gfs* can be expressed as Equation (3).

$$\begin{cases} \begin{aligned} g\_{fs} &= 0 & v\_{\mathbb{S}^3} &< V\_{th} \\\ g\_{fs} = \frac{di\_{th}}{dv\_{\mathbb{S}^3}} &= k5 \left( v\_{\mathbb{S}^5} - V\_{th} \right)^{k\_6 - 1} & v\_{\mathbb{S}^3} &\ge V\_{th} \end{aligned} \tag{3}$$

where *k*<sup>5</sup> and *k*<sup>6</sup> are the fitting parameters which are given in Table 1 as well. *Vth* is the threshold voltage of gate to source for the device. Figure 2b shows the curve of *ich* versus *vgs*. It is obvious that the modeling result makes an accurate estimation based on the proposed model.



#### **3. Transient Characteristic Analysis of Turn-On Process Based on the Proposed Model**

A typical waveform during turn-ON process of the GaN HEMT half bridge is shown in Figure 3. There are four stages during the switching process and each stage has different features according to the change of the circuit structure. At each stage, the equations can be obtained from the corresponding equivalent circuit which is illustrated in Figure 4. By solving the equations, we can obtain five variables, namely, the gate current *ig*, the gate source voltage *vgs*, the drain current *id*, the drain source voltage *vds*, and the drain source voltage *vds\_H*. The nonlinear junction capacitance and nonlinear transconductance modeling results proposed in Section 2 will be applied to the turn-ON process in the

following analysis. Thus, the analytical model of each variable during turn-ON process can be derived. Furthermore, the switching loss during the turn-ON process can be obtained.

**Figure 3.** Typical waveforms during turn-ON process.

**Figure 4.** Equivalent circuits for different stages during turn-ON period: (**a**) Stage I; (**b**) Stage II; (**c**) Stage III; (**d**) Stage IV.

#### *3.1. Stage I (t0–t1): Turn-On Delay Period*

As shown in Figure 3, at time *t*0, the gate drive voltage *Vg* is applied. In this stage, the gate current charges the capacitance *Cgs* which causes *vgs* to rise. The equivalent circuit of this stage is shown in Figure 4a. According to the equivalent circuit, the following equations can be obtained:

$$V\_{\mathcal{S}} = (L\_{\mathcal{S}} + L\_{\mathfrak{s}}) \frac{di\_{\mathfrak{s}}}{dt} + R\_{\mathfrak{s}} i\_{\mathfrak{s}} + v\_{\mathfrak{s}^{\mathfrak{s}}} \tag{4}$$

$$d\_{\mathcal{S}} = \mathcal{C}\_{\mathcal{S}^s} \frac{d\upsilon\_{\mathcal{S}^s}}{dt} \tag{5}$$

This stage ends at time *t*<sup>1</sup> when *vgs* reaches the threshold voltage *Vth*. During this stage, *Q* is still OFF, the drain source voltage *vds*, and the drain current *id* are constant, so there is no switching loss.

#### *3.2. Stage II (t1–t2): Current Rise Period*

As shown in Figure 3, at time *t*1, *vgs* reaches the threshold voltage *Vth*, and the channel current *ich* begins to rise which can be expressed by Equation (3). At the same time, the capacitances *Coss* begins to discharge through the channel of *Q*. The drain current id is clamped to the sum of the channel current *ich* and the *Coss* discharging current. However, *Q\_H* is still in reverse conduction condition, where *Ron* is the on-state resistance and *Vr* represents the reverse conducting voltage drop of *Q\_H*. There will be a voltage drop Δ*V* between *vds* and its initial voltage *VDC* + *Vr* on the parasitic inductance of the power loop. As shown in the equivalent circuit of Figure 4b, the equations of this stage are as follows:

$$V\_{\mathcal{S}} = v\_{\mathcal{S}^5} + R\_{\mathcal{S}}i\_{\mathcal{S}} + L\_{\mathcal{S}}\frac{di\_{\mathcal{S}}}{dt} + L\_{\mathcal{s}}(\frac{di\_d}{dt} + \frac{di\_{\mathcal{S}}}{dt}) \tag{6}$$

$$i\_{\mathcal{S}} = \mathbb{C}\_{\mathbb{S}^{\mathfrak{s}}} \frac{dv\_{\mathbb{S}^{\mathfrak{s}}}}{dt} + \mathbb{C}\_{\mathbb{S}^{d}} (\frac{dv\_{\mathbb{S}^{\mathfrak{s}}}}{dt} - \frac{dv\_{\mathbb{S}^{\mathfrak{s}}}}{dt}) \tag{7}$$

$$\dot{u}\_d = \mathcal{g}\_{fs}(\upsilon\_{\mathcal{S}^s} - V\_{th}) + \mathbb{C}\_{ds}\frac{d\upsilon\_{ds}}{dt} - \mathbb{C}\_{\mathbb{g}d}\frac{d(\upsilon\_{\mathcal{S}^s} - \upsilon\_{ds})}{dt} \tag{8}$$

$$V\_{DC} = v\_{ds} + v\_{ds\\_H} + (L\_d + L\_s)\frac{di\_d}{dt} + L\_s \frac{di\_s}{dt} \tag{9}$$

$$
\upsilon\_{ds\\_H} = R\_{on}(I\_L - i\_d) - V\_r \tag{10}
$$

This stage ends when the drain current *id* reaches the load current *IL*. Meanwhile, *vgs* reaches Miller plateau voltage. It should be especially noted that the voltage drop Δ*V* is shown in the following equation:

$$
\Delta V = (L\_d + L\_s) \frac{d\dot{l}\_d}{dt} \tag{11}
$$

In case of *Ld* and *Ls* being larger, Δ*V* will drop faster, so *id* would change even slower than *vds*. The transient will skip the voltage drop stage III into ringing stage IV directly. While for small *Ld* and *Ls* of properly designed PCB and reasonable current rising speed, stage III will occur as expected.

During this stage, the energy loss can be expressed as:

$$E\_{\rm ou} = \int\_{t2}^{t1} v\_{ds} \cdot i\_{\rm ch} dt \tag{12}$$

The power loss in this stage can be determined by:

$$\begin{aligned} P\_{\text{on}} &= f\_{\text{s}} \cdot E\_{\text{on}} \\ &= f\_{\text{s}} \cdot \int\_{t2}^{t1} v\_{ds} \cdot i\_{\text{ch}} dt \end{aligned} \tag{13}$$

where *fs* is the switching frequency. However, only id can be measured experimentally, ich cannot. During the turn-ON process, a part of the energy stored in *Coss* is dissipated through the channel, which is not included in the loss calculated by *id*. Thus, the relationship can be expressed as:

$$P\_{\rm out} = f\_{\rm s} \cdot \int\_{t2}^{t1} v\_{\rm ds} \cdot i\_d dt + P\_{\rm Cons} \tag{14}$$

where *PCoss* represents the energy stored in the output capacitance when the applied voltage is *VDC* + *Vr* and can be expressed as:

$$P\_{\text{Coss}} = f\_s \cdot \int\_0^{V\_{D\subset} + V\_r} v\_{ds} \cdot \mathbb{C}\_{\text{oss}}(v\_{ds}) dv\_{ds} \tag{15}$$

*Coss*(*vds*) can be determined by Equation (2), which is plotted in Figure 2a.

#### *3.3. Stage III (t2–t3): Voltage Decline Period*

As shown in Figure 3, at time *t*2, the upper switch GaN HEMT device *Q\_H* stops conducting, and the channel current *ich* surpasses the load current *IL*. This surpasses current charge of the output capacitance *Coss\_H* of *Q*\_*H*. The upper switch can be equivalent to the output capacitor *Coss\_H*, and *vds\_H* is increased. Correspondingly, *vds* decreases and *Coss* continues to discharge through the channel of *Q*. *id* may have a ringing because of the effect of parasitic *LC* elements on the device. The equivalent circuit of this stage is illustrated in Figure 4c. The circuit equations can be expressed as:

$$\dot{m}\_d = g\_{fs}(\upsilon\_{\mathcal{S}^s} - V\_{th}) + \mathbb{C}\_{ds}\frac{d\upsilon\_{ds}}{dt} - \mathbb{C}\_{\mathcal{g}d}\frac{d(\upsilon\_{\mathcal{S}^s} - \upsilon\_{ds})}{dt} \tag{16}$$

$$V\_{\mathcal{S}} = \upsilon\_{\mathcal{S}^5} + R\_{\mathcal{S}} i\_{\mathcal{S}} + L\_{\mathcal{S}} \frac{di\_{\mathcal{S}}}{dt} + L\_{\mathcal{s}} (\frac{di\_d}{dt} + \frac{di\_{\mathcal{S}}}{dt}) \tag{17}$$

$$\dot{a}\_{\mathcal{S}} = \mathbb{C}\_{\mathcal{S}^{\mathfrak{s}}} \frac{dv\_{\mathcal{S}^{\mathfrak{s}}}}{dt} + \mathbb{C}\_{\mathfrak{g}d} (\frac{dv\_{\mathcal{S}^{\mathfrak{s}}}}{dt} - \frac{dv\_{\mathcal{S}^{\mathfrak{s}}}}{dt}) \tag{18}$$

$$V\_{DC} = v\_{ds} + v\_{ds\\_H} + (L\_d + L\_s)\frac{di\_d}{dt} + L\_s \frac{di\_s}{dt} \tag{19}$$

$$i\_d = I\_L + C\_{\text{oss\\_}H} \frac{d\upsilon\_{ds\\_ H}}{dt} \tag{20}$$

This period ends when *vds* decreases to zero. A current overshoot is caused by the rapid *dv/dt* action on the output capacitance:

$$
\Delta \dot{t}\_d = \mathbb{C}\_{oss\\_H} \frac{dv\_{ds\\_H}}{dt} - \mathbb{C}\_{oss} \frac{dv\_{ds}}{dt} \tag{21}
$$

In addition, the Miller plateau time on *vgs* for GaN HEMT is less than Si MOSFET because of small transfer capacitance *Cgd*. This characteristic can help us to understand why GaN HEMT can turn-ON at a high speed. The turn-ON switching loss calculation method is the same as that of Equation (15).

#### *3.4. Stage IV (t3–t4): Ringing Period*

As shown in Figure 3, at time *t*3, *Q* will work in the linear region and behave equivalent to a loop resistor, as illustrated in Figure 4d. Usually, the ringing is serious due to small damping resistance with large parasitic inductances. The key equations can be expressed as:

$$V\_{\mathcal{S}} = v\_{\mathcal{S}^s} + R\_{\mathcal{S}}i\_{\mathcal{S}} + L\_{\mathcal{S}}\frac{di\_{\mathcal{S}}}{dt} + L\_{\mathcal{s}}(\frac{di\_d}{dt} + \frac{di\_{\mathcal{S}}}{dt}) \tag{22}$$

$$i\_{\mathcal{S}} = \mathbb{C}\_{\mathcal{S}^{\rm s}} \frac{dv\_{\mathcal{S}^{\rm s}}}{dt} + \mathbb{C}\_{\mathcal{S}^{\rm d}} (\frac{dv\_{\mathcal{S}^{\rm s}}}{dt} - \frac{dv\_{\mathcal{S}^{\rm s}}}{dt}) \tag{23}$$

$$V\_{DC} = v\_{ds} + v\_{ds\\_H} + (L\_d + L\_s)\frac{di\_d}{dt} + L\_s \frac{di\_s}{dt} \tag{24}$$

$$i\_d = \frac{v\_{ds}}{R\_{on}} + \mathcal{C}\_{ds}\frac{dv\_{ds}}{dt} - \mathcal{C}\_{\text{gd}}\frac{d(v\_{\text{gs}} - v\_{ds})}{dt} \tag{25}$$

$$i\_d = I\_L + \mathcal{C}\_{\text{oss\\_}H} \frac{dv\_{ds\\_H}}{dt} \tag{26}$$

where *Ron* represents the on-state resistance of *Q*. During this stage, the turn-ON switching loss can be expressed as:

$$P\_{on} = f\_s \cdot \int\_{t4}^{t3} (i\_d - I\_L)^2 \cdot R\_{on} dt \tag{27}$$

This period ends when the ringing is fully damped.

#### **4. Transient Characteristic Analysis of Turn-Off Process Based on the Proposed Model**

There are still four stages and the typical waveforms during turn-OFF process. At each stage, the equations can be obtained from each equivalent circuit. Similarly, the nonlinear junction capacitance and nonlinear transconductance modeling results proposed in Section 2 are applied to the turn-OFF process and five state variables can be calculated according to the equations obtained from the equivalent circuit of each stage. Furthermore, the switching loss during the turn-OFF process can be obtained. The calculation of each stage will be discussed as follows.

#### *4.1. Stage I (t5–t6): Turn-Off Delay Period*

As shown in Figure 5, at time *t*5, the gate drive voltage *Vg* declines to 0 V. In this stage, *Cgs* and *Cgd* are discharged, so *vgs* begins to reduce. However, *Q* is still in the turn-ON state, *IL* keeps flowing through the channel of *Q*. The equivalent circuit of this stage is shown in Figure 6a. The following equations can be obtained:

$$0 = (L\_{\mathfrak{g}} + L\_{\mathfrak{s}})\frac{d\dot{l}\_{\mathfrak{g}}}{dt} + R\_{\mathfrak{g}}\dot{l}\_{\mathfrak{g}} + v\_{\mathfrak{g}^{\mathfrak{s}}} \tag{28}$$

$$d\_{\mathfrak{J}} = (\mathbb{C}\_{\mathfrak{J}^{\mathfrak{z}}} + \mathbb{C}\_{\mathfrak{J}^d}) \frac{dv\_{\mathfrak{J}^{\mathfrak{z}}}}{dt} \tag{29}$$

This period ends at time *t*<sup>6</sup> when *vgs* reaches the Miller plateau voltage *vmiller*.

$$v\_{miller} = V\_{th} + \frac{I\_L}{\mathcal{S}\_{fs}}\tag{30}$$

*vds* and *id* are constants, so there is no turn-OFF switching loss in this stage.

**Figure 5.** Typical waveforms during turn-OFF process.

**Figure 6.** Equivalent circuits for different stages during turn-OFF process: (**a**) Stage I; (**b**) Stage II; (**c**) Stage III; (**d**) Stage IV.

#### *4.2. Stage II (t6–t7): Voltage Rise Period*

As shown in Figure 5, at time *t*6, the channel of *Q* starts to turn-OFF, so the channel current *ich* decreases and begins to charge the capacitances *Cds* and *Cgd*, then *vds* is rapidly increased. At the same time, *Coss\_H* begins to discharge, resulting in the decline of *vds\_H*. However, *Q*\_*<sup>H</sup>* is still not reverse conducting because *id* is limited by the power loop parasitic inductances. Therefore, the decrease rate of *id* is smaller than that of *ich*. The equivalent circuit is shown in Figure 6b, and the equations of this stage are as follows:

$$0 = v\_{\mathcal{S}^s} + R\_{\mathcal{S}} i\_{\mathcal{S}} + L\_{\mathcal{S}} \frac{di\_{\mathcal{S}}}{dt} + L\_s (\frac{di\_d}{dt} + \frac{di\_{\mathcal{S}}}{dt}) \tag{31}$$

$$d\_{\mathcal{S}} = \mathbb{C}\_{\mathcal{S}^s} \frac{dv\_{\mathcal{S}^s}}{dt} + \mathbb{C}\_{\mathcal{S}^d} (\frac{dv\_{\mathcal{S}^s}}{dt} - \frac{dv\_{ds}}{dt}) \tag{32}$$

$$\dot{\mathbf{u}}\_d = \mathcal{g}\_{fs}(\upsilon\_{\mathcal{S}^s} - V\_{th}) + \mathcal{C}\_{ds}\frac{dv\_{ds}}{dt} - \mathcal{C}\_{gd}\frac{d(\upsilon\_{\mathcal{S}^s} - \upsilon\_{ds})}{dt} \tag{33}$$

$$V\_{\rm DC} = v\_{ds} + v\_{ds\\_H} + (L\_d + L\_s)\frac{di\_d}{dt} \tag{34}$$

$$i\_d = I\_L + \mathcal{C}\_{\text{oss\\_}H} \frac{dv\_{ds\\_ H}}{dt} \tag{35}$$

This period ends when *vds\_H* reaches −*Vr*. During this stage, the energy loss can be calculated as:

$$E\_{off} = \int\_{t7}^{t6} v\_{ds} \cdot i\_{ch} dt \tag{36}$$

The power loss in this stage can be determined by:

$$\begin{aligned} P\_{off} &= f\_{\text{s}} \cdot E\_{off} \\ &= f\_{\text{s}} \cdot \int\_{t\mathcal{T}}^{t\mathbf{6}} v\_{ds} \cdot i\_{ch} dt \end{aligned} \tag{37}$$

Usually, the energy stored in *Coss* is quite large due to the high peak *vds*. The power loss is different from turn-ON process because *id* contains the charge current from *Coss*. Thus, the relationship can be modified as:

$$P\_{off} = f\_s \cdot \int\_{t7}^{t6} \upsilon\_{ds} \cdot i\_d dt - P\_{\text{Coss}} \tag{38}$$

where *PCoss* is the energy stored in *Coss* when the applied voltage is *v*Peak and can be calculated as:

$$P\_{\rm CSS} = f\_{\rm s} \cdot \int\_0^{v\_{\rm peak}} v\_{\rm ds} \cdot \mathbb{C}\_{\rm loss}(v\_{\rm ds}) dv\_{\rm ds} \tag{39}$$

*C*oss(*vds*) can be determined by Equation (2) and is plotted in Figure 2a.

#### *4.3. Stage III (t7–t8): Current Decline Period*

As shown in Figure 5, at time *t*7, *Q*\_*<sup>H</sup>* starts to reverse conduct. During this stage, *id* and *vgs* decreases, *vds* continues to increase, and *Cds* and *Cgd* are charged. The equivalent circuit is shown in Figure 6c, and the circuit equations can be expressed as:

$$0 = v\_{\mathcal{S}^s} + R\_{\mathcal{S}} i\_{\mathcal{S}} + L\_{\mathcal{S}} \frac{di\_{\mathcal{S}}}{dt} + L\_s (\frac{di\_d}{dt} + \frac{di\_{\mathcal{S}}}{dt}) \tag{40}$$

$$\dot{a}\_{\mathcal{S}} = \mathbb{C}\_{\mathcal{S}^{\mathfrak{s}}} \frac{dv\_{\mathcal{S}^{\mathfrak{s}}}}{dt} + \mathbb{C}\_{\mathfrak{g}d} (\frac{dv\_{\mathcal{S}^{\mathfrak{s}}}}{dt} - \frac{dv\_{\mathrm{ds}}}{dt}) \tag{41}$$

$$i\_d = g\_{fs}(v\_{\mathcal{S}^s} - V\_{th}) + \mathcal{C}\_{ds}\frac{dv\_{ds}}{dt} - \mathcal{C}\_{\mathcal{gd}}\frac{d(v\_{\mathcal{S}^s} - v\_{ds})}{dt} \tag{42}$$

$$V\_{DC} = v\_{ds} + v\_{ds\\_H} + (L\_d + L\_s)\frac{di\_d}{dt} + L\_s \frac{di\_s}{dt} \tag{43}$$

$$
\upsilon\_{ds\\_H} = R\_{on}(I\_L - i\_d) - V\_r \tag{44}
$$

This stage ends when *id* drops to zero. The turn-OFF power loss calculation method is the same as Stage II.

#### *4.4. Stage IV (t8–t9): Ringing Period*

As shown in Figure 5, at time *t*8, when *vgs* drops below *Vth*, the channel of *Q* is totally shut down. Then *vgs* continues to decrease until it reaches zero. During this stage, *vds* and *id* both have a ringing due to the oscillation between the parasitic inductances and *Coss*. The equivalent circuit is shown in Figure 6d, and the circuit equations can be expressed as:

$$0 = v\_{\mathcal{S}^\mathfrak{s}} + R\_{\mathcal{S}} i\_{\mathcal{S}} + L\_{\mathcal{S}} \frac{di\_{\mathcal{S}}}{dt} + L\_{\mathfrak{s}} (\frac{di\_d}{dt} + \frac{di\_{\mathcal{S}}}{dt}) \tag{45}$$

$$i\_{\mathcal{S}} = \mathbb{C}\_{\mathcal{S}^s} \frac{dv\_{\mathcal{S}^s}}{dt} + \mathbb{C}\_{\mathcal{S}^d} (\frac{dv\_{\mathcal{S}^s}}{dt} - \frac{dv\_{\mathcal{S}^s}}{dt}) \tag{46}$$

$$i\_d = \mathcal{C}\_{ds}\frac{dv\_{ds}}{dt} - \mathcal{C}\_{\mathbb{S}^d}\frac{d(v\_{\mathbb{S}^\mathbf{s}} - v\_{ds})}{dt} \tag{47}$$

$$V\_{DC} + V\_r = v\_{ds} + (L\_d + L\_s)\frac{di\_d}{dt} \tag{48}$$

During this stage, the turn-OFF power loss calculation method can be expressed as:

$$P\_{off} = f\_s \cdot \int\_{t9}^{t8} i\_d \cdot v\_{ds} dt \tag{49}$$

This period ends when the ringing is fully damped.

#### **5. Experimental Verifications**

In order to verify the accuracy of the proposed switching transient analytical model, a DPT experiment prototype was built, as shown in Figure 7. The double pulses will be applied to the gate of the bottom GaN HEMT by TMS320F28335. The device under test is the GS61004B 100 V enhanced GaN HEMT and the driver is Si8271. The oscilloscope is MDPO3054 by Tektronix Inc. The switching current is measured with 2000 MHz bandwidth current shunt SSDN-10 by T&M Research Products Inc. The parasitic inductance and package stray inductance can be acquired by Maxwell 3-D. The specifications and the main circuit parameters are shown in Table 2. The comparisons among the switching waveforms provided by the experiment, the proposed model, and the traditional mode in [16] are shown in Figure 8. The calculated results from the models for the variables *vds* and *id* with fitting value from Figure 2 will be used to evaluate the model accuracy. The loss calculation results are shown in Figure 9.

**Figure 7.** Experiment circuit prototype.

**Table 2.** Specifications and main circuit parameters.


It can be concluded that the proposed model matches more accurately with the experimental results than the traditional model according to the slope and spike of *id* and *vds* from Figure 8. The oscillation frequency and amplitude of the waveforms from the experimental results deviate from the traditional model while the proposed model results agree with that accurately. The reason is that the traditional model treats the nonlinear parameters in the device as fixed values.

Subsequently, the energy loss of *Eon* and *Eoff* is calculated by the proposed loss calculation method as shown in Figure 9. The results show that the energy loss increases when

the load current changes from 5 A to 10 A. It is obvious that the loss calculation results of the proposed model in this paper are more precise compared with the traditional model. Experiment results verify the accuracy of the proposed loss calculation method with a maximum relative error of less than 10%. Finally, it can be concluded that the proposed switching transient analytical model is quite accurate and the loss analysis results based on the model is believable.

**Figure 8.** Switching waveforms of the experiment, the proposed model, and the traditional model: (**a**) *VDC* = 40 V, *IL* = 7 A; (**b**) *VDC* = 60 V, *IL* = 7 A; (**c**) *VDC* = 40 V, *IL* = 15 A.

**Figure 9.** Switching loss of the experiment, the proposed model, and the traditional model: (**a**) turn-ON energy loss; (**b**) turn-OFF energy loss.

#### **6. Effect of Parameter Variation on the Analytical Model**

The effectiveness of the proposed switching transient analytical model is verified in the previous section. Moreover, it is important to evaluate how the gate resistance *Rg*, the nonlinear junction capacitances *Cgs*, *Cgd*, *Cds*, and the parasitic inductance *Lloop* affect the switching transient and switching loss, thus the further improvement of packaging and application of the device can be inspired.

Figure 10 shows the effect of different driving resistors *Rg* on the switching transition behavior. The waveforms of *vds* and *id* are plotted. It can be seen that the oscillation of *vds* and *id* can be effectively suppressed by increasing the *Rg*. However, the larger *Rg* limits the gate charging current and reduces the charging speed, thus resulting the switching time increase of the device. In addition, Figure 10 also calculates the influence of different *Rg* on switching loss. With the increase of *Rg*, the turn-ON and turn-OFF switching loss is also increased. However, with the increase of *Rg*, the current overshoot for turn-ON transient and the voltage overshoot for turn-OFF transient decreased. Therefore, considering the impact of switching loss and overshoot in practical application, it is necessary to select an appropriate *Rg* value.

In order to simplify the analysis, *Lloop* lumps all of the parasitic inductances and package stray inductances along the power loop. As the package stray inductances are accounted into *Ld* and *Ls*, so *Lloop* is the sum of *Ld* and *Ls*. The effect of different *Lloop* on the switching transition behavior is shown in Figure 11. During the turn-ON process, the change rate of *id* and *vds* become slower with the increase of *Lloop*. Meanwhile, the current overshoot decreases but the voltage overshoot increases. In addition, the ringing period of *id* and *vds* becomes larger. These factors cause the turn-ON switching loss to become larger due to overlap area increases. During the turn-OFF process, the increase of *Lloop* has an obvious influence on *id* overshoot, which also leads to the increase of loss. It can be concluded that the total loss also increases, therefore, the value of *Lloop* should be minimized as much as possible on the PCB design and optimization process.

For the same type of GaN HEMT, the value of the nonlinear junction capacitances should be the same. However, due to different production processes or different production lines, the capacitance values may change. In order to explore the effect of the nonlinear junction capacitance on the switching transient, we make corresponding changes for each nonlinear junction capacitance value within a reasonable range.

The influence of *Cgs* is shown in Figure 12. Set the variation value of *Cgs* as 200 pF, 400 pF, 600 pF. It is observed that the increasing of *Cgs* caused the charge time to become longer, thus resulting in the turn-ON delay time notably increasing. Meanwhile, the current overshoot and the voltage overshoot during the turn-OFF process can be suppressed by increasing *Cgs*. In general, *Cgs* can effectively reduce the waveform oscillation, but will also lead to an increase in switching loss. Therefore, an extra capacitor paralleled with *Cgs* can

be used to reduce the oscillation when the oscillation is too large. However, the value of the parallel capacitor should be selected properly, otherwise the loss will be too large.

**Figure 10.** Influence of different *Rg* on the switching transient: (**a**) turn-ON process; (**b**) turn-OFF process.

**Figure 11.** Influence of different *Lloop* on the switching transient: (**a**) turn-ON process; (**b**) turn-OFF process.

**Figure 12.** Influence of different *Cgs* on the switching transient: (**a**) turn-ON process; (**b**) turn-OFF process.

The effect of *Cgd* is shown in Figure 13. As stated previously, the increase of *Cgd* has a large effect on the switching loss model. It can be concluded that the magnitude of *Cgd* mainly affects the turn-ON process, i.e., the change rate of *id* and *vds* decreases and the conducting time increases. Although the increase of *Cgd* is only 5 pF–15 pF, it has a great impact on the on-off time and switching loss due to the capacitor which affects the length of Miller platform time. Therefore, *Cgd* should be designed as small as possible in device production. Compared with the Si devices, GaN HEMT is able to achieve much faster switching speeds and lower switching losses due to its smaller *Cgd*.

The influence of *Cds* is shown in Figure 14. As we know, *Coss* is a nonlinear junction capacitance of *vds*. It can be concluded that the increase of *Cds* mainly affects the change rate of *id*. Since *Coss* increases with the increase of *Cds*, according to Equation (17), the energy stored in *Coss* will increase, which will result in an increase in the switching loss. In addition, the switching speed is increased and the ringing period becomes larger. For the convenience of overall consideration, the influencing parameter of switching characteristics and their specific impact analysis are listed in Table 3.

**Figure 13.** Influence of different *Cgd* on the switching transient: (**a**) turn-ON process; (**b**) turn-OFF process.

**Figure 14.** Influence of different *Cds* on the switching transient: (**a**) turn-ON process; (**b**) turn-OFF process.


**Table 3.** Analysis of The Influencing Parameter of Switching Characteristics.

#### **7. Conclusions**

In this paper, an accurate switching transient analytical model for GaN HEMT under the influence of nonlinear parameters was proposed. The proposed model covers the process of turn-ON and turn-OFF, which is of great significance in understanding the dynamic characteristics during the switching process. In addition, this model can be applied to evaluate the influence of parameter changes on the switching characteristics of devices, and calculate the switching loss. Finally, the following conclusions can be drawn:


**Author Contributions:** All authors contributed to the writing and revisions; writing—review and editing, L.H.; writing—original draft, D.Y.; review, Y.H.; review, Z.H.; supervision, P.Z. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by the National Natural Science Foundation of China, grant numbers 51777049, 51707051.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** Data available on request due to privacy or ethical restrictions.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


### *Article* **Three-Level Active Power Filter Based on Model Predictive Control**

**Hanying Gao 1,\*, Weihao Zhang 1, Mingjie Ren <sup>2</sup> and Xiangnan Liu <sup>1</sup>**


**Abstract:** The model predictive control (MPC) algorithm is used in the harmonic compensation of active power filter (APF), which has a fast dynamic response and does not require a PWM modulation model. However, this method has some shortcomings, such as the mass computing and difficult selections of weight factors. To solve these problems, this paper proposes a single objective function improved MPC algorithm based on sector judgment, which only takes the reference current and feedback current as the objective function, omits the weight coefficient setting process, and reduces the number of rolling optimization from 27 to 7, thus reducing the computing time and control complexity. The improved model predictive control is applied to APF. Finally, the simulations and experiments show that the improved MPC algorithm is accurate and efficient.

**Keywords:** model predictive control; objective function; sector judgment; active power filter; small vectors

#### **1. Introduction**

With the advancement of power electronics technology and the development of manufacturing industry, more and more nonlinear devices are put into use. The input of these nonlinear loads brings a huge harmonic interference and a reactive power impact on the power grid. If not treated, it brings a huge pollution to the power grid, and causes major economic losses and safety accidents. The active power filter has excellent dynamic response, real-time performance, and controllability. It is an ideal device for compensating harmonics and improving power quality [1–4]. The three-level APF has the advantages of large capacity, more output levels and small filter inductance. It is widely used in medium and low voltage occasions [5–7]. At present, the studies on the three-level APF mainly focus on the optimization of control algorithm.

The studies on the optimization of the three-level control algorithm mainly focus on the harmonic current tracking strategy. The mature tracking strategies include the proportional integral control, hysteresis control, proportional resonance control, and model predictive control [8–11]. The PI control algorithm is not suitable for ac tracking [12]. More precisely, the response speed of hysteresis controller is affected by the loop width, while the loop width of different systems is difficult to adjust, and it is also difficult to balance the selection between switching frequency and tracking effect, which limits the use of this algorithm [13]. In general, in order to take the computational load and compensation performance into consideration, the proportional resonance control algorithm is only used for tracking specific harmonic frequency segments [14]. As a novel current tracking control algorithm, the model prediction has the advantages of fast dynamic response, flexible control and good stability. It has been widely used in the control of power converters [15,16].

The model predictive control mainly samples the device output current at the current time, and substitutes it into the established system mathematical model in order to predict

**Citation:** Gao, H.; Zhang, W.; Ren, M.; Liu, X. Three-Level Active Power Filter Based on Model Predictive Control. *Electronics* **2022**, *11*, 1291. https://doi.org/10.3390/ electronics11091291

Academic Editor: Maciej Ławry ´nczuk

Received: 3 March 2022 Accepted: 8 April 2022 Published: 19 April 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

the future device output current information according to the current or past current information [17]. Compared with other control algorithms, the model predictive control has great advantages in nonlinear systems, and can better deal with problems such as multiinput, multi variable, and multi constraint conditions [18]. However, the model prediction includes a rolling optimization process, which requires lot of processing time, thus reducing the dynamic performance of the model predictive control [19]. The weight factor reflects the importance of the objective function. It plays a crucial role in the control effect of the target. Therefore, when controlling the multi-objective function, the desired control effect can be obtained by adjusting the weight factor [20,21]. Although the model prediction can unify multiple constraints by adjusting the weight factor, it is difficult to adjust the weight coefficient in engineering applications. In [22], the model predictive control algorithm is applied to the three-phase four leg APF in order to predict the reference current and compensation current, and therefore perform harmonic compensation. However, this method has many rolling times, and the weight factor should be adjusted, which increases the complexity of the system. The authors in [23] apply model predictive control to the current tracking control of the three-level APF system. Although the values of the required parameters in the system are analyzed, a specific setting method of the parameters does not exist. The authors in [24] first classify different types of the objective function and weight factors, and then adjust the weight factors. This method has an excellent control effect. However, it is complex and it has a large computational load, which limits its use in practical application. Another approach [25] combines the model predictive control algorithm with a neural network algorithm. Compared with the traditional MPC algorithm, this method does not require an accurate mathematical model, and significantly improves the dynamic response ability of the APF system. However, the implementation process of this method is complex, and therefore it is difficult to be used in several application domains. The method in [26] applies the model predictive control algorithm to the T-type three-level neutral point clamped (NPC) inverter. It uses the predictive control for the grid current and capacitor voltage. Although the maximum power output and DC side capacitor voltage are stable, a specific setting method for the weight factor does not exist. The method in [27] introduces the idea of mixed logic dynamic (MLD) modeling into MPC control. Although the accuracy of the prediction model is improved, the modeling of this method is complex and difficult to implement. The authors in [28] select the optimal voltage vector according to the inverter output power and DC side voltage. They then optimize multiple objective functions by a constraint term, omitting the setting process of weighting factors. However, this method has more rolling times and a large computational load.

In this paper, a single objective function improved model predictive control algorithm based on sector judgment is proposed. It only takes the given current and feedback current as the objective function, determines the optimal voltage vector according to the influence of small vector and the change of DC voltage, omits the setting process of weight coefficient, and, finally, reduces the rolling optimization times to 7 times by judging the sector. The complexity of the algorithm is reduced and the dynamic response ability of APF system is improved. Finally, the improved MPC algorithm is applied to NPC three-level APF, and the correctness and feasibility of the algorithm are proved by system simulation and experiments.

#### **2. NPC Topological Structure Analysis**

#### *2.1. NPC Topological Structure and Working Principle*

Figure 1 shows the NPC three-level topology, which is composed of 6 diodes, 2 capacitors, and 12 switches. The midpoint of the 3 pairs of diodes is connected with point O. By controlling the switch, each phase of the topology can output three voltage states. The working process of the topology is analyzed as follows.

**Figure 1.** NPC three-level topology.

Considering point O as the zero potential reference point, in order to maintain the balance of two capacitors, that is, the voltage of each capacitor is +*V*dc/2, three levels can be output by changing the on and off states of the switch according to the modulation strategy: +*V*dc/2, 0, and −*V*dc/2.

For the convenience of analysis, the topological phase voltage output +*V*dc/2 is defined as P state, output −*V*dc/2 is N state and output 0 is O state. The NPC topology line voltage output has five states: +*V*dc, +*V*dc/2, 0, −*V*dc/2, and −*V*dc. Table 1 can be obtained by summarizing the three working states of NPC three-level topology.

**Table 1.** Relationship between switch status and output voltage.


Where: 1 represents the switch on, and 0 represents the switch off.

*2.2. Mathematical Model of Three-Level NPC APF*

According to the analysis, the output level function is given by:

$$\begin{array}{c} \text{1. (P) } S\_{x1}, S\_{x2} \text{ on } S\_{x3}, S\_{x4} \text{ off} \\ \text{2. (O) } S\_{x2}, S\_{x3} \text{ on } S\_{x1}, S\_{x4} \text{ off} \\ \text{ -1(N) } S\_{x3}, S\_{x4} \text{ on } S\_{x1}, S\_{x2} \text{ off} \end{array} \tag{1}$$

where: *Sx* is the output level function, and *x* has the value a, b, or c.

Block diagram of NPC three-level APF, as shown in Figure 2. Assuming that the grid is symmetrical without distortion and only contains the fundamental component, the three-phase load symmetrically ignores the line parasitic inductance and only considers the AC side output filter inductance. It also ignores the system line and device loss, and only considers the inductance internal resistance. Moreover, the three-phase inductance internal resistances are equal (*R* = *R*<sup>a</sup> = *R*<sup>b</sup> = *R*c), and the DC side capacitances are all equal to C.

**Figure 2.** Schematic diagram of NPC three-level APF.

According to these assumptions and to the Kirchhoff voltage law (KVL), the mathematical model of the APF system is expressed as:

$$\begin{cases} \left(\mu\_{\rm AO} + \mu\_{\rm ON}\right) = R i\_{\rm CA} + L \frac{d i\_{\rm CA}}{dt} + \mu\_{\rm sa} \\ \left(\mu\_{\rm BO} + \mu\_{\rm ON}\right) = R i\_{\rm CB} + L \frac{d i\_{\rm CB}}{dt} + \mu\_{\rm sb} \\ \left(\mu\_{\rm CO} + \mu\_{\rm ON}\right) = R i\_{\rm CC} + L \frac{d i\_{\rm CC}}{dt} + \mu\_{\rm sc} \end{cases} \tag{2}$$

where: *us*a, *us*b, and *us*<sup>c</sup> are the three-phase voltage, *i*CA, *i*CB, and *i*CC are the system compensation currents, *u*AO, *u*BO, and *u*CO are the potential voltages between the output point of each phase and the reference point O of the NPC topology, *u*ON is the voltage between the DC side neutral point and grid neutral point. *U*AO, *u*BO, and *u*CO can be expressed as (3).

$$
\mu\_{\text{xo}} = \frac{1}{2} S\_{\text{x}} \mathcal{U}\_{\text{dc}\prime} \ge = \text{a} \text{, b} \text{ c}\prime \tag{3}
$$

and therefore:

$$\begin{cases} \mathfrak{u}\_{\mathsf{sa}} + \mathfrak{u}\_{\mathsf{sb}} + \mathfrak{u}\_{\mathsf{sc}} = 0\\ \dot{\mathfrak{i}}\_{\mathsf{CA}} + \dot{\mathfrak{i}}\_{\mathsf{CB}} + \dot{\mathfrak{i}}\_{\mathsf{CC}} = 0 \end{cases} \tag{4}$$

By combining Equations (2)–(4), the difference between the point O potential and the point N potential is given by:

$$
\mu\_{\rm ON} = \frac{1}{6} (\mathcal{S}\_{\rm a} + \mathcal{S}\_{\rm b} + \mathcal{S}\_{\rm c}) \mathcal{U}\_{\rm dc} \tag{5}
$$

The three-level NPC APF output voltage and switching function then meet the following relationships:

$$\begin{cases} \boldsymbol{\mu\_{\rm AN}} = \boldsymbol{\mu\_{\rm AO}} + \boldsymbol{\mu\_{\rm ON}} = \frac{1}{6} (2\mathbf{S\_{a}} - \mathbf{S\_{b}} - \mathbf{S\_{c}}) \boldsymbol{\mathcal{U}\_{\rm dc}}\\ \boldsymbol{\mu\_{\rm BN}} = \boldsymbol{\mu\_{\rm BO}} + \boldsymbol{\mu\_{\rm ON}} = \frac{1}{6} (-\mathbf{S\_{a}} + 2\mathbf{S\_{b}} - \mathbf{S\_{c}}) \boldsymbol{\mathcal{U}\_{\rm dc}}\\ \boldsymbol{\mu\_{\rm CN}} = \boldsymbol{\mu\_{\rm CO}} + \boldsymbol{\mu\_{\rm ON}} = \frac{1}{6} (-\mathbf{S\_{a}} - \mathbf{S\_{b}} + 2\mathbf{S\_{c}}) \boldsymbol{\mathcal{U}\_{\rm dc}} \end{cases} \tag{6}$$

#### *2.3. Analysis of Neutral Point Potential of NPC APF*

Two main reasons exist for the capacitor voltage fluctuation: the various losses in APF system, including the loss of switch tube and line, as well as the load fluctuation and the power grid fluctuation. The load fluctuation and grid fluctuation belong to the external disturbance and cannot be controlled. Therefore, in order to suppress the capacitor voltage fluctuation, maintain the stability of the APF system and achieve a better tracking effect on the harmonic current, the relationship between the NPC topology output voltage vector and neutral point potential fluctuation is analyzed as follows.

As shown in Figure 3, there are 27 voltage vectors in NPC topology switching state vector, including 6 medium vectors, 6 large vectors, 12 small vectors, and 3 zero vectors. Among them, the medium vectors include: PNO(V1), PON(V3), OPN(V5), NPO(V7), NOP(V9), and ONP(V11). The large vector includes: PNN(V2), PPN(V4), NPN(V6), NPP(V8), NNP(V10), and PNP(V12). The small vectors includes: ONO(V13), POP(V14), ONN(V15), POO(V16), OON(V17), PPO(V18), NON(V19), OPO(V20), NOO(21), OPP(V22), NNO(V23), OOP(V24). Zero vectors include: NNN(V25), OOO(V26), and PPP(V27).

**Figure 3.** Voltage vector diagram of NPC three-level topology.

In order to analyze the influence of vectors on the neutral point potential, the equivalent circuits corresponding to these five vectors are analyzed, (cf. Figure 4).

It can be seen from Figure 4a, that the large vector (PNN) acts on the entire bus voltage and does not constitute a loop with the point O. The same applies for the other five large vectors. Therefore, when the large vector acts, it only affects the entire bus voltage on the DC side. When the output voltage vector is a medium vector, one phase is connected to point O, and the other phases are, respectively, connected to the bus voltage in order to form a loop with point O, and therefore affect its potential. However, this effect is uncontrollable. That is, the point O potential cannot be controlled by the medium vectors. The small vectors include positive and negative small vectors. It can be seen from Figure 4c,d that no matter which small vector acts, an electrical connection with point O which constitutes a circuit exists, so the small vectors will affect the neutral point potential balance. When the output state of the switch is a zero vector, it can be seen from Figure 4e that although the three bridge arms are connected to the point O, they do not form a current loop and do not affect the voltage balance. The other two zero vectors of the bridge arms are not connected to the point O, and will not affect the voltage balance. The influences of these four voltage vectors are summarized in Table 2.


**Table 2.** Influence of voltage vectors on neutral point potential.

**Figure 4.** Equivalent circuit diagram of different vectors: (**a**) large vector (PNN); (**b**) middle vector (PON); (**c**) small vector (ONN); (**d**) small vector (POO); (**e**) zero vector (NNN).

Assuming the neutral current is *io*, the load currents are *i*a, *i*b, and *i*c, the output direction of the inverter is positive direction, the corresponding relations among *i*o, the redundant small vectors, and load currents can be obtained, (cf. Table 3).


**Table 3.** Corresponding relationship between *i*o and redundant small vectors and output currents.

According to Table 3, the mathematical relationship between *i*<sup>o</sup> and the APF system output compensation current is expressed as:

$$i\_{\rm o} = -(i\_{\rm ca}|S\_{\bf a}| + i\_{\rm cb}|S\_{\bf b}| + i\_{\rm cc}|S\_{\bf c}|) \tag{7}$$

The relationship between *i*o and the DC side capacitance is given by:

$$\frac{\mathbf{d}(V\_{\rm dc1} - V\_{\rm dc2})}{\mathbf{d}t} = \frac{1}{\mathbf{C}} i\_0 \tag{8}$$

where: *V*dc1 and *V*dc2 are the voltage values of capacitors *C*<sup>1</sup> and *C*2, respectively.

By setting the voltage deviation to *V*<sup>O</sup> = *V*dc1 − *V*dc2, according to Equations (7) and (8), the following is obtained:

$$\frac{d\mathbf{V\_{o}}}{dt} = -\frac{1}{\mathbf{C}} \Sigma \dot{\mathbf{n}}\_{\mathbf{x}\mathbf{x}} |\mathbf{S\_{x}}|\tag{9}$$

where: *x* = a, b, c.

In summary, the reason of NPC topology DC side neutral point potential fluctuations is that *i*<sup>o</sup> is not null. Regardless of the magnitude and direction of *i*o, as long as a current flow exists between the neutral point O and the load circuit, the current will affect the point O voltage. Under the action of different vectors, different currents have different effects on the capacitance voltage. However, only the small vectors really affect the capacitance voltage and can be controlled in the system. Therefore, the small vectors can be used to solve the problem of neutral point fluctuation.

#### **3. Model Predictive Control**

#### *3.1. Fundamental Theory*

Figure 5 presents the overall control structure block diagram of the three-level APF system, including the harmonic current detection unit and model predictive control unit. The harmonic current control unit uses the *i*p-*i*<sup>q</sup> harmonic current detection method in order to obtain the three-phase harmonic reference current *i* \* fa, *i* \* fb, and *i* \* fc. The model predictive control samples the compensation current, capacitor voltage, and grid voltage, and predicts the compensation current and reference current in the future. It also selects the optimal switching vector output combined with the current capacitor voltage error.

**Figure 5.** Overall control scheme of three-level APF system.

Due to the limited switching state of the main circuit, MPC predicts the output of each switching state using the prediction model. By calculating the function values of all the switching states, the switch state corresponding to the minimum function is selected and applied to the next cycle. The detailed process is as follows. The output prediction model *f*mpc of the system is first developed according to the switching state *S*sta of the APF and the system control variable *x*. The value function *f*val is then established. At time *tk*, the output *x*(*tk*) is calculated using the system prediction model *f*mpc in order to calculate the predicted output *x* mpc *<sup>i</sup>* (*tk*<sup>+</sup>1) corresponding to n different switching states. Afterwards, the value function of the n switching states can be calculated using the output value *x*ref(*tk*<sup>+</sup>1) and predicted output value *x* mpc *<sup>i</sup>* (*tk*<sup>+</sup>1). Finally, the optimal switching state *S*sta(*tk*) corresponding to the minimum function value is obtained, and the switching state is output. The diagram of the system is illustrated in Figure 6.

**Figure 6.** APF MPC block diagram.

#### *3.2. Traditional MPC*

Model predictive control (MPC) belongs to optimal control in essence. It can predict the future output information of the system according to the current and past sampling information of the system. The switching states of the converter are limited, for example, there are 27 switching states in NPC three-level topology. Therefore, the traditional model is also called finite control set model prediction.

The model predictive control consists of the predictive model, rolling optimization and feedback correction. The overall control block diagram is shown in Figure 7. Establishing a systematic prediction model is the first step of MPC, that is, building a prediction model of future information according to the previous and current information, and then rolling optimization. Through rolling optimization, the size of the value function corresponding to all the cases can be judged, and the switch state output corresponding to the minimum value function can be selected. In the process of rolling optimization, the initial positioning link of the current information to the optimization process includes a feedback correction. Therefore, an additional feedback correction link does not exist in practical applications.

**Figure 7.** Model predictive control block diagram.

In order to reduce the control complexity and improve the real-time performance, the Clarke transform is performed on the APF mathematical model of the traditional MPC in order to obtain the following:

$$\begin{cases} \boldsymbol{\mu}\_{\boldsymbol{a}} = \, \prescript{\boldsymbol{R}}{}{\mathrm{L}}\dot{\boldsymbol{i}}\_{\boldsymbol{a}} + \, \prescript{\mathrm{div}}{}{\mathrm{d}}\dot{\boldsymbol{i}}\_{\boldsymbol{\mathcal{A}}} + \prescript{\boldsymbol{e}}{}{\mathrm{e}}\_{\boldsymbol{a}} \\\ \boldsymbol{\mu}\_{\boldsymbol{\beta}} = \, \prescript{\mathrm{R}}{}{\mathrm{L}}\dot{\boldsymbol{i}}\_{\boldsymbol{\beta}} + \, \prescript{\mathrm{d}}{}{\mathrm{d}}\frac{\mathrm{d}\boldsymbol{i}\_{\boldsymbol{\beta}}}{\mathrm{d}\boldsymbol{\mathcal{I}}} + \prescript{\boldsymbol{e}}{}{\mathrm{e}}\_{\boldsymbol{\beta}} \end{cases} \tag{10}$$

$$\begin{array}{rcl} \text{where:} \begin{bmatrix} \boldsymbol{u}\_{\boldsymbol{a}} \\ \boldsymbol{u}\_{\boldsymbol{\beta}} \end{bmatrix} & = & \mathbf{C}\_{\text{abc}-a\boldsymbol{\beta}} \begin{bmatrix} \boldsymbol{u}\_{\text{AN}} \\ \boldsymbol{u}\_{\text{BN}} \\ \boldsymbol{u}\_{\text{CN}} \end{bmatrix}, \quad \begin{bmatrix} \boldsymbol{i}\_{\boldsymbol{a}} \\ \boldsymbol{i}\_{\boldsymbol{\beta}} \end{bmatrix} & = & \mathbf{C}\_{\text{abc}-a\boldsymbol{\beta}} \begin{bmatrix} \boldsymbol{i}\_{\text{CA}} \\ \boldsymbol{i}\_{\text{CB}} \end{bmatrix} \\\ \mathbf{C}\_{\text{\\_\text{\textdegree}}} \begin{bmatrix} \boldsymbol{e}\_{\text{R}} \\ \boldsymbol{e}\_{\boldsymbol{\beta}} \end{bmatrix} & = & \mathbf{C}\_{\text{abc}-a\boldsymbol{\beta}} \begin{bmatrix} \boldsymbol{u}\_{\text{S3}} \\ \boldsymbol{u}\_{\text{s}\text{B}} \end{bmatrix}, \quad \mathbf{C}\_{\text{abc}-a\boldsymbol{\beta}} = \frac{2}{3} \begin{bmatrix} 1 & -\frac{1}{2} & -\frac{1}{2} \\ 0 & \frac{\sqrt{3}}{2} & -\frac{\sqrt{3}}{2} \end{bmatrix}. \end{array}$$

By applying the Clarke transformation on the pair of Equation (6), the following is obtained:

$$
\begin{bmatrix} u\_{\mathsf{a}} \\ u\_{\mathsf{\beta}} \end{bmatrix} = \mathsf{C}\_{\mathsf{abc} - \mathsf{a}\mathcal{\beta}} \begin{bmatrix} u\_{\mathsf{AN}} \\ u\_{\mathsf{BN}} \\ u\_{\mathsf{CN}} \end{bmatrix} = \frac{1}{\mathsf{6}} \begin{bmatrix} 2\mathsf{S}\_{\mathsf{a}} - \mathsf{S}\_{\mathsf{b}} - \mathsf{S}\_{\mathsf{c}} \\ \sqrt{3}(\mathsf{S}\_{\mathsf{b}} - \mathsf{S}\_{\mathsf{c}}) \end{bmatrix} \mathsf{u}\_{\mathsf{dc}} \tag{11}
$$

Equation (10) is then discretized to obtain:

$$\frac{\mathrm{d}i\_a}{\mathrm{d}t} \approx \frac{i\_a(k+1) - i\_a(k)}{T\_s} \tag{12}$$

$$\frac{\mathrm{d}i\_{\beta}}{\mathrm{d}t} \approx \frac{i\_{\beta}(k+1) - i\_{\beta}(k)}{T\_{s}} \tag{13}$$

where: *iα*(*k*) and *iβ*(*k*) are the actual compensation currents of APF at time k, *iα*(*k* + 1) and *iβ*(*k* + 1) represents the predicted compensation currents at *k*+1 time, and *T*<sup>s</sup> represents the sampling period of the system.

Using Equations (10), (12), and (13), the following can be obtained:

$$\begin{cases} \begin{array}{l} i\_a(k+1) = \frac{T\_\theta}{L} \left[ u\_a(k) - e\_a(k) - R i\_a(k) \right] + i\_a(k) \\\ i\_\beta(k+1) = \frac{T\_\theta}{L} \left[ u\_\beta(k) - e\_\beta(k) - R i\_\beta(k) \right] + i\_\beta(k) \end{array} \tag{14}$$

where *uαβ*(*k*) is the APF output voltage at time *k*, and *eαβ*(*k*) is the APF grid voltage at time k. In order to maintain a good current tracking effect and take into account the balance

of medium electric potential, Equation (9) is discretized:

$$\frac{\mathrm{d}V\_0}{\mathrm{d}t} \approx \frac{V\_0(k+1) - V\_0(k)}{T\_s} \tag{15}$$

where: *V*o(*k* + 1) and *V*o(*k*) are the deviation prediction value and deviation sampling value of capacitor *C*<sup>1</sup> and capacitor *C*<sup>2</sup> at *k* + 1 time and *k* time, respectively.

Equation (16) can be obtained from Equations (9) and (15):

$$V\_o(k+1) = V\_o(k) - \frac{T\_s}{C} \Sigma i\_{\rm cr}(k) |S\_x(k)| / \left(\mathbf{x} = \; a, b, c\right) \tag{16}$$

According to the objective function of the NPC three-level APF system, the square error function is selected as the value function model:

$$g\_1 = \left| i\_a^\*(k+1) - i\_a(k+1) \right|^2 + \left| i\_\beta^\*(k+1) - i\_\beta(k+1) \right|^2 \tag{17}$$

Considering the current tracking effect as the objective function, while taking into account the balance of neutral point potential, the value function can be expressed as:

$$\mathcal{g}\_2 = \left| i\_a^\*(k+1) - i\_a(k+1) \right|^2 + \left| i\_\beta^\*(k+1) - i\_\beta(k+1) \right|^2 + \left| V\_\mathbf{o}(k+1) \right| \tag{18}$$

Considering the weights of *g*<sup>1</sup> and *g*2, the final expression of the value function is given by:

$$g = \lambda\_1 |i\_a^\*(k+1) - i\_a(k+1)|^2 + \lambda\_1 \left| i\_\beta^\*(k+1) - i\_\beta(k+1) \right|^2 + \lambda\_2 |V\_0(k+1)| \tag{19}$$

where: *λ*<sup>1</sup> and *λ*<sup>2</sup> are weight coefficients.

The current prediction value given in Equation (19) can be obtained by Lagrange interpolation:

$$\dot{i}^\*(k+1) = \sum\_{l=0}^n (-1)^{n-1} \frac{(n+1)!}{l!(n+1-l)!} \dot{i}^\*(k+l-n) \tag{20}$$

For the sake of accuracy and computational complexity, *n* = 2 is selected, and then:

$$i\_x^\*(k+1) = \left. \mathfrak{H}\_x^\*(k) - \mathfrak{H}\_x^\*(k-1) + i\_x^\*(k-2) \right. \\ \left. \left. \left( \ge \ = \alpha, \beta \right) \right. \tag{21}$$

*3.3. Improved MPC*

3.3.1. Improved MPC Objective Function

The problem of setting the weight coefficient of the objective function can be solved by outputting the optimal small vector to equalize the DC side voltage, and omitting the DC side capacitor voltage error objective function in the cost function.

The realization of DC sides capacitor voltage stability is the premise of maintaining neutral points potential balances. The diagram of the DC sides capacitor voltage stabilizing control is illustrated in Figure 8. Where *e*a, *e*b, and *e*<sup>c</sup> are the grid voltage, *i*a, *i*b, and *i*<sup>c</sup> are the three-phase grid current. Firstly, the active current and reactive current components *i*p and *i*q in p-q coordinate system are obtained by Clarke transformation and Park transformation. Then, the fundamental component in the p-q coordinate system can be obtained by filtering the high-order harmonic component through the low-pass filter LPF. The difference between the DC side total voltage reference value and the DC side total voltage feedback can be processed by the PI controller to obtain the active power reference current Δ*i*p. The active current component Δ*i*<sup>p</sup> is superimposed with the active fundamental current component in the p-q coordinate system to obtain the final active fundamental current component. The three-phase fundamental current components *i*af, *i*bf, and *i*cf are obtained from the final active fundamental component and reactive fundamental component through the inverse transformation of Clarke and Park. Finally, by subtracting the three-phase fundamental current from the three-phase total current, the three-phase harmonic components *i*ah, *i*bh, and *i*ch can be obtained.

**Figure 8.** Schematic diagram of the overall voltage control.

The improved model predictive control algorithm can control the voltage of two capacitors on the DC side, by outputting a specific small vector. This method can omit the DC side capacitor voltage error value function, so as to solve the problem of setting the weight coefficient of the objective function. The specific form of the improved value function is given by:

$$\mathcal{g} = \left| i\_{a\beta}^\*(k+1) - i\_{a\beta}(k+1) \right| \tag{22}$$

Compared with the traditional model prediction value function, this function only needs to consider an objective function of current tracking error, which reduces the computational load and does not introduce a weight coefficient. Therefore, there is no problem of weight coefficient setting.

3.3.2. Single Objective Function Improved Model Predictive Control Strategy Based on Sector Judgment

Inspired by the three-level SVPWM vector control, the sector judgment is introduced into the model predictive control. Figure 9 presents the three-level NPC voltage vector diagram.

It can be seen that the linear *V<sup>β</sup>* + √3/3 *V<sup>α</sup>* = 0,*V<sup>β</sup>* − √3/3 *V<sup>α</sup>* = 0 and *β* coordinate axes divide the large hexagon into six regions, quadrilateral areas of I, II, III, IV, V, and VI, while each quadrilateral contains 8 vectors. It is first assumed that the projection of the reference voltage vector *V*ref on the *α* and *β* axes is *V<sup>α</sup>* and *Vβ*. The six quadrangles are divided according to three lines and voltage vector *V*ref. Specific regional divisions are shown in Table 4.


**Table 4.** Regional divisions.

The quadrilateral region of the reference voltage vector can be determined by assessing the mathematical relationship of the projection of the reference voltage vector on the *α* and *β* axes. Therefore, the mathematical model of the reference voltage is developed:

$$\begin{cases} \boldsymbol{\mu}\_{a}(k) = \boldsymbol{e}\_{a}(k) + \mathrm{Ri}\_{a}(k) - \frac{\boldsymbol{I}\_{\mathcal{P}}}{\boldsymbol{T}\_{\mathcal{P}}} [\boldsymbol{i}\_{a}(k+1) - \boldsymbol{i}\_{a}(k)] \\\ \boldsymbol{\mu}\_{\beta}(k) = \boldsymbol{e}\_{\beta}(k) + \mathrm{Ri}\_{\beta}(k) - \frac{\boldsymbol{I}\_{\mathcal{P}}}{\boldsymbol{T}\_{\ast}} [\boldsymbol{i}\_{\beta}(k+1) - \boldsymbol{i}\_{\beta}(k)] \end{cases} \tag{23}$$

In order to achieve a better current tracking effect of the system, it is necessary to predict that the output current is equal to the predicted harmonic given current:

$$i\_{a\beta}^{\*}\left(k+1\right) = i\_{a\beta}\left(k+1\right) \tag{24}$$

By simultaneously using Equations (23) and (24), the following can be obtained:

$$\begin{cases} \boldsymbol{\mu}\_{a}(k) = \boldsymbol{\varepsilon}\_{a}(k) + \mathrm{Ri}\_{a}(k) - \mathop{\rm l\!}\_{\Gamma\_{\mathsf{s}}} [i\_{a}^{\ast}(k+1) - i\_{a}(k)]\\ \boldsymbol{\mu}\_{\boldsymbol{\beta}}(k) = \boldsymbol{\varepsilon}\_{\boldsymbol{\beta}}(k) + \mathrm{Ri}\_{\boldsymbol{\beta}}(k) - \mathop{\rm l\!}\_{\Gamma\_{\mathsf{s}}} [i\_{\boldsymbol{\beta}}^{\ast}(k+1) - i\_{\boldsymbol{\beta}}(k)] \end{cases} \tag{25}$$

where: *u<sup>α</sup>* = *V<sup>α</sup>* and *u<sup>β</sup>* = *Vβ*.

After this evaluation, the region of the reference voltage vector can be determined. In addition, 8 vectors exist in each region, and there are 2 small vectors among the 8 vectors. Consequently, a redundant vector can be removed. Therefore, the proposed model predictive control algorithm has only 7 rolling optimized vectors, which greatly reduces the rolling times and system calculation, compared with the traditional prediction model.

#### 3.3.3. Flow and Analysis of Improved Model Predictive Control

The control flowchart is shown in Figure 10. Based on the traditional model predictive control, firstly, each parameter is sampled, the system parameters are initialized, *u<sup>α</sup>* and *u<sup>β</sup>* are calculated, the position of the reference voltage vector is then judged according to the size of *u<sup>α</sup>* and *uβ*, and, finally, its quadrilateral region is determined. Afterwards, the seven voltage vectors in this area are subject to rolling optimization. The compensation current is predicted and the value functions containing only current tracking error, are calculated. After seven rolling optimizations, the switching state corresponding to the value function that minimizes the current tracking error is output. Finally, the output voltage vector is judged. In the case of a small vector, a small vector output that is conducive to the capacitor voltage balance on the DC side is selected. Otherwise, it is directly output. Consequently, the optimal switching state output of single objective function improved model predictive control based on sector judgment is completed.

**Figure 10.** Flow chart of single objective function improved model predictive control based on sector judgment.

#### **4. System Simulation and Result Analysis**

The feasibility and efficiency of the proposed algorithm are verified by developing the simulation model of the NPC three-level APF. The model predictive control is written using the S-function module of MATLAB/Simulink. The two model predictions are simulated and compared. Table 5 presents the system simulation parameters.


**Table 5.** Specific parameters of APF simulation model.

#### *4.1. Simulation and Analysis of Traditional Model Predictive Control*

Figure 11 shows the current waveform of A-phase power grid before compensation. It can be seen that when APF is not working, the current waveform is saddle shaped and the waveform distortion is serious because it contains a large number of high-order harmonics. Figure 12 shows the FFT analysis diagram of A-phase grid current before compensation. It can be seen that THD is 27.08%, which is much higher than the national standard of 5%, which seriously reduces the power quality of the grid.

**Figure 11.** Current waveform of A-phase power grid before compensation.

**Figure 12.** FFT analysis diagram of A-phase current before compensation.

Figures 13 and 14 present the current waveform and THD diagram of A-phase power grid under the traditional model predictive control algorithm after APF system works. Compared with Figure 10, it can be seen that the current waveform after compensation changes from saddle shape to sinusoidal shape, and the sinusoidal degree is high. Its THD is 4.51% and less than 5%, which meets the national standard and realizes harmonic compensation.

**Figure 13.** A-phase current waveform after compensation of traditional model predictive control.

**Figure 14.** A-phase current THD diagram after compensation of traditional model predictive control.

Figure 15 is the reference current tracking effect diagram under traditional model predictive control. Under the traditional model predictive control, the feedback current can better track the reference current, but there are some deviations in the peak and trough. Figure 16 presents the error diagram of reference current and feedback current, the error range fluctuates within ±2.5 A, and the maximum error occurs at the peak and trough positions.

**Figure 15.** Reference current tracking effect diagram of traditional model predictive control.

**Figure 16.** Error diagram of reference current and feedback current of traditional model predictive control.

Figure 17 presents the overall voltage waveform of the capacitor at the DC side, and its voltage amplitude fluctuates around 801 V, which can maintain stable fluctuation. Figure 18 presents the waveform of neutral point potential at DC side, with a fluctuation range of ±1.4 V and stable.

**Figure 17.** Overall voltage waveform of DC side capacitor of traditional model predictive control.

**Figure 18.** DC neutral point potential waveform of traditional model predictive control.

In order to observe the MPC the selection of switching state vector, the switching state flag is set to observe the process of finding the optimal switching vector during rolling optimization. Figure 19 is a value diagram of the switching states flag of the traditional model predictive control algorithm. The value of flag is between 1 and 27, which verifies that the rolling optimization times of the traditional model predictive control algorithm is 27.

**Figure 19.** Switching state flag value diagram of traditional model predictive control.

#### *4.2. Single Objective Function Improved Model Predictive Control Based on Sector Judgment*

On the basis of keeping the previously mentioned simulation parameters unchanged, this section uses the single objective function improved model predictive control algorithm based on sector judgment to simulate the APF system.

Figures 20 and 21 present the current waveform and THD diagram of APF system after adding the improved model prediction algorithm. It can be seen that the sinusoidal degree of the current waveform is high. It can be deduced using the Fourier analysis that the THD is only 1.35%, and the APF system achieves an excellent compensation effect.

**Figure 20.** A-phase power grid current waveform after compensation based on improved model predictive control.

**Figure 21.** A-phase grid current THD diagram after compensation of improved model predictive control.

Figure 22 presents the effect diagram of the harmonic current tracking, while Figure 23 shows the error result diagram of the reference current and feedback current. It can be seen that the APF output current and reference current mainly coincide, and the tracking effect is efficient. The error between the reference current and feedback current is ±0.7 A, which is smaller than that of the traditional MPC algorithm.

**Figure 22.** Effect of harmonic current tracking of improved model predictive control.

**Figure 23.** Error of reference current and feedback current of improved model predictive control.

Figure 24 shows the overall voltage waveform of the DC side capacitor, which can be stable around 800 V with a small fluctuation. Figure 25 illustrates the fluctuation diagram of the neutral point potential, with a fluctuation range of ±0.37 V, performing a good voltage stabilizing effect.

**Figure 24.** Overall voltage waveform of DC side capacitor based on improved model predictive control.

**Figure 25.** Waveform of neutral point potential at DC side of improved model predictive control.

Figure 26 presents the value of the switch state flag, which value ranges between 1 and 7. In order to further observe the sector judgment, flag1 is defined as the sector judgment flag. Figure 27 shows the result values of flag1. It can be seen that the value of flag1 ranges between 1 and 6, which verifies the efficiency of the method of judging the sector position by the voltage vectors.

**Figure 26.** Result diagram of switch state flag value of improved model predictive control.

**Figure 27.** Value result of sector judgment flag1 of improved model predictive control.

In this section, the two MPC algorithms are simulated. Compared with the traditional MPC, the improved model prediction algorithm can judge the output voltage vector and select the switching state conducive to the neutral point potential balance of the capacitor on the DC side for output, so as to realize the voltage sharing control of the capacitor. Using the improved model prediction algorithm, the overall capacitor voltage is closer to 800 V, the neutral point potential fluctuation is smaller, and the harmonic current tracking effect is better. According to the diagram of the switch state flag, the rolling times are reduced from 27 to 7, which reduces the rolling optimization times. In conclusion, the control effect of the improved model prediction algorithm is significantly enhanced.

#### *4.3. System Performance Simulation and Analysis*

In practical applications, the operating conditions are often complex. A better compensation effect can be achieved only when the APF system has a good adaptability. Therefore, it is crucial to analyze the dynamic response capacity of the APF system. In order to study the dynamic performance of APF system based on improved model predictive control based on sector judgment, it is simulated and analyzed under different working conditions.

#### 4.3.1. System Simulation Analysis under Sudden Load Change

Based on the simulation model presented in Section 4.2, a same nonlinear load is input at 0.2 s and cut off at 0.4 s. Figure 28 shows the three-phase power grid current waveforms when the load suddenly changes. At 0.2 s, the current amplitude suddenly increases due to the load increase, which results in large spikes. However, the APF system can quickly compensate it and then eliminate the spikes. Figure 29 shows the THD diagram of the A-phase current before load mutation, while Figure 30 presents the THD diagram of the A-phase after load mutation. It can be seen that the THD content is 3.41%, which is higher than 1.94%. However, it is still less than 5%, which indicates that the system has a good dynamic compensation performance.

**Figure 28.** Power grid current waveform before and after load sudden change of traditional MPC.

**Figure 29.** THD diagram of A-phase current before load sudden change of traditional MPC.

**Figure 30.** THD diagram of A-phase current after load sudden change of traditional MPC.

Figures 31 and 32 are the overall voltage waveform and neutral point potential waveform of DC side capacitor under the traditional model predictive control algorithm respectively. The DC side voltage fluctuates greatly when the load is input, and then it stabilizes at about 800.5 V, about 0.5 V deviates from the reference voltage. The neutral point potential fluctuates greatly when the load is removed, and the maximum fluctuation is about 4.9 V.

Figures 33 and 34 present the overall voltage waveform and midpoint potential waveform of the DC side capacitor under the improved model predictive control algorithm. It can be seen that their fluctuation is smaller than that in Figures 31 and 32.

**Figure 31.** Overall voltage waveform of DC side capacitor before load and after sudden change of traditional MPC.

 **Figure 32.** Waveform of neutral point potential before and after load sudden change of traditional MPC.

**Figure 33.** Overall voltage waveform of DC side capacitor before load and after sudden change of improved MPC.

**Figure 34.** Waveform of neutral point potential before and after load mutation of improved MPC.

Compared with the simulation waveform of traditional MPC algorithm, the algorithm based on improved model predictive control has better control effect on DC side capacitor voltage and neutral point potential voltage, and it can better maintain the stability of the DC side voltage and reduce the voltage fluctuation range.

#### 4.3.2. System Simulation Analysis under Unbalanced Load

This section studies the compensation effect of the APF under load imbalance, where a 10 Ω unbalanced resistance is connected to the A-phase circuit in order to simulate the system. Figure 35 shows the waveform diagram of the power grid current under unbalanced load. It can be seen that the current distortion is significant, the amplitude of the B-phase and C-phase current is high, the amplitude of the A-phase is low, and the power grid current is unbalanced. Figure 36 presents the THD diagram of the A-phase current before compensation, while Figures 37 and 38 show the waveform diagram of the three-phase grid current and A-phase current THD diagram after compensation.

As can be seen from Figures 36 and 38 that under the action of the improved MPC control algorithm based on sector judgment, the grid current THD after compensation is reduced from 27.54% to 2.19%, performing an excellent compensation effect. It can be seen from Figure 37 that the APF system can make up the unbalanced three-phase current into a balanced state and it has a strong ability to suppress the three-phase imbalance.

**Figure 35.** Power grid current waveforms under unbalanced load.

**Figure 36.** THD diagram of A-phase grid current under unbalanced load.

**Figure 37.** Power grid current waveforms after compensation under unbalanced load of improved MPC.

**Figure 38.** THD diagram of A-phase grid current after compensation under unbalanced load of improved MPC.

#### **5. Experiment and Result Analysis**

Based on the simulation, the following experiments are performed in order to verify the feasibility and correctness of the proposed control algorithm in the APF system. The experimental parameters are shown in Table 6.

According to these system parameters, an experimental platform is built. It mainly includes a topology unit, main control unit, sampling unit, and driving unit. The topology unit is composed of a NPC three-level topology and a filter inductance. The main control unit is composed of DSP and FPGA to complete the data operation and drive the signal output, respectively. The sampling unit is mainly responsible for sampling grid voltage and current, DC side capacitor voltage and APF system output current. The driving unit is responsible for amplifying the PWM wave output by the controller in order to drive the power switching devices. The experimental system platform is shown in Figure 39.


**Table 6.** Key parameters of the system.

**Figure 39.** Experimental platform.

#### *5.1. DC Capacitor Voltage Waveform*

The waveform of the capacitor voltage is presented in Figure 40. The APF device detects the change of capacitor voltage by the Hall voltage sensor. The experimental waveform shows that the DC side voltage is stable at 800 V during operation. The results show that the capacitor voltage can remain stable with a small fluctuation, which meets the requirements of voltage stability. Therefore, the correctness of the proposed voltage stabilizing algorithm is proved.

**Figure 40.** Waveforms of capacitance voltage at DC side.

#### *5.2. Harmonic Current Extraction and Tracking Waveform*

Figure 41 channel A shows the harmonic current waveform in the A-phase load current, while Figure 41 channel B presents the compensation current waveform by the APF system. The diagram shows that the harmonic current wave is coherent with the simulation waveform. The variation trend of the harmonic current and output current is mainly the same, which indicates that the system can better perform the extraction and tracking of harmonic current. This demonstrates that the proposed improved MPC algorithm has a high current tracking performance.

**Figure 41.** Waveforms of A-phase harmonic tracking current.

#### *5.3. Algorithm Time-Consuming Comparison*

In the experiment, mark points are set at the beginning and end of the algorithm program, and the running time of the algorithm program segment is obtained by the timer, so as to compare the time consumption between the traditional MPC and the proposed improved MPC.

The program running time measured by this method when using the traditional MPC algorithm for compensation is 59.2 μs, while the running time of the MPC algorithm program section is 39 μs, as shown in Figure 42. When the improved MPC strategy is used for harmonic compensation, the running time of the whole program is 38.4 μs. Figure 43 shows that the running time of the improved MPC algorithm is 18 μs.

**Figure 42.** The time consumption of traditional MPC algorithm.

**Figure 43.** The time consumption of improved MPC algorithm.

The traditional algorithm requires 27 comparison operations when selecting the optimal vector each time, while the improved MPC algorithm only requires 7 comparison

operations. Therefore, the running time of the MPC algorithm in Figure 43 is shorter than that in Figure 42.

#### *5.4. Experiment of Power Grid Balance and Load Balance*

The three-phase gird voltages *U*A, *U*B, and *U*<sup>C</sup> are 220 V, 220 V, and 220 V, respectively. The resistance is 40 Ω after three-phase rectification.

Figure 44a is the waveform of three-phase grid current before compensation, and Figure 44b is the FFT analysis diagram of A-phase current before compensation. Because the load contains nonlinear devices, the grid current is seriously distorted and the sinusoidal degree is low. Taking A-phase as an example, the THD of A-phase grid current is 24.86%, which reduces the power quality of the grid.

**Figure 44.** Experimental waveform before compensation: (**a**) three-phase grid current and (**b**) A-phase current THD.

Figure 45a shows the current waveform after system compensation using the proposed improved algorithm. The FFT analysis of the A-phase current is shown in Figure 45b. It can be seen that the compensated current recovers the sinusoidal shape, and the sinusoidal degree is satisfactory. In the latter, the THD of the A-phase current is 2.86%, which improves the power quality. The experimental waveform is similar to the simulation results. The compensation effect is mainly coherent with the simulation results, and the compensation effect is clear. When the power grid and load are balanced, the system dynamic compensation performance is high, which verifies the efficiency of the single objective function improved model predictive control algorithm.

**Figure 45.** Experimental waveform after compensation: (**a**) three-phase grid current and (**b)** A-phase current THD.

#### *5.5. Experiment of Power Grid Balance and Load Imbalance*

Figure 46a shows the waveform of the three-phase power grid when the system is connected to unbalanced load. It can be seen that the three-phase power grid is asymmetric, and the current amplitudes are not equal. It can be observed from Figure 46b that the current THD of A-phase power grid is 28.32%.

**Figure 46.** Experimental waveform before compensation when load is unbalanced: (**a**) three-phase grid current abd (**b**) A-phase current THD.

Figure 47a presents the current waveform after compensation. It can be seen that the distorted and asymmetric power grid current waveform is compensated into a three-phase symmetrical sinusoidal shape. The A-phase current is analyzed by the FFT (cf. Figure 47b), the THD is 3.80%, which is close to the simulation results. Using the improved MPC strategy, the system compensates the harmonic current, and, also, restrains the three-phase imbalance.

**Figure 47.** Experimental waveform after compensation when load is unbalanced: (**a**) three-phase grid current and (**b**) A-phase current THD.

#### *5.6. Load Sudden Change Experiment*

Figure 48a shows the waveform of the three-phase power grid after compensation in case of sudden load change. It can be observed that the current suddenly increases due to the load increase. A FFT analysis is conducted on the A-phase current of power grid after sudden change, (cf. Figure 48b), It can be seen that the THD is 4.48%, which still meets the national standard. This indicates that although the load current significantly changes in case of sudden load change, the APF system based on the single objective function improved MPC algorithm can still quickly respond, and perform the rapid tracking of sudden harmonic current with a high dynamic performance.

**Figure 48.** Experimental waveform of sudden load change after compensation: (**a**) three-phase grid current and (**b**) A-phase current THD.

#### **6. Conclusions**

This paper tackles the NPC three-level active power filter and deeply studies the principle and shortcomings of the traditional MPC algorithm, in order to develop a novel model predictive control current tracking algorithm. Dealing with the problems of many rolling times, high computational load, and difficulty to adjust the weight factor of the multi-objective function, an improved MPC algorithm of single objective function based on sector judgment, is proposed. The sector judgment concept is introduced into the model predictive control. By judging the mathematical relationship between the three lines and the voltage reference vector, the location of the area where the reference vector is located is determined, and the number of rolling optimizations is reduced from 27 to 8. After removing the redundant small vector, the rolling number can be reduced to 7, which reduces the complexity of the algorithm and the computational load. The current tracking error, neutral point potential fluctuation on DC side, compensation effect and rolling times of the two MPC algorithms, are compared by simulations and engineering implementations. The obtained results demonstrate that the proposed single objective function improved MPC algorithm based on sector judgment, has a better current tracking effect and voltage stabilizing effect. In addition, it has a good dynamic response ability and compensation performance, which proved that the proposed algorithm is feasible and efficient.

**Author Contributions:** Conceptualization, H.G.; formal analysis, H.G. and W.Z.; data curation, M.R. and W.Z.; writing—review and editing, X.L. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research work was funded by the National Natural Science Foundation of China grant number 51177031.

**Data Availability Statement:** The data presented in this study are available on request from the corresponding author.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


**Thanh Nhat Trung Tran 1, Hung-Chia Wang <sup>2</sup> and Jian-Min Wang 2,\***


**Abstract:** A novel dual-mode control scheme is proposed in this paper that permits the active-clamp flyback (ACF) converter to operate in both the quasi-resonant (QR) mode under light load and the active-clamp mode under medium or heavy load. The mode transition is performed based on the external dual-mode control circuit. In addition, the proposed converter incorporates a new QR mode valley switching (VS) control circuit that reduces switching loss in the main switch by achieving VS. Under medium to full load, the proposed converter becomes an ACF converter designed to achieve zero-voltage switching (ZVS), which reduces switching losses in both power switches. The proposed dual-mode control ACF converter has the following advantages: (1) compared with conventional ACF converters, the proposed ACF converters minimize switching losses by combining VS and ZVS; (2) under light load conditions, the frequency-limiting QR control mechanism is used to avoid disadvantageous switching losses caused by high switching frequencies. The 65 W ACF converter prototype with a DC 155 V input and a DC 19 V/3.42 A output under 65 kHz switching frequency was implemented. The experimental results demonstrate the feasibility of the proposed control scheme. The efficiency of the proposed converter reached 79% at a load of 3.5 W, which is 11% higher than the conventional ACF converter.

**Keywords:** active-clamp flyback; dual-mode control; light load; valley switching; zero-voltage switching

#### **1. Introduction**

The flyback converter architecture, as shown in Figure 1, extended from the buckboost converter, is one of the most popular converters in the power electronics industry. This type of converter is characterized by its simple structure, few components, and easy compliance with electrical isolation safety specifications. Due to the fact of these advantages, flyback architecture is widely used in converters with output power levels less than 100 W such as light-emitting diode (LED) indoor lighting and portable chargers. However, in the transformer of the flyback converter, energy is stored in an air gap in the core. To store enough energy for the transformer, the size of the air gap must be increased with a corresponding increase in the leakage inductance of the transformer, resulting in a voltage spike on the switching device when it is turned off. The snubber circuit is a popular solution for suppressing this voltage spike; however, it lowers converter efficiency.

In recent years, numerous researchers have proposed efficiency improvements for flyback converters. Generally, these improvements can be classified into two major categories: constant-frequency control and variable-frequency control. In constant-frequency control, the active-clamp technique has been widely used in flyback converters. The ACF converter structure and key waveforms are presented in Figure 2a. In this technique, a circuit loop, comprising an auxiliary switch (*Q*2) and a capacitor (*Cclamp*), is added at the two terminals

**Citation:** Tran, T.N.T.; Wang, H.-C.; Wang, J.-M. A Dual-Mode Control Scheme to Improve Light Load Efficiency for Active-Clamp Flyback Converter. *Electronics* **2022**, *11*, 1308. https://doi.org/10.3390/ electronics11091308

Academic Editor: Pablo García Triviño

Received: 8 March 2022 Accepted: 19 April 2022 Published: 20 April 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

on the primary side of the transformer. This loop is used to perform ZVS at the main switch, improving converter efficiency and avoiding the high voltage spikes generated when the main switch is turned off [1–7]. However, conduction loss caused by resonant circulating current and additional switching in the *Q*<sup>2</sup> switch induces high power loss under light load [8]. Numerous studies [8,9] have described methods for addressing this drawback. Reference [8] employs a secondary-side post-regulator for minimizing power consumption. Consequently, this method requires an external post-regulator, resulting in a circuit with increased cost and size. In [9], a dual-mode control method was adopted in which the operation mode of the ACF converter was divided into two modes based on the load: the conventional flyback mode and the active-clamp mode. Briefly, the proposed converter works as a conventional flyback converter with the auxiliary switch turning off to decrease the converter's switching and conduction losses under no-load conditions but turns into an ACF converter under normal-load/full-load conditions. However, this method is only effective for reducing the power consumption of the ACF converter under no-load conditions. In categories of variable-frequency control, quasi-resonant (QR) control is the mainstream technique [10–14]. The quasi-resonant flyback (QRF) converter structure and key waveforms are presented in Figure 2b. In the QR control technique, the resonance signal generated by the parasitic capacitance of the switch, *COSS*, and the magnetizing inductance of the transformer, *Lm*, are used to turn on the main switch when its drain-source voltage reaches a minimum valley point. Hence, switching loss is significantly reduced. However, this technique cannot achieve ZVS.

**Figure 1.** Flyback converter topology.

**Figure 2.** (**a**) Active-clamp flyback converter structure and key waveforms; (**b**) quasi-resonant flyback converter structure and key waveforms.

Thus, as summarized above, constant-frequency and variable-frequency control have advantages and disadvantages. By combining the advantages of ACF and QRF, a novel dual-mode control scheme combining ZVS and VS is proposed in this paper.

Based on the structure of the ACF converter, in this dual-mode control scheme, an external logic circuit, called a dual-mode switching circuit, is integrated for switching the converter to the QR mode under light load adopting VS for the main switch to substantially reduce switching surges. However, the converter operating in the QR mode may cause high switching frequency and increased switching losses. Thus, the frequency-limiting QR control technology is combined to avoid the disadvantage of the increased switching frequency. This technique limits the maximum switching frequency during light load operation to allow the converter to achieve the frequency-limiting function. Under heavy load, the dual-mode switching circuit switches the converter back to the conventional ACF converter (active-clamp mode) to enable both power switches to achieve ZVS to obtain high efficiency.

#### **2. Proposed Novel Dual-Mode ACF Converter Structure**

#### *2.1. The Proposed Circuit Structure and Principle of Operation*

Figure 3 presents the block diagram of the proposed dual-mode control scheme and the related control sequence diagram under different load conditions. The control circuit consists of the current-mode controller UC3843 produced by STMicroelectronics (Geneva, Switzerland), a QR control circuit, and a dual-mode switching circuit. Among these components, the current mode controller UC3843 plays a critical role in stabilizing the output voltage. The QR control circuit and dual-mode switching circuit are the core circuits of the active-clamp and QR modes, respectively, as shown in Figure 3a. The working principle of the control circuit is explained in terms of two states: light load and heavy load.

#### 2.1.1. Light Load

Under light load, the controller proposed in this paper controls the ACF converter operating in the QR mode, and the related control sequence diagram is illustrated in Figure 3b. In this case, the output signal (*VC*) of the hysteresis comparator is low; thus, the high-side drive circuit is disabled, turning off the auxiliary switch (*Q*2) of the converter. At this moment, the feedback voltage signal (*VFB*) at the converter output is then compared with the internal reference voltage of the feedback circuit to generate the error signal (*VComp*), which is sent to the current mode controller. The controller processes error signals and generates the control driving signal (*VPWM*). Notably, the QR mode controller used in this paper has a mechanism to limit the maximum switching frequency, which is different from the conventional first VS method (as indicated by the red dashed circle in Figure 3b); this mechanism avoids disadvantageous switching losses due to the high switching frequencies.

#### 2.1.2. Heavy Load

When the converter transitions from light to heavy load, the operation mode of the converter is switched from the QR mode to the active-clamp mode by the controller. Figure 3c depicts the related control sequence diagram. At this moment, the magnitude of the error signal (*VComp*) generated by the feedback circuit increases, simultaneously increasing the duty cycle of the drive signal (*VPWM*) generated by the current mode controller. Due to the hysteresis comparator output signal (*VC*) in this state being high, the high-side drive circuit is enabled. Consequently, the auxiliary switch of the ACF *Q*<sup>2</sup> is activated in accordance with the drive signal of *VQ*2. In other words, the driving signals *VQ*<sup>1</sup> and *VQ*<sup>2</sup> are complementary operation signals.

**Figure 3.** *Cont*.

**Figure 3.** (**a**) Dual-mode control strategy proposed in this paper; (**b**) sequence diagram of the key waveform under light load; (**c**) sequence diagram of the key waveform under heavy load.

#### *2.2. The Control Circuit of the Proposed Novel Dual-Mode ACF Converter*

This section describes the control circuit of the dual-mode ACF proposed in this paper.

#### 2.2.1. Dual-Mode Switching Circuit

The gray block in Figure 4 is a dual-mode switching circuit. When the converter is operating under light load, the hysteresis comparator output (*VC*) is low, since the output voltage of the current sensor (*Vsense*2) is less than the reference voltage (*VREF*). Therefore, the drive signal (*VQ*2) of the high-side auxiliary switch remains low. The input signal (*Vpulse*) of the second AND gate (AND2) determines the state of the valley trigger signal (*Vreset*) because the voltage signal (*VC*) becomes high after the NOT gate. The valley trigger signal (*Vreset*) resets the main controller, which can precisely control the low-side main switch (*Q*1) to achieve VS and to enable the converter to operate in the QR mode.

**Figure 4.** Dual-mode switching circuit structure.

When the converter is operating under heavy load, the hysteresis comparator output (*VC*) is high; thus, the output state of the first AND gate (AND1) is determined by the voltage signal, *VGS*2. At this moment, the high-side auxiliary switch begins to operate. For the second AND gate (AND2), the output voltage signal (*Vreset*) is low since the signal (*VC*) is high, and the main controller is not affected by the reset signal. In this stage, the QR control circuit is disabled, enabling the transition of the converter to the active-clamp mode.

#### 2.2.2. Proposed QR Control Circuit

Before introducing the QR control technique proposed in this paper, the disadvantages of the conventional QRF converter are discussed. Conventional QR control methods rely on the phenomenon of resonance generated by the parasitic capacitance of the main switch and the magnetizing inductance of the transformer to turn on the main switch at the first resonance valley, which can reduce switching loss. However, as the output load increases, the switching frequency also increases, which leads to canceling out the advantages of VS as illustrated in Figure 5.

**Figure 5.** Quasi-resonant flyback converter structure and key waveforms correspond to load conditions.

One popular solution to overcome these inadequacies is the use of a frequency-limiting mechanism. In this paper, a control technology similar to that in [13] is adopted in which only pulse signals are used to adjust the maximum frequency of the oscillator. The operating principle of the proposed converter is divided into two parts: the operating principle of the ACF converter operating in the QR mode and the operating principle of the QR control circuit that limits the maximum switching frequency.

• The operating principle of the ACF converter operating in the QR mode:

The operating principle of the ACF converter in the QR mode is described as follows. This operation mode is divided into three states as shown in Figure 6, and the complete

key waveforms are presented in Figure 7. The following assumptions are used to simplify the analysis:


**Figure 6.** (**a**–**c**) Three operating states of the ACF converter in the QR mode.

**Figure 7.** Key waveforms of the ACF converter operating in the QR Mode.

State 1 (*t0* ≤ *t<t1*):

When *t* = *t0*, the main switch (*Q*1) is turned on, and the auxiliary switch (*Q*2) is turned off. The input source begins to supply energy to the transformer, and the magnetizing inductor current (*ILm*) increases linearly. Since the primary and secondary sides of the transformer have opposite polarity, the output rectifier diode (*Do*) is reverse-biased. The output energy is supplied by the output filter capacitor (*Co*). The detailed current path is presented in Figure 6a. For the auxiliary winding on the secondary side of the transformer, the voltage *VZCD* remains low because the voltage VS is less than zero.

State 2 (*t*<sup>1</sup> ≤ *t<t*2):

When *t* = *t*1, the main switch (*Q*1) and the auxiliary switch (*Q*2) are turned off. At this time, the magnetizing inductance (*Lm*) then begins to charge the parasitic capacitor (*Coss*1) of the main switch (*Q*1). As a result, the drain-source voltage (*VDS*) of *Q*<sup>1</sup> on the primary side of the transformer increases rapidly. When *VDS*<sup>1</sup> ≥ *Vin* + *nVo*, the diode, *Do*, conducts. The energy stored in the transformer is then transferred to the output capacitor and the output load. The detailed current path is shown in Figure 6b. For the auxiliary winding on the secondary side of the transformer, the voltage *VZCD* changes from low to high due to the transient transition of *Vs*.

State 3 (*t*<sup>2</sup> ≤ *t<t*3):

When *t* = *t*2, the energy stored in the transformer has been completely transferred to the secondary side, and the current *IDo* decreases to zero. The converter is thus operating in the discontinuous conduction mode (DCM). The magnetizing inductor (*Lm*) and the parasitic capacitor (*Coss*1) begin to resonate. The detailed current path is shown in Figure 6c. In the QR mode, when the voltage drops to the valley, the main switch (*Q*1) turns on to reduce switching loss. At this time, the output energy is provided to the load by the output

filter capacitor (*Co*). The auxiliary winding on the secondary side of the transformer is in the resonant state due to the voltage *Vs*, resulting in a square wave signal at the output of the comparator with the same resonant frequency.

• The operating principle of the QR control circuit with the maximum switching frequencylimiting function:

This section explains the operating principle of the QR control circuit with the maximum switching frequency-limiting function. Figure 8 depicts the QR control block with the maximum switching frequency-limiting function and related key waveforms. Notably, the circuit only operates when the ACF converter is in the resonant state. When voltage *VDS*<sup>1</sup> resonates through point 0 at *t*0, the voltage *VZCD* transiently changes from high to low. After being processed by the RC delay circuit, the voltage *VZCD*<sup>1</sup> will be delayed for a period Δ*t*. The falling edge of this square wave may coincide with the valley of the switching voltage *VDS*. Therefore, the pulse generator and the gain controller can generate an adjustable pulse signal *Vpulse*<sup>1</sup> at time *t*1. To control the maximum switching frequency limit, the original oscillator signal (*VOSC*) must be obtained from the current mode controller. After processing by the squarer, this signal becomes a triangular signal at the same frequency, *VOSC1*. This method is used to accentuate the peak voltage of *VOSC*. The multiplier is the main focus of this control strategy. The input voltages of the multiplier are *VOSC*<sup>1</sup> and *Vpulse*1; thus, the peak value of the output voltage *Vpulse*<sup>2</sup> gradually increases. Finally, the voltage *Vsum* is generated by adding *VOSC*<sup>1</sup> to *Vpulse*2. As the number of resonances increases, the peak value of *Vsum* also increases. When the voltage value of *Vsum* is higher than the reference voltage *VTH* of comparator CMP1 at *t*2, the output signal *Vreset* of CMP1 triggers the current mode controller to reset the oscillator. This technique enables the converter to achieve maximum switching frequency limiting. Thus, controlling the magnitude of the reference voltage *VTH* determines the valley point of the converter.

**Figure 8.** *Cont*.

**Figure 8.** (**a**) QR control block with the maximum switching frequency-limiting function and (**b**) key waveform sequence diagram.

#### **3. Design of the Proposed Novel Dual-Mode ACF Converter**

The converter structure and operating principles have been described in detail in the previous section. This section describes the design of the proposed dual-mode ACF converter. A 65 W power supply is used in the following example calculations and the description of the component design of the converter. The specifications of the prototype converter are listed in Table 1.

In the following, the design procedure of the converter is briefly presented. Step 1:

Given that the maximum output power *Po,max* = 65 W and the efficiency *η* = 0.9, the magnetizing inductance (*Lm*) of the transformer can be determined [15]:

$$L\_{\rm m} = \frac{\eta \times \left(V\_{\rm in,min} \times D\_{\rm max}\right)^2}{2 \times f\_{\rm sw} \times P\_{o,max}} = 409 \text{ }\mu\text{H} \tag{1}$$


**Table 1.** Specifications of the proposed ACF converter.

Step 2:

After the magnetizing inductance (*Lm*) of the transformer is known, the peak current of the transformer primary side winding can be calculated:

$$I\_{pp} = \frac{P\_{o,max}}{\eta \times V\_{in} \times D\_{max}} + \frac{V\_{in,min} \times D\_{max}}{2 \times L\_m \times f\_{sw}} \cong 2.357 \text{ A} \tag{2}$$

Step 3:

The maximum output power (*Po,max*) of the converter is 65 W, and the switching frequency is 65 kHz. In this paper, the PQ26/20 iron core produced by TDK (Tokyo, Japan) was used to calculate the primary winding turns of the transformer. Based on the actual design considerations, the magnetizing inductance (*Lm*) is 400 μH. From the core datasheet, the effective cross-sectional area of the core (*Ae*) is 1.19 cm, and the maximum magnetic flux density (*Bmax*) is 2000 G. The primary winding turns of the transformer (*Np*) can be calculated as follows:

$$N\_p = \frac{L\_m \times I\_{pp}}{A\_\varepsilon \times B\_{max}} \times 10^8 \cong 39\tag{3}$$

Step 4:

The secondary winding turns (*Ns*) can also be calculated:

$$N\_5 = \frac{V\_o \times (1 - D\_{\text{max}}) \times N\_p}{V\_{in} \times D\_{\text{max}}} \cong 7\tag{4}$$

Step 5:

The output diode must be selected considering the maximum output current and the withstand voltage. The withstand voltage and withstand current of the diode are calculated as follows:

$$V\_{D,max} = \frac{V\_{in,max}}{\frac{N\_p}{N\_s}} + V\_o \cong 46.82\text{ V} \tag{5}$$

$$I\_{\rm sec,peak} = I\_{L,peak} \times n \cong 13.22 \text{ A} \tag{6}$$

$$I\_{\rm sec,rms} = I\_{\rm sec,peak} \sqrt{\frac{1 - D\_{\rm max}}{3}} \cong 5.912 \text{ A} \tag{7}$$

In accordance with the results of Equations (5)–(7), the ultrafast rectifier diode BYV32E-150 produced by NXP Semiconductors (Eindhoven, Netherlands) was selected as the output rectifier diode with a peak reverse voltage of 150 V and a peak forward current of 20 A.

Step 6:

To achieve ZVS for the ACF converter power switch, enough energy must be stored in the resonant inductance (*Lr*) to completely discharge the parasitic capacitance (*Cr*) of the power switch; the calculations of this energy are as follows:

$$E\_{Lr} \geq E\_{\rm Cr} \tag{8}$$

$$\left(\left(I\_{pp}\right)^2 \times L\_r \ge \mathbb{C}\_r \times \left(V\_{\text{in}} + n \times V\_{\text{o}}\right)^2\right.\tag{9}$$

where *ELr* and *ECr* are resonant inductance energy and parasitic capacitance energy, respectively. Step 7:

After the resonant inductance has been determined, the appropriate value of the clamping capacitor (*Cclamp*) can be calculated as follows:

$$C\_{clamp} = \frac{\left(1 - D\_{\max}\right)^2}{\pi^2 \times L\_r \times f\_{sw}} \tag{10}$$

#### **4. Experimental Results**

In this experiment, the control IC UC3843 was used as the main controller. The proposed dual-mode ACF converter had the following specifications: the input voltage was 155 VDC, the output voltage was 19 VDC, and the maximum output power was 65 W. The experimental data included the measured critical switching waveforms, control signal waveforms, dual-mode switching waveforms, ZVS waveforms, and other key parameters. Finally, the comparison of efficiency between the conventional ACF converter and the proposed dual-mode ACF converter is presented in this section. The slope shape of the oscillator waveform is critical for the control technique proposed in this paper, because more precise slope changes result in more accurate VS. Generally, the traditional oscillator is an RC circuit; thus, the slightly curved slope causes the failure of frequency-limited VS. To overcome this challenge, a squarer was used to convert the oscillator waveform into a triangular waveform with a linear slope, improving the accuracy of VS. The relevant waveform is presented in Figure 9.

**Figure 9.** Oscillator waveform with (Ch4) and without (Ch3) the frequency-limiting control mechanism.

Figure 10a shows that when the voltage *VDS*<sup>1</sup> voltage starts to resonate generating a valley, a voltage pulse signal is generated. Through the multiplier, a linearly rising voltage pulse signal *Vpulse*<sup>2</sup> is then generated. Next, the oscillating voltage signal *VOSC*<sup>1</sup> and the voltage signal *Vpulse*<sup>2</sup> are added by the adder to generate the voltage signal *Vsum*. Finally, the voltage signal *Vsum* is compared with the reference voltage *VTH* to generate a reset voltage signal *Vreset*, which restarts the control IC UC3843 to complete the frequency-limiting VS as shown in Figure 10b. In other words, the voltage level of the reference voltage *VTH* determines the VS point, and higher *VTH* values cause a slower system switching frequency. Conversely, lower *VTH* causes a faster system switching frequency.

**Figure 10.** (**a**) Power switch voltage waveform and its generated signal waveforms; (**b**) key control signal waveforms of the proposed ACF converter in QR mode.

Figure 11 presents the key voltage waveforms of the converter operating at different output powers. If the converter operates was at an output power of 6.5 W, the switching frequency of the converter was approximately 70 kHz as presented in Figure 11a. For an output power of 19.5 W, the switching frequency of the converter decreased to approximately 68 kHz as presented in Figure 11b. Although the output power of the converter varied, the switching frequency of the circuit can be limited within a fixed range by the frequency-limiting QR control function of the QR control circuit proposed in this paper. If the output power increased above 19.5 W, the converter changed the operation mode from the QR to the active-clamp mode as presented in Figure 12. Figure 13 shows the ZVS waveforms of the power switches of the proposed converter. The figure shows that before the main switch (*Q1*) was turned on, the drain-source voltage of the main switch *VDS1* decreased to zero. The same principle was applied to the auxiliary switch (*Q*2); thus, both power switches achieved ZVS.

**Figure 11.** Key voltage waveforms of the proposed ACF converter operating at (**a**) 6.5 W and (**b**)·19.5 W. The converter is in the QR mode.

Figure 14 presents the key waveforms for switching between the two modes of the converter according to the change in output power when the input voltage *Vin* = 155 VDC. If the output power was 6.5 W, the driving signal *VGS*<sup>2</sup> of the auxiliary switch (*Q*2) was off, and the driving signal *VGS*<sup>1</sup> of the main switch (*Q1*) adjusted the pulse width modulation in accordance with the load. At this time, the converter operated in the QR mode. If the

output power increased from 6.5 to 65 W, the drive signal *VGS*<sup>2</sup> of the auxiliary switch (*Q2*) entered a working state, and the main switch (*Q*1) and the auxiliary switch (*Q*2) operated in a complementary manner to enable the converter to operate in the active-clamp mode as presented in Figure 14a. By contrast, if the output power decreased from 65 to 6.5 W, the driving signal *VGS*<sup>2</sup> of the auxiliary switch (*Q*2) changed from the working state to the off state, and the operation mode of the converter changed from the active-clamp mode to the QR mode as shown in Figure 14b. These experimental data demonstrated that the converter proposed in this paper can switch between the two modes.

**Figure 12.** Waveforms of the main switch and auxiliary switch of the proposed ACF converter under medium- to full-load conditions (above 19.5 W). The converter is in the active-clamp mode.

**Figure 13.** ZVS waveforms of the power switches of the proposed ACF converter in the activeclamp mode.

**Figure 14.** Key waveforms of dual-mode switching: (**a**) QR mode to the active-clamp mode; (**b**) activeclamp mode to the QR mode.

Table 2 presents the efficiency measurement data for the dual-mode ACF converter. In the table, input current, output current, output voltage, and efficiency are presented under different load conditions with a voltage of 155 VDC as the input power supply. Figure 15 provides a comparison of the efficiency curves of the conventional ACF converter and the dual-mode ACF converter at different output power levels. The curve comparison diagram reveals that for an output power of 3.5 W, the efficiency difference between the two converters is at a maximum of 11%. If the output load increases, conduction losses gradually increase; thus, the efficiency difference between the two converters decreases. Table 2 and Figure 15 show that the control technique proposed in this paper has good performance under light load conditions. In addition, Table 3 presents the load regulation measurement data. Based on the measurement results, it can be seen that the minimum load regulation value is 1.09% at the output power of 65 W (i.e., full load).

**Table 2.** Efficiency of the proposed dual-mode ACF converter.


**Table 3.** Load regulation measurement data of the proposed dual-mode ACF converter.




**Figure 15.** Efficiency curves of the conventional ACF converter and dual-mode ACF converters at different output powers.

#### **5. Conclusions**

This paper presented a new dual-mode switching control strategy for the ACF converter working in DCM, which can switch to the QR mode at light loads to improve overall efficiency. This paper proposed a new dual-mode switching control strategy for an ACF converter operating in DCM to enable operation in the QR mode under light load to optimize the overall operation. The control techniques and operating principles were described in detail. The operating principles and the results of an analysis of the control techniques were carefully discussed. A prototype of the 65 W dual-mode ACF converter was developed, and experiments provided satisfactory results. Experimental results revealed that the auxiliary switch of the resonant tank closed when the dual-mode ACF converter was under light load, which enabled the main switch to perform VS and achieve QR mode control. On the contrary, the converter operated in the active-clamp mode under medium and heavy load conditions, thereby achieving ZVS for both power switches to maintain the high efficiency of conventional ACF. In other words, the proposed dual-mode ACF converter uses QR mode VS characteristics to improve the poor efficiency of conventional ACF under light load. However, the switching frequency of the QR mode is critical to determining the light load efficiency. In general, it is recommended to design the QR mode switching frequency as close to the active-clamp mode switching frequency as possible, because excessively high switching frequencies increase switching losses at light loads. This proposed dual-mode control ACF topology is suitable for applications with relatively low power consumption (under 200 W).

**Author Contributions:** Conceptualization, J.-M.W. and T.N.T.T.; methodology, H.-C.W. and J.-M.W.; validation, T.N.T.T., H.-C.W. and J.-M.W.; resources, J.-M.W.; writing—original draft preparation, J.-M.W. and T.N.T.T.; writing—review and editing, J.-M.W. and T.N.T.T. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by the Ministry of Science and Technology, R.O.C. (grant number: MOST 110-2622-E-150-002).

**Data Availability Statement:** Not applicable.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


### *Article* **Motor Dynamic Loading and Comprehensive Test System Based on FPGA and MCU**

**Chunxiang Zhu 1, Linxin Bao 1, Bowen Zheng 2, Jiacheng Qian 1, Yongdong Cai <sup>1</sup> and Binrui Wang 3,\***


**Abstract:** In view of the problem that the traditional motor test system cannot directly test the transient parameters of the motor and the dynamic arbitrary load loading requirements during motor loading, as well as the high cost of implementation, this research uses STM32+FPGA as the core to form the main control of the motor test system unit, combining the superior control performance of the ARM processor and the high-speed data processing advantages of FPGA. FPGA and STM32 are controlled by the FSMC bus communication and data ping-pong algorithm. Using this method, a small-size control core board in the motor test system is manufactured. It can be embedded in the existing traditional dynamometer system to improve the dynamometer transient parameter test and the dynamic motor loading performance. The experimental results show that the system can basically meet the requirements of the motor transient test and dynamic loading, and can achieve the fastest data refresh rate of 1 ms when measuring the motor's speed and torque, as well as arbitrary waveform loading within a 100 M sampling frequency, with a loading error of 0.8%. It satisfies the motor transient test and dynamic loading requirements.

**Keywords:** motor transient test; dynamic loading; STM32+FPGA; FSMC; ping-pong algorithm

#### **1. Introduction**

In recent years, the application scope of motors has been expanding, and the universality of motor operating conditions determines the complexity of the motor experiment. Traditional testing devices and methods are time-consuming, use a wide range of instruments, and have a low precision, resulting in low intelligence and low efficiency, which greatly affect the accuracy and quality of testing. Most motor tests use a dynamometer as a loading instrument, connected to the motor being tested, and then simultaneously interpret different motors as required. The dynamometer is controlled by the central control computer, and then different test items are analyzed by the power analyzer. A dynamometer is one of the important devices for performance and equipment testing in motor manufacturing and product R&D. It can be used to simulate and control the load of the tested motor so as to measure the torque, speed, current, voltage, power, efficiency, and other parameters of the motor, as well as for other special dynamic test items, such as safety test, dynamic balance test, NVH test (vibration/noise/life), etc. [1–6]. With the development of modern technology, in addition to conventional items such as motor speed, torque, voltage, and current, the requirements for the motor transient performance test are also increased [7–10]. In the traditional dynamometer system, the loads can only be loaded one by one, but the motor performance parameters are measured for a certain load point, which cannot meet the transient performance test of the motor. The loading accuracy and testing accuracy cannot meet the modern requirements. Therefore, enterprises have put forward

**Citation:** Zhu, C.; Bao, L.; Zheng, B.; Qian, J.; Cai, Y.; Wang, B. Motor Dynamic Loading and Comprehensive Test System Based on FPGA and MCU. *Electronics* **2022**, *11*, 1317. https://doi.org/10.3390/ electronics11091317

Academic Editor: Ching-Ming Lai

Received: 22 March 2022 Accepted: 17 April 2022 Published: 21 April 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

the demand for high-performance loading and testing equipment. The equipment needs to meet the high bandwidth and high-precision loading and measurement of a variety of different waveforms, including step signal, square wave, trapezoidal wave, and sine wave. The measurement error should not be higher than 0.5%, and the loading error should not be higher than 0.2% [11–13]. According to the above analysis, the key technical points of the transient performance test of the motor and driver mainly include the following two aspects: First, the loading function of any load curve, that is, it can provide step, sine wave, square wave, sawtooth wave, and even arbitrary waveform loading of torque or speed [14–17]. The second is parameter transient waveform measurement, including the parameter transient waveform measurement of torque, speed, voltage, current, efficiency, and speed torque curve. According to this technical point, in order to meet the high-speed loading and high-speed processing at the same time, this paper innovatively designs a dual core dynamometer loading and testing integrated control system with FPGA and MCU communicating through FSMC. Regarding the industrial application requirements of the system, the corresponding software and hardware functions are designed to meet the requirements of various waveform loadings and measurements of different motor platforms, as well as the requirements of high-speed communication and responses with industrial computers. Therefore, this paper implements a motor dynamic loading and transient parameter testing device. In the process of motor testing, by loading any load curve and testing the transient performance of the motor, it can meet the use requirements of dynamometer equipment embedded in motor testing enterprises [18–20].

#### **2. Composition Principle of the Motor Test System**

High-speed measurements and dynamic loadings of the motor transient parameters are realized, as shown in the structural block diagram shown in Figure 1. The dynamometer is coaxially connected to the tested motor. Various loads are loaded on the tested motor through the dynamometer control system so as to simulate the torque, speed, current, voltage, power, efficiency, and other parameters of the motor in actual operation, as well as other special dynamic test items, such as the safety test, dynamic balance test, and NVH (vibration and noise life) test. When loading, the upper computer sends instructions to control the free loading engine to output the control signal, which is input to the dynamometer drive controller. After the power of the controller is amplified, the control signal is loaded on the load motor so as to drive the load motor in order to load the tested motor. At the same time, the torque−speed transducer feeds back the speed and torque of the measured motor to the free loading engine. The free loading engine adjusts the output of the load in real time according to the feedback value to realize constant speed loading or constant torque loading. The torque calculation formula is as follows:

$$T\_P = N(f - f\_0) / (f\_P - f\_0) \tag{1}$$

$$T\_r = N(f\mathbf{o} - f)/(f\mathbf{o} - f\_r) \tag{2}$$

where *Tp* is the forward torque, *Tr* is the reverse torque, *N* is the torque full scale, *f* <sup>0</sup> is the torque zero output frequency value (KHz), *fp* is the forward full-scale output frequency value (KHz), *fr* is the reverse full scale output frequency value (KHz), and *f* is the measured torque output frequency value (KHz). The speed calculation formula is as follows:

$$S = 60 \times f / Z \tag{3}$$

where *S* is the rotational speed (rpm), *f* is the measured rotational speed output frequency (Hz), and *Z* is the number of teeth (lines) of the speed-measuring code disk of the sensor.

**Figure 1.** System structure block diagram.

#### **3. System Hardware Design**

#### *3.1. Overall Structure*

The circuit structure of the motor test system based on STM32 and FPGA is shown in Figure 2. The system is composed of a user-defined signal output and a speed and torque acquisition circuit. Firstly, STM32 receives the control signals, such as the loading waveform type and waveform parameters, sent by the PC ethernet port, which generates the corresponding analog output or digital output, and obtains the output control signal through FMSC communication, FPGA analysis, magnetic coupling isolation circuit, and then the conversion of the corresponding functional modules. This signal is input to the tested motor or load motor driver to drive the corresponding motor. Secondly, when the real-time data waveform needs to be uploaded, STM32 receives the acquisition data command sent by the PC ethernet. After the speed torque feedback signal is sampled by the magnetic coupling isolation, level conversion circuit, and ADC, it is stored in the on-chip dual port RAM of FPGA, and then STM32 reads the data in the way of a ping-pong operation through the FMSC interface and sends it to the upper computer through the ethernet. The composition and functions of each part of the circuit are introduced below. The components are described below.

**Figure 2.** Hardware block diagram.

#### *3.2. Circuit Design of STM32 Module*

The minimum system circuit structure of the STM32 module is shown in Figure 3. The STM32 system selects STM32H743ZI2, with ARM-Cortex M7 as the core as the main control chip. The STM32H743ZI2 chip is a 32-bit microprocessor. It not only has rich peripheral resources, but also has a fast data processing speed and low power consumption. It is very suitable for occasions with high data speed and high system response requirements. According to the functional requirements of the project, circuits including the ethernet communication circuit, digital output circuit (DO), low-speed ADC circuit, display key circuit, SDRAM data cache, and so on, are designed. The ethernet communication circuit is

mainly responsible for the data transmission between the upper computer and the lower computer. The digital output circuit mainly realizes the digital output control relay to pull in or open. The low speed ADC is mainly used to collect the working environment, such as the external temperature/humidity. The display key circuit realizes the human−computer interaction function. The SDRAM memory circuit mainly realizes the high-speed data cache.

**Figure 3.** STM32 module minimum system circuit block diagram.

#### *3.3. FPGA Module Circuit Design*

The main control chip used in FPGA is the fourth generation EP4CE40F23C8N, which has rich logic resources and about 40,000 gates. There are about 532 user IO ports, so it is very suitable for multi-channel data acquisition and synchronous processing. The FPGA main control core circuit mainly includes a 10M magnetic coupling isolation circuit, pulse output circuit (CO), speed/torque input circuit (CI), high-speed DAC analog output circuit, two-stage operational amplifier circuit, high-speed ADC analog acquisition circuit, low-pass filter circuit, and DDR3 data buffer circuit. It mainly completes the data pingpong operation, analog quantity acquisition and output, speed and torque measurements, receiving control commands, outputting pulse signals, receiving encoder signals, and other functions of motor testing.

The structural diagram is shown in Figure 4.

**Figure 4.** FPGA core circuit block diagram.

#### *3.4. FSMC Communication Design between STM32 and FPGA*

FSMC, a flexible static storage controller, can be connected with synchronous or asynchronous memory and a 16-bit PC memory card. The FMSC interface of STM32H7 supports memory such as SRAM, NAND FLASH, NOR FLASH, and PSRAM. The communication between STM32H7 and FPGA adopts a parallel FSMC bus. The collected data are saved by constructing a dual port RAM built in FPGA, and STM32H7 accesses it through the FMSC bus. According to the requirements of the collected data volume, the FMSC bus

adopts a 24-bit address line and 16-bit data line, and contains six control signals at the same time. The STM32 chip selects FPGA to read and write data. The structural block diagram is shown in Figure 5.

**Figure 5.** FMSC communication structure block diagram.

#### **4. System Software Architecture**

#### *4.1. Overall Software Structure*

The software design of the motor test system can be divided into the upper computer and lower computer. As shown in Figure 6, the upper computer completes the functions of the man−machine interface, speed and torque loading, speed and torque transient data acquisition, control and display, ethernet connection between upper and lower computers, etc. The lower computer parses and executes the instructions sent by the upper computer, collects data, stores data, and uploads data in real time. The following section introduces the software design of each part seperately.

**Figure 6.** Software overall structure.

#### *4.2. STM32 Software Design*

The software architecture of the lower computer mainly includes the STM32H7 end and FPGA end. The main tasks of the STM32H7 terminal include analysis of the host computer instructions, real-time data transmission, TCP/IP connection, and low-speed ADC data acquisition. There are many tasks and complex functions, so it is necessary to reasonably plan the scheduling relationship between tasks. In order to improve the real-time performance of the software and reduce the coupling between tasks, the software is transplanted with the real-time embedded operating system—Ferrets. The operating system provides task management, time management, semaphore, message queue, memory management, and other functions, and the kernel supports both the priority scheduling algorithm and polling scheduling algorithm. The system is open source, tailorable, and free, which can effectively save the cost of instrument development and is suitable for industrial application. The software flow chart of the master operating system with the embedded real-time operating system FreeRTOS as the core is shown in Figure 7. After the system is initialized, the FreeRTOS operating system is initialized, and then the FPGA AO control thread is started at the same time so as to control the output of the analog quantity. The FPGA AI control thread is used to control the acquisition of the analog quantity. The

FPGA CI control thread is used to collect speed and torque. The FPGA PID control thread is used to control the speed and torque of the measured motor and load motor. The TCP server thread is used for data and instruction transmission, and has the function of TCP disconnection and reconnection.

**Figure 7.** STM32H7 software flow chart.

#### *4.3. FPGA Software Design*

FPGA mainly completes external analog input acquisition, motor encoder signal input acquisition, data storage, receiving control instructions from ARM, controlling the analog output, controlling the position output, and controlling the digital output. The software architecture of FPGA is shown in Figure 8.

**Figure 8.** FPGA software flow chart.

#### *4.4. Ping-Pong Algorithm for Data*

Ping-pong operation is a common data flow control processing technique that can realize seamless transmission of data flow. The specific algorithm is shown in Algorithom 1 below. During the first buffering cycle, the input data are cached to Data Buffer Module 1. In the second buffering cycle, the input data are cached to Data Buffer Module 2, and the data in Data Buffer Module 1 are output to the data stream operation processing unit through the selection of "Output Data Stream Selection Unit". In the third buffering cycle, the data are cached into Data Buffer Module 1 by the input data stream selection unit, and Data Buffer Module 2 is selected by the output data stream selection unit to the data stream processing entity. In this design, the ADC data are driven by the ADC and enter the sampling module. After oversampling 200 times, the ADC data are sent to the data ping-pong module at a sampling rate of 1 KHz, so as to achieve a 1 ms data update rate. The ADC data acquisition process is shown in Figure 9.

**Figure 9.** ADC data acquisition process.

**Algorithom 1** ping-pong operation Input: DATA\_Ti(i = 1,2,3, . . . *n*)

if(buffer\_1 ! = Full ) buffer\_1 = DATA\_Ti else if (buffer\_1 = Full) buffer\_2 = DATA\_Ti End if

#### **5. Experimental Verification and Result Analysis**

The system test mainly focuses on the measurement of the motor load and motor transient parameters. The test system is built with an SFT series electric dynamometer as the core, the model of the speed−torque sensor is the WSP speed−torque power sensor, and the output signals of the torque−speed are pulses with an amplitude of 5 V. The output range of the torque frequency signal is 5 KHz to 15 KHz, and the center frequency is 10 KHz. The output range of the speed frequency signal is 0 to 6 KHz, and the calculation formula for the speed and torque is given by Equations (1)–(3). The connection mode between the control system and the upper computer is 100 M ethernet. Figures 10 and 11 show the hardware platform of the project and PC control interface, respectively.

**Figure 10.** Motor test platform.

**Figure 11.** PC control interface.

#### *5.1. Motor Load Test*

The loading quantity includes the analog quantity output, pulse output, and digital quantity output. The analog quantity output also includes regular sine wave output, square wave output, triangular wave, and DC quantity output. The frequency range of the output of the three AC signals is 1 Hz to 10 MHz. The relative error of the frequency output is shown in Figure 12. It can be seen from the figure that the relative error of the frequency output is within 2%, and there is almost no error in the low frequency band.

**Figure 12.** Relative error of the load output frequency.

The output range of the analog DC bias output voltage is −5 V to +5 V. The relative error of the DC bias output is shown in Figure 13. The abscissa represents the peak value and the ordinate represents the output relative error. As can be seen from the figure, the maximum relative error of the output peak value should not exceed 0.4% in order to meet the needs of practical application. The continuous pulse output mode can control the output frequency and phase, so as to control the forward and reverse rotation of the motor. The square wave loading amplitude error, sine wave loading amplitude error, and triangular wave loading amplitude error are shown in Figures 14–16, respectively. With the increase in frequency, the relative error increases slightly, and the relative error is within 0.8%.

**Figure 13.** Real measurement when setting the 5 V bias output.

**Figure 14.** Square wave loading amplitude error.

**Figure 15.** Sine wave loading amplitude error.

**Figure 16.** Triangular wave loading amplitude error.

#### *5.2. Motor Transient Parameter Test*

According to the system requirements, the main concerns of the motor transient test include the following: the dynamic test of the motor torque and the dynamic input test of the motor speed signal. Because the feedback signal of the speed torque sensor used in this research is the frequency pulse, in which the speed input frequency range is 0–6 KHz, the torque input frequency range is 5 KHz–10 KHz, and the maximum data update rate is 1 ms. The measured system can measure a frequency ranging from 1 Hz to 1 MHz, and the fastest dynamic refresh rate is 1 ms. Figure 17 shows the speed−step response curve, in which the abscissa is time and the ordinate is motor speed. It can be seen from the curve that the system responds within a millisecond level and reaches a stable state after 1 s. The time to reach stability is also related to the lag effect of the servo motor. The test results show that the system has a fast response speed and preliminarily meets the expected design requirements. Figure 18 shows frequency measurement and analog measurement, which would be used to measure the speed and torque signal of the motor.

**Figure 17.** Speed and torque frequency accuracy.

**Figure 18.** The host computer displays the speed frequency and AD sampling waveform in real time.

#### **6. Conclusions**

Considering the problem that the traditional motor test system cannot directly test the transient parameters of the motor, the requirements of loading a dynamic arbitrary load when the motor is loaded, as well as the high cost, this paper realizes the main control unit of the motor test system with STM32+FPGA as the core, and FSMC bus communication and the data ping-pong processing algorithm are used to control the dual core and transmit the data stream continuously. The feasibility of the system is verified through its physical design and production. The results show that the project has the following characteristics:


The core of the dynamometer control system based on STM32+FPGA constructed in this way effectively improves the dynamic free loading of the dynamometer system and the measurement of motor transient parameters. It can be further customized and updated according to customer needs. It can provide a valuable experience for the development of dynamometer technology, especially in the measurement of motor dynamic parameters.

**Author Contributions:** Conceptualization, C.Z.; methodology, C.Z. and B.W.; software, C.Z.; validation, C.Z. and B.W.; formal analysis, C.Z.; investigation, B.W.; resources, C.Z.; data curation, L.B. and B.Z.; writing—original draft preparation, C.Z. and B.W.; visualization, J.Q.; supervision, Y.C.; project administration, C.Z.; funding acquisition, C.Z. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by The National Natural Science Foundation of China with grant number 62001149 and The Key R&D Program of Zhejiang Province with grant number 2021C01069.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


## *Article* **Energy Balance Control for Improving Transient Performance of DC Bus Voltage in Power Electronic Transformer for the Voltage-Sensitive Loads**

**Gaohui Feng 1,2,3, Pengsheng Bu 1,2,3 and Liqiang Yuan 4,\***


**Abstract:** The power electronic transformer (PET), as a main topology for the energy router in the energy internet, consists of the rectifiers, the dual active bridge (DAB), and the inverter, and these three parts are connected by two dc buses. So, the performance of the dc bus voltages is very important because it can totally affect the output waveforms of the dc and ac voltage, especially for the voltage-sensitive loads. Compared with the proportion integration (PI) control scheme, the energy control method utilizes the energy as the control variable, and the control strategy derived from the energy relationship, including the passive elements and all the interfaces, is more direct and explicit. In this paper, considering the energy between the dc bus capacitors and the input inductor and the load and the source in the PET topology, the energy balance control (EBC) strategy is proposed. For the two dc bus voltages, the energy balance relationship of the different time scales is used to decouple the interaction in the control scheme. The EBC strategy can obviously reduce the fluctuation and the transient time of the two dc bus voltages when the load power or voltage reference is changed. Thus, under the limited voltage fluctuation, the EBC strategy can reduce the dc bus capacitance in order to reduce the volume and weight of the converter and enhance the reliability. The simulation and experimental results verify the effectiveness of the proposed control strategy.

**Keywords:** dc bus voltage; energy balance control; power electronic transformer; different time scales

#### **1. Introduction**

With the gradual implementation of China's 'double carbon' goal in the distribution network, the power electronic transformer (PET), as the main topology of the energy router, has received wide attention [1–3]. In general, for a high-voltage, high-power converter in a high-power system, because of the limited voltage capacity of the power semiconductor, the topology of the module combination is usually used.

At present, the PET is connected to the distribution network through the high-voltage interface [4–7]. There are two main topologies of the high-voltage converter, which are a cascaded H-bridge topology [8,9] and a modular multilevel converter topology [10,11].

Using the three-stage structure with two dc buses, consisting of the rectifier, the dual active bridge (DAB), and the inverter, the load current feed-forward control strategy was utilized in [12] to improve the transient performance of the two dc bus voltages, and additional current sensors were required. The power synchronization control strategy was used to reduce the second harmonic voltage ripple by transmitting the second harmonic power from the primary dc bus to the secondary dc bus in [13], and the output power was set to be same phase with the input power at the same time to reduce the second voltage ripples. In this reference, the control strategy used the power balance among

**Citation:** Feng, G.; Bu, P.; Yuan, L. Energy Balance Control for Improving Transient Performance of DC Bus Voltage in Power Electronic Transformer for the Voltage-Sensitive Loads. *Energies* **2022**, *15*, 3129. https://doi.org/10.3390/en15093129

Academic Editor: Adolfo Dannier

Received: 23 March 2022 Accepted: 22 April 2022 Published: 25 April 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

the three stages to reduce the dc bus voltage ripples, but the transient performance was not shown. In the cascaded topology shown in [14], in considering the differences of the driving circuits in the PWM rectifiers, the differences of the switching characteristics of the IGBT, and the differences of the leakage inductances of the high-frequency transformer (HFT) in the DAB [15], four different modulation technologies and the control strategies for the cascaded dc bus voltage and power balance were introduced. The conclusion was that the rectifiers with the same duty cycle and the DAB used to realize the cascaded dc bus (CDB) voltage balance represent the optimal control scheme after comprehensive consideration of the control performance and the hardware cost. The energy stored in the dc-link capacitor of the Static Synchronous Compensator (STATCOM), especially the cascaded inverter-based STATCOM, whose dc-link capacitance is relatively large, and the virtual inertial control strategy using the energy are presented, and their effectiveness is also validated by simulation [16]. The energy-balance model was analyzed in [17] for the two-stage, single-phase, grid-connected photovoltaic inverters, and the dc voltage control scheme was proposed. In the feed-forward control scheme, through introducing the energy changes of the inverter inductors to the feed-forward variable, the control method has a better dynamic performance in the dc bus voltage compared with the conventional feed-forward control scheme [18].

For the second harmonic of the dc bus voltage in the single-phase converter, the PI controller does not have the capability to reduce the voltage ripple accurately, and it also could cause a third harmonic in the grid current. To avoid the odd harmonic current and enlarge the grid current total harmonic distortion (THD), corresponding solutions were proposed in many papers. In [19], the moving average filter instead of the low-pass filter was used for filtering the high and low frequency ripples of the dc bus voltage, and the feed-forward component was added to the shunt controller to regulate the grid current at a constant level in the presence of grid disturbances. In another method, to reduce the output current distortion, a Finite Impulse Response (FIR) filter notch filter is employed in the bus control system, and, to improve the dynamic performances, the input power feed-forward is used [20]. In the single-phase grid inverter, the LLCL filters are used to make zero impedance, and the grid-side inductor filter can be reduced. For the resonance phenomenon in the system, an active damping method based on proportional resonance controllers was proposed to suppress the resonance [21]. In the single-phase, grid-connected inverter with LCL filters, the PI inner loop is stabilized by using an inherent one-beat delay, achieved by a digital controller. Based on the inner loop system, a detailed design scheme of a repetitive controller is presented, through which direct control of the grid current is realized; the reference is tracked perfectly to a zero-phase shift, and high-attenuation gain is achieved in the high frequency range. In particular, the grid-voltage feed-forward control and the current reference feed-forward control are adopted to suppress grid-voltage disturbance and increase the dynamic tracking performance [22]. In [23], a repetitive dc link voltage predictor was proposed to improve the compensation performance. An areaequalization-based algorithm was used to calculate the second harmonic and generated the required pulse width. The minimum ripple-energy requirement was derived in [24], and a bidirectional buck-boost converter was used as the ripple energy storage circuit, which can effectively reduce the energy storage capacitance.

Based on the previous research, a novel control strategy is proposed in this paper, named the energy balance control strategy. According to the energy relationship among the sources, the passive elements, the equivalent load, and the EBC can improve the transient performance of the voltage and power balance demands of the cascaded H-bridge. The first section in the paper introduces the application background and the device research status of PET and the current situation of the dc bus voltage control method and deduces the basic principle of the energy balance control method. It is the background introduction of the research. Section 2 introduces the equivalent circuit model of the single-phase, two-stage PET and derives the energy relationship in the device, which is the basis of the following research in the paper. Based on the topology in Section 2, the concrete research

points are carried out in Sections 3 and 4. The two parts are parallel. The energy balance control method and the stability of the two-stage bus voltages (the low bus voltage and the cascade bus voltage) are deduced and verified, respectively. In addition, the influence of the parameter range of the passive components in the model is analyzed for the control law performance in the last, small part of Section 4. On the basis of the previous research contents, the voltage balance control strategy, implemented by the energy balance, is studied in Section 5 in order to form the overall energy balance control strategy in the cascaded PET. In Section 6, the main performance of the proposed energy balance control method is verified by simulation and experimental results. Section 7 is the conclusion of the full paper. The contents of each section and the relationship between them are shown in Figure 1.

**Figure 1.** The contents of each section and their relationship.

#### **2. Mathematical Model of the PET**

The topology of the single-phase PET is shown in Figure 2a, which contains a singlephase rectifier composed of four cascaded H-bridges, four dual active bridges (DAB) in parallel, and a three-phase inverter. The instantaneous power relationship in PET is shown in Figure 2b. The energy flow in PET is shown in Figure 2c.

**Figure 2.** The single-phase PET: (**a**) structure, (**b**) instantaneous power relationship in PET, (**c**) energy relationship in PET.

The single-phase rectifier consists of an input inductor *LS* and four H-bridge modules. Each module uses the same modulation method. The *drj* is the duty cycle of the module *j* and the *UHj* is the CDB voltage of the module *j* (*j* = 1, 2, 3, 4). Ignoring the internal impedances of the inductor and the converters, the cascaded rectifier model can be described as

$$\begin{cases} L\_s \frac{di\_S}{dt} = \mu\_S - d\_{r1} \mathcal{U}\_{H1} - d\_{r2} \mathcal{U}\_{H2} - d\_{r3} \mathcal{U}\_{H3} - d\_{r4} \mathcal{U}\_{H4} \\ \mathcal{C}\_{H1} \frac{d\mathcal{U}\_{H1}}{dt} = d\_{r1} i\_S - \frac{\mathcal{U}\_{H1}}{Z/4} \\ \mathcal{C}\_{H2} \frac{d\mathcal{U}\_{H2}}{dt} = d\_{r2} i\_S - \frac{\mathcal{U}\_{H2}}{Z/4} \\ \mathcal{C}\_{H3} \frac{d\mathcal{U}\_{H3}}{dt} = d\_{r3} i\_S - \frac{\mathcal{U}\_{H3}}{Z/4} \\ \mathcal{C}\_{H4} \frac{d\mathcal{U}\_{H4}}{dt} = d\_{r4} i\_S - \frac{\mathcal{U}\_{H4}}{Z/4} \end{cases} \tag{1}$$

where *Z* is the equivalent impedance of the cascaded rectifier.

Ignoring the DAB internal impedances, the transmitted power of the DAB *PDAB* is

$$P\_{DAB} = \frac{n! I\_H! I\_L d(1-d)}{2f\_s L\_s} = k! I\_H! I\_L \tag{2}$$

where *Ls* is the HFT leakage inductance, *UH* is the primary dc voltage, *UL* is the second dc voltage, *n* is the transformer turns ratio, *fs* is the switching frequency, *d* is the duty cycles, and *k* = *nd*(1 − *d)/*2*fsLs* is the phase shift ration. When *d* equals 0.5, the *PDAB* is the maximum, and when *d* equals 1 or 0, the *PDAB* is zero.

The three-phase inverter model is not the focus of this paper. Here, the load *Z* is used for replacing the equivalent impedance of the ac load and the dc load. So, the average model of the single-phase PET is given in Figure 3, where *k*1~*k*<sup>4</sup> are the phase shift ratios of the four DAB modules.

**Figure 3.** The average model of the single-phase PET.

For improving the transient performance of the PET, the CDB voltage and the LDB voltage in the PET should be controlled. In Figure 2a, the four CDB voltages (*UH*1, *UH*2, *UH*3, and *UH*4) and the LDB voltage (*UL*) should reach their reference as quickly as possible during the transient process. At the same time, in the real system, every H-bridge model is designed to be identical in order to reduce the production consumption and the control complexity. However, the leakage inductance variation of the HFTs can reach 10–20% [14], and the transmitted power variation will also be 10–20%. In extreme cases, if the voltage balance control among the four cascaded modules is not adopted, the dc bus voltage of the DAB module with the largest leakage inductance will be four times the normal dc bus voltage, while the dc bus voltages of the other modules will reduce to nearly 0, which is absolutely unacceptable.

So, the stability of two-stage bus voltages in the topology is very important, especially for the voltage-sensitive loads, such as the data server, the navigation and positioning instrument, and so on. In this paper, Sections 3 and 4 have a parallel relationship. In Section 3, the energy balance relationship around the low-voltage bus is deduced, and the control law and its stability analysis are also introduced in detail. Moreover, in Section 4, the energy balance relationship with the cascade buses is deduced, the stability and the control law for the cascaded voltage balance are analyzed, and the influence of the parameter range of the passive components in the model is analyzed for the control law performance.

#### **3. Energy Balance Control for LDB Voltage**

*3.1. Energy Balance Control Scheme for DAB*

Based on the equivalent circuit in Figure 3 and the energy relationship in Figure 2c, the energy relationship between the DAB, the LDB capacitor, and the equivalent load can be described as

$$E\_{DAB} = E\_{CL} + E\_{Lond} \tag{3}$$

where the four DAB transmitted energies are regarded as the same under the voltage balance control. Considering the energy relationship in one switching period, it can be written as

$$P\_{DAB} = \frac{1}{2} \mathbb{C}\_L \left( \left\| I\_L^{\*2} - \left\| I\_L \right\|^2 \right) / T\_s + P\_{\text{Load}} \right. \tag{4}$$

where *Ts* is the switching period, *fs* = 1/*Ts*.

Then, the total energy relationship becomes

$$4 \times \frac{n! I\_{H\_s s}! I\_{L\_s s} d(1 - d)}{2 f\_s L\_s} = \frac{1}{2} \mathbb{C}\_L \left( \mathcal{U}\_L^{\*2} - \mathcal{U}\_L^{-2} \right) / T\_s + P\_{\text{Load}} \tag{5}$$

where *UH\_s* and *UL\_s* are the expectation values of the CDB and the LDB voltage. After simplification and approximation, the duty cycle *d* for the DAB is

$$d = \frac{\left(\frac{1}{2}C\_L(\mathcal{U}\_L^{\*2} - \mathcal{U}\_L^{\*2})f\_s + P\_{Load}\right) \times 2f\_sL\_s}{4n\mathcal{U}\_{H\_{-s}}\mathcal{U}\_{L\_{-s}}}\tag{6}$$

Considering the control delay of the DAB stage as a first-order inertial element with a constant time *Td*, the control scheme is depicted in Figure 4, and the DAB model is in the green block, where *kd*<sup>1</sup> = *nUH*1/2*fsLs*1, *k*<sup>i</sup> = 1/*UL*.

**Figure 4.** EBC Control model for the LDB voltage.

#### *3.2. Small-Signal Analysis*

Performing small-signal decomposition of the system variables in Figure 4, we have

$$\begin{cases} \begin{array}{c} \mathcal{U}\_{L}^{\*} = \overline{\mathcal{U}}\_{L}^{\*} + \tilde{\mathcal{u}}\_{L}^{\*} \\ \mathcal{U}\_{L} = \overline{\mathcal{U}}\_{L}^{\*} + \tilde{\mathcal{u}}\_{L}^{\*} \\ \mathcal{P}\_{Load} = \overline{\mathcal{P}}\_{Load} + \tilde{\mathcal{P}}\_{Load} \end{array} \tag{7}$$

where *U*<sup>∗</sup> *<sup>L</sup>* is the reference of the LDB voltage, *UL* is the real value of the LDB voltage, and *PLoad* is the real value of the load power. These values are the large-signal component. *u*3∗ *<sup>L</sup>*,*u*3*L*, and *<sup>P</sup>*3*Load* are the small-signal values of the counterparts. The square values of the small signals are small enough to be ignored. The small-signal expression of the duty cycle is

$$\overline{d} = \frac{(\frac{1}{2}\mathbb{C}\_{L}(\overline{\mathcal{U}}\_{L}^{\*}\overline{\mu}\_{L}^{\*} - \overline{\mathcal{U}}\_{L}\overline{\mu}\_{L})f\_{s} + \overline{P}\_{\text{Load}}) \times 2f\_{s}\mathcal{L}\_{s}}{4n\mathcal{U}\_{H\_{s}s}\mathcal{U}\_{\text{L}\_{s}s}}\tag{8}$$

The corresponding small-signal control model is given in Figure 5.

**Figure 5.** Small-signal model for the LDB voltage based on EBC controller.

The closed-loop transfer function of the LDB voltage control system based on EBC is

$$G\_{dc\\_L}(\mathbf{s}) = \frac{\overline{u}\_L}{\overline{u}\_L^\*} = \frac{f\_s \overline{\mathcal{U}}\_L^\* \mathcal{U}\_{H1\\_s}}{8\pi (T\_ds + 1)\mathbf{s} + \mathcal{U}\_{H1\\_s} f\_s \overline{\mathcal{U}\_L}}\tag{9}$$

From (9), it can be seen that the LDB voltage is irrelevant to the dc bus capacitance *CL*. Considering that the expectation value of the CDB voltage *UH1\_s* and the LDB voltage *UL\_s* remains constant, the load power *P*3*Load* fluctuation in the DAB model is counteracted by the load power fluctuation, including in the feed-forward terms in the EBC. So, the load power fluctuation has no impact on the dc bus voltage, as is shown in Figure 5.

When the system adopts the low-bandwidth PI controller, the small-signal control model is as depicted in Figure 6.

**Figure 6.** Small-signal model for the LDB voltage based on PI controller.

The closed-loop transfer function of the LDB voltage control system based on the PI controller is

$$G\_{dc\\_L}(s) = \frac{\tilde{u}\_L}{\tilde{u}\_L^\*} = \frac{(P\_1s + I\_1) \mathcal{U}\_{H1\\_s}}{8\pi f\_s L\_s \mathcal{C}\_L s^2 (T\_d s + 1) + (P\_1s + I\_1) \mathcal{U}\_{H1\\_s}} \tag{10}$$

From (10), it can be seen that the LDB voltage with the PI controller is affected by the capacitance *CL*. When *UH*<sup>1</sup>*\_s* remains constant, from Figure 6, the dc bus voltage is affected by the load power *P*3*Load* fluctuation. The closed-loop transfer functions are

$$G\_{dp\\_L}(s) = \frac{\overline{u}\_L}{\overline{p}\_{Load}} = \frac{8\pi f\_s L\_s (T\_d s + 1)s}{8\pi f\_s L\_s \mathcal{C}\_L s^2 (T\_d s + 1) \mathcal{U}\_{L\\_s} + (P\_1 s + I\_1) \mathcal{U}\_{H1\\_s} \mathcal{U}\_{L\\_s}}\tag{11}$$

It is shown that compared with the PI controller, the EBC controller can eliminate the impacts of the LDB capacitor and the fluctuations of the load power by importing the load power into the control model. The robustness of the EBC is increased.

#### *3.3. Stability Analysis*

The stability analysis of the EBC closed-loop transfer function for the LDB voltage was conducted. The switching period is set as *Ts* = 5 × <sup>10</sup>−<sup>5</sup> s. Considering the sampling and the control delay, *Td* = 2*Ts*, the LDB voltage reference *U*<sup>∗</sup> *<sup>L</sup>* is 700 V and the CDB voltage expectation value *UH*1\_*<sup>s</sup>* is 700 V. When the LDB voltage *UL* changes from 400 V to 1000 V, the denominator of Equation (9) has two poles. The two poles are far away from the origin, with the increasing of the voltage value, as shown in Figure 7. This figure shows that all the poles are located in the left half plane, and so, the system is stable.

**Figure 7.** Pole distribution of the LDB voltage control system based on EBC controller.

#### **4. Energy Balance Control for CDB Voltage**

*4.1. Derivation of CDB Average Voltage Reference*

Based on the equivalent model in Figure 3 and the instantaneous power relationship in Figure 2b, the instantaneous power relationship of the PET is as follows:

$$p\_s = p\_{Ls} + p\_{\bar{C}H1} + p\_{\bar{C}H2} + p\_{\bar{C}H3} + p\_{\bar{C}H4} + p\_{\bar{C}L} + p\_{Load} \tag{12}$$

In the steady state, the voltages in the cascade bus capacitors are equal, and the instantaneous powers of the cascaded capacitors are also same, namely *PHC*<sup>1</sup> = *PCH*<sup>2</sup> = *PCH*<sup>3</sup> = *PCH*<sup>4</sup> = *PCH*; Equation (12) can be simplified as

$$p\_s = p\_{Ls} + 4p\_{CH} + p\_{CL} + p\_{Load} \tag{13}$$

Assume that the grid voltage and current are

$$
\mu\_{\rm s} = \sqrt{2}I l\_{\rm s} \sin(\omega t) \tag{14}
$$

$$
\dot{a}\_s = \sqrt{2}I\_s \sin(\omega t + \theta) \tag{15}
$$

where *Us* and *Is* are the RMS values of the grid voltage and current, *ω* is the grid angular frequency, and *θ* is the initial phase angle of grid current.

Thus, the instantaneous power of the grid is

$$p\_s = u\_s \cdot i\_s = lL\_s l\_s [\cos\theta - \cos(2\omega t + \theta)] = P\_s - lL\_s l\_s \cos(2\omega t + \theta) \tag{16}$$

where the dc component is the constant power of the grid, and it is expended by the load. The second harmonic power of the grid will cause the second harmonic voltage ripple in the CDB voltages.

The instantaneous power of the input inductors is

$$p\_{Ls} = L\_s \frac{di\_s}{dt} i\_s = L\_s I\_s^2 \sin(2\omega t + 2\theta) \cdot \omega \tag{17}$$

The whole instantaneous power of the four cascaded capacitors is

$$4p\_{CH} = 4\mathcal{C}\_H \frac{d\mathcal{U}\_H}{dt} \mathcal{U}\_H \tag{18}$$

The instantaneous power of the capacitors in the LDB is

$$p\_{CL} = \mathbb{C}\_L \frac{d\mathcal{U}\_L}{dt} \mathcal{U}\_L \tag{19}$$

In the steady state, the LDB voltage *UL* is constant, then *PCL* = 0. The load power equals the grid constant power.

$$P\_{\mathbb{S}} = p\_{Load} \tag{20}$$

The phase of the grid voltage and current are set to be the same value. Substituting (14)~(20) into (13), it becomes

$$4\mathcal{C}\_{H}\frac{d\mathcal{U}\_{H}}{dt}\mathcal{U}\_{H} + A\cos(2\omega t - \varphi) = 0\tag{21}$$

where

$$\begin{array}{l} A = I\_s \sqrt{l I\_s^2 + \left(L\_{\text{ac}} I\_s \omega\right)^2} \\ \rho = \arctan \frac{L\_{\text{ac}} I\_s \omega}{l I\_s} \end{array} \tag{22}$$

Then, the average reference of the CDB voltage is

$$\begin{array}{l} \mathrm{LI}\_{H}^{\*} = \sqrt{\mathrm{LI}\_{\mathrm{Have}}^{\*} - B} \\ B = \frac{\lambda}{4\mathbb{C}\_{H} \cdot \omega} \sin(2\omega t - \varphi) \end{array} \tag{23}$$

where *B* is the square value of the second harmonic voltage amplitude of the CDB voltage.

#### *4.2. Energy Balance Control Scheme for Rectifier*

Based on the equivalent model in Figure 3 and the energy relationship in Figure 2c, the energy relationship is as follows:

$$E\_s = E\_{Ls} + 4E\_{CH} + E\_{CL} + E\_{Load} \tag{24}$$

According to the analysis of the two-stage, single-phase photovoltaic grid-connected inverters [17], for the single PWM rectifier, when the system is in steady state, the absolute value of the grid current remains constant after half line cycle *Tg*/2; then, the stored energy of the filter inductor also remains constant after *Tg*/2, namely *ELs* = 0. When ignoring the internal impedances of the PET, the energy relationship of the PET in *Tg*/2 is

$$\frac{T\_{\mathcal{S}}}{2}P\_{\text{Load}} + \frac{1}{2} \cdot 4\mathbb{C}\_{H}(\mathcal{U}\_{H}^{\*,2} - \mathcal{U}\_{H}^{\*,2}) + \frac{1}{2}\mathbb{C}\_{L}(\mathcal{U}\_{L}^{\*,2} - \mathcal{U}\_{L}^{\*,2}) = \mathcal{U}\_{\text{s}}I\_{\text{s}}^{\*}\frac{T\_{\mathcal{S}}}{2} \tag{25}$$

Thus, the grid current reference is

$$I\_s^\* = \frac{P\_{Load} + 4\mathbb{C}\_H f\_\mathcal{\mathcal{S}} (\mathcal{U}\_H^{\*,2} - \mathcal{U}\_H^{\*,2}) + \mathbb{C}\_L f\_\mathcal{\mathcal{S}} (\mathcal{U}\_L^{\*,2} - \mathcal{U}\_L^{\*,2})}{\mathcal{U}\_s} \tag{26}$$

Considering the control delay of the rectifier stage as a first-order inertial element with a constant time *TR*, the control scheme is depicted in Figure 8, and the rectifier model is in the green block, where *kg* = 4*CHfg*, *kT* = 1/*US*, *PR = Lac/TR*, *ur =* 4*dUH*, and *kR = US/*4*UH*.

**Figure 8.** EBC control model for the CDB voltage.

#### *4.3. Small-Signal Analysis*

In the condition that the calculated value *B* is consistent with the actual second harmonic voltage ripple, and the equivalent load power in the CDB side is replaced by the load power in the LDB side, the EBC control model can be depicted as shown in Figure 9.

**Figure 9.** Simplified EBC control model for the CDB voltage.

Performing small-signal decomposition of the system variables in Figure 9, we have

$$\begin{cases} \begin{array}{l} I\_s^\* = \overline{I}\_s^\* + \overline{i}\_s^\* \\ \mathcal{U}\_H^\* = \overline{\mathcal{U}}\_H^\* + \overline{\mathcal{u}}\_H^\* \\ \mathcal{U}\_H = \overline{\mathcal{U}}\_H + \overline{\mathcal{u}}\_H \\ P\_{Load} = \overline{P}\_{Load} + \overline{P}\_{Load} \\ \mathcal{U}\_L^\* = \overline{\mathcal{U}}\_L^\* + \overline{\mathcal{u}}\_L^\* \\ \mathcal{U}\_L = \overline{\mathcal{U}}\_L + \overline{\mathcal{u}}\_L^\* \end{array} \tag{27}$$

where *I* ∗ *<sup>s</sup>* is the grid current, *U*<sup>∗</sup> *<sup>H</sup>* is the reference of the CDB voltage, *UH* is the real value of the CDB voltage, *U*<sup>∗</sup> *<sup>L</sup>* is the reference of the LDB voltage, *UL* is the real value of the LDB voltage, and *PLoad* is the real load power. These values are the large-signal component. 3*i* ∗ *s* , *u*3∗ *<sup>H</sup>*, *<sup>u</sup>*3*H*, *<sup>u</sup>*3<sup>∗</sup> *<sup>L</sup>*, *<sup>u</sup>*3*L*, and *<sup>P</sup>*3*Load* are the variation in the transient process; these variations are the small-signal values of the counterparts. The square values of the small signals are small enough to be ignored. The small-signal expression of the current reference is

$$\overline{i\_s}^\* = \frac{\overline{P}\_{Load} + 4\mathbb{C}\_H f\_\mathcal{g} (\Box^\*\_H \overline{u}^\*\_H - \Box\_H \overline{u}\_H) + \mathbb{C}\_L f\_\mathcal{g} (\Box^\*\_L \overline{u}^\*\_L - \Box\_L \overline{u}\_L)}{\mathcal{U}\_s} \tag{28}$$

The corresponding small-signal model is shown in Figure 10.

**Figure 10.** Small-signal model for the CDB voltage based on EBC controller.

The closed-loop transfer function of the CDB voltage control system based on the EBC controller is

$$G\_{dc\\_H}(s) = \frac{\tilde{\mathcal{U}}\_H}{\tilde{\mathcal{U}}\_H^\*} = \frac{f\_{\mathcal{S}} \overline{\mathcal{U}}\_H^\*}{[T\_R s(T\_R s + 1) + 1] \mathcal{U}\_{Hav} s + f\_{\mathcal{S}} \overline{\mathcal{U}}\_H} \tag{29}$$

It can be seen that the CDB voltage is irrelevant to the dc bus capacitance *CH*. Considering that the grid voltage *Us* remains constant, the load power *P*3*Load* fluctuation in the rectifier model and the stored energy fluctuation of the LDB capacitor are counteracted by the same power fluctuation, including in the feed-forward terms in the EBC. So, the fluctuation of the load power and the LDB capacitor power have no impact on the dc bus voltage, as shown in Figure 10.

When the system adopts the low-bandwidth PI controller, the small-signal model is as depicted in Figure 11.

**Figure 11.** Small-signal model for the CDB voltage based on PI controller.

The closed-loop transfer function of the CDB voltage control system based on the PI controller is

$$G\_{dc\\_H}(s) = \frac{\tilde{\mathcal{U}}\_H}{\tilde{\mathcal{U}}\_H^\*} = \frac{(Ps + I)\mathcal{U}\_S}{4s^2 \mathcal{U}\_{Have} \mathcal{C}\_H[T\_Rs(T\_Rs + 1) + 1] + (Ps + I)\mathcal{U}\_S} \tag{30}$$

It can be seen that the CDB voltage with the PI controller is affected by the capacitance *CH*. When the grid voltage *US* remains constant, the dc bus voltage is affected by the load power *P*3*Load* fluctuation, the capacitance on the LDB side *CL*, and the LDB voltage fluctuation *<sup>u</sup>*3<sup>∗</sup> *<sup>L</sup>*. The closed-loop transfer functions are

$$G\_{dp\\_H}(s) = \frac{\tilde{u}\_H}{\tilde{P}\_{Load}} = \frac{[T\_Rs(T\_Rs + 1) + 1]s}{4s^2 \mathcal{U}\_{Have} \mathcal{C}\_H [T\_Rs(T\_Rs + 1) + 1] + (Ps + I)\mathcal{U}\_S} \tag{31}$$

$$G\_{\bar{d}l\_{-}H}(s) = \frac{\bar{u}\_{H}}{\bar{u}\_{L}^{\*}} = \frac{\mathbb{C}\_{L}f\_{\mathcal{S}}\overline{\mathcal{U}}\_{L}^{\*}[T\_{R}s(T\_{R}s+1)+1]s}{4s^{2}\mathcal{U}\_{H\text{ave}}\mathbb{C}\_{H}[T\_{R}s(T\_{R}s+1)+1] + (Ps+I)\mathcal{U}\_{S}}\tag{32}$$

It can be concluded that compared with the PI controller, the EBC controller can eliminate the impacts of the CDB capacitors and the fluctuations of the load power and the power of the LDB capacitor by importing their power into the control structure. The robustness of the EBC for the CDB voltage is increased.

#### *4.4. Stability Analysis*

The stability analysis of the EBC closed-loop transfer function for the CDB voltage was conducted. The switching period is set as *Ts* = 1 × <sup>10</sup>−<sup>4</sup> s. Considering the sampling and the control delay, *TR* = 2*T*s, the grid frequency *fg* = 50 Hz, and the dc bus voltage reference *UHave* = 700 V. When the dc bus voltage *UH* changes from 400 V to 1000 V, the denominator of Equation (29) has three poles. Two poles are far away from the origin and the other one is the dominant pole, moving away from the origin with the increasing of the voltage value, as is shown in Figure 12. This figure shows that all the poles are located in the left half plane, and the system is stable.

**Figure 12.** Pole distribution of the CDB voltage control system based on EBC controller.

#### *4.5. Adaptability Analysis of Model Parameter*

When EBC control mode is adopted, the parameter deviation of the passive components in the model has limited influence on the control effect. In the simulation shown in Figure 13a, the load power increases rapidly from 1.4 kw to 28 kw at 0.7 s, when the capacitance value of two-stage bus has the same direction deviation of ±30%. From the simulation waveform, it can be seen that the voltage of the cascade bus basically does not overshoot in the dynamic process, and the maximum difference of the intermediate bus voltage in the steady-state process is within 2 V, which is consistent with the relationship between the capacitance value of the intermediate bus and the ripple amplitude of the secondary voltage in Formula (23). At the same time, the difference of the capacitance value will affect the average value of the bus voltage. There is almost no overshoot of low-voltage bus voltage in the dynamic process. In the steady state, the bus voltage fluctuates slightly with the increase in power, but the fluctuation value is very small and can be ignored.

As shown in Figure 13b, when the capacitance value of the two-stage bus has a reverse deviation of ±30%, the simulation waveform of the bus voltage is similar to that with the same deviation. It shows that EBC has good adaptability to capacitance parameter deviation, but the ripple of the steady-state process is affected, and the dynamic performance is not affected.

As shown in Figure 13c, when the grid side inductance value deviates by ±30%, the CDB voltage and the LDB voltage have almost no overshoot in the dynamic process. It is verified that EBC has good adaptability to the inductance parameters, and the change of inductance parameters has no impact on the steady-state and dynamic control effects.

**Figure 13.** *Cont.*

**Figure 13.** Influence of capacitance and inductance deviation on bus voltage: (**a**) ±30% samedirection deviation in two-stage bus capacitance, (**b**) ±30% reverse-direction deviation in two-stage bus capacitance, (**c**) ±30% deviation in the grid side inductance.

#### **5. Overall Structure of Proposed Control Strategy**

When the CDB voltages of each cascaded module are equal under the voltage balance control, and the duty cycles transmitted to each of the rectifier modules are the same, the received powers of each module are also equal. Therefore, when the CDB voltages are equal, the same duty cycle transmitted to each of the rectifier modules can conveniently ensure the power balance with a small error.

In the DAB controller, the first DAB module controls the LDB voltage, and the other three DAB modules control their respective primary side voltages to follow that of the first DAB module. The control scheme of the parallel DABs is shown in Figure 14; the four DAB modules adjust their respective duty cycle (*d*f1, *d*f2, *d*f3, *d*f4) and use the EBC to change the transmitted power and guarantee that the other three CDB voltages follow the first CDB voltage. The *d*f1 is the phase shift control duty cycle of the first DAB module, and *d*f2, *d*f3, *d*f4 are the phase shift control duty cycle of the second, third, and fourth DAB modules, respectively.

The cascaded rectifier modules adopt the same duty cycle for achieving the transmitted power balance. At the same time, the carrier phase shift is utilized to increase the equivalent switching frequency.

The energy balance control diagram of PET is revealed in Figure 15. In the rectifier, the control scheme adopts a double-loop control structure. The automatic energy regulator (AER) is used in the outer loop for controlling the CDB voltage, and the automatic current regulator (ACR) is used in the inner loop for controlling the grid current. In the DAB, the AER controls the LDB voltage and the CDB voltage balance, and the phase shift (PS) modulation is used in the DAB. For the inverter, the ordinary double-loop d-q decoupling control scheme is adopted. For the DC/DC converter, the ACR is used to control the output

current or the output power when the PET is on the grid. In the off-grid state, the DC/DC converter is used to control the LDB voltage.

**Figure 14.** Control scheme in the parallel DABs.

**Figure 15.** Proposed EBC strategy for PET.

#### **6. Simulation and Experimental Verification**

#### *6.1. Simulation Results*

As a comparison, the PI control scheme is used in the PET. In the CDB control loop, the voltage sampling values are filtered with a low-pass filter, whose bandwidth is 30 Hz. The simulation parameters are listed in Table 1.



When the CDB voltage is controlled by the EBC controller and the LDB voltage is controlled by the PI controller, the waveforms of the variables are as presented in Figure 16, in which the red curves *UHx\_ave* represent the average values of the real voltage *UHx*. It is shown that the four CDB voltages are stable and balanced in the steady state, and this proves the effectiveness of the EBC scheme.

**Figure 16.** Comparison of the four CDB voltages for the load power steps (from 1.4 kW to 28 kW).

For the transient performance of the CDB voltages and the LDB voltage, Figure 17 demonstrates the waveforms of the *UH*1, *UH*<sup>1</sup>*\_ave*, and the *UL* when the load power increases from 1.4 kW to 28 kW at 0.7 s, in which the PI controller and the EBC controller are used, respectively. The EBC control strategy can achieve a better transient performance than the PI controller, both in the CDB voltage and the LDB voltage, as is shown in Figure 17b,c. Two different time-scale EBC controllers used in two dc bus voltages simultaneously can realize the optimal transient performance, which has the minimum transient time and a very small overshoot, as is shown in Figure 17d.

**Figure 17.** Comparison of the CDB voltage and the LDB voltage for load power steps (from 1.4 kW to 28 kW): (**a**) with PI controller in CDB voltage and LDB voltage, (**b**) with EBC controller in CDB voltage and with PI controller in LDB voltage, (**c**) with PI controller in CDB voltage and with EBC controller in LDB voltage, (**d**) with EBC controller in CDB voltage and LDB voltage.

The corresponding track of the time-domain waveform in the phase plane is shown in Figure 18, which is composed of the average of CDB voltage *UH*<sup>1</sup>*\_ave* in the horizontal axis and the LDB voltage *UL* in the vertical axis. The smaller the area that is surrounded by the track in the figure means the smaller the change of the energy storage of the two-stage bus capacitance in the transient process, which means the smaller the voltage fluctuation. It can be found from the comparison that the transient performance of the two-stage dc bus voltage can be effectively improved by using EBC.

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**Figure 18.** Phase-plan diagrams of the average of the CDB voltage and the LDB voltage: (**a**) With PI controller in CDB voltage and LDB voltage, (**b**) with EBC controller in CDB voltage and with PI controller in LDB voltage, (**c**) with PI controller in CDB voltage and with EBC controller in LDB voltage, (**d**) with EBC controller in CDB voltage and LDB voltage.

When the voltage reference changes from 680 V to 700 V at 0.7 s, the waveforms of the variables with the EBC controller are shown in Figure 19. It is shown that four CDB voltages are kept in good consistence whether in the steady state or the transient state.

**Figure 19.** Comparison of the four CDB voltages for voltage reference rises (from 680 to 700 V).

To verify the voltage balance control effect in the different parameters of the DAB modules, the leakage inductance of the HFTs in the 4th DAB module is set to be 10% larger than the others in the simulation setup (*Ls*<sup>1</sup> = *Ls*<sup>2</sup> = *Ls*<sup>3</sup> = 328 uH, *Ls*<sup>4</sup> = 360 uH). The four CDB voltages and the parallel transmitted power are shown in Figure 20. It can be seen that when the voltage balance control is not adopted, the *UH*<sup>4</sup> is out of control when the transmission power increases. When the PI controller is used for voltage balance control, the voltage and power balance of the four modules can be realized after a period of time. After adopting the EBC controller, the voltage balance speed of the four modules is accelerated, and the power in the four DAB modules can be quickly balanced.

**Figure 20.** *Cont.*

#### *6.2. Experimental Results*

The photograph of the experimental prototype is displayed in Figure 21. Considering the load power limitation in the lab, the load power in the experiment changes from 5.20 kW to 9.68 kW, and the other parameters are the same as those used in the simulations.

**Figure 21.** Photograph of the prototype.

Figure 22 demonstrates the experimental waveforms of the four CDB voltages (*UH*4, *UH*3, *UH*2, and *UH*1), the LDB voltage (*UL*), the input current (*is*), the input voltage (*us*), and output ac line voltage (*uab*), and the output ac currents (*ia*, *ib*, and *ic*) used by the PI controller and the EBC controller, respectively, in the rectifier and the DAB. For displaying clearly the deviation of the CDB voltage during the transient process, the second CDB voltage *UH*<sup>2</sup> is shown in an ac coupling method, and the others are shown in a dc coupling

method. With the load power steps, the recovery time of the CDB voltage with the EBC controller is smaller than that in the PI controller, as is shown in Figure 22a,b. The CDB voltage deviation with the EBC controller is similar than that in the PI controller, as is shown in Figure 22b,c. The experiment results have a little difference from the simulation waveforms; the reason is that the changed load power is not obvious for the previous load, and the calculation deviation for the second harmonics voltage ripple has been influenced by measurement error.

**Figure 22.** *Cont.*

**Figure 22.** The transient experiment waveforms for load power steps (from 5.20 kW to 9.68 kW) (from top to bottom: *UH*<sup>4</sup> (500 V/div), *UH*<sup>3</sup> (500 V/div), *UH*<sup>2</sup> (2 V/div, ac coupling), *UH*<sup>1</sup> (500 V/div), *UL* (200 V/div), *is* (5 A/div), *us* (1 kV/div), *uab* (400 V/div), *iabc* (20 A/div)): (**a**) with the PI controller in the CDB and LDB voltage, (**b**) with the EBC controller in the CDB voltage, with the PI controller in the LDB voltage, (**c**) with the PI controller in the CDB voltage, with the EBC controller in the LDB voltage, (**d**) with the EBC controller in the CDB and LDB voltage.

The different time scales of the EBC controllers are used in the rectifier and the DAB simultaneously; the transient performance of the two dc bus voltages is more improved than those with the PI controller, as is shown in Figure 22d. The reason is that the interaction between the energy of the CDB capacitors and the LDB capacitors has been considered in the EBC control strategy.

The trajectories of the above four experimental waveforms in the phase plane are shown in Figure 23. The area surrounded by the trajectories obtained by the EBC controller is the smallest, which verifies that EBC has good transient performance. In the figure, the horizontal axis is the voltage of LDB *UL*, and the vertical axis is the ac coupling value of the 2nd CDB voltage *UH*2.

**Figure 23.** *Cont.*

**Figure 23.** Phase-plane diagrams of the average of the CDB voltage and the LDB voltage: (**a**) with the PI controller in the CDB and LDB voltage, (**b**) with the EBC controller in the CDB voltage, with the PI controller in the LDB voltage, (**c**) with the PI controller in the CDB voltage, with the EBC controller in the LDB voltage, (**d**) with the EBC controller in the CDB and LDB voltage.

The experimental results also verify the control performance of the EBC controller when the CDB voltage reference changes from 680 V to 700 V. Figure 24 demonstrates the experimental waveforms of the signal of the voltage reference changes, the four CDB voltages (*UH*4, *UH*3, *UH*2, and *UH*1), the LDB voltage (*UL*), the input current (*is*), the input voltage (*us*), and the output ac line voltage (*uab*); the output ac currents (*ia*, *ib*, and *ic*) used the PI controller and the EBC controller, respectively, in the different current-limited references. In Figure 24a, the current-limited reference is set up to 10 A; the input current rises to 10 A and then decreases slowly for the charging of the dc bus voltages under the PI controller. In Figure 24b, the current-limited reference is also set up to 10 A; the input current rises to 10 A and then keeps within the limited value until the dc bus voltage reaches the reference value. If the current-limited reference can increase further, for example from 10 A to 30 A, the dc bus voltage can realize the faster transient performance in Figure 24c. Therefore, by utilizing the reasonable current-limit value, the EBC controller can achieve a better transient performance than the PI controller.

(**a**)

**Figure 24.** *Cont.*

**Figure 24.** The transient experiment waveforms for voltage reference rises (from 680 to 700 V) (from top to bottom: the signal for the voltage reference changes, *UH1* (500 V/div), *UH2* (25 V/div), *UH3* (500 V/div), *UH4* (500 V/div), *is* (5 A/div), *us* (1 kV/div), *UL* (200 V/div), *uab* (400 V/div), *iabc* (20 A/div)): (**a**) with the PI controller in current-limited reference, (**b**) with the EBC controller in current-limited reference, (**c**) with the EBC controller in increased current-limited reference.

#### **7. Conclusions**

For the voltage-sensitive loads connected with the PET, the EBC strategy can achieve a better transient performance of the dc bus voltages than the conventional PI control strategy. The essential reason is that the interaction between the energy of the CDB capacitors and the LDB capacitors has been considered in the EBC control strategy with different time scales. Through the small-signal analysis of the control strategy in the CDB voltage and LDB voltage, the EBC control strategy can eliminate the impacts of the dc bus capacitors and the fluctuations of the load power compared with the PI control scheme. The stability of the EBC strategy is proved by the stability analysis. The expression of the second harmonic in the CDB voltage is deduced through the instantaneous power-balance relationship in the single-phase PET, and it is helpful in improving the transient performance. Combined with the voltage balance control scheme, the proposed EBC strategy can realize the voltage balance in the cascaded modules. The EBC strategy can be extended to PET, which consists of *n*-H-bridge rectifier modules and *n*-DAB converter modules. The simulation and the experimental results prove the effectiveness of the proposed control strategy.

**Author Contributions:** Conceptualization, G.F.; data curation, P.B.; formal analysis, G.F.; methodology, G.F.; project administration, L.Y.; software, P.B.; supervision, L.Y. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by the National Key Research and Development Program of China grant number 2020YFB1314002 And The APC was funded by 2020YFB1314002.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** The data presented in this study are available on request from the corresponding author.

**Conflicts of Interest:** The authors declare that there are no conflicts of interest regarding the publication of this paper.

#### **References**


### *Article* **Evaluation of GaN HEMTs in H3TRB Reliability Testing**

**Jose A. Rodriguez \*, Tsz Tsoi, David Graves and Stephen B. Bayne**

Center for Pulsed Power and Power Electronics, Department of Electrical and Computer Engineering, Texas Tech University, Lubbock, TX 79409, USA; tsz.tsoi@ttu.edu (T.T.); david.graves@ttu.edu (D.G.); stephen.bayne@ttu.edu (S.B.B.)

**\*** Correspondence: jose.a.rodriguez@ttu.edu

**Abstract:** Gallium Nitride (GaN) power devices can offer better switching performance and higher efficiency than Silicon Carbide (SiC) and Silicon (Si) devices in power electronics applications. GaN has extensively been incorporated in electric vehicle charging stations and power supplies, subjected to harsh environmental conditions. Many reliability studies evaluate GaN power devices through thermal stresses during current conduction or pulsing, with a few focusing on high blocking voltage and high humidity. This paper compares GaN-on-Si High-Electron-Mobility Transistors (HEMT) device characteristics under a High Humidity, High Temperature, Reverse Bias (H3TRB) Test. Twentyone devices from three manufacturers were subjected to 85 ◦C and 85% relative humidity while blocking 80% of their voltage rating. Devices from two manufacturers utilize a cascade configuration with a silicon metal-oxide-semiconductor field-effect transistor (MOSFET), while the devices from the third manufacturer are lateral p-GaN HEMTs. Through characterization, three sample devices have exhibited degraded blocking voltage capability. The results of the H3TRB test and potential causes of the failure mode are discussed.

**Keywords:** power electronics; reliability; wide-bandgap

#### **1. Introduction**

Gallium Nitride (GaN) High-Electron-Mobility Transistors (HEMT) have become favorable devices for power electronics applications due to their high bandgap, mobility, and critical field [1]. GaN devices have lower thermal conductivity than silicon (Si) devices but offer lower overall power dissipation and improved efficiency [2]. Compared to Silicon Carbide (SiC) power devices, commercially available GaN HEMTs have lower blocking voltage capability due to their lateral design. However, they have lower parasitic capacitance, making them suitable for high-frequency operation [3]. The lower blocking voltage for GaN HEMTs can be overcome using modular power converter designs by stacking several low voltage devices for high voltage operation with high efficiency [2]. These characteristics have allowed the development of high-power density and highefficiency power electronics systems, resulting in GaN HEMTs being heavily integrated into power supplies and fast chargers for EV applications [4]. These applications require high-power density systems that limit the available cooling capacity and thus operate the GaN HEMT at high operating temperatures. Implementing GaN HEMTs in EV charging stations means operating in potentially humid environments. Thus there is great interest in evaluating the reliability of GaN power HEMTs under thermal stresses.

Reliability testing of GaN HEMTs has primarily focused on thermal stresses. A known reliability issue with GaN HEMTs is its dynamic on-state resistance due to hot-carrier injection and trap buffers [5], resulting in higher conduction losses and reduced current conduction. This effect is temperature-dependent and can be suppressed by using a substrate with high thermal conductivity, such as a SiC substrate [6]. However, most GaN HEMTs for power electronics applications are grown on a Si substrate due to cost [4], so reliability tests have focused on thermal stresses induced by a current bias. Several

**Citation:** Rodriguez, J.A.; Tsoi, T.; Graves, D.; Bayne, S.B. Evaluation of GaN HEMTs in H3TRB Reliability Testing. *Electronics* **2022**, *11*, 1532. https://doi.org/10.3390/ electronics11101532

Academic Editors: Ching-Ming Lai, Yitao Liu and Elias Stathatos

Received: 18 March 2022 Accepted: 9 May 2022 Published: 11 May 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

works in reliability testing of GaN HEMTs evaluated its current capabilities in single or repetitive pulsing [7,8], where the change in its current conduction determines the degradation. Q. Song et al. have evaluated GaN cascode HEMTs under surge current events and transient overvoltage conditions [9]. There have also been works focused on accelerated aging due to thermal stresses from thermal power cycling between 25 and 125 ◦C [10]. S. Song et al. observed electrical cracks in the degraded devices, corresponding to increased leakage current, while the threshold voltage and on-state resistance have been unaffected [11]. These works have not included a combination of humidity, high temperature, and blocking voltage in their testing, as they can accelerate power devices' failure mechanisms [12].

The High Humidity, High Temperature, Reverse Bias (H3TRB) accelerated lifetime test evaluates the robustness of the semiconductor device. Humidity can penetrate the device's packaging, causing accelerated cracking and corrosion [12]. The presence of high ambient temperature can further accelerate corrosion once moisture is present in the package [13]. Several works have evaluated Si IGBT modules and discrete devices using the H3TRB test [14–16] to identify characteristics that help estimate the remaining lifetime. Electrochemical corrosion and electrochemical migration were the primary failure mechanisms of these Si IGBTs [16]. These works have implemented current sensing to monitor the leakage current of the devices during testing. Changes in leakage current are potential signs of accelerated aging of the device or device degradation [17]. An end-of-life H3TRB reliability study was conducted for 600/650 V enhancement-mode GaN HEMTs [18]. These devices were tested at 85 ◦C with relative humidity (RH) of 85% and blocking voltage of 480 V, with pauses for device characterization every 500 h. A. Brunko et al. found no device failure unit after 2300 h of testing. The PCB housing for their devices had degraded after 1200 h of testing, highlighting the challenge of conducting reliability testing under humidity. Although different enhancement-mode GaN HEMTs were tested, the discussion about the observed failure modes was limited. The proposed work establishes a testbed to subject commercial GaN HEMTs to an H3TRB test to evaluate their reliability and to investigate any failure mechanism that arises due to humidity.

This paper presents a comparative study of GaN HEMTs evaluated under the H3TRB test, following the JEDEC standard JESD22-A101. GaN power devices from three manufacturers were utilized based on blocking voltage and current rating. Seven devices from each manufacturer were selected for a total of twenty-one devices. These devices were placed in an environmental chamber with an ambient temperature of 85 ◦C and 85% RH while blocking 80% of their voltage rating as part of the JEDEC standard. Their leakage current was monitored for each device under test (DUT) during testing to detect when device failure has occurred. Testing was conducted for one thousand hours. After testing, the characteristics of the devices were measured to identify degradation. The result of the test and potential failure mechanisms are discussed.

#### **2. Methodology**

This section presents the methodology for performing the H3TRB test on the GaN HEMTs. A sample of twenty-one devices was used for testing, sharing a blocking voltage rating of 650 V and a forward current rating between 30 A and 42 A. Device group D1 consists of TP65H035G4WS from Transphorm, device group D2 consists of GAN063-65WSAQ from Nexperia, and device group D3 consists of GS-065-030 from GaN Systems. Devices from groups "D1" and "D2" utilize a HEMT cascode configuration, where a GaN depletionmode HEMT is in series with an internal low voltage Si metal–oxide–semiconductor field-effect transistor (MOSFET) to achieve a normally-off transistor device. This topology is the most common among GaN HEMTs for power electronics applications [4]. Devices from group "D3" are p-GaN HEMTs that use a p-type gate to achieve a normally-off device. The main advantage of p-GaN HEMTs over the cascode configuration is direct control of the GaN device and a less complex device structure. However, it has a lower threshold voltage that is prone to instability [19]. Table 1 lists the electrical parameters of the DUTs [20–22].


**Table 1.** Characteristics of devices under test.

Each DUT has its biasing circuit consisting of a fuse and a current sense resistor (CSR) for low-side sensing. Figure 1 shows the biasing circuit for a single DUT. A Sorensen XHR 600-1.7 high voltage power supply provides the high voltage bias of 520 V across the drain and source of the DUT, following JEDEC standards. The 200 mA fuse allows the H3TRB test to run uninterrupted from device catastrophic failures. A 100 Ω CSR is utilized to measure the leakage current of each device during testing. The DUTs are mounted onto a daughterboard which allows several devices to be tested simultaneously. An acrylic coating is applied to the daughterboard to withstand operation inside the environmental chamber. High voltage putty was also applied around unused and exposed terminals to minimize the likelihood of voltage breakdown not caused by device degradation. The DUTs are subjected to 85 ◦C and 85% RH inside a T2RC-A-F4T Environmental Chamber for a thousand hours. Figure 2 shows the overall H3TRB testbed.

**Figure 1.** Schematic of H3TRB testbed.

An NI data acquisition system (USB-6255 myDAQ) measured the voltage drop across the CSR with a sampling rate of 1 sample every 10 s. Fast sampling rates are unnecessary as the devices are DC-biased, and the leakage current is expected to increase gradually. The average leakage current per hour was calculated, and the averaged data are presented in Figure 3.

**Figure 2.** H3TRB testbed.

**Figure 3.** Leakage current of DUT during testing.

The average leakage current for all devices was between 10 μA and 20 μA. Devices "D11", "D13", and "D17" exhibit an increase in leakage current before sharply increasing above the leakage current threshold of 200 μA. Table 2 shows a summary of the results from the H3TRB test. The fuses for these three DUTs were blown, suggesting that the devices had shorted during testing. From Figure 3, device "D11" is expected to have shorted 825 h into the test, device "D13" has shorted after 950 h, and device "D17" has shorted after 650 h. Device "D14" has also shown increased leakage current but has not sharply risen above the threshold like the other three devices. Leakage current data are missing for devices "D36" and "D37" due to a software error but were otherwise tested under the same test conditions as the other devices. Out of the sample of devices tested, devices "D11", "D13", and "D17" are considered degraded.


**Table 2.** Summary of H3TRB test.

#### **3. Results**

The characterization results of the DUTs are presented. The DUTs were characterized using a B1505A curve tracer before and after the test to identify degraded electrical characteristics. The blocking voltage curve, transfer characteristic curve, gate-source leakage curve, and output characteristic curve was measured for all DUTs.

Figure 4 shows the blocking voltage curve for device group "D1". For all DUTs except devices "D11", "D13", and "D17", the leakage current is consistent between testing. The breakdown voltage curve for devices "D11", "D13", and "D17" quickly increases to the leakage current threshold of 100 μA, confirming that the devices are unable to hold off voltage in the off state. Device group "D1" utilizes the GaN cascode topology, where the Si MOSFET initially holds off the voltage in the off state. As the blocking voltage increases, the gate-source of the internal GaN HEMT is biased negatively, pinching off its channel and thus allowing the internal GaN HEMT to block voltage. The degraded DUTs' inability to hold off voltage suggests that either a short is present between the drain and source of the DUT or the DUT's internal Si MOSFET is damaged. Figure 5 shows the gate-source leakage current for device group "D1". The gate current is below 40 pA for all devices and between testing. The internal Si MOSFET oxide layer of the degraded devices is intact.

Figure 6 shows the transfer characteristics for device group "D1". The threshold voltage was measured with a compliance limit of 10 mA on the SMU of the B1505A. The threshold voltage curve for the non-degraded devices is consistent between testing. However, the curve tracer cannot measure the threshold voltage curve for the degraded devices due to its drain current limit.

**Figure 4.** Blocking voltage curve for device group "D1".

**Figure 5.** Gate leakage current curve for device group "D1".

**Figure 6.** Transfer characteristic curve for device group "D1".

Figures 7–9 show the output characteristics between testing of the degraded devices "D11", "D13", and "D17", respectively. For all three devices, significant current flow is measured at 0 VGS and 4 VGS, where it was in the off state in the initial characteristics. The forward current reached 6 A, 1 A, and 2 A with a 3 VDS bias at 0 VGS for devices "D11", "D13", and "D17", respectively. However, the forward current of the degraded devices increases approximately to the same level as their initial characteristics at 8 VGS and above. Table 1 and Figure 6 show that the degraded devices' initial threshold voltage is 4 V. The output characteristic curves show that the internal Si MOSFET channel resistance can be controlled with the gate–source voltage.

**Figure 7.** Output characteristic curve of device "D11".

**Figure 8.** Output characteristic curve of device "D13".

**Figure 9.** Output characteristic curve of device "D17".

The drain–source resistance was calculated using the same data from the previous output characteristic figures. Figures 10–12 show the drain–source resistance of the degraded devices "D11", "D13", and "D17", respectively. The gate–source voltage was swept from 0 to 20 VGS. The measured drain–source resistance varies between 0.4 and 2.0 Ω from 0 to 4 VGS, whereas at 5 VGS and above, the drain–source resistance drops towards its initial on-state resistance value. The resistance difference between the initial and final on-state resistance was 0.3 mΩ for device "D11". However, devices "D13" and "D17" have a much more significant drop of 4.0 mΩ and 2.0 mΩ. The overall current-conducting capabilities of the degraded devices were not affected, but their ability to block voltage was.

**Figure 10.** Drain–source resistance curve of device "D11".

**Figure 11.** Drain–source resistance curve of device "D13".

The remaining devices from groups "D2" and "D3" were characterized. Figures 13 and 14 show the blocking voltage curve for device groups "D2" and "D3", respectively. The leakage current in the figures is consistent between testing. As shown in Figure 3, the leakage current from device groups "D2" and "D3" were constant throughout testing.

Figures 15 and 16 show the transfer characteristic curve for device groups "D2" and "D3", respectively. The threshold voltage was measured with a compliance limit of 100 mA for device group "D3". The high compliance limit was set to the threshold voltage at 10 mA following the datasheet specifications of device group D3, while the other two groups specified threshold voltage at 1 mA. While the threshold voltage curve for device group "D2" is consistent between testing, there was an increase in the rate of drain current for devices "D31", "D32", "D36", and "D37". This increase in the current drain rate suggests that the transconductance has shifted. All devices from device group "D3" have minor threshold voltage shifts up to 0.2 V, and both positive and negative shifts are observed.

**Figure 13.** Blocking voltage curve for device group "D2".

**Figure 15.** Transfer characteristic curve for device group "D2".

**Figure 16.** Transfer characteristic curve for device group "D3".

Figures 17 and 18 shows the output characteristic curve of device "D27" and "D37". Since the previous characterization curves for device group "D2" have not shown any changes, it is expected that all the devices in that group have a similar forward current profile, as shown in Figure 17. An increased current flow is observed for device group "D3" once the gate–source voltage is above the threshold. However, the forward current reaches the same level as the initial characteristics at 3 VGS and above. This behavior is observed for all devices in device group "D3". The devices' forward current and blocking voltage capability from device groups "D2" and "D3" have not been affected by the H3TRB test.

**Figure 17.** Output characteristic curve of device "D27".

**Figure 18.** Output characteristic curve of device "D37".

#### **4. Discussion**

Utilizing the output characteristics and drain–source resistance curves of the degraded devices "D11", "D13", and "D17", some inferences can be made about the likely cause of degradation. For each degraded device, the drain–source resistance is between 0.41 Ω and 2.6 Ω when the gate bias is below the initially tested threshold voltage value. However, the degraded drain–source resistance falls below the initial values once the gate bias surpasses the threshold voltage. This change in drain–source resistance indicates that the internal Si MOSFET is intact and that there is a secondary path between the gate and drain of the internal GaN HEMT that allows current flow when the device is in the off state. Transphorm and Q. Song et al. [9,23] observed and documented this short in their reliability testing and caused dielectric failure in the device when subject to a high electric field. The test conditions of the previous works are different from the presented work. However, all three cases subject the DUT to heat, either localized or from the environment, and a high electric field due to a transient or static voltage bias. Based on the characteristic curves of the degraded devices, it is believed that the failure mode observed in the degraded devices are like the failure modes seen in [9,23].

Although the underlying cause for this failure is known, the results from the presented work still provide novel information on the long-term reliability of GaN HEMTs operating in high humidity, high temperature environments. Similar failure modes have been observed in three different testing environments. The test conditions and time to failure reported by Transphorm are of interest for comparison due to using the same devices. Transphorm provides reliability data under High Temperature Reverse Bias (HTRB) testing following the JEDEC standard JESD22-A108. The devices were biased at 520 V between drain and source with an operating temperature of 150 ◦C. Transphorm tested 231 devices for qualification, with all devices passing after one thousand hours of testing [24]. When comparing the HTRB results presented by Transphorm to the presented work results, there is a clear distinction between the number of device failures seen. The lower operating temperature of the H3TRB test should result in a significantly longer lifetime. However, more devices failed well before the one thousand hour mark indicating a different factor is a dominant cause for equiree. With both tests being held to their respective JEDEC standard, the additional humidity component is the only substantial environmental factor. Thus, it is evident that the presence of high humidity drastically reduces the time to failure of the devices in group "D1". The high humidity in the environment likely exacerbated this failure mode, as it increases the presence of mobile charges, such as Na+ and K+, for charge trapping [25,26]. As humidity penetrates the packaging, positive mobile charges attach to the passivation layer on the edge termination, enhancing the local electric field above the critical field of the insulator to create a short [9,27].

Through analyzing the electrical characteristics of the DUTs, some inferences can be made as to possible reasons why the high humidity did not cause any failures in device group "D2". The difference between the processing techniques of each manufacturer is speculated to create a passivation layer that is less susceptible to defects caused by charge trapping in high humidity environments. As the passivation layer degrades due to charge trapping, these processing techniques influence the enhancements on localized electric fields and whether dielectric breakdown occurs. Such differences include passivation material and implementation of field rings. Simulation work was conducted by R. Natarajan et al. on different passivation materials for GaN HEMT devices and found differences in the electric field distribution, thus influencing the breakdown voltage [28]. From a design perspective, increasing the number of field rings between the gate and drain of the GaN HEMT would better shield the passivation from a high localized electric field [29]. Further investigation into the device structure for device groups "D1" and "D2" is equireed.

Humidity is also expected to have changed the transfer characteristic curve for some devices in device group "D3". Unlike GaN cascode HEMTs, p-GaN are more prone to threshold voltage instability issues [19,30–32] due to their Magnesium acceptors [19,31]. Much of the reliability assessment for threshold voltage for wide-bandgap has been under a high temperature, gate bias (HTGB) test [33,34], or gate bias stress under characterization [30,32] for p-GaN HEMTs. Ultimately, performance degradation was not observed in the device group "D3".

#### **5. Conclusions**

This paper evaluates commercial GaN devices under high humidity, high temperature, and high voltage accelerated tests. Twenty-one GaN HEMTs from three manufacturers were tested at 85 ◦C, 85%, while blocking voltage at 520 V for one thousand hours. Degradation was observed in three devices. Although two manufacturers used similar device topology, all degraded devices were from one manufacturer. The degraded devices could not block voltage, but their forward current capabilities were unaffected. It is suspected that the humidity has accelerated charge trapping in the degraded devices, resulting in higher localized electric fields. It is speculated that the differences seen between device groups "D1" to "D2" are due to either a processing difference in the passivation layer or a design difference in the number of field rings. Future work includes failure analysis of the degraded devices through decapsulation to verify the failure mechanism and an investigation into the device structure of the devices.

**Author Contributions:** Conceptualization, S.B.B.; methodology, J.A.R.; data collection, J.A.R. and T.T.; formal analysis, J.A.R., T.T. and D.G.; writing—review and editing, J.A.R., T.T. and D.G.; supervision, S.B.B.; project administration, S.B.B.; funding acquisition, S.B.B. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research received no external funding.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


## *Article* **An Approach to the Design and the Interactions of a Fully Superconducting Synchronous Generator and Its Power Converter**

**Sebastian Lengsfeld 1,\*,†, Sebastian Sprunck 1,\*,† , Simon Robin Frank 2,\*,†, Marco Jung 1,3, Marc Hiller 2, Bernd Ponick <sup>4</sup> and Stefan Mersche <sup>2</sup>**


**Abstract:** The design of a fully superconducting wind power generator is influenced by several factors. Among them, a low number of pole pairs is desirable to achieve low AC losses in the superconducting stator winding, which greatly influences the cooling system design and, consecutively, the efficiency of the entire wind power plant. However, it has been identified that a low number of pole pairs in a superconducting generator tends to greatly increase its output voltage, which in turn creates challenging conditions for the necessary power electronic converter. This study highlights the interdependencies between the design of a fully superconducting 10 MW wind power generator and the corresponding design of its power electronic converter.

**Keywords:** fully superconducting generator; synchronous generator; HTS; power converter; wind energy

#### **1. Introduction**

For several years, wind power plants have shown a trend toward higher power classes [1,2]. To enable technically feasible solutions for Megawatt-scale systems, the generator needs to be designed for a low rated rotor speed and a high rated input torque. However, this design approach drastically increases the mass and the volume of the generator [3]. Because a larger generator also leads to higher investment costs, lightweight concepts such as those proposed in [4–6] have been investigated. Besides these conventional lightweight concepts, the use of superconductors is very promising, as shown in [7], because superconducting generators offer a much better power to mass ratio. To exploit the full potential of the superconductor, the generator should be fully superconducting [8], i.e., both the DC and the AC winding should be designed and manufactured with superconducting materials. However, the AC current leads to AC losses in the superconductor, which have to be handled by the cryogenic cooling system, reducing the overall efficiency of the system. Because each loss contribution at cryogenic temperatures has to be extracted through a proportionally larger power consumption of the cooling system, the generator has to be optimised for low AC losses. One of the key parameters to achieve low AC losses is the number of pole pairs, as described in Section 2.

The influence of the number of pole pairs on the cost of a generator is demonstrated in [9]. Additionally, the number of pole pairs is also coupled to the output voltage and

**Citation:** Lengsfeld, S.; Sprunck, S.; Frank, S.R.; Jung, M.; Hiller, M.; Ponick, B.; Mersche, S. An Approach to the Design and the Interactions of a Fully Superconducting Synchronous Generator and its Power Converter. *Energies* **2022**, *15*, 3751. https://doi.org/10.3390/ en15103751

Received: 26 April 2022 Accepted: 17 May 2022 Published: 19 May 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** c 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

the electric frequency of the generator, which in turn influence the design of the power electronic converter (PEC) . Its weight, size, cost and efficiency have an impact on the overall system as well. However, the consequences for the design of a PEC for fully superconducting generators with minimised AC losses have not yet been discussed in literature.

This study investigates the interdependencies between the design of a fully superconducting synchronous generator (FSSG) and its PEC in the context of the project Supra-GenSys. First, the influence of the number of pole pairs on the output voltage of the generator will be investigated analytically in Section 2. An exemplary design of a fully superconducting generator is then presented in Section 3. This design is investigated regarding the influence of the number of pole pairs and of the pole pitch on the overall design feasibility in Section 4. The influence of these design parameters on the output voltage of the generator is provided for each studied parameter. Based on the feasible generator design options, Section 5 highlights available choices for the rectifier–machine interface. Section 6 then investigates possible design concepts of PECs and their influence on the overall FSSG system design.

This study is not intended to provide a complete design method for FSSGs but to enable an understanding of the challenges and available options for the interface between an FSSG and its PEC.

#### **2. Dependencies and System Design Conflicts**

One of the key aspects regarding the design of superconducting generators is the minimisation of the AC losses occurring inside their superconducting AC winding. Together with the conductive heat flow from the environment through the electrical connections and into the superconducting winding they form the major part of the heat that has to be extracted by the cryogenic cooling system. The higher these losses are, the larger (more powerful) the cooling system has to be designed and the higher is its power consumption, lowering the overall efficiency of the system. A rough estimation for the AC losses in High Temperature Superconductor (HTS) tapes *P*AC was introduced in ([10], p. 21) and [11] and can be expressed with

$$P\_{\rm AC} = B\_{\rm t} \cdot f\_1 \cdot d \cdot l\_{\rm tape} \cdot l\_{\rm c} \tag{1}$$

where *B*<sup>t</sup> is the tangential flux density that the HTS tape is exposed to, *f*<sup>1</sup> is the frequency of the AC current of the generator, *d* is the width of the HTS tape, *l*tape is the effective length of the HTS tape and *I*c is the critical current of the HTS tape. With a lower operating temperature, the critical current of the HTS tape increases, but at the same time the electrical power required for the cryogenic cooling system increases as well. Therefore, an operating temperature of 65 K for the armature winding is selected as a tradeoff between a high critical current and a low cryogenic cooling power. The field winding is only driven by DC current; hence, a lower operating temperature of 30 K becomes feasible.

This equation was developed in ([10], p. 21) as an estimate of the AC losses and is only valid for coil currents close to the critical current. This condition is observed for all investigations presented in this study.

In other applications, e.g., distribution grids, superconductors are often used to increase the current handling capability compared to conventional copper or aluminium wires in limited spaces. Based on these applications, it might therefore be expected to use high coil currents in FSSGs as well. However, one possibility to minimise AC losses in HTS tapes that follows (1) is the reduction in the width of the tape *d*. Because HTS tapes greatly impact the overall investment costs for a FSSG, a tape width of *d* = 2 mm was selected, providing a critical current of *I*<sup>c</sup> = 52 A. This tape width is currently the most narrow one available.

A second approach to minimise AC losses is the electric frequency *f*1, which—for a synchronous generator—is directly coupled to the rotor speed *n* through the number of pole pairs *p*:

$$f\_1 = n \cdot p \; . \tag{2}$$

Combining (1) and (2) to (3) clearly shows the dependency of the HTS tape AC losses *P*AC on the number of pole pairs *p*:

$$P\_{\rm AC} = B\_{\rm t} \cdot n \cdot p \cdot d \cdot l\_{\rm tape} \cdot I\_{\rm c} \quad . \tag{3}$$

This equation also shows the dependency of the AC losses on the tangential flux density *B*t and the effective HTS tape length *l*tape, which in turn are coupled to the power density of the generator. Apart from the AC losses, the number of coils of the armature winding is coupled to the number of pole pairs as well. Each coil has two coil sides which need to be placed in slots. A common description for this physical placement is the number of slots per pole and per phase

$$q = \frac{Z\_1}{2 \cdot p \cdot m} \quad \text{\textsuperscript{1}} \tag{4}$$

which is coupled to the chosen winding scheme. *Z*<sup>1</sup> is the number of slots and *m* is the number of phases. The armature coils per phase can be connected in series, in parallel or in a series–parallel combination, as long as all coils are used. For a fixed number of turns per coil, a series connection increases the voltage between the phase contacts whereas a parallel connection increases the phase current. These properties have to be handled by the PEC and need to be known before it is designed. They can be identified through the apparent power *S*<sup>1</sup> of the generator according to

$$S\_1 = \mathfrak{Z} \cdot I\_1 \cdot \mathcal{U}\_1 \tag{5}$$

where *I*<sup>1</sup> and *U*<sup>1</sup> are the RMS phase current and the RMS phase voltage at the terminals of the generator, respectively, assuming a star connection of *m* = 3 phases. The internal connection of the coils inside the armature winding can be described through the number of parallel branches per phase *a*. Through this number, the phase current for the PEC is given as

$$I\_1 = I\_{\text{coil}} \cdot a \; . \tag{6}$$

Expressing the apparent power *S*<sup>1</sup> of the generator in (5) through the real power *P*<sup>1</sup> and the power factor cos *ϕ* allows the calculation of the phase voltage according to

$$dI\_1 = \frac{S\_1}{3 \cdot I\_{\text{coil}} \cdot a} = \frac{P\_1}{3 \cdot \cos \, \varphi \cdot I\_{\text{coil}} \cdot a} \,\, . \tag{7}$$

Equation (7) demonstrates the strong dependency of the phase voltage *U*<sup>1</sup> on the number of parallel branches *a*, because *U*<sup>1</sup> ∝ <sup>1</sup> *<sup>a</sup>* . For a power rating in the MW range and a coil current of *I*coil ≈ *I*<sup>c</sup> = 52 A, large phase voltages *U*<sup>1</sup> have to be expected even without a series connection of the coils inside the armature winding. Although a suitable PEC could theoretically be designed, practical issues such as component properties and device costs usually aim for a more balanced distribution of voltage and current load for a PEC, which in this case requires the parallel connection of the FSSG coils.

However, the possibility to connect coils in parallel is limited by the number of pole pairs. By selecting *q* = 1 in (4) and choosing a single-layer winding, the number of parallel branches *a* cannot to be higher then the number of pole pairs *p*, which in this case defines the number of connectable coils per phase. Combined with (3), this behaviour presents a conflict between the design of the PEC and the minimisation of AC losses.

After presenting an exemplary FSSG design in Section 3, the following sections will therefore explore design options both for the FSSG and the PEC to find suitable compromises between these design goals.

#### **3. Design of a Fully Superconducting Synchronous Generator (FSSG)**

This section will introduce the basic design of an FSSG to provide an example for armature and field winding made from HTS tapes, which is used to demonstrate the design conflict mentioned above.

#### *3.1. Basic Design Constraints of a 10 MW FSSG for Wind Power Plants*

The target application requires a rated output power of *P*<sup>N</sup> = 10 MW, a rated input torque approximately of *T*<sup>N</sup> = 10 MN m and a rated rotor speed of *n*<sup>N</sup> = 10 min<sup>−</sup>1. The system design has to enable a high efficiency, a low mass to power ratio and feasible capital expenditures (CAPEX). A sectional model of the generator design is shown in Figure 1.

**Figure 1.** Generator model with *<sup>q</sup>* <sup>=</sup> <sup>1</sup> <sup>2</sup> for FEM calculations.

#### *3.2. Armature Winding*

The armature winding carries AC current and, therefore, its design requires different measures to reduce the AC losses. It uses a star configuration presented in [12], which distributes six coils into each slot with the field lines, where each coil is composed of 50 turns of HTS tape. This concept uses narrow HTS tapes with a width of *d* = 2 mm, enabling low AC losses according to (1) but having a low critical current of *I*<sup>c</sup> = 52 A at a temperature of 65 K. However, the individual coils of the star configuration are connected in series, because otherwise unsymmetrical current distributions must be expected.

In the presented example, the star configuration will be used in a concentrated winding (see Figure 1). This approach enables small winding heads, which will simplify the manufacturing process and reduce the danger of accidental damage to the narrow, sensitive HTS tape during manufacturing. In common FSSG designs, an air gap winding is often preferred [2,13], but by using a slot-based winding, the field penetration of the coils can be significantly reduced and much better operation conditions of the coils and lower losses can be achieved [12]. Due to the selected winding scheme, the number of parallel branches *a* cannot be higher than half the number of pole pairs *p* (8). The winding is covered by a 25 mm thick, multi-layered cryostat.

$$a\_{\text{max}} = \frac{p}{2} \tag{8}$$

#### *3.3. Field Winding*

The field winding is distributed in small slots and its coils are designed as racetrack coils. Similar to the armature winding, it uses a cryostat with 25 mm thickness as well, but it is operated at a lower temperature of *T* = 30 K. To achieve an air gap flux density of *B* ≈ 2 T, the rotor coils have 170 turns, each using an HTS tape with a width of *d* = 4 mm.

#### **4. Parameter Studies for an FSSG**

As described in Section 2, the number of pole pairs *p* influences both the AC losses inside the HTS tape and the phase voltage at the terminals of the generator. To find a feasible range for the number of pole pairs, a parameter study was performed (Section 4.1), investigating its impact on the design of the FSSG.

For this investigation, a generator design based on the constraints and design rules of Section 3 is varied. These variants are each parameterised analytically and then modelled and simulated in FEMAG-DC. The simulation is used to validate the targeted output torque and to acquire the phase inductance, power factor, output voltages and the flux density distribution for the HTS coils. These results, especially the flux density, are then used to estimate the AC losses according to (1).

Beside the number of pole pairs, the power density is a major design parameter with an impact to the AC losses and the PEC. Due to the fixed number of turns per coil and coil current, it is mainly defined by the pole pitch. Hence, a second parameter study investigates the effects of varying pole pitches (Section 4.2).

All parameter studies consider the target values and design principles described in Section 3. The study regarding the influence of varying pole pair numbers assumed a fixed pole pitch of 350 mm whereas the following pole pitch investigation assumed a fixed number of pole pairs of *p* = 35.

#### *4.1. Parameter Study 1: Variation of the Number of Pole Pairs*

Figure 2 shows a linear, positively coupled relation between the inner diameter of the stator and the number of pole pairs, whereas the axial stack length of the iron sheets decreases with higher number of pole pairs. These changes in turn influence the iron mass and the required HTS tape length.

Even though a lower number of pole pairs reduces the diameter of the generator, the corresponding increase in its axial length has a significant impact on its mass and on the required amount of HTS tape. In contrast, a design with a higher number of pole pairs will result in a shorter, more lightweight generator with much lower demand of HTS tape length. On the other hand, the AC losses are increasing with the number of pole pairs, which increases the energy demand of the cryogenic cooling system significantly.

Figure 3 shows the dependency of the phase voltage, the phase inductance and the power factor with a changing number of pole pairs. The number of pole pairs has no impact on the power factor, because the winding and thus the field distribution are not affected. A higher number of pole pairs enables a higher number of parallel branches and, therefore, a lower output voltage according to (7) and (8). The number of parallel branches together with the change of the HTS tape length results in the shown behaviour of the inductance, which is also the reason for the small differences between the interpolated curve and the calculated values of the inductances.

**Figure 2.** Dependency of the AC losses, the iron mass, the inner diameter, the axial length and the total HTS tape length on the number of pole pairs.

**Figure 3.** Dependency of the phase voltage, the power factor and the inductance on the number of pole pairs.

The results of this parameter study can be summarised to the basic design rule: A smaller number of pole pairs has a positive impact on the AC losses in an FSSG but in turn requires an increase in the total iron core mass and HTS tape length. Therefore, a decreasing number of pole pairs results in a higher material cost for the generator.

#### *4.2. Parameter Study 2: Variation of the Pole Pitch*

The previous investigation showed that the axial length of the generator greatly influences its mass, and, consecutively, its material cost. It was therefore interesting to investigate design methods that could counter this mass increase, e.g., by choosing a higher bore diameter, which in turn changes the pole pitch. A larger pole pitch will have a negative impact on the iron losses but can enable more desirable machine lengths to reduce the mass and the HTS tape length.

Figure 4 shows the properties of the generator for varying pole pitches. Because the number of pole pairs is fixed for this part of the parameter study, a reduced pole pitch results in a smaller diameter and a larger active length. Hence, a smaller pole pitch enables lower total iron losses, but the larger active length of such a machine requires more HTS tape and increases the AC losses inside the superconductor.

The generator output voltage, the phase inductance and the power factor are shown in Figure 5. For larger pole pitches, neither the iron mass, the output voltage, the power factor nor the phase inductance decrease monotonously but exhibit extrema between pole pitches of 350 to 400 mm. The output voltage is inversely coupled to the power factor as described in (7), which in turn is influenced by the phase inductance that is affected by the saturation of the iron sheets.

#### *4.3. Summary of Parameter Studies*

Overall, the study regarding the influence of the pole pitch suggests an optimal value between 300 and 400 mm for the investigated FSSG concept. However, choosing the number of pole pairs is a tradeoff between CAPEX, generator mass, size and efficiency.

A smaller number of pole pair numbers reduces the total losses of the FSSG but results in heavier, longer machine designs that require more HTS tape. At the same time, lower pole pairs create higher generator output voltages of several kV with relatively low phase currents of 52 A. Within the framework of the SupraGenSys project, it was found that the decision for a specific number of pole pairs cannot be made without investigating the

power rectifier as well. Therefore, the FSSG design has to go hand in hand with the design of the PEC.

**Figure 4.** Dependency of the AC losses, the iron mass, the inner diameter, the axial length and the total HTS tape length on the pole pitch.

**Figure 5.** Dependency of the phase voltage, the power factor and the inductance on the pole pitches.

#### **5. Design Options for the Rectifier–Machine Interface**

As described in Section 2, the RMS phase voltage *U*<sup>1</sup> of a synchronous generator can be calculated according to (7). Depending on the topology of the PEC, either the peak phase voltage or the peak phase-to-phase voltage define the maximum voltage that power semiconductors inside a power rectifier are exposed to. Ignoring overvoltage events and observing (8) for the investigated FSSG concept, these peak values calculate according to (9) and (10), respectively.

$$\hat{u}\_1 = \sqrt{2} \cdot U\_1 = \frac{\sqrt{2}}{3} \cdot \frac{P\_1}{\cos \, \varphi \cdot I\_{\text{coil}} \cdot a} = \frac{2 \cdot \sqrt{2}}{3} \cdot \frac{P\_1}{\cos \, \varphi \cdot I\_{\text{coil}} \cdot p} \tag{9}$$

$$
\hat{\mu}\_{\text{phase-phase}} = \sqrt{3} \cdot \hat{\mu}\_1 = \frac{2 \cdot \sqrt{2}}{\sqrt{3}} \cdot \frac{P\_1}{\cos \varphi \cdot I\_{\text{coil}} \cdot p} \tag{10}
$$

By applying a sweep of the number of pole pairs *p* to (10) with an assumed power factor of cos *ϕ* = 0.85, the respective voltages displayed in the bottom-left graph of Figure 6 can be calculated. These calculated peak values are in good agreement with the simulated RMS values presented in Figure 3.

**Figure 6.** Interdependencies between the power electronic rectifier and the generator design. **Top**: Non-complete survey of available power IGBT modules (**left**) and their working voltage capabilities (**right**) with an assumed safety margin of 40%. **Bottom**: Peak phase-to-phase voltages for the investigated generator concepts (**left**) and the possible segmentation options for each concept (**right**). A combination of these investigations, marked by the solid, dashed and dotted lines in the bottomright graph allows the identification of technically and economically feasible generator/rectifier combination candidates.

These peak voltages define the maximum voltage stress that the PEC has to endure when connected to the generator. The voltage stress for individual power semiconductor devices inside the PEC can be reduced, which will be addressed in Section 6. A noncomplete market survey of available IGBT power semiconductors that focuses on the available *range* of devices for different breakdown voltage classes is presented in the topleft graph of Figure 6. This survey does not include SiC devices, as commercial products of that technology are not available above breakdown voltages of 3.3 kV. Test setups with experimental SiC devices with breakdown voltages of 6.5 kV, 10 kV and 15 kV have been reported in [14–18] but are not yet commercially available.

From the perspective of the PEC, it is preferable to use lower-voltage power semiconductors, as these devices enable the use of higher switching frequencies and therefore the design of more compact and lightweight passive devices. However, these lower-voltage devices require lower phase-to-phase voltages at the terminals of the FSSG, which is only possible if the generator is constructed with a larger number of pole pairs *p* (see (9)). This in turn would increase the electrical frequency (2) and hence the AC losses inside the HTS tape (3). It is therefore necessary to find a compromise between a lower-voltage, compact, suitably dimensioned rectifier and a higher-voltage, low pole pair, low AC loss FSSG concept.

The following subsections will highlight the respective design possibilities and their consequences for the machine–rectifier interface.

#### *5.1. Rectifier-Side Possibilities*

The breakdown voltage ratings shown in the top-left graph of Figure 6 must not be confused with the actual working voltage of these power semiconductor devices. Influences such as turn-off overvoltages, background radiation ruggedness and lifetime optimisation require a safety margin applied to these values, often in the range of 30% to 50%. In turn, these devices can only be operated at about 50% to 70% of their rated voltage. For example, operation of a 1.7 kV device at 60% of its breakdown voltage results in a working voltage of 1020 V, which is a common application, for e.g., contemporary PV inverters [19–21]. By applying this safety margin to each surveyed device, we receive the top-right graph of Figure 6.

This enables the outlining of possible application areas for single power semiconductors, i.e., topologies without a series or parallel connection of identical semiconductors (see Section 6), as indicated by black solid lines. The right-hand and upper envelopes for each device are "hard" borders in the sense that an application outside of these boundaries would exceed the rated current or voltage handling capabilities of these devices, respectively. The lower envelopes for each voltage class are defined by the upper envelope of the next lower voltage class devices. These lower envelopes are "soft" borders, as it is very possible to use, e.g., a 6.5 kV device at a working voltage of 2 kV or even below. However, it is unusual to do so because devices of lower voltage classes often offer a better performance at such relatively low voltages and are usually less expensive than higher-voltage devices. No left-hand side envelope is shown in the top-right graph of Figure 6, as it is also possible to operate each device well below its rated current, though devices with lower current ratings are preferable in this case.

#### *5.2. Machine-Side Possibilities*

Each generator concept in the bottom-left graph of Figure 6 provides a number of three-phase systems *s*Gen that is—for the investigated FSSG concept presented in Section 3 dependent on half the number of pole pairs *p* of the generator:

$$s\_{\text{Gen}} = \frac{p}{2} \tag{11}$$

Because a series connection of the corresponding phases of these branches would further increase the voltage at the terminals of the generator, the following approach will not cover this possibility.

To use all three-phase systems for power conversion, each of them has to be connected to a PEC. However, from the PEC point of view, the combination of rather high voltages of several kV (see Figure 3) and a rather low phase current of 52 A is quite an unusual combination which can certainly be managed with available power semiconductors, but those high-voltage devices are usually designed for much higher currents so that their utilisation factor is very poor. Through parallelisation of the corresponding phases of the available three-phase systems, it is possible to combine the individual phase currents so that the power semiconductors inside the PEC are utilised better. However, not all of the branches have to be connected to the *same* PEC: as long as all branches are used, it is possible to connect a subset of the available branches *s*Gen to one PEC and the remaining subset(s) to other, identical PECs. If *n*PEC is the number of individual PECs and *s*PEC is the number of parallel three-phase systems per PEC, then this requirement can be expressed through

$$m\_{\rm REC} \cdot s\_{\rm REC} \stackrel{!}{=} s\_{\rm Gen} = \frac{p}{2} \; . \tag{12}$$

At the same time, the PEC phase current *I*PEC is given by

$$I\_{\rm PEC} = \text{s}\_{\rmPEC} \cdot I\_{\rm coil} \cdot \text{.} \tag{13}$$

The bottom-right graph in Figure 6 displays these possible machine/rectifier segmentation options, where each "row" corresponds to the pole pair concept with the same voltage in the bottom-left graph. The possible options per concept row are marked through different symbols. For example, a machine with *p* = 20 pole pairs provides *s*Gen = 10 available three-phase systems according to (12). With *I*coil = 52 A and (13), the electrical power of such a generator can be segmented in four different ways, as shown in Table 1. For better visualisation, not all available options for all investigated pole pairs are shown in the bottom-right graph of Figure 6.


**Table 1.** Exemplary options for the electric segmentation of a machine with *p* = 20, *s*Gen = 10 and *I*coil = 52 A.

With these segmentation options, it is much easier to design a technically and economically feasible rectifier, as its phase current *I*PEC can be matched to the current handling capabilities of available power semiconductors more easily, as can be seen when comparing the top-right and the bottom-right graphs of Figure 6. Additionally, a segmentation of the output power of the generator to several rectifiers increases the system reliability by reducing the impact of single device failures and introduces the possibility to control the torque ripple of the generator within tighter limits.

#### **6. Rectifier Concepts and Topologies for FSSGs**

State-of-the-art PECs can be categorised into two main groups:


Conventional converters tend to have a comparably low degree of complexity and fewer components than modular converters. Two examples of this group that will be discussed in Section 6.1 are the B6 topology, consisting of six power semiconductors with a single DC capacitor, and the ANPC topology, consisting of 18 power semiconductors and a split DC capacitor.

Cell-based converters, which are discussed in Section 6.2, tend to be more flexible and often offer additional benefits such as redundancy or improved power quality, but usually require more components and a more complex control system. They present the possibility to use lower-voltage semiconductors with current ratings that fit better to the relatively low FSSG phase currents, produce lower losses and can be operated at higher switching frequencies [22]. Moreover, the increased number of voltage levels results in a better approximation of the sinusoidal AC voltages and therefore lower harmonics in the generator phase currents. Depending on the ratio of load current and harmonic content, this in turn can lead to lower AC losses in the HTS tape as well and opens possibilities to reduce the size of filters or to omit them entirely. Furthermore, assuming the same semiconductor technology, the resulting voltage slopes d*u*/d*t* can be reduced, resulting in lower insulation stress.

#### *6.1. Conventional Converter Concepts*

Suitable conventional converter concepts for the above-mentioned compromise for an FSSG can be identified directly through the bottom-right graph of Figure 6. By transferring the envelopes of the top-right graph of Figure 6 to its bottom-right graph, we can visually select the machine concepts that can be addressed with the envelope that corresponds to a given rectifier concept. The steps in the envelopes correspond to the different semiconductor voltage class applications surveyed in the upper graphs of Figure 6. The marked machine options that fall below and to the left of the respective envelopes are candidates that make further investigations viable.

#### 6.1.1. Two-Level Active Rectifiers

A standard B6 bridge rectifier (Figure 7a) requires that each individual semiconductor can endure the maximum phase-to-phase voltage on its own. The solid black envelope in the bottom-right graph of Figure 6 corresponds to this requirement, leading to the conclusion that this approach would not provide any viable options even for a generator with *p* = 60 pole pairs, as the minimum possible voltage for this design is well above the operational voltage of individual 6.5 kV power semiconductor modules.

However, power semiconductors could be connected in series to distribute the voltage load of the generator to multiple devices, yet this distribution also has to be ensured during each switching process. The additional effort required to secure this voltage balancing both in the blocking state as well as during switching transients cannot be neglected and is rarely used in practical applications, because multi-level topologies in this case often offer a better alternative. It is therefore not advisable to use a B6 topology, even a series-connected one, for the investigated FSSG concepts.

#### 6.1.2. Three-Level Active Rectifiers

Several multi-level topologies, such as an ANPC shown in Figure 7b, offer an even voltage load between the individual semiconductors both during static and switching transient operation. The third voltage level also allows a better approximation of ideal sine waves, reducing the need for filter equipment. Rectifier concepts using multi-level topologies could enable the use of lower-voltage devices and/or the use of machine concepts with a lower number of pole pairs.

The dashed black envelope in the bottom-right graph of Figure 6 shows the application limit of 3-level ANPC rectifiers for FSSG wind turbines. Due to the high voltages of the generator, 6.5 kV devices are required for this topology, enabling a match with concepts with at least *p* ≥ 50 ... 52 pole pairs. According to (3), such designs are subjected to relatively large AC losses. Additionally, the high-voltage devices are limited to switching frequencies of a few hundred Hz to a few kHz at best. This topology provides a technical possibility to solve the interface problem, but its performance will certainly not be satisfactory—neither from the perspective of the FSSG nor from the perspective of the PEC.

**Figure 7.** Example topologies for active rectifiers. (**a**) Standard B6, (**b**) 3-Level ANPC as an example of multi-level topologies.

Higher-level topologies can extend the voltage load capabilities of a PEC, but at the same time increase the complexity with little benefit regarding size, weight and efficiency of the PEC. For example, a 5-Level ANPC can in theory bear twice the voltage load of a 3-Level ANPC, but this approach would still require 6.5 kV devices to enable FSSG concepts with phase voltages below approximately 16 kV (see the dotted black line in the bottom-right graph of Figure 6), corresponding to *p* > 24 pole pairs. Devices with voltage ratings of 4.5 kV and 3.3 kV can also be used but only for FSSGs with higher numbers of pole pairs.

Additionally, higher-level topologies require non-negligible effort to balance the additional capacitors, which increases with the number of levels. It is therefore questionable if these conventional PEC design approaches can provide desirable effort to performance ratios for the investigated application.

#### *6.2. Cell-Based Multi-Level Converters*

Due to the specific requirements of the medium voltage FSSG and the above described difficulties resulting for a B6 or ANPC converter, multi-level topologies can present an interesting alternative. In this section, several multi-cell converters are therefore discussed in terms of their suitability for use with FSSGs.

Two scenarios are considered: one in which the generator is connected to a medium voltage (MV) AC grid through an inverter and a second one in which it is connected to a MV DC grid via a galvanically isolated DC/DC converter. For both scenarios, the three-phase AC voltage of the generator is first rectified using *n*PEC rectifiers. These two scenarios are pictured in Figure 8.

The common DC voltage link at the rectifier output provides a certain flexibility, because the same rectifier unit can be used for both scenarios. Therefore, only topologies which have a DC voltage link are considered here. These topologies can be constructed with single IGBTs or SiC-MOSFETs and provide a lower complexity and/or component count compared to topologies that require bidirectional blocking capabilities, e.g., current source inverters that require an additional diode [23,24].

Possible topologies for the rectifier unit are presented in Sections 6.2.1–6.2.4. A converter concept based on cascaded power cells is then investigated for the use with the FSSG in Section 6.2.5, followed by proposals for an AC side converter in Section 6.2.6.

**Figure 8.** Proposed converter concept with a common DC voltage link for a superconducting generator with *s*Gen three-phase systems. For the AC grid connection, a galvanic isolation is also to be ensured, which can be realised, e.g., with a grid-side transformer on system-level or, depending on the topology, by several medium frequency (MF) transformers on cell level.

#### 6.2.1. Flying Capacitor Converter

The flying capacitor (FC) converter was first introduced in [25]. An example of its cell-like structure is pictured for one phase of a 5-Level FC in Figure 9a. For *n* levels it consists of *n* − 2 flying capacitors per phase and one common DC link capacitor. The flying capacitors have to be pre-charged before operation and their voltages have to be held at nominal voltage during operation, which results in a much higher modulation and balancing effort compared to a B6 converter and even in a higher effort compared to NPC converters. On the other hand, this topology limits the maximum voltage across each power semiconductor to the (*n* − 1)th part of the DC link voltage. Thus, in comparison to topologies with a lower number of levels, semiconductors with a significantly lower blocking voltage can be used, which in turn enables higher switching frequencies.

**Figure 9.** (**a**) 5-Level Flying Capacitor (FC) Converter. (**b**) 5-Level Stacked-Multi-Cell Converter (SMC).

The main disadvantage of this topology is the requirement of relatively expensive and bulky capacitors. This is especially problematic when the DC voltage is increased, because the stored energy in one capacitor grows with the square of the applied voltage, which then translates to larger capacitors. By using fast switching semiconductors and new operation principles, e.g., Quasi-Two-Level operation, the size of the capacitors can be reduced significantly, making this topology interesting for future MV applications [26].

#### 6.2.2. Stacked-Multi-Cell Converter

The stacked-multi-cell converter (SMC), introduced in [27], is a further development of the FC topology. A number of *N* FC converters are stacked on top of each other, resulting in a lower maximum voltage for each FC and therefore smaller and less expensive capacitors. Figure 9b shows a 5-Level-SMC (*N* = 2) and the resulting relative voltages of the FCs.

However, compared to the FC topology, the same number of semiconductors is required for the same number of voltage levels and the blocking voltage of the outer transistors *T*o has to be twice as high (compare Figure 9). Because the required blocking voltage of the inner transistors *T*<sup>i</sup> is only half the required blocking voltage of the outer transistors *T*o, each outer transistor can be theoretically replaced by a series connection of two transistors, so that the blocking voltage of all semiconductors is the same.

Several proposals can be found in literature to further improve this kind of converter, e.g., in [28] by decreasing the number of required voltage sources or in [29] by adding four low-frequency switches that are switched only twice per fundamental period to double the RMS value of the AC voltage and the number of voltage levels for the same DC link voltage.

#### 6.2.3. Modular Multi-Level Converter

The modular multi-level converter (MMC), pictured in Figure 10, is known from highvoltage direct current (HVDC) electric power conversion applications. However, it can also be used for MV applications. The basic topology that converts a DC voltage to a three-phase AC voltage is introduced in [30] and consists of two converter arms for each of the three phases. One arm itself is realised by a series connection of several cells. Each cell consists of a capacitor which can either be switched into the respective arm voltage or be bypassed using a half-bridge circuit. Alternatively, a full bridge circuit can be used, allowing for the insertion of a negative capacitor voltage as well. Due to the identical structure of the cells, the whole concept is highly modular and high voltages as well as a high number of voltage levels can be reached. Therefore, this topology enables low harmonics at the cost of a larger number of semiconductors. Hence, compared to the previously presented topologies, it could theoretically further reduce the HTS AC losses.

**Figure 10.** Topology of the Modular Multi-Level Converter (MMC) and the exemplary circuit diagram of one cell, configured as full bridge circuit.

In future scenarios where the wind generator could be either directly connected to an MV AC or to an MV DC offshore grid, the converter has to ensure a galvanic isolation between the generator and the grid. Without such an isolation, the FSSG winding would require extensive isolation strength. Assuming a grounded stator and a symmetrical DC grid, this isolation would need to be designed for voltages in the range of the amplitude of the AC grid phase voltage or half of the DC grid voltage, respectively. All topologies mentioned above present no intrinsic galvanic isolation between their input and output. When using these topologies, the isolation has to be guaranteed on system level, e.g., with a transformer operated at grid frequency.

#### 6.2.4. Cascaded Power Cells

Using a topology based on the cascaded H-bridge (CHB) converter introduced in [31] allows for galvanic isolation at cell level. On the generator AC side, *n*Cell,ph H-bridges are connected in series to address high generator phase voltages even with low-voltage semiconductors. At the output of each H-bridge, a highly efficient DC/DC converter stage with a very high galvanic isolation is connected. The DC outputs can then again be connected in series to reach the required DC link or DC grid voltage.

Its high modularity makes this topology very interesting for a superconducting wind generator converter. It offers the possibility to use the same converter concept for different generator designs by simply matching the number of cells to the respective voltage requirements. Theoretically, a very high generator phase voltage can be realised, limited only by practical issues such as isolation clearances. Figure 11 shows the topology for one three-phase system. The combination of an H-bridge and a DC/DC converter is called "power cell" in the following investigation.

**Figure 11.** Cascaded power cell topology for one generator three-phase system.

In this example, all DC terminals are connected in series to enable the direct connection to a future MVDC grid. A proposal for the design of a single power cell is pictured in Figure 12. On the AC side, the H-bridge rectifies the single-phase AC voltage of the generator. Because very low electric frequencies in the range of a few Hz (see (2)) and rather large phase inductances in the range of several mH are expected for the FSSG (see Figure 3), it is possible to realise this input rectifier stage with commercial IGBTs.

**Figure 12.** Possible design for a single power cell, consisting of an H-bridge rectifier and an isolated DAB.

The DC/DC converter can be realised with different topologies, e.g., with a resonant converter such as an LLC or a CLLC converter or non-resonant options such as a dual active bridge (DAB). A single-phase and a three-phase DAB are proposed in [32]. The single-phase DAB is compared with an LLC converter for a fixed, high conversion ratio in [33], whereas [34] compares a single-phase DAB with an LLC and a CLLC converter for a 1:1 conversion ratio. Hereinafter, a single-phase DAB is assumed for reasons of simplification. However, other topologies might show advantages compared to the DAB for that specific application and are worth investigating further.

The isolation in a DAB is provided using a medium frequency (MF) transformer and the semiconductors are usually switched with several tens of kHz. Due to lower switching losses compared to Si-IGBTs, SiC-MOSFETs are well suited for this task.

One challenge regarding this topology is the non-constant power input of one power cell, because it is a single-phase converter. If a constant power flow through the DAB is desired, the input DC link capacitor has to buffer the difference between the AC generator power and the constant power through the DAB, resulting in a reactive power at the input with double the electrical generator frequency *f*1. It is possible to use the capacitors on the primary and secondary side of the power cell to buffer the AC power ripple with a suitable control of the DAB if they are dimensioned accordingly. Alternatively, the power transfer through the DAB could be modulated to follow the single-phase AC power of the generator. A constant total DC power flow at the converter output is then realised by paralleling the DC outputs of the converters of all three generator phases.

Further challenges for this approach are the high isolation strength required for the MF transformers as well as the demand of high reliability in terms of isolation failure. With *n*Cell,tot MF transformers, each transformer must provide a failure rate that is lower by a factor of 1/*n*Cell,tot compared to a topology with one central transformer to reach the same overall system failure rate. Despite these challenges, the proposed topology concept should be investigated further due to its high degree of modularity and its flexibility. One possible adaption to the FSSG application is presented in the next subsection.

#### 6.2.5. Cascaded H-Bridge Concept for the FSSG

Due to their high availability even at lower rated currents, the following investigations of the Cascaded H-bridge concept are performed for 1200 V and 1700 V semiconductor modules. According to Section 5.1 these semiconductors ensure working voltages of 720 V or 1020 V, respectively, which define the maximum DC link voltage *U*Cell,DC of each power cell. For sine-triangle modulation without overmodulation, this in turn is identical to the maximum possible AC voltage amplitude *u*ˆCell,ph,max of each power cell [35].

Because the power cells of one phase are connected in series and the phases themselves are star connected, the sum of the individual power cell AC voltage amplitudes must be equal to or higher than the amplitude value of the generator phase voltage *u*ˆ1, that is calculated with (9) and (11). The minimum number of series connected power cells can then be determined using

$$
\eta\_{\text{Cell,ph,min}} = \lceil \frac{\hat{\mu}\_1}{\hat{\mu}\_{\text{Cell,ph,max}}} \rceil \;. \tag{14}
$$

Assuming the exemplary values used in Section 5 (cos *ϕ* = 0.85, *s*Gen = 10, *I*coil = 52 A and *P*<sup>1</sup> = 10 MW), an FSSG phase voltage amplitude of *u*ˆ1 ≈ 10.67 kV is calculated. Therefore, at least 15 power cells with 1200 V semiconductors or eleven power cells with 1700 V semiconductors are to be series connected per phase. A higher amount of cells is possible and will increase tolerance against failures. In case of a failure inside a single power cell except for isolation failure of the transformer—the faulty cell could then be short circuited at the input and output, allowing the system to still operate at the nominal power. The minimum total number of power cells can be calculated using

$$
\eta\_{\text{Cell,tot}} = 3 \cdot \eta\_{\text{Cell,ph}} \cdot \frac{s\_{\text{Gen}}}{s\_{\text{PEC}}} = 3 \cdot \eta\_{\text{Cell,ph}} \cdot \eta\_{\text{PEC}} \,. \tag{15}
$$

As displayed in Table 2 for a three-phase machine with ten branches and no direct branch parallelisation, this results in 450 or 330 cells for 1200 V or 1700 V semiconductors, respectively.

To reduce the number of power cells, several three-phase systems can be parallelised directly as illustrated in Figure 13. This approach reduces the possibilities in the independent branch control but leads to a less complex converter design with higher currents per converter phase.

**Table 2.** Total number of required power cells and corresponding maximum reachable DC link voltages for a 10 MW FSSG depending on the used semiconductor voltage class and the number of parallel connected branches. The maximum reachable voltages for the options without parallel branches, marked with ∗, are purely theoretical. In practice, several DC cells or DC three-phase rectifier outputs would be paralleled for these options.


For a machine with ten three-phase systems, five parallel systems result in a converter phase current of 260 A, which is a common current rating for several commercial 1200 V and 1700 V SiC-MOSFET and Si-IGBT semiconductor modules. The minimum number of cells can then be reduced down to 90 or 66 cells for 1200 V or 1700 V semiconductors, respectively (See Table 2).

**Figure 13.** Two possible rectifier concepts. (**a**) Each branch is connected to one three-phase rectifier; therefore, 50 A modules can be used. (**b**) Direct parallelisation of five generator branches leads to a lower number of three-phase rectifiers but reduces the possibilities in the independent branch control. Here, 250 A modules can be used.

Assuming a 1:1 transfer ratio of the DAB and a series connection of all power cells on the DC side, this concept can provide a maximum total DC voltage *U*Grid,DC,max according to

$$\mathcal{U}\_{\text{Grid},\text{DC},\text{max}} = \mathcal{S} \cdot \mathcal{U}\_{\text{Cell,DC},\text{max}} \cdot \boldsymbol{\pi}\_{\text{Cell,ph}} \cdot \boldsymbol{\pi}\_{\text{PEC}} \, . \tag{16}$$

For the above mentioned exemplary FSSG, this would lead to the maximum total DC voltages displayed in Table 2. Lower total DC voltages can be reached by parallelising certain power cell outputs *U*Cell,DC, three-phase converter outputs *U*PEC,DC or by adapting the transfer ratio of the DAB. The latter can be achieved by changing the winding turns ratio of the MF transformer or by modifying the modulation of the DAB [32]. Higher voltages could be reached by increasing the number of cells per phase *n*Cell,ph. However, for all types of power cells a direct connection on the DC side to a MV DC grid with, e.g., ±25 kV is theoretically possible for the exemplary generator concept with ten branches.

The concept can be easily adapted to generators with different pole pair numbers or number of branches, respectively. Using (14), (15) and the respective cell voltage maximum possible AC amplitudes *u*ˆCell,ph,max, the necessary minimum total number of power cells for the 10 MW FSSG can be calculated. The resulting values are illustrated in Figure 14.

It is evident that the number of power cells is hardly dependent on the number of pole pairs or three-phase systems. The generator phase voltage *u*ˆ <sup>1</sup> decreases with 1/*s*Gen according to (9) and (11). At the same time, the number of three-phase converters *n*PEC increases with *s*Gen ((12) with constant *s*PEC) so that the total number of power cells stays nearly constant. The deviations result from the ceiling function in (14). For some FSSG concepts (corresponding to a certain numbers of pole pairs), not all power cell concepts are possible due to the fact that the ratio of the number of three-phase systems *s*Gen and parallel three-phase systems per converter *s*PEC would not be an integer. However, with an appropriate choice of pole pairs, this topology offers the possibility to use standard 1200 V or 1700 V semiconductors over a wide range of number of pole pairs and three-phase systems, even if an unusual combination of large phase voltage and low phase current is present.

**Figure 14.** Total number of power cells *n*Cell,tot necessary for the 10 MW FSSG depending on the number of pole pairs *p* and the semiconductor voltage and current rating. A current rating of 50 A corresponds to *s*PEC = 1 (one three-phase rectifier for each branch), 200 A to *s*PEC = 4 (one threephase rectifier for four parallelised branches) and 250 A to *s*PEC = 5 (one three-phase rectifier for five parallelised branches). A power factor of *cos*(*ϕ*) = 0.85 and a HTS current of *I*coil = 52 A are assumed as well as a semiconductor voltage utilisation of 60% and a current utilisation of 105% to handle the HTS current.

#### 6.2.6. Realising an AC Grid Connection

Besides the direct connection to a MV DC grid, the generator could also be connected to an MV AC grid. To achieve this, the power cells could be extended by an additional single-phase AC inverter at the output, which can be implemented with 1200 V or 1700 V components. The AC outputs are then connected in series to reach the grid phase voltage. Figure 15 shows an exemplary circuit that pictures the basic idea. As for the DC grid connection, not all outputs per phase need to be connected in series. It is also conceivable to parallelise several three-phase system outputs, provided that all sets are used and all subsystems are identical.

If a constant power flow over the DABs is required, this solution shows a high demand of reactive power on both sides of the converter: on the machine side with double the electrical generator frequency *f*<sup>1</sup> (2); on the grid side with double the grid frequency *f*grid. Accordingly, the required energy storage can be disadvantageous compared to other concepts or operations.

Another possibility is the use of a central DC link at the output of all DABs, combined with a single common grid inverter. Using this configuration, the output H-bridges from above are not necessary and with an appropriate series or parallel connection of the power cell DC outputs, the voltage of the central DC link can be designed to be in the same range as the AC grid voltage. One possible topology for the grid inverter could be the above mentioned MMC, but other topologies can be viable as well, depending on the grid voltage and the grid-side requirements for the inverter, e.g., fault ride through capability. Those investigations are not the subject of this study.

**Figure 15.** Proposed topology for a direct MV AC grid connection. Each power cell is extended by another H-bridge single-phase AC inverter.

In summary, the proposed multi-cell topology based on series connected power cells, each consisting of an H-bridge and a DAB, is well-suited as a rectifier and galvanic isolation unit for the FSSG application. Because it consists of low-voltage, low-current power semiconductors, it can be optimised for the low phase currents of the FSSG. Despite the challenges of the double-frequency reactive power and the high isolation and failure rate requirements on the MF transformer, this topology is worth investigating further, especially due to its high modularity, which allows for the easy adaptation to various generator designs.

#### **7. Conclusions**

To make use of the potential of superconductors in wind power generators, the design process of an FSSG has to consider the AC losses of the HTS winding. Only a few design measures enable the reduction in these losses, but they can cause conflicts with the design of corresponding PECs. This aspect has not yet been discussed in literature so far. Therefore, this study highlights the interactions between the design of an FSSG and its PEC.

The first sections discuss the general dependencies of the AC losses on the generator design. The AC loss reduction can be achieved through the use of narrow HTS tapes, which operate at very low coil currents, and by a reduction in the electric frequency and the perpendicular field strength. The frequency is influenced by the number of pole pairs whereas the perpendicular field strength is coupled to the pole pitch. Both of these design options are investigated by their respective parameter studies. The parameter optimisation leads to FSSG designs with high output voltages, low output currents and low electric frequencies which have to be handled by their PEC.

After these generator-related investigations, the following sections focused on the influence of such unusual parameter combinations on standard PEC designs. It was found that available power semiconductor modules can supply the necessary blocking voltage if multi-level topologies, e.g., an ANPC, are used. However, the current utilisation factor of these semiconductor modules would be poor due to the low phase currents. Additionally, the corresponding converter concepts tend to require higher numbers of pole pairs for the generator, which would lead to higher AC losses inside the HTS tape. Therefore, multi-cell designs are discussed in the last section as an alternative to standard PEC topologies. Among several concepts, a topology based on series connected power cells is presented, which offers practicable solutions with available power semiconductors at the cost of a larger component count and a higher system complexity.

Overall, the design of PECs for FSSGs is challenging, but there are technical solutions available. This study provides insight on how to consider the requirements of both an FSSG and its PEC and presents guidance for future designs.

**Author Contributions:** Conceptualization S.L., S.S. and S.R.F.; Data curation S.L., S.S. and S.R.F.; Formal analysis S.L., S.S. and S.R.F.; Funding acquisition B.P., M.J. and M.H.; Investigation S.L., S.S. and S.R.F.; Methodology S.L., S.S. and S.R.F.; Project administration S.L.; Resources S.L., S.S. and S.R.F.; Software S.L., S.S. and S.R.F.; Supervision M.J. and M.H.; Validation B.P., M.J., S.M. and M.H.; Visualization S.L., S.S. and S.R.F.; Writing—original draft S.L., S.S. and S.R.F.; Writing—review and editing B.P., M.J., S.M. and M.H. All authors have read and agreed to the published version of the manuscript.

**Funding:** The underlying work of this article was funded by the German Federal Ministry for Economic Affairs and Climate Action (project name "SupraGenSys", funding reference numbers 03EE3010A and 03EE3010E). The responsibility for the content of this article lies with the authors and does not necessarily reflect the opinion of the SupraGenSys project consortium.

**Conflicts of Interest:** The authors declare no conflict of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, or in the decision to publish the results.

#### **Abbreviations**

The following abbreviations are used in this manuscript:


#### **Nomenclature**


#### **References**

1. Polinder, H.; Ferreira, J.A.; Jensen, B.B.; Abrahamsen, A.B.; Atallah, K.; McMahon, R.A. Trends in Wind Turbine Generator Systems. *IEEE J. Emerg. Sel. Top. Power Electron.* **2013**, *1*, 174–185. [CrossRef]

2. Kalsi, S.S. Superconducting Wind Turbine Generator Employing MgB2 Windings Both on Rotor and Stator. *IEEE Trans. Appl. Supercond.* **2014**, *24*, 47–53. doi: [CrossRef]


## *Article* **Swiveling Magnetization for Anisotropic Magnets for Variable Flux Spoke-Type Permanent Magnet Motor Applied to Electric Vehicles**

**Yin-Hui Lee and Min-Fu Hsieh \***

Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan; yhlee.work@gmail.com

**\*** Correspondence: mfhsieh@mail.ncku.edu.tw

**Abstract:** This paper investigates the application of anisotropic low-coercive force (LCF) magnets to a novel variable-flux spoke-type permanent magnet synchronous motor (VFS-PMSM) for electrical vehicles with a wide speed range. In the VFS-PMSM, flux is regulated by swiveling the magnetization of the anisotropic LCF magnets instead of directly magnetizing or demagnetizing them. The previously proposed VFS-PMSM uses only isotropic LCF magnets for easily swiveling the magnetic pole direction, resulting in lower torque density. The challenge thus lies in the feasibility to swivel the magnetic pole direction of the anisotropic LCF magnet, and the impact of the different magnetization strengths of the anisotropic magnets on the motor performance. This paper first studies the feasibility to swivel the magnetization direction of anisotropic LCF magnets through experiments. It is confirmed that the magnetization direction can be successfully swiveled by 90 degrees with a reduced external magnetizing field. Then, two VFS-PMSM topologies and various rotor configurations are compared in terms of key performance indices to determine critical sizing factors for performance enhancement. Finite element analysis is used for simulations. In comparison with the VFS-PMSM equipped with isotropic LCF magnets, the maximum torque of the proposed topology can be improved for the same flux adjustment ability. Alternatively, the flux adjustment ability can also be enhanced by 37.43% for the same maximum torque.

**Keywords:** electric vehicles; magnetization; memory machine; variable-flux motor; permanent magnet synchronous motors

#### **1. Introduction**

Electric vehicles (EVs) have been rapidly developed in recent years due to the growing concerns about environmental protection and the demand for green transportation. Traction motors are treated as key to electric vehicle performance. Interior Permanent Magnet Synchronous Motors (IPMSM) are a mature candidate for EV tractions with their merits of high torque density and high efficiency [1,2], and therefore, they have been widely studied. Huynh et al. analyzed and compared the performances of IPMSMs and permanent-magnetassisted synchronous reluctance machines (PMa-SynRMs) on constant power speed range (CPSR) for EV applications [3]. Kim et al. studied the shape parameters of IPMSMs and improved their efficiency by about 1% [4]. However, common EVs usually face various road conditions, such as high torque for hill climbing or high speed for long-distance cruises, and the constant flux linkage contributed by permanent magnets (PMs) may limit the speed of IPMSMs [5]. Flux-weakening control is usually used to weaken the field and increase the speed range [6,7]. Inoue et al. analyzed the performance of current control and direct torque control (DTC) with flux-weakening applied and summarized their advantages and disadvantages [8]. However, weakening the flux would sacrifice part of the stator current to suppress flux and lead to extra copper loss. Additionally, motor mathematical models are often needed to calculate the current phase advance angle, and the errors are

**Citation:** Lee, Y.-H.; Hsieh, M.-F. Swiveling Magnetization for Anisotropic Magnets for Variable Flux Spoke-Type Permanent Magnet Motor Applied to Electric Vehicles. *Energies* **2022**, *15*, 3825. https:// doi.org/10.3390/en15103825

Academic Editor: Calin Iclodean

Received: 14 April 2022 Accepted: 19 May 2022 Published: 23 May 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

likely to occur under dynamic operations [9]. The motor speed can also be expanded with an auxiliary coil to accurately control rotor magnetic flux [10,11]. Some designs, such as the double excited synchronous machine [12] and the synchronous/permanent magnet hybrid AC machine [13], place the auxiliary windings and permanent magnets in series or parallel. Nevertheless, the presence of the slip rings is the main drawback of this type of motor. To mitigate the problem of slip rings, a doubly salient PM motor was proposed [14], which placed the auxiliary windings, stator windings, and PMs in the stator, resulting in the stator being prone to saturation. A motor having an auxiliary winding with a hybrid radial and axial magnetic circuit was proposed [15,16]; however, the torque and power density may likely reduce, and the power consumption and copper loss are still inevitable for weakening the field [17]. The appearance of memory motors, also known as variable flux motors (VFMs), effectively resolves the above problems [18]. In the memory motors, an impulse current can be generated by stator windings to change the magnetization state (MS) of a low coercive force (LCF) magnet to achieve the purpose of adjusting air gap flux density. The loss caused by the impulse current to change the MS of the LCF magnet is almost negligible for motors in operation [19].

Low coercive force (LCF) magnets (e.g., AlNiCo) are often used in the VFMs to reduce the impulse current needed for magnetization or demagnetization of the magnets. However, using only LCF magnets is prone to unexpected demagnetization [20]. To prevent this situation, Kato et al. [21] proposed a variable-flux flux-intensifying interior permanent magnet machine (VFI-IPMM), where demagnetization can be avoided because the d-axis current is positive at heavy load. To further enhance the torque density of the VFMs, various topologies of hybrid variable flux motors (H-VFM) combining LCF magnets and high coercive force (HCF) magnets were proposed [22,23]. The H-VFM rotor can be divided into series and parallel configurations according to the arrangements of permanent magnets. The series type of H-VFM [24] possesses a higher torque density at low speed since the flux of the HCF and LCF magnets can be combined by the series arrangement. In the series type of H-VFM, a much smaller impulse current is needed to switch the MS of the LCF magnet from flux weakening to enhancing due to the influence of the HCF magnet. Conversely, it requires a larger impulse current to switch from flux enhancing to weakening. For the parallel type of H-VFM [25], an active flux leakage bypass is established which is advantageous for flux regulation. Hua et al. compared the series and parallel types of H-VFMs and revealed that the operating point of the LCF magnet in the parallel type is unstable [26]. To have a stable operation of the LCF magnet and excellent flux regulation ability, a variable-flux permanent-magnet synchronous machine with a quasi-series magnet configuration and passive flux barrier was proposed [27,28]; however, the problem of a large magnetizing current to switch from flux enhancing to weakening is yet to be resolved. Yang et al. proposed a hybrid-magnet-circuit VFM [29–31] that combines the advantages of both types of H-VFMs mentioned above to achieve high torque density, good flux adjustment ability, and reduce magnetizing currents. However, the rotor configuration seems complex and requires more expensive HCF rare-earth magnets.

Lee et al. proposed a novel variable flux spoke-type permanent magnet motor (VFS-PMSM) [32], which combines the advantages of the series and parallel types of H-VFMs. The flux regulation can be achieved by swiveling the magnetic pole of the isotropic LCF magnet. By so doing, the flux produced by the LCF magnets is ensured to align with that produced by the HCF magnet, and therefore accidental demagnetization can be avoided. The magnetizing impulse current is also greatly reduced for switching the MS and regulating air gap flux density. However, there is still room for improvement in torque density and flux regulation ability due to the use of the weaker isotropic LCF magnets.

To simultaneously achieve the above-mentioned advantages, i.e., high torque density, excellent flux regulation ability, low demagnetization risk, low magnetizing impulse current demand, high efficiency at high speed, and expanded motor operating range, this paper proposes a novel VFS-PMSM topology combining HCF magnets and anisotropic LCF magnets, instead of the isotropic LCF magnet used in a previous study [32]. The

method of swiveling the magnetic pole of the LCF magnet [32] is adopted, which differs from the previously mentioned methods that magnetize/demagnetize the magnets in the same axis [18–31]. It should be noted that there is a significant difference in flux generated and magnetizing field required between the easy and hard axes in the anisotropic magnets. Therefore, it is generally believed that the magnetic pole of an anisotropic magnet cannot be swiveled. This is the key challenge and the major difference from the isotropic design previously reported [32]. In this paper, analyses and experiments are conducted to study the feasibility of swiveling magnetization for the anisotropic magnet applied to the VFS-PMSM. Then the torque density and flux regulation ability of the motor are investigated. Several configurations of the VFS-PMSM are compared to highlight a suitable arrangement to reduce magnetizing current while enhancing the maximum torque and flux regulation ability.

This paper is organized as follows. In Section 2, the characteristics of the proposed variable flux PM motor topologies and the previously developed VFS-PMSM are analyzed and compared. Their features are explained in detail. The feasibility of applying the anisotropic AlNiCo in the VFS-PMSM is experimentally verified in Section 3. In Section 4, the key characteristics of the proposed anisotropic VFS-PMSM with different rotor types are compared by adjusting the sizing parameters of the LCF magnets and HCF magnets. The electromagnetic characteristics of the proposed motor topologies are simulated and compared with other types of motors in Section 5, followed by Section 6 to conclude this paper.

#### **2. Variable Flux PM Motor Topologies and Proposed VFS-PMSM**

The VFS-PMSM [32], like the general series and parallel types of H-VFMs, uses both LCF magnets and HCF magnets in the rotor; however, the principal difference of this design is to use the magnetic field excited by the stator to "swivel" the magnetization vector of the LCF magnet to achieve flux regulation. When the flux density of the air gap needs to be enhanced, the impulse current produced by the stator winding generates a magnetizing field on the +d axis (phase advance is −90◦) to magnetize the LCF magnet radially. The flux of the HCF magnet is guided to the air gap and the stator through the LCF magnet. To weaken the flux density of the air gap, the impulse current generates a magnetizing field on the -d axis (phase advance is +90◦) to swivel the magnetization direction of the LCF magnet to align in the tangential direction. The flux of the HCF magnet is guided to the flux leakage bypass via the LCF magnet. The details for the magnetization of the LCF magnets can be referred to in a previous study [32]. Theoretically, the impulse current applied on the +d or −d axis will not result in an undesirable torque surge. To successfully adjust the air gap flux density of the VFS-PMSM by swiveling the magnetization vector of the LCF magnet (called the "swiveling magnetization technique" in what follows), isotropic AlNiCo was used in the previously developed VFS-PMSM [32] (called the "isotropic VFS-PMSM" in what follows). The magnetic characteristics of isotropic magnets should be the same regardless of the direction of magnetization.

To investigate the feasibility of anisotropic AlNiCo magnets for swiveling magnetization, the demagnetization curves of the isotropic and anisotropic AlNiCo magnets in different directions, as shown in Figure 1, are first measured by a B-H tracer. Both magnets are 10 mm × 10 mm × 10 mm cubes. As shown in Figure 1, the "0◦" indicates one side of the cube, and the "90◦" is the other. As can be seen, the isotropic magnet has almost identical demagnetization curves in the two directions and its remanence *Br* and maximum energy product are lower than those in the easy axis of the anisotropic magnets. It should be noted that the swiveling magnetization technique involves the magnetization of an anisotropic LCF magnet in two directions separated by 90◦ (i.e., either on the easy axis or hard axis), the arrangements of the anisotropic LCF magnet should be considered for magnetizations to regulate the flux and torque production.

**Figure 1.** B-H curve of LNGT18 (isotropic) and LNGT40 (anisotropic).

One merit of the VFMs is their air gap flux density regulation ability to improve the constant power and high-efficiency operating range. Therefore, the key index used to evaluate a VFM is the highest torque at flux enhancing state and the back electromotive force (back EMF) difference between the flux enhancing and weakening cases at a certain speed. In the enhancing state, the motor air gap flux density is maximized and in the weakening state, it is minimized. This paper proposes two topologies that apply anisotropic AlNiCo to the VFS-PMSM, as shown in Figure 2 (called the "anisotropic VFS-PMSM" in what follows). In Topology I, the easy axis of the anisotropic magnet is arranged to be aligned with the radial direction of the rotor, as shown in Figure 2b while the hard axis of the anisotropic magnet in Topology II is aligned radially (Figure 2c).

**Figure 2.** (**a**) Isotropic variable-flux spoke-type permanent magnet synchronous motor (VFS-PMSM), (**b**) Anisotropic Topology I, and (**c**) Anisotropic Topology II.

#### *2.1. Torque Generation*

The material properties and dimensions of the motor are given in Table 1. As can be seen, the difference between Topologies I, II, and the isotropic VFS-PMSM only lie in the LCF magnets used. The AlNiCo magnet (model: LNGT 18) is used for the isotropic VFS-PMSM, and the anisotropic AlNiCo magnet (LNGT 40) is for Topologies I and II. The performance of the three models in Figure 2 is compared by simulations using finite element analysis (FEA) of transient electromagnetic fields (FEA, ANSYS Maxwell). The material properties of the LCF magnets (e.g., the hysteresis loops) used in the simulations are obtained from the measurements conducted in Section 3. The material properties of the HCF magnets can be found in the database of the FEA software. Note that the two anisotropic models are only preliminary designs by directly replacing the isotropic magnets with the anisotropic magnets. As shown in Figure 3, the maximum torque produced at flux enhancing is compared between the isotropic VFS-PMSM and Topologies I and II of the anisotropic VFS-PMSM. As can be seen, the isotropic VFS-PMSM produces larger torque than the other two, and Topology II has slightly higher torque than Topology I. This seems that the application of the anisotropic magnets is not effective; however, as previously mentioned, it would not be appropriate to directly replace the isotropic magnets with anisotropic ones due to their different strengths in different directions, as indicated in Figure 1. Therefore, with slightly lower peak torque than that of the isotropic VFS-PMSM, the topology with anisotropic LCF magnets will be optimized in a later section.

**Table 1.** Motor parameters and material properties.


**Figure 3.** Maximum torque of isotropic VFS-PMSM, Topologies I and II in enhancing state obtained through Maximum Torque per Ampere (isotropic VFS-PMSM = 12.12 Nm, Topology I = 11.42 Nm, Topology II = 11.6 Nm).

#### *2.2. Flux Regulation Ability*

The flux regulation ability can be indirectly evaluated through the difference in the back EMF between the flux enhancing and weakening states. The back EMF difference *Er* is defined as:

$$E\_I = E\_+ - E\_- \tag{1}$$

where *E*<sup>+</sup> is the back EMF at flux enhancing and *E*<sup>−</sup> is that at flux weakening. Note that the air gap flux density is considered proportional to the back EMF at the same speed (assuming no saturation), and thus the back EMFs at flux enhancing and weakening represent the maximum and minimum air gap flux densities, respectively. The larger the back EMF difference is, the better the flux regulation ability is. Figure 4 shows the simulated back EMF of the isotropic VFS-PMSM, Topologies I and II at flux enhancing and weakening, and *Er* of the three cases can be obtained and expressed by *Er*\_*iso*\_*VFS*, *Er*\_*T*−*<sup>I</sup>* and *Er*\_*T*−*I I*, respectively. As shown in Figure 4, *Er*\_*T*−*I I* is the largest, and *Er*\_*T*−*<sup>I</sup>* is the smallest.

#### *2.3. Discussion*

The correlation between the LCF magnet features and the back EMF difference *Er* should be investigated. The remanence of the LCF magnets toward the radial and tangential directions (indicated in Figure 2) are considered separately here for their individual contributions to air gap flux. As shown in Table 2, the LCF magnet in Topology I has the largest radial remanence, followed by that of the isotropic VFS-PMSM and then Topology II. It seems that the remanence of the LCF magnet in the radial direction does not directly correlate to the maximum torque production. For the tangential remanence of the LCF magnet, Topology II has the highest, the isotropic VFS-PMSM is the second, and Topology I the least. From these discussions, it can be seen that *Er* and the flux regulation ability are strongly related to the tangential remanence of the LCF magnet rather than the radial one. This is a key to the arrangement of anisotropic LCF magnets for improving flux regulation ability (placing the easy axis of the LCF magnet tangentially).

**Table 2.** Radial and tangential remanence of isotropic VFS-PMSM, Topology I, and Topology II.


For torque production, from the study previously mentioned, the remanence of the LCF magnet should not be the main cause that affects the maximum torque (neither radial nor tangential). It is presumed that the HCF magnet is key to the maximum torque of the motor, and when enhanced, as mentioned, optimization will be conducted.

**Figure 4.** *Cont*.

**Figure 4.** Back EMF of (**a**) isotropic VFS-PMSM, (**b**) Topology I, and (**c**) Topology II at enhancing and weakening (*Er iso*\_*VFS* = 8.39, *Er T*−*<sup>I</sup>* = 3.18 V, *Er T*−*I I* = 12.83 V).

#### **3. Feasibility Verification of Anisotropic AlNiCo Application in VFS-PMSM**

The aforementioned VFS-PMSM topologies are studied using anisotropic AlNiCo as the LCF magnet to adjust the air gap flux density. It is generally believed that the easy axis of an anisotropic magnet should only be used for applications as a stronger field can be produced. Furthrmore, for the swiveling magnetization technique, the MS of the anisotropic LCF magnet is required to be switched between the hard axis and easy axis by an external magnetizing field. Therefore, whether the magnetization of an anisotropic magnet can be successfully swiveled should be investigated, and experiments can be conducted for validation. Moreover, the magnetizing field strength required to swivel the magnetization direction should also be tested. Then, the demagnetization curves obtained by the "swiveling magnetization technique" and the "general magnetizing method" (i.e., magnetization in the same axis) can be compared. Note that commercial finite element simulation software is not capable of simulating the swiveling magnetization technique, and thus the following experiments are planned, and the results are obtained.

The magnets to be measured are cube anisotropic AlNiCo magnets LNGT40. The measurements include:


The experimental setup is shown in Figure 5, where item "A" is the B-H tracer, item "B" is the magnetizing coil, item "C" is the magnet holder, item "D" is the magnet to be measured, and item "E" is the pickup secondary coil. The experimental steps are explained as follows.

(I) The unmagnetized magnet is placed in the B-H tracer with its easy axis aligned with the pickup coil. The external magnetizing field is slowly increased until the measurement of the initial magnetization curve in the easy axis is completed (general magnetizing method). Then, the coil current is released, and then a sufficiently large external field opposite to the previous magnetizing direction is applied and gradually reduced until the current in the magnetizing coil drops to zero to complete the measurement of the demagnetization curve in the easy axis (general magnetizing method). Then, these are all repeated for the hard axis of another piece of magnet. Moreover, from all these processes there will be two pieces of anisotropic magnets magnetized in different axes.


**Figure 5.** Experimental setup. Item "A" is the B-H tracer, item "B" is the magnetizing coil, item "C" is the magnet holder, item "D" is the magnet to be measured, and item "E" is the pickup secondary coil.

From the results obtained via the above steps, the initial magnetization curves in the easy and hard axis by the swiveling magnetization technique and the general method are presented in Figure 6. As can be observed, the swiveling magnetization technique can fully magnetize the magnet with an external magnetizing field smaller than that of the general method in the easy axis. On the hard axis, the swiveling magnetization technique can also magnetize the magnet with a slightly smaller field, as shown in Figure 6b. To show the difference between the two methods clearly, the results in Figure 6 are summarized in Table 3. The MS of the magnet can be defined as 100% when it is fully magnetized, and thus the MS can be expressed by the percentage of magnetization. As can be seen in Table 3, for the MS to achieve 100% in the easy axis, the general magnetization method requires a magnetizing field strength of 4.55 kOe, and for the swiveling method, only 3.32 kOe, which is 27% lower. The comparison in Table 3 shows the magnetizing field strengths required by the two magnetization methods for the MS to achieve 100%, 75%, and 50%. When the magnet is magnetized to 50% MS in the hard axis, the swiveling method can also save 10.4% magnetizing current compared to the general method. Note that the impulse current for magnetization and changing the MS in a VFS-PMSM is generated by its stator winding. Therefore, the smaller the magnetizing field needed, the smaller the inverter capacity required. From Figure 6 and Table 3, the swiveling magnetization technique can effectively reduce the magnetizing field required for producing an equivalent demagnetization curve to that with the general method, as shown in Figure 7. This indicates that the swiveling method can produce the same characteristics of the magnets as the general method does.

**Figure 6.** (**a**) Initial magnetization curve on the easy axis, and (**b**) initial magnetization curve on the hard axis.

**Figure 7.** Comparison of demagnetization curves by the swiveling method and the general method in easy axis and hard axis.

Note that from the previous study, the anisotropic LCF magnets with the easy axis aligning tangentially are adopted in the following analyses.

**Table 3.** Comparison of external magnetizing field strength required by the swiveling method and the general method in the easy axis and hard axis.


#### **4. Performance Comparison of Anisotropic VFS-PMSM with Different Rotor Configurations**

From the discussion in Section 2, the main factor that affects the peak torque of the VFS-PMSM at flux enhancing would be the HCF magnet. Therefore, various HCF magnet configurations in the rotor are studied, covering the flat-type, V-type, and spoke-type magnet arrangements. Their performances are compared based on the same amount of LCF magnets used in terms of maximum torque at flux enhancing, flux regulation ability, and torque ripple at maximum torque. This aims at choosing the most suitable rotor configuration for the VFS-PMSM that would produce high peak torque. Note that as previously mentioned, the LCF magnets here are anisotropic with the easy axis being aligned tangentially.

#### *4.1. Scenario I*

The first condition for comparison includes (referring to Figure 8):


The angle *θ<sup>h</sup>* for the spoke-type rotor is 36 degrees. For the V-type rotor, three angles are considered: 72, 108, and 144 degrees. The angle is 180◦ for the flat-type rotor. These rotor configurations are shown in Figure 8.

It can be seen in Figure 9 that as *θ<sup>h</sup>* increases, the current phase advance to achieve maximum torque per ampere (MTPA) also increases, which means that the proportion of reluctance torque increases. A larger *θ<sup>h</sup>* brings the HCF magnets closer to the air gap and can provide more torque. However, the maximum torque at flux enhancing decreases with the increase of *θh*. This is likely because as *θ<sup>h</sup>* increases and the thickness of the HCF magnet remains, a larger *θ<sup>h</sup>* leads to a smaller HCF magnet length *Lh*, which greatly reduces the air gap flux density. As shown in Figure 10, the torque ripple gently rises, and the flux regulation ability decreases as *θ<sup>h</sup>* increases. The flux concentration factor decreases as *θ<sup>h</sup>* increases, and the amount of flux leakage will be lower accordingly even if the flux leakage bypass is opened. Therefore, it is believed that the flux adjustment ability will be affected.

**Figure 8.** Rotor configurations with different *θh*: (**a**) *θ<sup>h</sup>* = 36◦ (spoke-type), (**b**) *θ<sup>h</sup>* = 72◦ (V-type), (**c**) *θ<sup>h</sup>* = 108◦ (V-type), (**d**) *θ<sup>h</sup>* = 144◦ (V-type), and (**e**) *θ<sup>h</sup>* = 180◦ (flat type).

**Figure 9.** Maximum torque and phase advance change with *θh*.

**Figure 10.** *Er* and torque ripple variation with *θh*.

#### *4.2. Scenario II*

From the discussion for Scenario I, it can be concluded that as *θ<sup>h</sup>* increases, the maximum torque at flux enhancing decreases. The main reason is that the amount of HCF magnets is reduced as *θ<sup>h</sup>* increases. To enhance the maximum torque, the angle *θ<sup>L</sup>* of the LCF magnet is adjusted. In the rotor of the anisotropic VFS-PMSM, the LCF magnet should be placed in a location related to the HCF magnet, as indicated in Figure 11. The reason for this arrangement is to allow the MS of the LCF magnet to be easily changed by the swiveling magnetization technique.

**Figure 11.** Schematic diagram of the low coercive force (LCF) magnet arrangement to align with the high coercive force (HCF) magnet.

In addition, the minimum width of the ribs is 0.5 mm, as shown in Figure 8d, by considering the manufacturing capability, and thus the thickness *Wh* and length *Lh* of the HCF magnet will be limited and vary with *θ<sup>L</sup>* due to the limited rotor space, rib sizes and the position constraint given in Figure 11. The simulated maximum torque at different *θ<sup>h</sup>* varying with *θ<sup>L</sup>* is shown in Figure 12, where under the limited magnet size, the torque of the V-type and flat-type increases as *θ<sup>L</sup>* decreases while that of the spoke-type hardly changes. The reason is that *Lh* of the V-type and flat-type increases as *θ<sup>L</sup>* decreases. Although this also decreases *Wh*, the HCF magnet length *Lh* appears to have a greater impact on torque production, and torque increases as *θ<sup>L</sup>* decreases. On the other hand, no matter how *θ<sup>L</sup>* changes, it has only a very minor effect on *Lh* for the spoke-type rotor, but *Wh* is greatly reduced. Therefore, the effect of the two changes (i.e., *Lh* and *Wh*) cancels each other out. Meanwhile, it can be seen from Figure 12 that even if the amount of HCF magnets for the V-type and flat-type are increased to the maximum usage limited by the ribs size between two pieces of HCF magnets, the maximum torque is still lower than that of the spoke-type rotor, whose amount of HCF magnets are the largest for the space constraint.

Torque ripple increases as *θ<sup>L</sup>* increases, as shown in Figure 13, but the maximum value does not exceed 7.5%. The spoke-type rotor has the best performance on torque ripple, which is only 4.1%. As shown in Figure 14, the flux regulation ability increases with *θ<sup>L</sup>* when *θ<sup>h</sup>* is 36◦, 72◦, and 108◦. This is because as *θ<sup>L</sup>* increases, *Wh* will increase, which will then increase the magnetic field strength of the HCF magnet, resulting in more flux passing through the LCF magnet at flux weakening. However, as shown in Figure 14, when *θ<sup>h</sup>* is 144◦ and 180◦, the flux regulation ability decreases. The reason is that the flux adjustment ability is enough to reduce the flux of the HCF magnet at flux weakening to almost zero, which makes *E*<sup>−</sup> almost zero, as shown in Figure 15. Therefore, as *E*<sup>+</sup> decreases, the flux regulation ability decreases.

**Figure 12.** Maximum torque variation with *θ<sup>h</sup>* and *θL*.

**Figure 13.** Torque ripple variations with *θ<sup>h</sup>* and *θL*.

It can be concluded from Figure 9 in Scenario I that the reluctance torque generated by changing *θ<sup>h</sup>* is not the main factor that affects the maximum torque of the anisotropic VFS-PMSM. Instead, the HCF magnet length, *Lh*, which decreases with the increase of *θh*, is the main factor affecting the maximum torque. For Scenario II, *Wh* and *Lh* are increased by changing *θ<sup>L</sup>* due to the manufacturing limitations of the ribs. Although the maximum torque of the V-shaped and the flat-type increases with the decrease of *θL*, it still cannot be larger than that of the spoke-type. As shown in Figure 14, the flux regulation ability decreases as *θ<sup>h</sup>* increases. Under the same *θh*, if *θ<sup>L</sup>* becomes smaller, the flux regulation ability will also decrease, but the torque will increase instead. Subsequent designs of the anisotropic VFS-PMSM will be based on the above results.

**Figure 14.** *Er* variation with *θ<sup>h</sup>* and *θL*.

**Figure 15.** *E*<sup>−</sup> variation with *θ<sup>h</sup>* and *θL*.

To sum up, as previously mentioned, the maximum torque and flux regulation ability (i.e., *Er*) are the two key performance indices to consider, and, therefore, *θ<sup>h</sup>* and *θ<sup>L</sup>* can be determined from Figures 12–14 for maximizing the torque and flux regulation. Note that due to the constraints explained in Figure 11, the other dimensions, i.e., *Wh* and *WL* will also be determined simultaneously. These four parameters are listed in Table 4. However, the parameters, *Lh* and *LL* have not been decided and will be discussed in Section 5.


**Table 4.** Rotor parameters of the final type of design.

#### **5. Comparison of Anisotropic and Isotropic VFS-PMSMS by Simulation**

From the comparison presented in Section 2, it is confirmed that the radial magnetic flux of the LCF magnet has a slight effect on the maximum torque of the VFS-PMSM, while the tangential magnetic flux of the LCF magnet has a great influence on the flux regulation ability; therefore, Topology II has more advantages than Topology I. From the comparison given in Section 4, the conclusion of Section 2 regarding the fact that the tangential magnetic flux of the LCF magnet has a great impact on flux regulation ability is reconfirmed; meanwhile, it is also shown that under the limited size, the spoke-type motor has better key performance such as maximum torque at flux enhancing, flux regulation ability, and torque ripple than other rotor types. Therefore, from the previous comparison, Topology II with the spoke-type rotor is chosen as the final type of design, with the rotor parameters shown in Table 4.

The reason for *Lh* and *LL* not being able to be determined in the previous stage discussed in Section 4 is that *Lh* has a divergent effect on the maximum torque (proportional) and the flux regulation *Er* (inversely proportional), as shown in Figure 16. Note that *LL* will vary with *Lh* and will not be discussed here. To highlight the strengths of the proposed design, two comparisons are made: (a) with the isotropic VFS-PMSM, and (b) with the general types of VFMs, i.e., the series and parallel types. For a fair comparison, the following criteria are considered:


**Figure 16.** Maximum torque and *Er* of the target type rotor versus *Lh*.

Based on the two principles given above, the parameters, *Lh* and *LL*, can be determined accordingly referring to the results shown in Figure 16. For example, when comparing with the isotropic VFS-PMSM, a certain *Lh* (and thus *LL*) can be chosen from Figure 16 to achieve the same maximum torque as the isotropic VFS-PMSM (Criterion I), and, therefore, the *Er* of these two motors can be directly compared. For the basis in Criterion II, it is the maximum torque to be compared.

As summarized in Table 5, with a similar *Er*, the maximum torque of the isotropic VFS-PMSM is 12.12 Nm, and that for the final type of design is 13.47, improved by 11.14%. In this condition, the rotor parameter *Lh* is 27.5 mm. For a similar maximum torque, the flux regulation ability *Er* of the final type of design is enhanced by 37.43% when *Lh* is 25.5 mm. This clearly shows the advantages of the proposed design.


**Table 5.** Comparison of maximum torque and *Er* between final type and isotropic VFS-PMSM.

In Figure 16, it can also be observed that the decrease of *Er* with respect to *Lh* is faster than the increase of the maximum torque against *Lh*. Thus, *Lh* should be carefully chosen for a target *Er* while gaining the torque as much as possible.

To make a complete comparison, the general series and parallel types of variable flux motors [25,26] are designed for the same HCF magnet usage. The stator and rotor dimensions also remain the same as that for the final type of design. From the simulation results shown in Table 6, when the flux regulation ability is similar, the maximum torque of the final type of design improves by about 7.25% compared to that of the general series type VFM. When the maximum torque is similar, the flux regulation *Er* of the final type of design is 26.84% higher than that of the general series type VFM. The general parallel type does not consider the potential risk of demagnetization, and thus the simulated maximum torque and *Er* in Table 7 are better than that of the final type of design. However, if the risk of demagnetization is considered, it will be unstable [26].

**Table 6.** Comparison of maximum torque and *Er* between final type and series type.


**Table 7.** Comparison of maximum torque and *Er* between final type and parallel type.


<sup>1</sup> Note demagnetization risk is not considered.

The proposed motor is a variable flux motor, and thus it has different torque-speed curves at different air gap flux densities between the two extreme conditions represented by *E*<sup>+</sup> and *E*−, as discussed in Section 2.2. The torque-speed and the power-speed curves of the final type of design with the flux density condition (flux enhancing) to produce the maximum torque are shown in Figure 17a. After switching to a weaker air gap flux density to produce the maximum speed (20,358 rpm), the torque-speed and output power-speed curves are shown in Figure 17b. Finally, the torque-speed curves at various air-gap flux densities can be merged to produce the maximized operating range, as shown in Figure 18. It can be seen that the final type of design has both high torque and high speed with a CPSR of 3.99 (CPSR is defined as the ratio of the maximum speed maintaining the same power as the based speed to the based speed).

**Figure 17.** Torque-speed and output power-speed curve of the final type of design that produces (**a**) maximum torque; (**b**) maximum speed.

**Figure 18.** Complete torque-speed and output power-speed curve of the final type of design.

From the studies shown above, the proposed anisotropic VFS-PMSM appears to possess more advantages in terms of maximum torque, flux adjustment ability, and the stable LCF magnet operating point compared with the isotropic VFS-PMSM and the conventional series type of VFM. Therefore, these features make the proposed design suitable for EV traction applications.

#### **6. Conclusions**

This paper has proposed a variable flux spoke-type permanent magnet synchronous motor using anisotropic AlNiCo as the LCF magnets based on the previously developed isotropic VFS-PMSM. It is confirmed through the experiments that the magnetization direction of the anisotropic AlNiCo can be successfully swiveled with a reduced external magnetizing field/current (a reduction of up to 27% to achieve full magnetization). The spoke-type rotor has been found to be the most suitable configuration for the proposed anisotropic VFS-PMSM. Finally, the comparison with other conventional variable flux motors has shown clear advantages of the proposed design in terms of flux adjustment ability, maximum torque and magnetizing current required. Compared with the general series VFM, the maximum torque of the final type of design improves by about 7.25% and the flux regulation is 26.84% higher. Therefore, it can be concluded that the proposed design is suitable to be applied as an EV traction motor. Further research will be conducted in the future to improve the maximum torque and consider the influence of rotor temperature on motor performance.

**Author Contributions:** Conceptualization, Y.-H.L. and M.-F.H.; methodology, Y.-H.L.; software, Y.-H.L.; validation, Y.-H.L. and M.-F.H.; formal analysis, Y.-H.L. and M.-F.H.; investigation, Y.-H.L. and M.-F.H.; resources, M.-F.H.; data curation, Y.-H.L.; writing—original draft preparation, Y.-H.L. and M.-F.H.; writing—review and editing, Y.-H.L. and M.-F.H.; visualization, Y.-H.L.; supervision, M.-F.H.; project administration, M.-F.H.; funding acquisition, M.-F.H. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by the Ministry of Science and Technology of Taiwan under contract 110-2221-E-006-184-MY2 and the National Space Organization under contract NSPO-S-109343.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** Not applicable.

**Acknowledgments:** The authors would like to thank Y.Z. Weng and W.D. Chen, for their assistance in the experiments. ANSYS is acknowledged for providing Maxwell, the finite element package.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


## *Article* **A Literature Review of the Control Challenges of Distributed Energy Resources Based on Microgrids (MGs): Past, Present and Future**

**Darioush Razmi and Tianguang Lu \***

Department of Electrical Engineering, Shandong University, Jinan 250061, China; darush.razmi@yahoo.com **\*** Correspondence: tlu@sdu.edu.cn

**Abstract:** Different types of distributed generation (DG) units based on renewable and non-renewable energy sources can create a local energy system in microgrids. The widespread penetration of distributed energy resources (DERs) has affected many power system issues, such as the control and operation of these networks. For the optimal operation of microgrids, optimal energy planning and management in the new space governing the distribution system requires extensive research and analysis. Getting acquainted with the latest research about the evaluation of the problems and challenges in the design of control systems plays an important role in providing a guidance map for researchers to find the recent challenges and propose new solutions. This paper tried to list the challenges of distributed generation sources for MG applications, opportunities, and solutions. These challenges are reported in hierarchical control strategies and power-sharing categories. Therefore, Model Predictive Control (MPC)-based approaches are reviewed for different recent control levels and power sharing strategies in a comprehensive and simple point of view. The performance comparison of MPC methods together and different allocated fitness functions and implementation algorithms are dedicated. Another hand, the potential of MPC methods to control inverters for increasing the reliability of the grid, which this feature could not be achieved by using conventional strategies, while has not been investigated by researchers widely, is introduced in a short review. Therefore, this paper shows an intersection guidance map for readers to facilitate future research works in these exciting and undiscovered fields.

**Keywords:** model predictive control; distributed generation sources; power sharing; reliability

#### **1. Introduction**

Energy sources that use fossil fuels to generate electricity always have a devastating effect on the environment, so the attention of distribution network planners has been attracted to the use of renewable energy sources [1]. On the other hand, the existing advances in technologies related to the connection of renewable energy sources to the grid have caused the distributed generation resources connected to the grid to be considered more than before. These distributed generation resources, if installed in the right place and in the right size, can include many economic and technical benefits, such as reducing power losses, improving power quality, improving reliability, eliminating distribution density and causing economic benefits for the power grid [2].

The fundamental difficulty in integrating renewable energy sources is their intermittent nature and unpredictability. Intermittent power means that distributed renewable generations cannot produce power continuously and change dramatically in the short term. Uncertainty means that it is very difficult to predict renewable energy sources [3]. Therefore, this situation may cause changes in energy losses and an unexpected droop or increase in voltage. Increasing the influence of these resources along with the random nature of their output power has created many challenges in the operation of distribution networks [4].

**Citation:** Razmi, D.; Lu, T. A Literature Review of the Control Challenges of Distributed Energy Resources Based on Microgrids (MGs): Past, Present and Future. *Energies* **2022**, *15*, 4676. https:// doi.org/10.3390/en15134676

Academic Editor: Abu-Siada Ahmed

Received: 8 April 2022 Accepted: 28 May 2022 Published: 26 June 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** c 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

The injected power by distributed generations changes size and direction of power flow in distribution networks. In recent years, the integration of distributed renewable generations in distribution systems has received much attention. With penetration of distributed generation in distribution networks, the concept of smart grids was formed [5].

Distributed energy sources are a key element in the formation of smart grids. The large distribution systems can be subdivided into a set of microgrids to build control and operational infrastructure capabilities in future distribution systems [6]. These sources are crucial in the development of microgrids. One approach to maximizing the potential benefits of distributed renewable generations and energy storage batteries is to optimize their allocation and sizing in a distribution system [7]. In this situation, the integration of energy storage devices such as energy storage batteries in distribution networks is one of the possible solutions to facilitate the penetration of high levels of distributed renewable generations in power system [8].

According to their applicability in microgrids, distributed generation sources are divided into two major types [9]:


The control and operation of resources, in which the interface with the microgrid consists of power electronic devices, are different from the sources of energy generation in which electric machines act as an interface. Thus, the dynamic behavior and control of a microgrid with a traditional grid will be different [10]. The existence of distributed generation sources in the distribution network has an influence on the network's current and voltage, which can have a positive or negative impact on system performance [11]. Its positive aspects include increasing reliability, improving power quality, improving voltage profile and reducing losses. On the other hand, the most important problem created by installing distributed generation sources in distribution networks is increasing the level of the short circuit [12].

The task of the power grid is not only to supply electricity to consumers with the lowest number of blackouts. The quality of power delivered to consumers along with providing high reliability, generating power from clean sources and reducing costs at various levels are of great importance [13]. Therefore, the idea of a microgrid to generate electrical energy from various types of energy sources was proposed. A microgrid can be considered as a part of a power system that includes one or more distributed generation that will not lose its functionality if separated from the system [14]. A grid-connected device for power storage can also be classified as a DER system, often referred to as a distributed energy storage system (DESS) [15]. Using an interface, DER systems can be managed and synchronized within an intelligent network [16].

The microgrid can be disconnected from the centralized network and operate independently, which makes the network more flexible and helps reduce network disruptions [17]. Microgrids are increasingly being utilized to combine distributed energy sources, such as hybrid solar energy systems, greatly lowering carbon emissions [18]. The distributed power supply systems are small-scale power generation or storage technologies (usually in the range of 1 to 10,000 kilowatts) that are used as an alternative or upgrading a traditional power system. The following are the benefits of employing distributed generation sources [19]:


Despite all the advantages of distributed generation, one of its possible negative effects on the distribution network is voltage level and protection coordination issues. The DGs develops a network protection system, and as a result, the operation and control of the network will be difficult. With connecting the DGs to the network, harmonics are created in the network and short-circuit impedance is reduced as well. In the rest of this paper, the features and challenges of distributed energy resources in microgrids are reviewed in Section 2, then the hierarchical control methods are discussed in Section 3. In Section 4, the power sharing control strategies are presented. Section 5 is related to the presented solution in the literature based on MPC control strategies. Section 6 first provides an overview of microgrid reliability, then provides predictive control approaches to increase microgrid reliability. Challenges and future perspectives are followed in Section 7; finally, the conclusion section is presented in Section 8.

#### **2. Distributed Energy Resources in Microgrids**

Any low-capacity energy generator of any type can be used in microgrids, which are divided into two main types [20]:


Due to the small size of the network, diesel generators and gas microturbines are used in the microgrid, which are in the category of fossil fuel generators [21]. These units are of special importance in microgrids due to their high controllability in energy production, although they are considered as units for the production of environmental pollutants. The renewable generators, which are increasing their penetration in the power grids, are another type of generators that are of special importance due to their low or cheap fuel and their lack of environmental pollution. The most important of these units are wind turbines, solar cells and fuel cells [22]. Due to the unpredictability of the behavior of distributed generation sources, including wind turbines, solar cells and fuel cells, the frequency and power produced by these sources are variable and will not be able to connect directly to the main grid [23]. Therefore, in order to connect these sources to the power grid, power electronic converters with the ability to convert DC or AC voltage to desirable AC voltage will be required [24]. A power electronic converter can respond to rapid changes to control active and reactive powers and frequency control [25]. However, the use of DG units complicates the structure and poses challenges in the operation, control, stability, protection and security of power distribution networks [26]. Hence, new strategies have been proposed to connect these resources to the grid. According to these standards, whenever a fault occurs in the grid, the DG units are disconnected from the main grid and operate as an island [27]. However, in order to achieve the desired reliability and power quality, it is necessary to review these standards.

#### *2.1. Wind Turbines*

Nowadays, demand for renewable energy sources has increased significantly. Among renewable energies, wind energy is one of the most economical methods of generating electricity that does not pollute the environment. Wind generators are used in both standalone systems for powering remote loads and in grid-connected applications. The wind energy conversion system receives the wind energy from the wind turbine and converts it into electrical energy through a generator, which is available in two forms, fixed speed and variable speed. Due to the low energy production, stress in mechanical parts and low power quality, the fixed speed wind energy conversion systems have been replaced by variable speed energy conversion systems that reduce mechanical stress and aerodynamic noises. These systems can be controlled in such a way as to enable the turbine to operate at its maximum power factor under different wind conditions and receive maximum energy from the wind. Block diagrams of different types of wind turbines are shown in Figure 1 [28].

**Figure 1.** Block diagram of wind turbines. (**a**) Block diagram of squirrel cage induction generator. (**b**) Block diagram of wound rotor induction generator. (**c**) Block diagram of doubly-fed induction

#### *2.2. Photovoltaic (PV) Generation Units*

Photovoltaic systems for general and agricultural use operate in both connected and island operating modes. The advantage of moving systems is the ability to track the sun and increase the energy of the sun during the day. In grid-connected mode, the electrical energy from the photovoltaic system is injected into the main grid using the inverters while changing the shape and matching the voltage level and frequency of the electrical energy

(**d**)

generator. (**d**) Block diagram of permanent magnetic synchronous generator.

from the photovoltaic system. The use of photovoltaic power plants connected to the main grid in a centralized or decentralized manner (while amplifying the current energy in the distribution network), due to the injection of voltage and current, prevents the voltage drop of the distribution network. Block diagrams of photovoltaic solar cells are shown in Figure 2 [29,30].

**Figure 2.** Basic diagram of photovoltaic solar cells.

#### *2.3. Microturbines*

Microturbines are small turbines that generate electricity using wind, water or various fuels, such as natural gas. Microturbines have more advantages than other small-scale technologies, some of which are fewer moving parts, compact size, light weight, higher efficiency, lower emission, lower power costs and use of wasted fuel [31].

#### *2.4. Fuel Cells*

Among the distributed energy sources, fuel cells have been highly regarded due to their high efficiency. In a fuel cell, the method of generating electricity is from the chemical reaction of hydrogen fuel and air oxygen. One of the characteristics of the fuel cell is its slow dynamics due to the chemical process [32].

#### *2.5. Diesel Generators*

A diesel generator is a combination of a diesel engine, a generator and various accessories such as chassis, control systems, emergency circuit breakers, heat generating system, automatic start system, etc. that are used to generate electricity. Diesel generators have lower initial costs, easier maintenance and shorter turning times than small turbines. The production capacity of a diesel generator depends only on the amount of fuel. The relationship between fuel content and diesel generator output power can be modeled as a linear relationship [33].

#### *2.6. Batteries*

Rechargeable batteries belong to the group of electrochemical cells that store electrical energy. These types of cells are called secondary cells, because electrochemical reactions occur reversibly in them. Rechargeable batteries exist in a range of sizes and kinds, ranging from small button batteries to grid-connected megawatt batteries. Lead-acid, nickel-cadmium, nickel-metal, lithium-ion and lithium-ion-polymer are some of the most popular chemical compounds used in rechargeable batteries. Rechargeable batteries are less expensive than other disposable batteries and have less environmental impact. Some rechargeable batteries are produced and supplied in the same sizes as other batteries, except that they can be charged and reused. In grid energy storage applications, rechargeable batteries are used to balance the grid load when they want to inject electrical energy into the grid for use at peak times. New power grids, such as solar power, also use rechargeable batteries to store energy during the day and consume it at night [34,35].

#### *2.7. Challenges and Limitations of Distributed Generation Resources*

With penetration of distributed generation sources in the microgrid, the dynamics of the system are affected [36]. In this case, the analysis of the connection of distributed generation resources to the network becomes complicated, especially when it is necessary to analyze the types of distributed generation sources in the distribution network, which usually passes power in one direction [37]. Researchers and operators of microgrids face these challenges when distributed generation resources are widely used. Some of these challenges are [38,39]:


#### **3. Hierarchical Control of Microgrid**

Hierarchical control of microgrids has been proposed in several studies. The overall microgrid control structures are in three levels that each have specific objectives, and different methods for their operation have been proposed and controller of each level must be calculated and designed. Figure 3 shows the hierarchical control of the microgrid [40,41].

**Figure 3.** The hierarchical control strategy.

#### *3.1. Microgrid Primary Control*

The main controller is in charge of ensuring the reliability of the microgrid system as well as increasing the performance and stability of each converter's local voltage control system. This control level also regulates the reference voltage required for the internal voltage and current loops so that the distribution of active and reactive powers between the distributed generation sources is done optimally. The most common method for the primary controller is droop control, which aims to compensate for the mismatch between the generated power and demand. Based on this requirement, the droop control generates a reference voltage signal for the source and then the internal control loop (voltage and current) ensures that the actual voltage is equal to its reference value. In reality, in gridconnected mode, the primary controller of a microgrid regulates the active and reactive powers of each DG unit, as well as the voltage and frequency in island mode [42–44]. Various approaches to primary control have been proposed, especially for the inverter voltage source interface of distributed energy sources [45]. Most of these approaches use an inner/outer control loop based on the PI controller [46]. In [47], an intelligent load strategy based on a three-phase-single-phase AC-DC converter is proposed as a virtual synchronous machine to reduce frequency fluctuations in the island microgrid. This approach can also carry out grid support operations. By increasing the sources of distributed generation in a microgrid, the inertia of the system decreases, In case of load changes or generation loss, the primary frequency controller faces the problem of high-frequency change rate. A new way to increase system inertia is to use solid-state transformers as virtual synchronous machines in island operation mode. The solid state transformers can play an effective role in improving the island microgrid frequency [48]. Several studies have evaluated the role of electric vehicles in regulating the primary frequency of microgrids; with the penetration of electric vehicles in microgrids, the load profile will change significantly. The authors in [49] illustrated that the high penetration of electric vehicles can have a significant effect on reducing the primary frequency fluctuations in microgrids. In [50], an adaptive droop controller for optimal power distribution in the DC microgrid is presented. The problem of economic distribution of microgrids has been proposed by distributed hierarchical control. The droop controller receives the reference values from the economic regulator and provides the desired output power while maintaining system stability. The conventional droop control method is a decentralized method that is mostly used to control parallelconnected converters in the DC microgrid. One of the disadvantages of the conventional droop control method is incorrect power sharing and voltage deviation in the DC bus [51]. The small signal stability in a hybrid microgrid has been analyzed by considering changes in renewable energy sources. Due to the fact that the wind speed fluctuates, the active output power of the DGs will change significantly, and as a result, power sharing will also change. A suitable power sharing strategy is provided to manage the fluctuations of energy sources that regulate the voltage and frequency of each DG [52].

#### *3.2. Microgrid Secondary Control*

A centralized control strategy is proposed for distributed multipurpose inverters that allows the detection of adverse current components. It also allows the inverter to monitor and measure the desired values through the Internet protocol [53]. With the increase of renewable energy sources and due to its oscillating nature, the separation of secondary and tertiary control levels has negative effects on the overall efficiency of the microgrid. An optimal and robust control strategy for the secondary control level and the distributed MPC approach are proposed to solve the optimization problem [54]. The secondary controller, also known as a microgrid energy management system, is used to ensure the reliability, economics and safety operation of microgrids in both grid-connected and island modes. This level of control is important when the microgrid with the presence of distributed energy sources enters the island mode. This level of control can include a synchronization control loop. It also intervenes when the primary control is not able to return the frequency to the desired values and returns the system frequency values to the reference values [55]. In general, the secondary controller will be responsible for recovering the frequency deviation and voltage range. Furthermore, this control level provides network connection conditions for the microgrid when synchronizing. Many control systems have been proposed for this level of control, which may be grouped into three categories: distributed, centralized and decentralized [56]. The microgrid controllers in the centralized method are based on the same internal loop controllers. In this method, there is a central microgrid controller called MGCC (Microgrid Cenral Control), which allows each DG to communicate with the distribution management system. This type of control is used for small microgrids that are manually controlled. In fact, the definition of centralized and decentralized control for secondary control is based on the status of the MGCC [57]. In centralized control, the frequency and voltage amplitude of DGs are compared with the reference values received from the main grid (in grid-connected mode) [58]. The advantage of this control structure is that due to the fact that the message transmission path is one-way, the telecommunication system does not suffer from high traffic, but the disadvantage of this method is the existence of a central controller, which if it malfunctions can cause the system to also be affected. In order to connect the microgrid to the main grid, the voltage and frequency of the network must be measured [59]. These values are used as a secondary control reference. Furthermore, the phase angle between the microgrid and the main grid must be synchronized using the synchronization control loop. The consensus-based secondary frequency control is provided for islanded microgrids under weak communication conditions. In this research, to reduce the effects of weak communication conditions, a new approach with time-varying control gain is proposed [60]. A distributed secondary control approach is proposed to distribute power and voltage restoration in island mode, which, unlike other secondary controller methods, is based on the idea of feedback, and only by knowing the voltage of each bus, can the secondary controller be designed for each DG [61]. The authors of [62] proposed a method for island mode of inverter-based microgrids. The proposed method is able to predict system dynamics at high and low frequencies. The wireless power sharing approach is proposed for DGs and converts the output impedance of the inverter to the pure impedance by adjusting the virtual impedance. Table 1 summarizes the advantages and disadvantages of control strategies.


**Table 1.** Advantages and disadvantages of control strategies.

#### *3.3. Microgrid Tertiary Control*

The purpose of this control layer is to manage the microgrid power flow in the gridconnected mode by adjusting the voltage and frequency, which is done by the secondary controller. By measuring the P/Q ratio at the Point of Common Coupling (PCC), the active and reactive powers of the grid can be compared with the desired reference values. This level of control is the last level and the slowest in terms of response. In fact, tertiary control consists of the optimal operation of the microgrid in the economic and technical sectors. Technically, if there is an error or unplanned islanding in the microgrid, the third-party control tries to absorb the active power from the grid, so that if the main grid is not available, the frequency will be reduced. It is noteworthy that depending on the allocation of active and reactive powers values, the distribution of active and reactive powers can be from the microgrid to the main grid or vice versa [63]. Table 2 evaluates the performance modes of microgrids [64].

**Table 2.** Comparison of microgrid performance modes [64].


#### **4. Power Sharing Theory**

In order to investigate the distribution of active and reactive powers by distributed generation sources and power distribution equations, the equivalent circuit of a distributed generation source is considered according to Figure 4. In this equivalent circuit, the distributed generation source is modeled with an alternating voltage source that is connected to the ac bus via a *Z*-impedance supply line and supplies the load. The power transferred from the distributed generation source to the ac bus is as follows:

$$S = P + jQ \tag{1}$$

$$S = \bar{E}I^\* = E\angle\left[\frac{E}{Z}\angle(\theta-\delta)-\frac{V}{Z}\angle\theta\right] = \frac{E^2}{Z}\angle\theta - \frac{EV}{Z}\angle(\theta+\delta) \tag{2}$$

$$P = \frac{E^2}{Z} \text{Cost} \theta - \frac{EV}{Z} \text{Cost} (\theta + \delta) = \frac{(E^2 - EV \text{Cost} \delta) \text{Cost} \theta}{Z} + \frac{EV \sin \theta \sin \delta}{Z} \tag{3}$$

$$Q = \frac{E^2}{Z} \text{Sin}\theta - \frac{EV}{Z} \text{Sin}(\theta + \delta) = \frac{(E^2 - EV \cos \delta) \text{Sin}\theta}{Z} - \frac{EV \sin \theta \sin \delta}{Z} \tag{4}$$

In which *S*, *P* and *Q* are apparent power, active and reactive powers transmitted to the load, respectively, *E* and *V* are inverter output voltage amplitude and AC bus and *δ*, *Z* and *θ* are load angle, line impedance amplitude and phase, respectively. Table 3 shows the general equations of droop and power sharing based on different impedance angles according to Equations (1)–(4).

**Figure 4.** Single line diagram of power system [65].

According to the equations of active and reactive powers distribution (3) and (4), the line impedance is proportional with the inverse power distribution, i.e., *P* ∝ <sup>1</sup> *<sup>Z</sup>* , *<sup>Q</sup>* <sup>∝</sup> <sup>1</sup> *Z* . This means that in the high line impedance, the amount of power transmitted to the load will be lower [66]:

$$P = \frac{(E^2 - EV\cos\delta)\cos\theta}{Z} + \frac{EV\sin\theta\sin\delta}{Z} \tag{5}$$

$$Q = \frac{(E^2 - EVcos\delta)\sin\theta}{Z} - \frac{EVsin\theta\sin\delta}{Z} \tag{6}$$

Therefore, the output power of each unit can be controlled by controlling the line impedance.

**Line Impedance Type Line Impedance Angle Power Equation Droop Equation** <sup>L</sup> *<sup>θ</sup><sup>i</sup>* <sup>=</sup> <sup>90</sup>◦ *Pi* <sup>=</sup> *EiVPCCSinδ<sup>i</sup> Xi Qi* <sup>=</sup> *<sup>E</sup>*<sup>2</sup> *<sup>i</sup>* −*EiVPCCCosδ<sup>i</sup> Xi f* ∗ *<sup>i</sup>* = *f*<sup>0</sup> − *kpiPi E*∗ *<sup>i</sup>* = *E*<sup>0</sup> − *kqiQi* RL 0◦ <sup>&</sup>lt; *<sup>θ</sup><sup>i</sup>* <sup>&</sup>lt; <sup>90</sup>◦ *Pi* <sup>=</sup> *<sup>E</sup>*<sup>2</sup> *<sup>i</sup> Cosθi*−*EiVPCCCos*(*θi*+*δi*) *Zi Qi* <sup>=</sup> *<sup>E</sup>*<sup>2</sup> *<sup>i</sup> Sinθi*−*EiVPCCCos*(*θi*+*δi*) *Zi f* ∗ *<sup>i</sup>* = *f*<sup>0</sup> − *kpiPi* + *kqiQi E*∗ *<sup>i</sup>* = *E*<sup>0</sup> − *kpiPi* − *kqiQi* <sup>R</sup> *<sup>θ</sup><sup>i</sup>* <sup>=</sup> <sup>0</sup>◦ *Pi* <sup>=</sup> *<sup>E</sup>*<sup>2</sup> *<sup>i</sup>* −*EiVPCCCosδ<sup>i</sup> Ri Qi* <sup>=</sup> <sup>−</sup>*EiVPCCSinδ<sup>i</sup> Ri f* ∗ *<sup>i</sup>* = *f*<sup>0</sup> + *kqiQi E*∗ *<sup>i</sup>* = *E*<sup>0</sup> − *kpiPi* RC 90◦ <sup>&</sup>lt; *<sup>θ</sup><sup>i</sup>* <sup>&</sup>lt; <sup>0</sup>◦ *Pi* <sup>=</sup> *<sup>E</sup>*<sup>2</sup> *<sup>i</sup> Cosθi*−*EiVPCCCos*(*θi*+*δi*) *Zi Qi* <sup>=</sup> *<sup>E</sup>*<sup>2</sup> *<sup>i</sup> Sinθi*−*EiVPCCSin*(*θi*+*δi*) *Zi f* ∗ *<sup>i</sup>* = *f*<sup>0</sup> + *kpiPi* + *kqiQi E*∗ *<sup>i</sup>* = *E*<sup>0</sup> − *kpiPi* + *kqiQi* <sup>C</sup> *<sup>θ</sup><sup>i</sup>* <sup>=</sup> <sup>−</sup>90◦ *Pi* <sup>=</sup> <sup>−</sup>*EiVPCCSinδ<sup>i</sup> Xi Qi* <sup>=</sup> <sup>−</sup>*E*<sup>2</sup> *<sup>i</sup>* −*EiVPCCCosδ<sup>i</sup> Xi f* ∗ *<sup>i</sup>* = *f*<sup>0</sup> + *kpiPi E*∗ *<sup>i</sup>* = *E*<sup>0</sup> + *kqiQi*

**Table 3.** Power sharing and droop equations [65].

#### *Control Strategies for Power Sharing*

One of the most important and challenging issues in the control of island microgrids is the control of power sharing among distributed generation sources, so that each unit must feed the load in proportion to its nominal value. The main purpose of power sharing is to increase the network capacity to meet power demand. Power sharing among distributed generation units is one of the most important challenges; lack of power sharing among them leads to unequal load sharing, which may damage the load and often leads to instability. Various methods have been proposed to control the power sharing in microgrids, one of the most famous of which is the droop control method. The droop control method is a decentralized control method that uses local control signals such as frequency and voltage to control power sharing in microgrids. In the droop control method, active and reactive powers, frequency and voltage amplitude of distributed generation sources are the control variables that are used to share power [67,68].

In microgrids with a large amount of reactance to resistance ratio (X/R), due to the relationship between active power and frequency, as well as the relationship between reactive power and voltage, the conventional droop control method is used. However, in low voltage microgrids, due to the small ratio of reactance to line resistance, there is a resistance connection between the inverters, and therefore, the active power depends on the voltage and the reactive power depends on the frequency. In island microgrids with inverter-based distributed generation sources, mismatching the impedance of the supply lines leads to a voltage difference between the inverter terminals, which can cause a rotational current between inverters and over-current in the distributed generation sources. In order to solve the challenges in microgrids, including the dependence of active and reactive powers on low voltage microgrids by the distributed generation sources in the microgrids, as well as the rotational current between these sources, various methods, such as the virtual power method, voltage method and virtual frequency and virtual impedance methods, are proposed. Figure 5 shows the challenges and proposed solutions [69–78].

A network-based power sharing strategy under unknown impedance is presented [79–81]. This improved strategy can provide acceptable power sharing while keeping the steadystate frequency constant. In addition, it improves microgrid dynamic performance and power sharing errors under unknown impedance. Network-based active power sharing

strategies have been proposed in previous research [82–84]. However, there are two main drawbacks: (1) Due to the presence of voltage and frequency droop loops, the frequency droop cannot be eliminated. (2) Communication delays under the uncertainties parameters increase system sensitivity. In microgrids, the virtual impedance method was used to eliminate the dependence of active and reactive powers between power supplies that were connected directly to the PCC in microgrids through resistance lines [85,86]. Virtual impedance has been proposed to stabilize the line impedance of distributed generation sources to improve the power sharing performance by droop control method [87], which can be placed in the inverter output without a physical connection. By implementing virtual impedance in the controller of the distributed generation unit, the line-equivalent impedance can be divided into two parts: physical impedance and virtual impedance. When virtual impedance is considered, the distributed output source can be considered as a voltage droop source controlled by the droop method in series with the virtual impedance [88]. Table 4 shows the challenges of active power sharing for different types of control strategies.

**Figure 5.** Challenges and proposed solutions.

**Table 4.** Active power sharing strategies.


Virtual impedance is used for various purposes, such as independent control of active and reactive powers, the realization of proper power sharing, increasing power transmission capacity, etc. [89]. Therefore, if the virtual impedance is properly designed and controlled, it can have a significant impact on improving the performance of control methods by reducing the dependence of power distribution on line impedance. In order to facilitate the use of the conventional droop control method in microgrids and to solve the problem of line impedance mismatch, a virtual and physical impedance interface inductor is considered to reduce the dependence of active and reactive power sharing as well as to stabilize the output impedance [90,91].

#### **5. Control Approaches Based on MPC**

The basic idea of model predictive control or Receding Horizon Control (RHC) was introduced in the 1960s and then in the 1970s in industrial control applications, especially in the chemical industry. Then, this control approach entered the academic and research space and was welcomed by researchers. Various papers have described and compared the types of predictive controllers well. MPC is an intuitive method for systems that have constraints. This fact demonstrates why predictive controllers are so popular among other controller types. In general, the predictive controller sends the appropriate control signal to the converter by minimizing the cost function that provides the proper behavior of the system. For each sampling time, MPC calculates a series of control signals that minimize the cost function, with this description that the first signal is applied to the converter [92]. Table 5 shows some cost functions for power electronics applications.


**Table 5.** Example of cost functions for power electronic applications.

In recent years, widespread research has been done on microgrid control systems. In small-scale microgrids, the most important issue is to attain reliable performance, balancing supply and demand, while in other structures, optimal performance is required. Several types of research have been performed using the hysteresis band control method to energy management due to the simplicity of the structure and its implementation. On the other hand, predictive controllers have found a wide range of applications in the field of power electronics and drives, also minimizing the cost function by solving optimization problems while considering technical constraints [98].

The predictive controller is very suitable for electronic power converters and drives due to its fast dynamic response. Some of the features that make predictive control a suitable method to microgrids are as follows [99]:


In modern industrial control, the model predictive control method is used for many industrial applications. These methods can be divided into two categories: 1. Finite control set MPC (FCS-MPC), which uses the advantage of limiting the number of switching possibilities to optimize the problem; 2. Continuous control set MPC (CCS-MPC), which requires a modulator to generate switching pulses according to the control system settings [100].

As we know, in a converter, the switches can only be switched on and off in two states, and their combination creates a limited number of different states. Using this inherent feature, the converter switching model can be easily presented and the prediction can be summarized only in the limited situations mentioned. The main elements of this control schemes are the mathematical model of the system and the predefined cost function. One of the most important advantages of FCS-MPC is its simplicity. The operation of this controller is that first, the system variables are measured or estimated, then the system model is extracted and discretized according to the controlled variable, which can be current, voltage and power. By discretizing the system model and knowing the value of current variables, controlled variables can be predicted in future times [101]. Table 6 provides a general classification of MPC approaches.


**Table 6.** General classification of the MPC approaches.

All predictive control strategies are based on solving an optimization problem so that it can select the appropriate control signal and apply to power electronic converter. Cost functions also define the appropriate behavior for the system. Thus, cost functions can be complex depending on what type of variable is considered.

#### *5.1. MPC-Based Primary Control*

In [102], the FCS-MPC approach is proposed as the primary control layer to control the output power of each DGs (grid-connected mode) and the voltage regulate in PCC (in island mode). In the grid-connected mode, the Direct Power Model Predictive Control approach (DPMPC) is applied to manage the power sharing between each DG and the grid, and in island mode, Voltage Model Predictive Control (VMPC) approach is provided as a droop control and secondary to adjust the output voltage of DGs. In [103], a research on the design of predictive controller based on discrete time model for voltage control in island microgrids is presented. In this research, several distributed generation units are connected in parallel to build a microgrid. The purpose of the controller design is to control the mains voltage on different loads. The design of this controller is done using a discrete-time function that provides extensive microgrid tracking function; the controller is for a single-phase microgrid design. The performance of this controller has been tested in various ways. This controller offers acceptable performance in microgrids against the dynamics of different loads and shows better tracking performance.

In the reference [104], a study on the method of controlling multiple photovoltaic systems in a DC microgrid using a predictive controller is presented. Direct current microgrid sys- tems are beneficial due to higher efficiency, reliability and easier connection of

renewable energy sources compared to AC microgrid systems. The finite set of predictive control models is a robust control technique that predicts the future behavior of the system in a number of arbitrary sampling steps over the time horizon, based on a set of possible control operators [105]. The proposed predictive controller for DC microgrids includes maximum power point tracking and bidirectional DC-DC converter control to evacuate the battery power storage system. Using predictive controller features with the ability to add design constraints, the proposed system ensures maximum output power from the PV system due to the battery SoC. The controller increases the speed of the control loop because it increases the prediction and correction of the error before the switching signal is applied to the DC-DC converters. In [106], a MPC-based VSG control structure is proposed for the primary controller for voltage control and power sharing, i.e., firstly this predictive controller is applied to the inner loop, which provides a faster dynamic response as well as increased bandwidth and stability; then, a VSG has been proposed to proper power sharing in an outer loop, and a comprehensive comparison between the proposed control structure and the conventional structures is presented in Table 7.

**Table 7.** Comparison of control strategies.


#### *5.2. MPC-Based Secondary Control*

In [107], a unified model predictive voltage and current control (UMPVIC) strategy is presented for both grid-connected mode and island mode, which can be flexibly applied in the primary control layer for proper load sharing and in the tertiary layer for power flow. A fuzzy control algorithm is proposed to reduce the voltage and frequency deviations caused by the primary droop layer. This fuzzy controller can optimize secondary layer coefficients to improve voltage quality. The dynamic response of converters is much faster than the frequency load. Usually, the droop control method is used to share the active and reactive powers of microgrids. The disadvantages of this method are the deviation of voltage and frequency from its nominal value in the steady state. A distributed secondary controller based on the prediction model with a state space approach is proposed to return the voltage and frequency of the microgrids. Therefore, a secondary controller is provided to eliminate voltage and frequency deviations, and the performance of the proposed method is evaluated by evaluating it under a feeder impedance that is inconsistent with balanced and unbalanced linear load conditions [108]. A distributed model predictive control strategy based on voltage observer for multiple energy storage systems is proposed. In order to reduce the effects of communication delay on the voltage observer, an improved distributed predictive control algorithm is proposed. This proposed scheme strengthens the delayed system. A small-signal dynamic model with a predictive controller is used to analyze the dynamic performance [109].

#### **6. Fault Tolerant of Microgrids**

Assessing the reliability of the distribution system is one of the most important studies for power system operators and planners. Existing distribution networks are designed to be powered on one side, but with the presence of distributed energy resources, it is possible to transfer power from both sides. In other words, power may be transferred from the distribution network to the transmission network. For this reason, conventional risk management methods will not be used to calculate the reliability of this type of network, and researchers are looking for new solutions to calculate the reliability of this type of network. Reliability is predicted based on expected performance; in other words, performance without failure. Increasing the use of power generation units using renewable energy in microgrids has led to attention to the reliability of these systems. Since such distributed generation sources have a lot of uncertainty, necessary measures should be considered to provide sustainable power to the consumer [110,111].

Recently, the predictive control method of the model has found increasing interest among researchers in the field of reliability. In [112], a combined method of dynamic planning based on predictive control is presented. In [113], a predictive-based approach is proposed for the management of grid-connected photovoltaic power generation. In [114], a microgrid scheduling method based on MPC is proposed to increase the flexibility of distribution networks. A robust MPC-based two-layer model has been developed considering the worst case scenario for microgrids. It is shown that the proposed solution can ensure the reliability and feasibility of microgrids in the presence of uncertainties. A microgrid power management framework that is connected to the grid via a transformer and contains a local consumer, a wind turbine and an energy storage system is provided to minimize costs based on optimal battery planning. The model predictive control approach has been used to improve power, cost and production in the presence of uncertainties [115]. In [116], a predictive control algorithm is proposed to solve the problem of economic optimization in the presence of distributed generation sources.

#### **7. Challenges and Future Perspectives**

Among different types of microgrids, DC microgrids have problems in the field of power quality and one of the important obstacles to the development of this type of microgrids is limited DC loads. Therefore, with the development of technologies, it is expected that DC loads will be more compatible. On the other hand, due to the high cost of energy storage systems in AC microgrids, such advances in technology can make these systems more costeffective. Since the issue of power quality and grid stability are the most important issues in the field of microgrids, with the widespread penetration of renewable energy sources in microgrids, more efforts should be made in this area [117].

An integrated distributed planning model can provide an effective solution for balancing the efficiency and allocation of costs of DERs. Among the items that can play an important role include [118]:

• Improving connection cost estimates can develop an integrated planning model for energy resources to make photovoltaic system equipment installation more efficient;

• Estimating and predicting more accurate, robust economic distribution of distributed generation resources can help reduce the risk of recovering potential future costs due to uncertainty in the future development of distributed generation resources.

Accurate forecasts of distributed energy sources are of particular importance in the long-term planning of distribution and transmission. In both over and under forecasting, the transmission line in turn can have special consequences for the system. In other words, if this forecast is done too much, the reliability and flexibility of the system will be affected. In case of under forecasting, unnecessary generation distribution resources can be added.

The two forecast methodologies for future distributed energy sources are shown in Table 8. Top-down approaches provide a significant improvement in data and methodological complexity. Time series, econometric and bass diffusion models are among the top-down models that have been employed to anticipate DER adoption. Time-series models extrapolate historical, cyclic data to future outcomes. Econometric models are statistical models that are used to explain observable data and can be expressed in a variety of ways. The most often utilized strategy for forecasting DER adoption is the use of bass diffusion models.

**Table 8.** Methods used for DER forecasting [118].


#### **8. Conclusions**

Microgrids are a modern concept for the future of energy systems that have made it possible to use renewable energy and require electrical and control structures and equipment for optimal performance. One of the most important and fundamental issues in microgrids are how to control distributed generation sources to supply local load. Since most distributed generation sources are connected to the grid by electronic power converters, appropriate methods must be used to control electronic power converters to ensure the microgrid's economic performance. The purpose of this research is to review what has been done so far about energy source-based microgrids in the literature. Hierarchical control structures are expressed and its control method is evaluated. The MPC play an important role in microgrid performance and system reliability. Therefore, a review of MPC-based control structures and following that a comparison between its control strategies are performed.

**Author Contributions:** Conceptualization, D.R. and T.L.; Investigation, D.R. and T.L.; Writing original draft preparation, D.R.; Writing—review and editing, D.R. and T.L.; Supervision, T.L.; Project administration, T.L.; Funding acquisition, T.L. All authors have read and agreed to the published version of the manuscript.

**Funding:** This work is financially supported by the General Program of National Natural Science Foundation of China (No.52107110); Young Elite Scientists Sponsorship Program (No. YESS20200239); The Shandong Natural Science Foundation for Excellent Young Scientists Program of China (2022HWYQ039); The Shandong Natural Science Foundation of China (ZR2021QE018).

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Informed consent was obtained from all subjects involved in the study.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**


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