Nanoscale CMOS Devices and Their Applications
A special issue of Applied Sciences (ISSN 2076-3417). This special issue belongs to the section "Electrical, Electronics and Communications Engineering".
Deadline for manuscript submissions: closed (20 August 2023) | Viewed by 249
Special Issue Editor
Special Issue Information
Dear Colleagues,
The scaling of CMOS technology has been a primary driving force of the semiconductor industry, enabling more compact and faster integrated circuits. The technology has evolved from planar MOSFET to Tri-gate FinFET and then gate-all-around (GAA) structures with improved electrostatics. Design technology co-optimization enables further improvements in performance, power efficiency, and area density. There is no doubt that silicon CMOS technology still has strong vitality in the foreseeable future. However, it has become increasingly difficult to shrink transistors along the path of Moore's Law due to power, interconnection, and fabrication challenges. Innovations from low-dimensional materials, new device structures, monolithic 3D integration, cryogenic electronics, and alternative switching principles provide additional possibilities to sustain the scaling and improve energy efficiency. This Special Issue invites researchers and scientists to submit research papers, short communications, and review articles focusing on cutting-edge research and recent advances in nanoscale CMOS devices from fundamental research to applications.
Dr. Fei Liu
Guest Editor
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Keywords
- nanoscale CMOS devices
- design technology co-optimization (DTCO)
- reliability and variability
- emerging nanoelectronic devices and physics
- low‐dimensional materials
- steep slope devices
- cryogenic electronics
- fabrication of nanodevices
- modeling and simulations
- compact modeling and circuit simulation
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