Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16040057

Authors: Sadiq Alinsaif Ammar Ahmed E. Elhadi

Modern Cyber–Physical Systems (CPS) face severe performance bottlenecks due to the high latency and computational overhead of centralized processing, limiting their efficacy in time-critical applications such as digital health and smart mobility. To overcome these constraints, this paper presents an integrated architecture that cohesively integrates Edge Intelligence (EI) with Quantum-Inspired Algorithms (QIAs). The framework decentralizes immediate decision-making to edge computing nodes through a novel Quantum-Inspired Task Offloading and Scheduling (Q-TOS) algorithm that uses probabilistic Q-bit state representations and phase rotation gates to solve multi-objective latency-energy optimization problems. Rigorous simulation experiments performed across dynamic workload, surge load, and channel-impaired scenarios demonstrate that Q-TOS achieves a 29.3% reduction in decision-making latency, a 22.3% decrease in dynamic energy consumption, and a 98.6% constraint feasibility rate relative to state-of-the-art metaheuristics such as Particle Swarm Optimization (PSO). Furthermore, the framework sustains an average decision latency of 0.78ms with a RAM footprint below 3.4MB, validating quantum-inspired edge architectures as a viable paradigm for expandable, real-time CPS operations.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16040056

Authors: Parisa Rahimi Didar Nanakaly Amit Kumar Singh Seyedali Pourmoafi Xiaohang Wang Alexios Mylonas

The increasing complexity of Internet of Things (IoT) environments necessitates efficient and reliable anomaly detection. This study experimentally evaluates established tree-based machine-learning models instead of proposing a new detection algorithm. Decision Tree (DT), Random Forest (RF), and XGBoost are compared using CPU- and GPU-based implementations on the highly imbalanced DS2OS dataset by considering training time, overall classification performance, and minority-class detection. GPU experiments were conducted using an NVIDIA T4 in a cloud-based environment; the results do not establish performance on physical IoT or edge devices. The recorded training times yielded CPU-to-GPU time ratios ranging from 2.12 to 2.94 across the evaluated implementations. However, the original CPU hardware configuration could not be verified, preventing these differences from being attributed exclusively to GPU acceleration and limiting their reproducibility under equivalent conditions. In the initial evaluation, Random Forest configurations failed to detect minority attack classes despite high overall accuracy, whereas supplementary evaluations demonstrated substantially improved performance with alternative feature encoding. XGBoost achieved near-perfect classification in the initial test partition and reduced-training configurations. Although supplementary evaluations initially showed lower and more variable performance with the complete-training partition under automatic initialisation, a controlled ten-fold evaluation demonstrated that fixing the initial prediction score eliminated this deterioration on both the CPU and GPU within the evaluated DS2OS configurations. Supplementary experiments further demonstrated that the GPU-based Decision Tree proxy achieved classification performance comparable to the CPU Decision Tree following adjustments to its model configuration, indicating that the original performance difference was primarily configuration-dependent rather than an inherent limitation of GPU hardware. Energy efficiency and embedded-device performances were not experimentally established.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16040055

Authors: Edgar López-Molina Víctor Sámano-Ortega Alejandro Israel Barranco-Gutiérrez Alejandra Ramírez-Segovia Ricardo Lozoya-Ponce Juan Martínez-Nolasco

This study analyzes the energy consumption, operating costs, and associated CO2 emissions of electric vehicle (EV) charging under different residential photovoltaic system (RPVS) configurations using a Hardware-in-the-Loop (HIL) platform. Three charging scenarios were evaluated: (i) EV charging supplied exclusively by the main grid (MG); (ii) EV charging supplied by an off-grid RPVS; and (iii) EV charging supplied by an interconnected RPVS supported by the MG. To perform the experimental evaluation, an HIL platform integrating a microgrid (µG) and an EV emulator was developed. The EV emulator was configured using the parameters of a Tesla Model S battery pack based on 18,650 lithium-ion cells. The embedded µG architecture was reprogrammed to include an RPVS, a battery bank (BB), an AC bus, and the capability to operate either autonomously or interconnected with the MG. Energy balance within the µG was managed through an Energy Management System (EMS) designed to maximize the utilization of photovoltaic energy. The experimental results showed that Scenario 1 Level 1 required 100.344 kWh, while Scenario 1 Level 2 required 105.982 kWh. In Scenario 2, energy consumption was 101.856 kWh, and Scenario 3 required 104.4 kWh. Based on these data, the estimated monthly energy consumption, CO2 emissions, and costs were as follows: for Scenario 1, 251.23 kWh, 111.54 kg CO2, and 1692.25 MXN; for Scenario 2, 251.23 kWh, 12.53 kg CO2, and 262.28 MXN; and for Scenario 3, an exportation of 1007.45 kWh to the MG, 174.36 kg CO2, and 1340.81 MXN. These results provide technical and environmental evidence supporting the feasibility of RPVS for EV charging and highlight the importance of renewable energy-based solutions for sustainable electric mobility. The proposed HIL-based methodology offers a reliable framework for assessing the technical, economic, and environmental impact of RPVS integrated with EV charging infrastructure.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16040054

Authors: Yifeng Zhou Kaijun Song

Traditional methods for measuring the dielectric constant of solid materials are often limited by bulky equipment, stringent sample preparation, and difficulty in on-site non-destructive testing. This study proposes a compact, low-cost, and planar microwave sensor based on a defected microstrip structure (DMS) for the non-destructive measurement of solid dielectric constants. The sensor is fabricated on a low-cost 1.6 mm thick FR4 substrate and features a miniaturized planar design. By placing the material under test above the DMS resonant region, the dielectric constant is determined via the shift in the resonant frequency. Simulation and experimental results demonstrate a large, normalized frequency shift and a high average sensitivity over the experimentally validated permittivity range, and full-wave simulations predict a monotonic resonant response over a considerably broader permittivity range. A second-order calibration curve is established for the quantitative extraction of unknown permittivities. Furthermore, the ultra-low-power characteristics of the sensor were explicitly evaluated. Experimental results indicate that the sensor maintains stable sensing performance at an ultra-low input power of −50 dBm (10 nW) and remains operable down to −70 dBm (100 pW). With its advantages of ultra-low power, compact size, low cost, planar structure, portability, and non-destructive capability, this sensor provides an effective solution for efficient solid material dielectric measurement.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16040053

Authors: Marcello De Matteis

This paper presents a MATLAB-assisted EKV–gm/ID methodology for the systematic synthesis of fully differential two-stage Miller-compensated CMOS OTAs. A sensitivity-based analysis maps the required closed-loop gain, bandwidth, and noise into OTA-level targets. An EKV-inspired analytical model, independently calibrated for nMOS and pMOS devices, provides continuous ID/W, gm/W and gm/ID characteristics with errors below 5% in the design region. Noise-driven sizing explicitly accounts for the different carrier mobilities of the pMOS differential pair and nMOS active load. Transistor parasitic capacitances are estimated from bias-dependent Cgg–VGS characteristics, thereby capturing the reduced gate capacitance of devices operating in moderate or weak inversion. The framework automatically generates transistor dimensions, bias conditions, and Miller-compensation components. These parameters are transferred directly from MATLAB to CADENCE without simulator-assisted resizing or optimization, except for width quantization into 5 μm/300 nm fingers. In 0.18 μm CMOS implementation, MATLAB and nominal CADENCE simulations predict, respectively, 61.80 and 59.27 dB DC gain, 430.78 and 431.52 MHz unity-gain bandwidth, 69.24° and 68.81° phase margin, 5.0 and 5.3 nV/√Hz input-referred noise at 100 MHz, and 1.426 and 1.314 mW core power. Robustness is assessed over 45 process-voltage-temperature corners, where the nominal solution remains close to the center of the evaluated performance distributions. The results confirm accurate nominal prediction and stable transistor-level behavior across PVT conditions and demonstrate that the proposed methodology accurately designs the OTA operating point, small-signal dynamics, and noise behavior, enabling transistor-level sizing directly from system-level specifications without iterative simulator-assisted optimization.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16040052

Authors: Abed Al Raoof K. Bsoul Yazan Alshboul

Large language models (LLMs) commonly employ key–value (KV) caching to avoid recomputing previous attention states during autoregressive inference. However, its measured performance benefit depends on workload characteristics and the memory environment. This study presents a controlled systems characterization across input context length, model-specific grouped-query attention configurations, and GPU-memory residency. Experiments use Qwen2.5-3B and SmolLM3-3B under verified fully resident conditions with fixed 128-token generation, prompt lengths from 128 to 2048 tokens, randomized cache-enabled/cache-disabled execution, GPU telemetry, and repeated paired validation. End-to-end generation speedup increases from 1.34× to 8.31× for Qwen2.5-3B and from 1.28× to 8.62× for SmolLM3-3B. At 2048 prompt tokens, 30 randomized paired trials confirm mean speedups of 8.10× and 8.51×, corresponding to runtime reductions of 87.65% and 88.25%, while physical GPU-memory utilization remains below 61%. SmolLM3-3B requires twice the theoretical KV-cache storage per token, yet both models show comparable context-dependent scaling in the fully resident regime. Because the models differ in characteristics beyond KV-head count, this cross-model comparison is descriptive and does not attribute the observed performance difference causally to GQA configuration. A separate Mistral-7B case study shows that apparent end-to-end speedup changes substantially under memory pressure; the underlying memory-system mechanism is not isolated. These results establish cache-related end-to-end generation speedup as workload- and system-dependent and demonstrate that meaningful benchmarking requires reporting context length, cache configuration, model and cache footprints, physical accelerator-memory residency, runtime, throughput, and relevant GPU-memory conditions during each inference experiment.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16040051

Authors: Sanaz Kazemi Abharian Sathwika Bavikadi Sai Manoj Pudukotai Dinakarrao

Processing-in-memory (PIM) architectures have emerged as promising alternatives to conventional von Neumann architectures for accelerating memory-bound applications, such as Graph Neural Networks (GNNs), by reducing data movement between memory and processing units, thereby improving energy efficiency and reducing computational latency. Feature aggregation is a fundamental operation in GNNs; however, the sparsity of graph data leads to poor spatial and temporal locality. This results in dynamic and irregular memory access patterns, ultimately limiting performance and increasing latency. To address this issue, we propose LUPIN, a look-up table (LUT)-based PIM architecture to accelerate GNNs. In this design, logic-based processing is replaced with precalculated results stored in LUTs to perform the required computations within the DRAM memory platform. The proposed LUPIN architecture achieves enhanced performance and markedly improved energy efficiency compared to conventional bitwise-parallel PIM designs. Moreover, it avoids the fabrication challenges associated with integrating logic circuits into memory. It leverages the extensive internal parallelism of DRAM to accelerate the execution of GNN models while maintaining high energy efficiency. Our results demonstrate that LUPIN achieves geometric-mean energy improvements of 32× and 51× on GCN and GIN, respectively, over the CPU and 15× and 19.5×, respectively, over the GPU. Moreover, LUPIN reduces latency by 35.8× and 25.7× on GCN and GIN, respectively, compared with the CPU and 29.6× and 20.5×, respectively, compared with the GPU. The proposed LUPIN architecture achieves nearly 10× higher energy efficiency and 5× speedup compared with the state-of-the-art PIM architectures.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16040050

Authors: Elmehdi Nasri Mariyam Ouaissa Mariya Ouaissa Tarik Jarou

Permanent magnet synchronous motors (PMSMs) are widely used in electric vehicle (EV) traction, where speed control must be accurate, robust, and executable in real time on resource-limited embedded hardware. This paper presents an adaptive nonsingular terminal sliding-mode controller combined with a radial basis function neural network (NTSMC–RBFNN), in which the network estimates and compensates the lumped disturbance online. Stability is analyzed in continuous time under stated assumptions and, for the sampled-data implementation, only in a conditional, practical sense. The controller is reformulated in fixed-point arithmetic and deployed on a Xilinx Zynq-7000 FPGA through a parallel, pipelined architecture. In FPGA-in-the-loop (FIL) tests, it achieves a speed-tracking RMSE of 0.072 rad/s and recovers from a step load change within 4 ms, and it remains stable under ±50% variations in rotor inertia and flux linkage. One control update takes 3.2 µs (0.32% of the 1 ms sampling period), uses less than 6% of the device resources, and consumes an estimated 1.02 µJ of dynamic energy (Vivado post-implementation estimate). In an ablation study, removing the RBFNN estimate multiplies the load-step RMSE by 3.7, and replacing the nonsingular terminal surface by a conventional one increases the tracking RMSE by 75%. A sensitivity study identifies Nh = 7 hidden neurons as the retained compromise between accuracy, resources, and energy. The plant is simulated and the power figures are estimates; experimental validation on a physical drive is left for future work.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16040049

Authors: Jian Zhou Juan Wang Yewen Yao Yongliang Wang Man Wang Wei Peng

The critical current (Ic) of a Josephson junction (JJ) is a significant physical parameter that plays a crucial role in the design of subsequent devices and circuits, as well as in the optimization of manufacturing processes. To ensure accurate measurements, testing should ideally be conducted in a magnetically shielded room. However, due to laboratory constraints, tests are often performed in unshielded environments, where they are inevitably influenced by various environmental noises. This introduces significant uncertainty into the measured Ic values, thereby impacting the design of subsequent superconducting circuits. This study examines the impact of conductive, radiated, and flux noise on the repeatability of Ic measurements in an unshielded environment and establishes an empirical formula for predicting Ic values in shielded environments based on unshielded data. The deviation between the empirically predicted Ic and the experimentally measured value is less than 1%, verifying the effectiveness of the proposed formula. This approach offers a relatively accurate and cost-effective method for testing the critical current (Ic) of Josephson junctions (JJs) under unshielded conditions.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16040048

Authors: Wallace Cavalcante Jozias Oliveira Rubens de Andrade Fernandes Israel Gondres Torné

Edge Artificial Intelligence (Edge AI) is used in wildlife monitoring to reduce communication demand, support decision-making, and enable energy-aware operation, yet embedded inference alone does not establish whether a system can sustain useful service after installation. This scoping review searched four bibliographic databases through 5 August 2026 and complemented these searches with studies identified from prior work on the topic, identifying 41 eligible English-language papers published from 2021 onward on camera-primary intelligent wildlife systems. The review aimed to assess operational maturity, field-validated operational role, energy evidence, and operational continuity. Full texts were charted and analyzed across sensing, decision-making, communication, response, energy, and continuity. Post-installation evidence exposed triggering, environmental, connectivity, maintenance, and energy-supply constraints not established through non-field evaluation. Field-validated alert delivery did not extend to quantitative validation linking human action to mitigation outcomes, while field activation of physical intervention alone did not establish behavioral or management effectiveness. Energy evidence was even more limited, with limited direct operational electrical measurement, rare main-state characterization, and no complete lifetime energy budget evidence. By separating architectural capability from the evidence supporting its operational realization, the review provides a systems-level basis for interpreting how far reported functions are actually validated. Across the corpus, optimization often shifts constraints among computation, triggering, communication, energy supply, and availability rather than eliminating them. Wildlife Edge AI should therefore be evaluated as a complete field system under application-relevant conditions.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16040047

Authors: Pavel Kyurkchiev Anton Iliev

Mathematical expression evaluation is a critical component in high-performance software systems. Traditional state-dependent algorithms resist Single Instruction, Multiple Data vectorization, while managed runtime environments introduce Garbage Collection overhead. This paper presents a hybrid parsing pipeline that isolates sequential state operations from parallelizable tasks, combining a SIMD-accelerated lexical analyzer with a vector evaluator that allocates no managed memory in its inner loop. Against established .NET evaluators the pipeline leads only below a few hundred evaluations of a given expression (approximately 230 on AMD and 310 on Intel), above which compiling once to a delegate dominates, and vectorized tokenization inverts beyond roughly thirty thousand characters of input. AVX-2 (Vector256) instructions reduce the isolated evaluation of a seven-operand reference expression to 69.30 ns with zero bytes allocated, while the complete pipeline allocates 1216 bytes and remains subject to generational collection. Under a fixed duty cycle holding delivered work constant, active-state residency falls from 69.1% to 51.6% and package energy falls by 15.9%, a measured effect rather than an inferred one. Benchmark-synchronized power instrumentation shows that the energy cost of wider vectors on AMD Zen 4 is expressed in time rather than in power. On both platforms 512-bit packed operations essentially retain the latency of their 256-bit counterparts but consume twice the issue slots. In the evaluation workload they take longer. Where lanes are fully occupied and operations independent, the ordering reverses and the 512-bit path draws less power and consumes 23.8% less energy per element. Power and energy were measured on the AMD platform only. The Intel platform supports the latency and allocation comparison.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16040046

Authors: Xinxin Pan Dongxv Xiao Jiacong Wu Henghai Cai Yixuan Xuan

Polynomial fitting is widely used for analog circuit calibration but is sensitive to polynomial order and can become numerically unstable at high orders. This paper presents a systematic comparison between a lightweight Gradient Boosting Decision Tree (GBDT) approach and classical interpolation methods for analog circuit calibration, using two case studies: a 0–100 dB variable-gain amplifier (VGA) and a low-dropout regulator (LDO) under three operating conditions. Unlike prior work that reports only fitting accuracy, we evaluate predictive generalization using leave-one-out and repeated random hold-out validation, with all hyperparameters selected on the training set only. The experimental results show that method selection depends critically on data characteristics and that the advantage of GBDT is far less general than commonly assumed for the smooth one-dimensional calibration datasets investigated in this work. On smooth, one-dimensional calibration data—including the VGA and all three LDO sweeps—polynomial fitting, piecewise-linear interpolation, and cubic splines consistently achieve lower held-out error than GBDT. For example, on the VGA dataset, the held-out MAE of GBDT is 1.02 dB, whereas polynomial fitting achieves 0.0072 dB and piecewise-linear interpolation 0.0055 dB. GBDT does not provide a systematic advantage under sparse sampling in the one-dimensional cases studied here; its apparent zero-error behavior in earlier fitting-only evaluations is shown to reflect training-set memorization rather than predictive accuracy. The trained GBDT models remain lightweight (97–250 KB) with sub-millisecond inference time, but on the smooth, low-dimensional data considered in this work, classical interpolation methods are the preferred choice. This work provides practical, data-driven guidance for method selection in analog circuit calibration and clarifies the conditions under which tree-based models are and are not appropriate.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16040045

Authors: Heng-Hai Cai Kai-Zhe Su Dong-Xv Xiao Xin-Xin Pan

This paper presents the implementation and post-layout evaluation of a source-follower-buffered CMOS low-dropout regulator in a 0.18 μm process. The design combines an error amplifier, a cascode bandgap reference, a source-follower buffer, a PMOS pass device, and resistive feedback. The extracted RC evaluation uses an ideal 4.7 μF output capacitor. At the typical process corner, 27 °C, and a 3.0 V input, the simulated output decreases from 1.80446 V to 1.79236 V as the load increases from 0 to 500 mA, corresponding to a load-regulation magnitude of approximately 0.02420 mV/mA. A post-layout STB sweep at 11 loads and three process corners gives a minimum defined sampled phase margin of 21.04° at SS and 150 mA. At SS and 500 mA, the DC output drops to approximately 1.646 V and the loop gain has no 0 dB crossing, so conventional phase and gain margins are undefined. At 300 mA, the integrated output noise is 1.339 mVrms over 1 Hz–100 MHz, with the bandgap reference accounting for 95.68% of the simulated integrated noise power. The results reveal load-dependent stability and regulation limitations; the 500 mA nominal-corner result is not a process-independent rating. Silicon measurements and comprehensive statistical and physical-reliability verification remain outside the demonstrated scope.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16040044

Authors: Papavarin Wathoy Chatrpol Pakasiri Sen Wang

This article presents the design and analysis of a three-way wideband Wilkinson power divider using a lump-type transmission line circuit instead of quarter-wave transmission lines, and a two-section cascaded lumped transmission line circuit technique instead of a single-section lumped transmission line to improve bandwidth efficiency. The proposed circuit is analyzed using even-mode and odd-mode techniques to find the synthesized parameters. Due to the design challenges in X-band applications, parasitic capacitors play a crucial role in layout design. This work presents a parasitic extraction method using the Y-parameter to analyze the layout of each input/output port. The layout is designed to be compact at (0.03λ0 × 0.03λ0) on 0.12 um GaN on SiC Technology. The resulting measurement yields a −10 dB fractional bandwidth of 80.39%, while the amplitude and phase balance are 0.1 dB and 5.8° (−13 dB fractional bandwidth of 52.4%, while the amplitude and phase balance are 0.04 dB and 4.9°). Overall, the circuit is compact and provides good performance for X-band frequency applications.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16040043

Authors: Akram Refaei Sebastien Genevey Yves Audet Yvon Savaria

Radio-frequency (RF) energy harvesting for Internet of Things (IoT) nodes must combine low-power sensitivity, efficient conversion over variable input levels, and a stable load supply. This paper presents a 900 MHz adaptive harvester that integrates complementary three-phase and varactor-based ladder rectifiers with self-powered, voltage-based path selection, dual undervoltage lockout, storage control, and capacitive buck–boost regulation. The ladder rectifier supports low-input-power harvesting, while the three-phase rectifier provides higher efficiency as input power increases. Post-layout simulations of the GF 22FDX implementation investigate −30 to 0 dBm within an active area of 0.017 mm2. Under matched 50 kΩ conditions, the higher-efficiency envelope of the individual rectifier curves extends the predicted interval with power conversion efficiency (PCE) ≥ 15% from 17.0 to 25.8 dB. Sensitivity is −11 dBm at 1 V, and peak PCE is 24% at −5 dBm and 1.9 V. The power management unit targets 0.6 V across 50 kΩ, with stored energy supporting delivery when harvested power is insufficient. Converter settling times range from approximately 0.2 µs in boost mode to a maximum of 3.6 µs in buck mode. These results demonstrate a compact architecture combining adaptive RF conversion with coordinated power delivery for IoT sensing.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16040042

Authors: Banafsheh Saffari Kye-Shin Lee

This work describes a compact transistor model-based low-power CMOS analog circuit design methodology using particle swarm optimization (PSO). The proposed approach replaces the actual transistor-level circuit with equations that represent the DC and AC characteristics and performance of the circuit block. As such, the optimization engine can directly use the equations to find the optimum design variables, including the transistor size (W, L) and operating conditions (ID, VGS, VDS). In this way, circuit simulation is not required for each optimization step, which leads to significant design time reduction. For concept validation, an actual design of a two-stage amplifier that meets the required performance for DC gain, GBW, PM, and slew rate under minimum power consumption using CMOS 65 nm technology has been performed, where the proposed design framework led to a DC gain of 67.13 dB, a GBW of 50.21 MHz, a PM of 58.08°, and a slew rate of 28.7 V/μs under power consumption of 45.39 μW with 16,000× and 1198× optimization time reduction compared to conventional PSO and parallel PSO.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16040041

Authors: Meiyan Chen Jinru Ou Yue Zhang Xuan Liu Ke Yao Xueping Geng Deli Tang Wei Zou Fanya Jin Jun Zhou

Polytetrafluoroethylene (PTFE) is an important dielectric and structural substrate for high-frequency, flexible, low-background, and other electronic systems because of its low dielectric loss, high electrical resistivity, low moisture absorption, chemical inertness, and thermal stability. However, its fluorine-rich surface, low surface energy, and weak boundary layer hinder metal nucleation and interfacial bonding, frequently leading to discontinuous film growth, high interfacial resistance, and premature delamination. This focused review summarizes recent progress in low-temperature plasma-assisted metallization of PTFE, with particular emphasis on the relationships among plasma activation, interface formation, electrical functionality, reliability, and manufacturability. The effects of plasma-induced physical etching, defluorination, radical generation, polar functionalization, weak-boundary-layer removal, and hydrophobic recovery are first discussed. Representative metallization routes are then reviewed, including direct physical vapor deposition, plasma-assisted electroless plating, plasma-induced grafting, metallic interlayers, ion implantation, and hybrid plasma-deposition processes. Particular attention is given to interface-strengthening mechanisms involving chemical bonding, mechanical interlocking, diffusion control, carbon-rich or graded transition regions, and interdiffusion. The key trade-offs among adhesion strength, conductor resistance, dielectric integrity, surface-modification stability, and mechanical or environmental reliability are further analyzed for electronic-substrate applications. Although metallic interlayers, ion implantation, and hybrid processes can provide more stable interfaces than plasma activation alone, challenges remain in controlling plasma-induced damage, surface aging, interfacial carbonization, and process reproducibility. Recent 2024–2026 studies further show that these interface technologies can translate into low-loss Cu/PTFE laminates, flexible circuits, integrated vacuum metallization stacks, and selectively patterned conductors. The relevance to low-power systems is therefore treated as one application context at the substrate/interconnect level rather than as evidence that PTFE metallization directly reduces circuit switching power.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030040

Authors: Quentin Vermot des Roches Emilie Avignon-Meseldzija Anthony Kolar Caroline Lelandais-Perrault Delphine Mika David Boulate Frédéric Perros Philippe Benabes

This article proposes a new integrated analog implementation of the Pan–Tompkins algorithm. This algorithm, generally implemented in the digital domain at the cost of higher power consumption, is one of the most efficient for QRS detection in electrocardiographic signals. This circuit has been designed for use on small mammals like rats for the study of pulmonary arterial hypertension. The specificities of the architecture proposed in this article are a sub-threshold-operated architecture to perform the amplification, noise filtering, and differentiation of the signal in a unique block to limit the power consumption; an analog squarer; and an analog monostable reshaping-circuit followed by a digital counter clocked by an ultra-low power relaxation oscillator. Compared with the state of the art, this circuit, designed with the X-FAB xh018 180 nm CMOS technology, presents one of the lowest power consumptions currently reported, at 28.5 nW, 76% of which is consumed in the current, voltage, and time references. Post-layout simulation results show a reliable 98.57% heart beat detection accuracy using the MIT-BIH arrhythmia database and 99.85% accuracy for healthy sinus rhythm electrocardiograms. The robustness of the circuit is also investigated, and mitigating solutions are proposed for each critical block.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030039

Authors: Meiyan Chen Yue Zhang Xuan Liu Li Zhong Ke Yao Xueping Geng Jinru Ou Deli Tang Fanya Jin Jun Zhou

Reliable Cu/polyimide (PI) metallization requires strong interfacial adhesion while minimizing the thickness of the metallic adhesion layer. In this study, Ni ion implantation was combined with physical vapor deposition to construct an ultrathin Ni interlayer on a 25 μm-thick PI substrate. Three metallization schemes were compared: 20 nm Ni/2 μm Cu, 10 nm Ni/2 μm Cu, and Ni-ion-implanted PI/5 nm Ni/2 μm Cu. Ni ions were implanted at an energy of 5 keV and a fluence of 1 × 1014 ions cm−2. The implantation treatment decreased the water contact angle of PI from 75° to 64° and increased its surface free energy from 36.41 to 42.99 mJ m−2, primarily through an increase in the polar component. Surface observations showed uniformly distributed implantation-associated micro/nanostructures with characteristic dimensions of approximately 50–300 nm, which may provide additional nucleation and anchoring sites for the subsequently deposited Ni layer. Cross-sectional transmission electron microscopy showed an undulating, locally embedded Ni/PI interface, while elemental profiles were consistent with a gradual transition across the modified interfacial region. The Ni-ion-implanted sample with a 5 nm Ni interlayer exhibited an average 180° peel strength of 1.13 N mm−1, compared with 0.62 and 0.30 N mm−1 for the 20 and 10 nm Ni interlayers, respectively. It also showed the lowest measured sheet resistance of 3.25 mΩ sq−1. Taken together, these results suggest that, under the conditions examined, Ni ion implantation can support a reduction in deposited Ni thickness while maintaining or improving the adhesion and electrical performance of Cu/PI metallization.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030038

Authors: Punmanut Meedech Sen Wang Chatrpol Pakasiri

This paper presents a wideband circularly polarized (CP) stacked patch antenna for 5G Sub-6 GHz applications. A major challenge in wideband dual-feed antennas is the fabrication limit caused by standard chemical etching and mechanical milling processes for extremely narrow high-impedance microstrip lines in two-stage branch-line couplers. To overcome this bottleneck, a Defected Ground Structure (DGS) is utilized. By etching the ground plane, the distributed inductance is increased, allowing the highly sensitive narrow traces to be physically widened while strictly maintaining the 50 Ω impedance. The antenna features an aperture-coupled mechanism via an H-shaped slot to excite the driven and parasitic patches, which are separated by an air gap to maximize bandwidth. The fabricated prototype demonstrates an impedance bandwidth (|S11|<−10 dB) of 41.6% (2.92–4.37 GHz) and a simulated 3 dB axial ratio bandwidth of 23.14% (3.26–4.07 GHz) with a peak realized gain of 7.54 dBi. Excellent agreement between simulated and measured results validates the robustness of the proposed DGS technique against fabrication tolerances.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030037

Authors: Raed Daraghma

Massive Multiple-Input Multiple-Output (MIMO) is a key enabling technology for fifth-generation (5G) and beyond wireless communication systems because of its ability to greatly enhance both spectral efficiency (SE) and energy efficiency (EE). However, maximizing these two performance metrics simultaneously remains a challenging multi-objective optimization problem due to the conflicting effects of the transmit power, antenna deployment, and circuit power consumption. This paper investigates the EE–SE trade-off in a downlink Massive MIMO system with Minimum Mean Square Error (MMSE) channel estimation (CE) and different linear combining and precoding techniques. A power optimization framework based on transmit power allocation and antenna configuration is analyzed to identify operating points that maximize EE while maintaining high SE. Performance analysis of the number of base station (BS) antennas in MIMO systems, user equipment density, transmit power, and inter-cell interference on system performance is evaluated through numerical simulations. The results demonstrate that appropriately selecting the number of transmit antennas and optimizing the transmit power significantly improve the EE–SE trade-off. Furthermore, although increasing the number of antennas enhances SE, EE exhibits a non-monotonic behavior because of the additional circuit power required by the radio-frequency hardware. The findings confirm that MMSE-based CE provides higher spectral efficiency than the MR, ZF, RZF, and S-MMSE schemes, albeit at increased computational complexity, offering useful design guidelines for energy-efficient Massive MIMO networks.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030036

Authors: Rúben Teixeira João Barreiros Rodrigues Jaime Aguiar Jiao Li José T. de Sousa

Edge inference on resource-constrained embedded nodes demands accelerators that are energy-efficient and compact. This paper presents Versat-AI, an open-source compiler that accepts a standard Open Neural Network Exchange (ONNX) model and generates a complete, synthesisable RISC-V System-on-Chip (SoC) with an embedded CGRA accelerator. The key innovation is applying a known hardware merge strategy to collapse structurally compatible neural network operators into a physical CGRA instance. The Versat-AI compiler also derives memory-mapped interconnects, firmware drivers, and RISC-V application software co-generated by the Py2HWSW SoC framework, eliminating the manual hardware/software co-design effort that previously tied this accelerator’s own design lineage to a single target network. The next phase of the project is to extend this same automatic derivation from sizing the operator vocabulary to sizing per-operator parallel instancing and bandwidth, following the bandwidth-matched scaling principle already demonstrated, by hand, in this accelerator’s own design lineage. The current phase of the project has succeeded in creating a sound automation flow that produces an accelerator that maps each operator onto a single physical datapath instance and occupies 8763 LUTs, 9833 flip-flops, 4 DSPs, and 202 BRAMs on a Xilinx Kintex UltraScale field-programmable gate array (FPGA)—a footprint unchanged across all evaluated models regardless of size—and draws 0.65 W (1.96 W for the complete SoC including the DDR4 controller, by Vivado post-implementation power estimation), achieving 2.3× to 9× speedup over the software-only baseline produced by the same flow on four MLPerf Tiny benchmark tasks. The paper further examines the design choices that delimit this first phase—single-precision arithmetic, a single datapath instance per operator, and the block-RAM cost of the accelerator’s streaming buffers—and sets out the path to quantised integer support and parallel operator instancing. A condensed account of the two-decade lineage of reconfigurable accelerators and open-source SoC platforms that motivated Versat-AI’s design is also given.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030035

Authors: Mrinalini Joshi-Pangaonkar Pratibha Shingare

This paper presents an FPGA (Field-Programmable Gate Array) implementation of a low-power VLSI (Very Large-Scale Integration) architecture for medical image scaling in portable diagnostic systems. The proposed architecture employs bilinear interpolation optimized through FSM (Finite-State-Machine)-based control, a clock-enable technique, and selective block activation to reduce switching activity and dynamic power consumption while preserving image quality. The architecture is described in Verilog HDL, synthesized using Vivado 2024.1, and implemented on the Xilinx Zynq-7000-based ZedBoard platform. A controlled post-implementation power analysis on the same FPGA platform demonstrates a reduction in estimated total on-chip power from 3.739 W for the unoptimized baseline architecture to 1.053 W for the optimized architecture, corresponding to an approximately 71.8% reduction. The system supports multiple operational modes, including original image display, grayscale conversion, Sobel X filtering, and Sobel Y filtering, providing enhanced diagnostic flexibility. Quantitative assessment of the exemplary X-ray Image 1 yielded PSNR (Peak Signal-to-Noise Ratio) of 42.97 dB and SSIM (Structural Similarity Index) of 0.9557, demonstrating satisfactory image-quality preservation after scaling. The proposed architecture demonstrates the feasibility of low-power FPGA-based medical image scaling for portable diagnostic and telemedicine imaging systems, offering an effective balance between energy efficiency and image fidelity.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030034

Authors: Tanvi Mishra Manoj Tolani Gaurav Suman Himanshu Chaudhary Pankaj Kumar Simmi Sharma

Battery-powered IoT sensor nodes require energy-efficient Medium Access Control (MAC) protocols to extend network lifetime while supporting priority-sensitive traffic. This paper proposes a Priority-Aware Packet Aggregation/Piggybacking-Based (Priority + Packet Aggregation) Hybrid Energy-Efficient MAC (P2A-HMAC) protocol that integrates bit-mapped priority signaling with lightweight packet aggregation/piggybacking to reduce control overhead. The protocol classifies traffic into emergency, buffer-overflow, priority, and normal categories, providing guaranteed access to delay-sensitive data while minimizing radio activity, idle listening, and contention. A mathematical energy model is developed for both priority- and contention-based operations. MATLAB-based evaluation demonstrates that P2A-HMAC consistently achieves lower energy consumption than TDMA, EA-TDMA, ASHMAC, E-BMA, and P2A-HMAC across varying network sizes, packet sizes, and event-generation probabilities. The proposed protocol provides substantial energy savings, particularly in large-scale and moderate-traffic networks, while maintaining priority-aware communication and QoS, making it suitable for low-power IoT and wireless sensor network applications.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030033

Authors: Jian Yang Yanfeng Jiang

Physical unclonable functions (PUFs) convert device-specific physical variations into responses for chip identity, key reconstruction, secure boot, and hardware roots of trust. This review examines the complete PUF chain from entropy generation and response digitization to stabilization, post-processing, deployment, security evaluation, and low-power implementation. Mature CMOS delay, SRAM, and DRAM PUFs are treated as engineering baselines, while representative emerging-memory PUFs provide comparison points for a MRAM-centered analysis. The main focus is placed on MRAM PUFs, including static MTJ variation, stochastic STT/SOT switching, response digitization and stabilization, reconfigurability, magnetic-specific attack surfaces, and system integration. The main contents include MRAM-PUF energy costs across device operation, raw-response generation, response stabilization, key reconstruction, and complete authentication. This cross-layer perspective distinguishes cell-level read/write energy from repeated sampling, reliable-bit-selection, ECC/KDF, controller, retry, and reconfiguration overheads. MRAM offers distinctive features including non-volatility, high endurance, and stochastic switching behavior. Their system-level energy benefits are treated as application-dependent and should be evaluated at the complete transaction level.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030032

Authors: Dwipak Prasad Sahu

Memristive devices have emerged as promising candidates for next-generation non-volatile memory and neuromorphic computing systems owing to their simple device architecture, low power consumption, and capability for analog conductance modulation. In this work, Fe2O3-incorporated TiO2 thin films were employed as the active switching layer to investigate their resistive switching and artificial synaptic characteristics. The fabricated Ag/TiO2 + Fe2O3/FTO device exhibits stable switching performance with a low operating voltage of approximately ±0.6 V, a large ON/OFF ratio of ~103, retention of nearly 104 s, and endurance over 5000 pulse cycles, representing a significant improvement compared with pristine TiO2 devices. Electrical transport analysis demonstrates Schottky emission-dominated conduction in the high-resistance state and Ohmic conduction in the low-resistance state. Furthermore, analog switching behavior was achieved by operating the device under a higher compliance current, demonstrating gradual conductance modulation and synaptic weight update characteristics, indicating the potential of the device for neuromorphic applications. These results demonstrate that Fe2O3 incorporation provides an effective approach for simultaneously enhancing memory performance and synaptic functionality in TiO2-based memristors, highlighting their potential for future memory and neuromorphic computing applications.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030031

Authors: Kai-Ting Huang You-Wen Fan Jung-Yi Lin Chien-Lung Chen Yen-Chih Yeh Yu-Chen Ou Li-Chen Lin Yu-Hsien Lin Guang-Li Luo Yung-Chun Wu Fu-Ju Hou

In this work, a plasma-free atomic layer deposition (ALD)-based H2O post-treatment method is proposed to precisely modulate hydrogen-related (H-related) traps in indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) by the number of H2O treatment cycles. Under the optimized condition, the scaled device with a channel length of 70 nm exhibits a near-ideal subthreshold swing of 62.9 mV/dec, a low threshold voltage (VTH) of 0.18 V, an acceptable static leakage current, and a high drive current of 3.29 μA/μm at an overdrive voltage and drain voltage of 1 V. In addition, the treated device shows only a 13 mV of VTH shift after 1000 s positive bias stress (PBS), corresponding to a 94% improvement compared with the pristine device. These improvements are attributed to the introduction of two different polarities of hydrogen-related traps after H2O treatment. Furthermore, the influence of H-related traps on bias stability and the mechanisms responsible for VTH shift are systematically clarified. These results establish that an optimized hydrogen incorporation window that maximizes the beneficial effects while balancing severe hydrogen-induced degradation caused by excessive hydrogen incorporation. Consequently, scaled IGZO TFTs with fast switching, low-power operation, high performance, and high reliability can be achieved, providing strong potential for back-end-of-line (BEOL)-compatible electronics and monolithic three-dimensional integrated applications.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030030

Authors: Joel Artemio Morales-Viscaya Martin Moreno Alberto Traslosheros-Michel H. J. Vergara-Hernández

This paper proposes a sensorless current estimation method for piezoelectric energy harvesting (PEH) systems using a first-order Takagi–Sugeno fuzzy system. Unlike invasive current sensing, the proposed estimator uses only non-invasive measurements: output voltage VO, its derivative V˙O, and load resistance RL. The fuzzy rules are initialized directly from the physical equivalent circuit parameters and trained via the ANFIS on a large-scale dataset (78 million samples). The proposed model achieves a mean coefficient of determination R2=0.9999 (95% CI: [0.99989, 0.99991]), root mean square error RMSE=3.12×10−8 A, mean absolute percentage error MAPE = 2.51% (95% CI: [1.98, 3.04]%), and fitness FIT = 98.98%—outperforming multiple linear regression (R2=0.9738 and MAPE = 116.25%) and a shallow neural network with 211 parameters (R2=0.9991 and MAPE = 13.85%) despite having only 170 trainable parameters. Unlike black-box neural networks, the fuzzy model provides interpretable rules whose consequent parameters map directly to physical quantities (effective capacitance Cp(eff) and leakage conductance 1/Rp(eff)). The low computational footprint (170 parameters, <5 μs inference, and ≈1.4 kB of memory) makes it suitable for real-time deployment on low-power microcontrollers. These results demonstrate the viability of the proposed approach under controlled laboratory conditions for the single, series, and parallel PEH configurations considered. This work establishes that physically informed fuzzy modeling is a viable, interpretable, and efficient alternative to deep learning for sensorless monitoring in low-power energy harvesting systems.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030029

Authors: Erick Iván Barros de la Cruz Juan David Salazar Cardona Maria Teresa Sanz-Pascual Nicolás Medrano Belén Calvo

This paper presents a low-power fully integrated sine signal generator for on-chip bioimpedance spectroscopy applications. The circuit is based on a relaxation oscillator, which generates a triangular signal, followed by a sixth-order Gm-C bandpass filter (BPF) that linearizes the waveform. Both blocks, designed in a 0.18 μm CMOS process with 1.8 V supply, make use of a current division technique to generate low-frequency signals without requiring high-valued passive components. The relaxation oscillator features an extended frequency tuning range from 300 Hz to 300 kHz, controlled via a tuning current and a digital capacitor bank. The sine output waveform spans from 1 kHz to 50 kHz, and exhibits a −48.8 dB total harmonic distortion at 10 kHz with 18 mV amplitude. The overall system area is 0.7 mm2 and the power consumption is lower than 30 μW.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030028

Authors: Alishba Masood Muhammad Khurram

Recent advances in biologically inspired neural computation have sparked increasing interest in developing hardware-efficient architectures capable of emulating brain-like cognitive abilities like low power consumption and less inference latency. However, significant hardware overhead and spike-processing complexity remain major challenges in FPGA implementations of spiking neural networks. In this work, we propose a sparse spike-aware and weight pruning FPGA architecture based on LIF neurons that minimizes spike activity and synaptic operations through pruning-aware event-driven computation. The proposed sparse spike-aware SNN architecture was evaluated using the Iris dataset. The dataset was divided into 80% training and 20% testing samples. Pre-trained weights obtained from software-level training were deployed onto the FPGA-based LIF classifier. Classification accuracy was computed by comparing predicted output spikes against ground-truth class labels. Experimental results demonstrated that the proposed architecture achieved an overall classification accuracy of 93.3% while maintaining low hardware resource utilization and reduced power consumption. Moreover, the implementation achieves superior energy efficiency, consuming only 3.5 W total on-chip power and utilizing 587 logic cells, confirming its suitability for compact, real-time edge computing neuromorphic applications.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030027

Authors: Xu Wang Guanyu Fu Zhiwei Xu Yuelong Zhang Junchao Zhang Yinlong Zhu Ying Liu

Achieving precise microstructure control in composite dielectric layers remains a key challenge for enhancing the sensitivity and reducing the power consumption of flexible capacitive sensors. In this work, an ultrasonic needle-induced acoustic streaming strategy is proposed to regulate the spatial distribution of Fe particles within a silicone matrix, enabling controllable particle migration and aggregation in liquid silicone. Multiphysics simulations reveal that, at an excitation frequency of 75.49 kHz, Fe particles are effectively driven toward the ultrasonic focal region, forming a tunable microstructure. Experimental results confirm that this method enables precise morphological control of the composite dielectric layer. The composite with 25 wt% Fe exhibits the highest measured relative permittivity of about 3.45, enabling a capacitive sensor sensitivity of 0.423 kPa−1 in the 0–1 kPa range. After acoustic-streaming optimization and integration into a four-unit capacitive array, the device achieved 0.509 kPa−1 sensitivity, retained 92.04% of its response after 5000 cycles at 3 kPa, and maintained 97.8% of its initial capacitance after 24 h. The proposed approach provides an effective route to improving sensor performance through microstructure engineering while maintaining low electrical loss. This work not only advances the design of high-performance functional composites but also expands the application of acoustic streaming techniques in low-power flexible electronics.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030026

Authors: Mrittika Chowdhury Ziyi Niu Shuai Song Anurag Dhungel Md Sakib Hasan

In this work, we present a systematic framework to optimize robust 1-D chaotic maps, focusing on expanding the uninterrupted chaotic region and enhancing chaotic properties throughout the entire parameter space. To achieve these objectives, we propose three distinct techniques, each involving systematic manipulations of chaotic seed maps. These manipulations include shifts and operations such as multiplication and division, which result in significant improvements in their chaotic characteristics. The effectiveness of the proposed methods is demonstrated through a comprehensive analysis using bifurcation plots, the maximum Lyapunov exponent, the correlation coefficient, Shannon entropy, the average Lyapunov exponent, and the chaotic ratio. The results illustrate the attainment of an extensive and uninterrupted chaotic range, alongside enhanced chaotic behavior due to the application of shifted maps. Additionally, in this work we also investigate the impact of combining general shifted maps with halfway-shifted maps, showing that their product leads to further improvements in chaotic properties and their division widens the chaotic ratio. In the last proposed method, the combined product division (CPD) maps achieve the highest overall performance, attaining a maximum Lyapunov exponent of 1.3567 and an average Lyapunov exponent of 1.3498, while maintaining a perfect chaotic ratio (CR = 1) across the entire parameter space. To demonstrate hardware feasibility, some of the proposed maps were also implemented on an FPGA, and the results were compared with MATLAB R2022b simulations. The close match between the two validates the practicality of implementing these chaotic systems in hardware. The proposed techniques have potential applications in areas such as random number generation, chaos-based cryptography, and secure communication, among others. To prove this, the optimized maps are leveraged to design a chaos-based pseudo-random number generator (PRNG) that passes statistical tests including NIST SP 800-22 (all 15 sub-tests passed) and TestU01 (38/38 Rabbit, 17/17 Alphabit, 102/102 BlockAlphabit), validating cryptographic-grade randomness.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030025

Authors: Kaijun Song Hanzhou Luo Yuting Yuan Yong Fan

This paper presents a compact, ultra-wideband (UWB) antenna designed for low-power wireless systems requiring upper WLAN (5.725–5.825 GHz) interference mitigation. The antenna integrates a tapered-slot radiator for broadband impedance matching with a dual C-shaped slot resonator on the ground plane to achieve targeted signal rejection. By leveraging the resonant properties of the slots, interference from the WLAN band is suppressed without requiring any active components, ensuring zero additional power consumption for the filtering function. The fabricated prototype, with a compact size of 31 × 40 mm2, demonstrates an operational bandwidth from 2.68 to 16 GHz (S11 < −10 dB) with a stable peak realized gain of 2–10 dB and a radiation efficiency above 80% across the passband. At the notch center frequency of 5.72 GHz, the gain decreases by 6.4 dB and the radiation efficiency falls to 0.6, there is effective signal rejection in the target notch band, and there are stable, omnidirectional H-plane radiation patterns. The reflection coefficient at the notch frequency rises to approximately −2.2 dB, effectively suppressing radiation in the WLAN band while maintaining stable gain and omnidirectional patterns in the remaining UWB spectrum. The proposed design offers a simple, low-cost, and energy-efficient solution for achieving spectral coexistence in power-constrained UWB applications.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030024

Authors: Tymoteusz Miller Irmina Durlik

The proliferation of Internet of Things (IoT) devices operating at the network edge has created unprecedented demand for distributed machine learning capable of functioning under severe resource constraints. Federated learning (FL) has emerged as a promising paradigm for privacy-preserving collaborative model training across distributed nodes; however, its application to energy-constrained edge environments remains insufficiently characterized at the system level, particularly with respect to reproducible evaluation of resource consumption and communication efficiency. In this paper, we present EcoFL (Energy-Conscious Federated Learning), a modular, energy-aware benchmarking and orchestration framework for systematic evaluation of lightweight machine learning models under emulated edge hardware constraints. Rather than proposing a new federated optimization algorithm, EcoFL extends a standard FedAvg-based training pipeline with three principal components: (i) an energy-aware communication scheduler that dynamically adapts aggregation rounds and client participation based on per-node resource availability; (ii) a comprehensive system-level profiling pipeline capturing CPU utilization, RAM consumption, inference latency, communication overhead, and estimated computational energy consumption per training round; and (iii) a reproducible benchmarking methodology enabling fair comparison of centralized, standard federated (FedAvg), and energy-aware federated configurations. We evaluate five lightweight model families—Logistic Regression, Random Forest, XGBoost, Multilayer Perceptron, and Isolation Forest—under emulated Raspberry Pi 4 hardware constraints using an anomaly detection task on synthetic IoT sensor telemetry (50,000 samples, 12 features, Dirichlet non-IID partitioning). Experimental results across five independent seeds show that, within the evaluated benchmark setting, EcoFL reduces estimated federated training energy by 79.9–92.9% (mean 84.4%) relative to standard FedAvg through adaptive round termination (4–7 rounds versus 20 fixed rounds), while showing no statistically significant F1-score degradation for four of the five evaluated model families under the tested seed regime. Notably, EcoFL achieves a higher F1-score than FedAvg for Random Forest (+0.052), which we attribute to reduced overfitting resulting from earlier convergence under non-IID data distributions. The full EcoFL framework is released as open-source software to promote reproducibility in energy-aware federated learning research and to facilitate systematic investigation of the trade-offs between predictive performance, resource utilization, and communication overhead in resource-constrained edge environments.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030023

Authors: Tao Zhang Yao Zhang Yufeng Zhang Zhonghua Yao Yunhong Shao

This paper proposes a practical heuristic engineering strategy for automated capacity allocation in a multifunctional parallel active power filter (PAPF) that simultaneously provides harmonic and reactive power compensation. Unlike theoretically optimal methods, our approach prioritizes real-time feasibility and ease of implementation. The key features are: (1) an event-triggered, closed-loop THD-feedback mechanism that dynamically recalculates the minimum active power required for harmonic compensation only when the load harmonic content changes, avoiding periodic computational waste; (2) a strict priority handling that guarantees grid current THD below 5% (IEEE-519 compliant) under all operating conditions, even when capacity is severely insufficient; (3) a closed-loop transition mechanism that uses measured grid current THD and remaining capacity as feedback inputs to continuously adapt power distribution. The proposed rule-based strategy does not claim theoretical optimality but provides a verifiable, ready-to-implement solution with experimental evidence. Simulation and experimental results on a three-level NPC PAPF prototype demonstrate that the strategy maintains grid current THD below 5% while keeping the apparent power within the rated capacity, achieving near-optimal reactive compensation (92–96% of the optimum) without iterative optimization. The experimental validation includes efficiency measurements, switching-loss estimation, DSP timing analysis, and robustness tests under grid disturbances. Future work will extend the concept to multi-inverter systems using multi-objective optimization and AI-based allocation.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16030022

Authors: David Ng King Hang Lam Si Qi Bu Wen Chin Lo Chi Hong Chan Roy Ng Sunny Chan Matt Mak Hugo Wong Steve Chim Patrick Chang Raymond Chik Steven Wong Wai Ming To

Analog in-memory computing (AIMC) has emerged as a promising approach to mitigate the Von Neumann bottleneck in matrix operations, which are common in deep learning applications. However, the practical implementation of resistive crossbar arrays is limited by challenges in signed weight representation, conductance quantization, and device nonlinearity. This paper presents a differential mixed-signal architecture for accurate signed matrix–vector multiplication (MVM), integrated with a RISC-V microcontroller for edge inference applications. A structured digital-to-analog mapping framework encodes quantized neural network weights into programmable conductance values while preserving arithmetic correctness. The design employs voltage-mode input encoding, differential current summation, and transimpedance-based readout followed by analog-to-digital conversion, enabling single-cycle signed accumulation without duplicating crossbar resources. A 32 × 16 dual-layer prototype crossbar was fabricated and experimentally characterized. Measurements demonstrate a mean absolute percentage error (MAPE) below 1% within the linear operating region and below 4% over the full-scale conductance range. These results validate the robustness of the proposed mapping methodology and confirm the feasibility of hybrid analog–digital acceleration for edge AI systems. Consequently, this discrete prototype serves as a physical verification platform for the AIMC approach, providing valuable insights for more efficient mixed-signal computing integrated circuit (IC) designs.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16020021

Authors: Abrar Abdurrob Aristotelis Tsekouras Evangelos Tzouvaras Vasilis F. Pavlidis Emre Salman

The rapid growth of Deep Neural Networks (DNNs) has led to the development of application-specific DNN accelerators. Conventional 2D von Neumann architectures suffer from memory bandwidth limitations between the memory and the processing core. 3D DNN accelerators have emerged as a promising solution by leveraging 3D integration to enable near-memory logic or in-memory computation. By shifting computation closer to memory, these accelerators significantly reduce data movement and therefore latency, resulting in more energy-efficient operations. Monolithic 3D (M3D) integration, in particular, enables high-bandwidth systems by utilizing high-density monolithic inter-tier vias (MIVs). This paper provides a critical review of recent advances in 3D DNN accelerators that combine near-memory and compute-in-memory with various 3D technologies, offering a useful discussion and future prospects of the available technologies and architectures that have advanced the performance of DNN accelerators. Particular attention is devoted to accelerators for emerging transformer-based large language model (LLM) networks due to the higher memory demands. Thermal-aware design techniques of 3D DNN accelerators are also discussed as a means to address the fundamental challenge of heat dissipation. A detailed review is finally conducted on package-level constraints, considering signal integrity, power delivery, and thermo-mechanical reliability.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16020020

Authors: Jegan Rajendran Nimi Wilson Sukumari Manikandan Rajendran

The increasing demand of digital technologies and their integration with wearable health devices provides an efficient trigger for next-generation wearable healthcare devices for long-term physiological monitoring. The advancement of energy harvesting mechanism, nanomaterial-based sensor fabrication and their integration with digital technologies have emerged as a promising solution for transforming future of digital health. This study provides a comprehensive summary and framework for wearable self-powered electronic devices, enabling continuous, battery-free health monitoring and advancing the development of sustainable, next-generation digital healthcare systems. This review paper presents a broad and detailed overview of current technologies and sensors advancement in developing low-power wearable, self-powered electronic devices suitable for healthcare applications. The importance and reliable use of key energy harvesting approaches including triboelectric, piezoelectric, thermoelectric, and photovoltaic approaches are systematically presented which focused on development of energy efficient wearable devices. This review further examines the low-power circuit design strategies for flexible electronics focusing personalized healthcare monitoring. Current challenges and limitations related to advanced manufacturing of wearable health devices focusing on large-scale deployment are also analyzed. Finally, the key future research directions are outlined for advancing a next-generation intelligent digital health system.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16020019

Authors: Yen-Ying Peng Syu-Bin Li Sen Wang Chatrpol Pakasiri

This paper presents the design and implementation of an X-band voltage-controlled oscillator (VCO) fabricated in a standard 180-nm CMOS process. To sustain stable oscillation under a constrained power budget, a gm-boosted topology is employed, integrating vertically stacked cross-coupled transistors with a center-tapped transformer to enhance the equivalent negative conductance. The boosting is achieved through two complementary mechanisms: the center-tapped transformer performs an impedance transformation that repurposes the layout parasitic capacitances into transconductance-enhancing elements, while the stacked cross-coupled pair reuses the DC current and suppresses the source-degeneration of a conventional pair, jointly sustaining a robust start-up margin at a low 0.75 V supply. On-wafer measurement results demonstrate a frequency tuning range from 8.78 GHz to 9.13 GHz as the control voltage is swept from 0 V to 1.8 V, with an average VCO gain KVCO of 447.5 MHz/V. Under a total DC power consumption of 6.9 mW, the oscillator delivers an output power of 4.54 dBm and exhibits a measured phase noise of −103 dBc/Hz at a 1-MHz offset.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16020018

Authors: Larisa Goffman-Vinopal

AI accelerators increasingly operate under tight power, thermal, voltage, and timing margins, making workload-dependent thermal nonuniformity an important reliability concern. In systolic AI accelerators, localized activity concentration can create spatially uneven thermal stress, but thermal or timing-exposure analysis alone does not determine whether such stress remains benign, becomes numerically masked, or propagates into silent corruption. This paper presents a cross-layer early-stage screening methodology for thermal nonuniformity-aware reliability analysis in systolic arrays. The framework links workload-aware activity extraction, relative power concentration modeling, diffusion-based thermal proxy analysis, an explicit thermal-to-timing stress abstraction, path class-aware corruption modeling, and clean/masked/silent outcome classification. The revised framework is formalized mathematically and evaluated across dense, low-dynamic-range, and sparse GEMM workloads under weight-stationary and output-stationary execution. To strengthen statistical and methodological confidence, the study includes 100-seed corruption reruns with Wilson confidence intervals, thermal scaling across 8×8, 16×16, and 32×32 arrays, calibration sensitivity, path weight sensitivity, component ablations, and preliminary compact thermal reference alignment. The results show that sparse workloads consistently produce the largest thermal spread across tested array sizes, while dense and low-dynamic-range workloads remain more spatially uniform. Under the default calibrated screening regime at 16×16, sparse output-stationary and sparse weight-stationary cases reach 49% and 40% silent corruption rates, respectively, while dense cases remain mostly clean or masked and low-dynamic-range cases remain largely clean. Sensitivity and ablation experiments show that the sparse workload risk is not caused by one isolated modeling component, although the masked/silent split depends on path class weighting and thermal diffusion assumptions. The main contribution is not signoff-accurate silicon failure prediction, but a reproducible screening front end for identifying workload, dataflow, and path class combinations that deserve deeper thermal, timing, RTL-level, and application-level validation.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16020017

Authors: Thi Phuong Ha The Khai Chu Van Tung Nguyen Orazio Aiello Xuan Thanh Pham

This paper introduces a novel analog-to-digital converter (ADC) employing a passive noise-shaping (NS) technique combined with a chopper-stabilized comparator, enhancing performance and reducing ripple factor while maintaining low power consumption. The NS architecture is built on a cascade-integrator feedforward (CIFF) structure, using both infinite- and finite-impulse response filters to minimize quantization and kT/C noise. Additionally, it employs a low-power two-stage chopper amplifier to compensate for the offset voltage and enhance system stability. Validated according to the 180 nm CMOS process, the proposed ADC has an effective number of bits of 10.6, a signal-to-noise-and-distortion ratio of 68.4 dB, and a signal-to-noise ratio of 59.33 dB. With a compact area of 0.17 mm2 and a power consumption of 650 µW from a 1.8 V supply, the proposal is well suited to biomedical sensor applications requiring strict accuracy and low energy consumption.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16020016

Authors: Mohammad Okour Mohannad Alkhalil Mutaz Al Fayad Juhyun Bak Kevin R. James Sulaiman Mohaidat Xiaoqi Liu Fadi Alsaleem Michael Hempel Hamid Sharif-Kashani Mahmoud Alahmad

Accurate estimation of lithium-ion battery State of Health (SoH) is critical for emerging applications such as reconfigurable battery systems. Although data-driven machine learning methods are promising, they often rely on costly, time-intensive aging experiments and extensive feature engineering. This work proposes a lightweight SoH-prediction framework validated on both physics-informed synthetic aging data and the NASA battery aging dataset. We evaluated Random Forest (RF) and Feedforward Neural Network (FNN) models that use only a limited number of samples from an early segment of the raw discharge voltage curve as input. Results show that RF consistently outperforms FNN across input sizes in deterministic or noise-free environments, achieving an RMSE of 0.07% SoH using just 5 voltage samples. In inherently stochastic experimental data, however, FNN can achieve an RMSE 50% lower than RF (1.28 vs. 2.87), but requires 37× more mathematical operations per inference. These findings emphasize the predictive value of the early-discharge-voltage region and demonstrate that compact, low-feature-complexity models can deliver accurate SoH estimates. Overall, the approach supports a goal of combining informed synthetic data with limited real measurements to build robust, scalable SoH predictors, reducing dependence on labor-intensive degradation testing and feature-heavy pipelines.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16020015

Authors: Nicolas Medrano Diego Antolin Daniel Eneriz Belen Calvo

The measurement of the magnetic field generated by a flowing current constitutes a non-invasive sensing technique for online energy consumption monitoring. In this work, based on the use of low-cost linear Hall effect sensors, a low-form-factor custom contactless ammeter probe is presented. The differential configuration of the sensor module and the subsequent fully digital programmability in range and sensitivity, together with the included self-calibration and compensation circuits for mismatching, managed by a microcontroller, allow for optimum detection for both continuous and mains current with a resolution of 10 mA for input ranges of 2 A. The proposed ammeter power consumption and measurement accuracy in different scenarios are tested, including the power monitoring of an IoT-based device, obtaining results matched to those featured by a commercial oscilloscope current probe, which validates its suitability and reliability as autonomous low-cost probe for portable contactless power monitoring.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16020014

Authors: Manfredi Caruso Andrea Ballo Minoo Eghtesadi Egidio Ragonese

This paper provides a comprehensive analysis of active frequency doubler architectures adopted for efficient generation of millimeter-wave (mm-wave) signals. The operational principles of each topology are explained to address a thorough comparison based on essential performance metrics such as conversion gain, power efficiency, and spectral purity. The review covers several topologies from the standard push–push (PP) doubler to its power-efficient evolution, the complementary push–push (CPP) doubler. Furthermore, this paper focuses on more recent and advanced topologies, including the complementary common gate capacitive cross-coupled (CCGCCC) doubler. Finally, this work proposes and evaluates an improved version of the CCCGCC doubler, offering insights into the state of the art and future directions in mm-wave frequency multiplication.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16020013

Authors: Juan Cruz-Cozar Javier Mendez Miguel Molina Jorge Perez-Martinez Alberto Martin-Martin Noel Rodriguez Diego P. Morales

Distributed energy systems open up a vast field of research in power electronics. Local solar power generation requires DC-DC converters that adapt the energy generated by the panels to on-site distribution buses. In addition, the control of the power converter to obtain the maximum possible energy from the solar source is crucial for the correct deployment of these distributed grids. In this work, system-level solutions are proposed for this application as follows: On the one hand, the use of novel resonant forward-flyback converters allows for a higher energy density than that of a conventional flyback and more relaxed withstand voltages on the switching elements. On the other hand, the implementation of maximum power point tracking algorithms for solar energy using Edge AI enables the deployment of algorithms that maximize the energy obtained locally. These improvements are shown by means of a prototype demonstrator, using cutting-edge microcontrollers and the implementation of a DC-DC power converter based on the proposed topology.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16020012

Authors: Giovanni Nicolini Alessio Passaquieti Giuseppe Scotti Riccardo Della Sala

A 0.3 V nanowatt CCII− is presented in 0.18 μm TSMC CMOS, targeting ultra-low-power current-mode interfaces. Post-layout extracted simulations demonstrate correct conveying operation with a total DC power consumption of less than 2.40 nW. The low-frequency tracking factors evaluated at 1 Hz are β0=0.9452 (−0.48 dB) and α0=0.9609 (≈−0.35 dB), with −3 dB bandwidths of 22.95 kHz and 63.95 kHz for the voltage and current transfers, respectively. Small-signal extraction confirms the intended impedance profile, yielding RX=46.73 MΩ, RZ=1.204 GΩ, and a very high input resistance RY=392 GΩ. Robustness is verified through full PVT and mismatch analyses, showing stable functionality across process corners, a 0–80 °C temperature range, and 270–330 mV supply variations while maintaining nanowatt-level dissipation.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16020011

Authors: Qiang Wang Libo Yang Mengdi Wang Bin Ma Long Yuan Shaobo Li Zhangjie Liu

High penetration of renewable energy sources (RESs) introduces significant power fluctuations, threatening voltage and frequency stability in modern power systems. This paper presents an integrated framework for static voltage stability assessment and stability-constrained optimization of under-frequency load shedding (UFLS) in renewable-dominated grids. A low-conservativeness analytical criterion is first derived for static voltage stability margin assessment. Then, a hybrid Deep Belief Network–Long Short-Term Memory (DBN–LSTM) model is developed for accurate renewable power forecasting, capturing temporal variability and uncertainty. Finally, UFLS-based stability-constrained dispatch is formulated to prevent voltage collapse, enhance the system stability, and minimize RES curtailment. Simulations on a modified IEEE benchmark system demonstrate that the proposed approach improves voltage and frequency stability while maintaining high renewable energy utilization.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16010010

Authors: Yu Qi Hossein Yaghobi Hossein Miri Lavasani

This paper presents a secure 2.4 GHz frequency shift keying (FSK) transmitter front-end with minimal overhead on the data stream using analog obfuscation techniques applied to the modulated waveform. An off-chip true random number generator (TRNG) unit is used to generate the required key for the encryption. Moving away from traditional FSK schemes, which benefit from constant local oscillator (LO) frequency within the channel, the proposed secure FSK scheme shifts the LO frequency in very small steps using an innovative capacitor-bank structure with a calibrated digitally controlled oscillator (DCO). The proposed capacitor bank uses a combination of parallel switches and series capacitors to minimize the impact of the layout parasitics on the minimum capacitor in the bank, thereby reliably creating sub-fF unit capacitors. When combined with the proposed capacitor bank, the cross-coupled CMOS LC voltage-controlled oscillator (VCO) forms a digitally controlled oscillator (DCO). The post-layout simulation results of the DCO reveal that the proposed scheme can achieve a resolution of <20 kHz for the LO frequency shifting while maintaining the phase-noise performance. The reported phase shift allows an equivalent entropy > 6 bits in the implemented analog-inspired secure transmitter front-end.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16010009

Authors: Gerardo Arno Sonck-Martinez Victor A. Gonzalez-Huitron Abraham Efraím Rodríguez-Mata Isidro Robledo-Vega Guillermo Valencia-Palomo Jose-Agustin Almaraz-Damian

This research addresses the increasing need for efficient energy management in residential settings in response to the increasing global energy demands, focusing on the integration of artificial intelligence to identify energy burdens. We employ and compare some machine learning models, like Decision Trees, K-nearest neighbors, and Feedforward Neural Networks, with a primary focus on electrical current as a key parameter. The Fine K-NN model shows notable efficiency, achieving an accuracy of 99.1% in the identification of active household appliances using a single sensor. Our methodology encompasses rigorous data acquisition and preprocessing under controlled experimental conditions, ensuring the integrity and reliability of our results. This study contributes to the field by illustrating the effectiveness of specific AI models in energy management under controlled conditions, paving the way for future advancements in AI-driven energy conservation strategies.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16010008

Authors: Yifeng Fu Jianguang Xu

In the post-Moore’s Law era, conventional Von Neumann architectures face critical limitations, such as the “memory wall” and excessive power consumption, particularly when processing unstructured data. Neuromorphic computing, inspired by the human brain, offers a promising solution through parallel processing and adaptive learning. Among the candidates for artificial synapses, memristors based on two-dimensional MXenes (specifically Ti3C2Tx) have attracted significant attention due to their unique layered structure, high metallic conductivity, and tunable physicochemical properties. This review provides a comprehensive analysis of MXene-based memristors, from material synthesis to system-level applications. We examine how different synthesis strategies, including etching methods, directly influence device performance and elucidate the underlying resistive switching mechanisms driven by ion migration, valence change, and interfacial processes. Furthermore, the review demonstrates the efficacy of MXenes in emulating biological synaptic functions—such as spike-timing-dependent plasticity (STDP) and long-term potentiation/depression (LTP/LTD)—and their application in tasks like handwritten digit recognition. Finally, we highlight emerging frontiers in flexible electronics and in-sensor computing, offering insights into the future trajectory of integrated sensing, memory, and computation.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16010007

Authors: Paolo Esposito Vincenzo Stornelli Giuseppe Ferri

In this work, the authors introduce an entirely solar-powered LoRa-based WSN consisting of several nodes, two stoplights, and four cameras. The system has been used to monitor the semi-rural area of Panni (FG), Puglia, Italy. The WSN has a totally custom implementation in both the node-gateway side and the gateway-user interface side. In particular, the communication framework is entirely IoT-based, featuring both the MQTT protocol, for the direct control of apparatuses from the system user interface, and the more traditional TCP/IP protocol, implemented on NB-IoT. The proposed system is entirely solar-powered and features a 34.68 mWh/day consumption. Around a single communication session, the average power consumption inside the single node amounts to 1.4 mW. This paper gives an overview of the proposed system, with detailed explanations of each part, and measurements retrieved over a wide period to assess the functionality of the system.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16010006

Authors: Andreas Tsiougkos Georgia Amanatiadou Vasilis F. Pavlidis

A new approach to end-to-end power delivery for increasingly sought-after hierarchical power delivery units (PDUs) is presented, improving the power efficiency of portable systems. The benefits of the technique are demonstrated through a PDU comprising multiple DC–DC converters, such as low-dropout regulators (LDOs), and the support of heterogeneous loads. A properly tailored Q-algorithm is combined with power gating to manage the power supplied by a multi-level PDU. The effectiveness of the proposed method is evaluated via a realistic PDU for different combinations of loads. The learning-based technique yields up to 13% higher total end-to-end power efficiency in the case of similar loads by utilizing four available LDOs compared to the case of a single LDO, which supports the same span of loads. Moreover, the proposed method improves power efficiency by up to 5% in the case of heterogeneous loads when compared to other autonomous state-of-the-art power management units.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16010005

Authors: Elisei Ilies Magdalena Marinca Aurel Gontean

This paper examines the implementation and resource utilization of Cascaded Integrator Comb (CIC) filters within FPGA-based Pulse Density Modulation (PDM) microphone applications. Three CIC filter designs were analyzed: one generated using MATLAB’s HDL Coder toolbox, one generated via AMD’s CIC Compiler IP, and one generated using an open-source CIC filter architecture. The study compares the efficiency of these three implementations in terms of slice LUTs and slice register usage. The maximum working frequency was also investigated. The results demonstrate that filters generated with the CIC Compiler require fewer FPGA resources, provide optimized multi-channel support, and have the option to utilize DSP48 slices for enhanced performance, while MATLAB-generated filters have higher working frequency and have great flexibility regarding the parameter, like the open-source CIC filter version.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16010004

Authors: Yeh-Liang Hsu Chun-Hung Yi Shu-Chiung Lee Kuei-Hua Yen

(1) Background: In hospitals, mattresses are often relocated for cleaning or patient transfer, leading to mismatches between actual and recorded bed locations. Manual updates are time-consuming and error-prone, requiring an automatic localization system that is cost-effective and easy to deploy to ensure traceability and reduce nursing workload. (2) Purpose: This study presents a pragmatic, large-scale implementation and validation of a BLE-based localization system using RSSI measurements. The goal was to achieve reliable room-level identification of smart mattresses by leveraging existing hospital infrastructure. (3) Results: The system showed stable signals in the complex hospital environment, with a 12.04 dBm mean gap between primary and secondary rooms, accurately detecting mattress movements and restoring location confidence. Nurses reported easier operation, reduced manual checks, and improved accuracy, though occasional mismatches occurred when receivers were offline. (4) Conclusions: The RSSI-based system demonstrates a feasible and scalable model for real-world asset tracking. Future upgrades include receiver health monitoring, watchdog restarts, and enhanced user training to improve reliability and usability. (5) Method: RSSI–distance relationships were characterized under different partition conditions to determine parameters for room differentiation. To evaluate real-world scalability, a field validation involving 266 mattresses in 101 rooms over 42 h tested performance, along with relocation tests and nurse feedback.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16010003

Authors: Tanzeel-ur-Rehman Khan Sanghamitra Roy Koushik Chakraborty

In the pursuit of real-time object detection with constrained computational resources, the optimization of neural network architectures is paramount. We introduce novel sparsity induction methods within the YOLOv4-Tiny framework to significantly improve computational efficiency while maintaining high accuracy in pedestrian detection. We present three sparsification approaches: Homogeneous, Progressive, and Layer-Adaptive, each methodically reducing the model’s complexity without compromising its detection capability. Additionally, we refine the model’s output with a memory-efficient sliding window approach and a Bounding Box Sorting Algorithm, ensuring precise Intersection over Union (IoU) calculations. Our results demonstrate a substantial reduction in computational load by zeroing out over 50% of the weights with only a minimal 6% loss in IoU and 0.6% loss in F1-Score.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16010002

Authors: Arnab Raha Shamik Kundu Arghadip Das Soumendu Kumar Ghosh Deepak A. Mathaikutty

Modern deep neural network (DNN) accelerators must sustain high throughput while avoiding performance degradation from supply voltage (VDD) droop, which occurs when large arrays of multiply–accumulate (MAC) units switch concurrently and induce high peak current (ICCmax) transients on the power delivery network (PDN). In this work, we focus on ASIC-class DNN accelerators with tightly synchronized MAC arrays rather than FPGA-based implementations, where such cycle-aligned switching is most pronounced. Conventional guardbanding and reactive countermeasures (e.g., throttling, clock stretching, or emergency DVFS) either waste energy or incur non-trivial throughput penalties. We propose SparseDroop, a unified hardware-conscious framework that proactively shapes instantaneous current demand to mitigate droop without reducing sustained computing rate. SparseDroop comprises two complementary techniques. (1) SparseStagger, a lightweight hardware-friendly droop scheduler that exploits the inherent unstructured sparsity already present in the weights and activations—it does not introduce any additional sparsification. SparseStagger dynamically inspects the zero patterns mapped to each processing element (PE) column and staggers MAC start times within a column so that high-activity bursts are temporally interleaved. This fine-grain reordering smooths ICC trajectories, lowers the probability and depth of transient VDD dips, and preserves cycle-level alignment at tile/row boundaries—thereby maintaining no throughput loss and negligible control overhead. (2) SparseBlock, an architecture-aware, block-wise-structured sparsity induction method that intentionally introduces additional sparsity aligned with the accelerator’s dataflow. By co-designing block layout with the dataflow, SparseBlock reduces the likelihood that all PEs in a column become simultaneously active, directly constraining ICCmax and peak dynamic power on the PDN. Together, SparseStagger’s opportunistic staggering (from existing unstructured weight zeros) and SparseBlock’s structured, layout-aware sparsity induction (added to prevent peak-power excursions) deliver a scalable, low-overhead solution that improves voltage stability, energy efficiency, and robustness, integrates cleanly with the accelerator dataflow, and preserves model accuracy with modest retraining or fine-tuning.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea16010001

Authors: Ziyang Chen Ming Hao Xinye Cao Jingwei Zhang Chaoyao Shen Guoqing Li Meng Zhang

The Transformer architecture has achieved remarkable success across numerous computer vision tasks due to its superior capability for global dependency modeling. However, the high computational complexity and hardware-unfriendly operations such as Layer Normalization (LN), Softmax, and GELU severely hinder its deployment on resource-constrained platforms. To address these challenges, this paper proposes a hardware-friendly CNN-Transformer hybrid pyramid architecture that effectively balances accuracy, efficiency, and deployability. The proposed model integrates convolutional bottlenecks with Transformer encoders to capture both local and global contextual information while maintaining low computational cost. A pyramid feature extraction structure is further introduced to enhance multi-scale semantic representation. To improve hardware efficiency, we redesign key nonlinear components by introducing hardware-friendly activation, normalization, and Softmax approximations. Specifically, GELU and LN are replaced by ReLU and Batch Normalization (BN), and a simplified logarithmic-exponential formulation termed Softmax2 is proposed, which eliminates complex exponential and division operations, significantly reducing hardware implementation cost. Extensive experiments demonstrate the effectiveness of the proposed framework. The experimental results validate that the proposed architecture offers a promising and practical solution for real-time and embedded vision applications.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040071

Authors: Michelle Libang Kriz Kevin Adrivan Jefferson A. Hora Charade G. Avondo Robert M. Comaling Xi Zhu Yichuang Sun

This paper presents a self-contained startup charging circuit designed for energy-harvesting batteryless IoT devices. The proposed circuit consists of a current-biasing block, a current mirror, a reference voltage generator, and a comparator circuit. The current-biasing circuit drives the current mirror, which supplies the charging current to the energy storage element. Simultaneously, the reference voltage generator—also biased by the current source—produces a stable DC reference voltage. When the energy storage device (e.g., a supercapacitor) lacks sufficient charge, the comparator enables the charging path by activating the current-biasing and mirror circuits. Once adequate energy is stored, the comparator disables these circuits to prevent overcharging. This self-contained solution is intended to autonomously initialize and manage the cold-start charging process in energy-harvesting systems without relying on external controllers. This paper highlights the circuit architecture and validated performance, demonstrating a charging current of up to 27 mA, a reference voltage of 700 mV, and an operating range from 0.9 V to 1.8 V across a temperature range of −40 °C to 85 °C.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040070

Authors: Sreehari K. Narayanan Ramesh Bhakthavatchalu Remya Ajai Ajayan Sarala

Physically unclonable functions (PUFs) generate keys for cryptographic applications, eliminating the need for conventional key storage mechanisms. Since PUF responses are inherently noise-sensitive, their reliability can decrease under varying conditions. Integrating channel coding can enhance response stability and consistency. This work presents an efficient scheme that integrates a delay-base d PUF with a Low-Density Parity-Check (LDPC) code. Specifically, a feed-forward PUF is combined with LDPC coding to reliably regenerate the cryptographic key. Our design reproduces the key with minimal error using channel coding. The scheme achieves 96% key-generation reliability, representing a notable improvement over PUF-based key generation without error-correction coding. LDPC decoding with the min-sum algorithm provides better error correction than the bit-flipping algorithm, but it is more computationally intensive. We could design the proposed scheme with minimum hardware resource utilization using Xilinx Vivado 2018.2 and Cadence Genus tools.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040069

Authors: Mathieu Ginet Eric Feltrin Nicolas Jeanniot Bruno Allard Xuefang Lin-Shi

Single-Input, Multi-Output (SIMO) converters present significant challenges when operated under current-mode control, due to their strongly non-linear dynamics and susceptibility to bifurcation phenomena. To mitigate the effects on the converter’s steady-state, a double slope compensation solution is proposed. The compensation parameters play a critical role in shaping the system dynamics and rejecting the susceptibility to bifurcation. This paper proposes a detailed analysis methodology to investigate the design parameter space regarding the slope compensations with respect to bifurcation phenomena. The approach is validated on a CMOS integrated converter, where theoretical predictions are compared to the simulation results of a full transistor-level model of the circuit.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040068

Authors: Leena Ladge Y. Srinivasa Rao

As technologies like Artificial Intelligence, Blockchain, Virtual Reality, etc., are advancing, there is a high requirement for High-Performance Computers and multi-core processors to find many applications in today’s Cyber–Physical World. Subsequently, multi-core systems have now become ubiquitous. The core temperature is affected by intensive computational tasks, parallel execution of tasks, thermal coupling effects, and limitations on cooling methods. High temperatures may further decrease the performance of the chip and the overall system. In this paper, we have studied different parameters related to core performance. The MSI Afterburner utility is used to extract the hardware parameters. Single and multivariate analyses are carried out on core temperature, core usage, and core clock to study the performance of all cores. Single-variate analysis shows the need for action when core temperatures, core usage, and clock speeds exceed threshold values. Multivariate analysis reveals correlations between these parameters, guiding optimization strategies. We have also implemented the ARIMA model for core temperature estimation and obtained an average RMSE of 2.44 °C. Our analysis and ARIMA model for temperature estimation are useful in developing smart scheduling algorithms that optimize thermal management and energy efficiency.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040067

Authors: Yujia Huo Roy H. Olsson

Low noise and low power neural recording amplifiers are required for implantable devices measuring action potentials. This paper presents a dynamic current pulsing technique combined with a special type of two-stage low-pass filter (LPF) that demonstrates an improvement in the noise efficiency factor (NEF) beyond that achievable using traditional design. A low NEF of 1.55 is achieved at an average power consumption of 587.8 nW and 5.18 µVrms noise, integrated from 0.1 to 9.8 kHz, inclusive of the impacts of sampling and aliasing. The NEF is improved from 1.76 in the static low current state (LCS) and 1.67 in the static high current state (HCS), measured on the same amplifier chip.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040066

Authors: Jing Zhou Xiangyu Zhao Shengbing Zhang Lei Chen Ke Xiao Shuo Wang

SRAM-based FPGAs, with their flexible programmability and parallel execution features, have been widely used, and the security of such devices has drawn significant attention. Especially in the era of artificial intelligence, FPGA architectural optimizations and evolving application models have introduced novel security characteristics and threats. In this work, we introduce a taxonomy of FPGA threats and explore new threat features and potential countermeasures in the era of AI. We focus on evaluating the research trends of FPGA security, including both security threats and protection measures. Then, we propose a new perspective on the involvement of FPGA manufacturers in FPGA security and introduce the main security measures used in COTS FPGA products. Finally, we summarize the security challenges and offer future research directions.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040065

Authors: Mehdi Shahabi Noemi Perez Hector Solar Andoni Beriain

This work presents an ultra-low-power on-chip energy management (EM) circuit, which is the most critical and power-intensive block in power management integrated circuits (PMICs) used for energy harvesting (EH) applications. Ultra-low power consumption was the primary design priority to ensure suitability for systems operating under strict energy limitations. The design relies on a compact latch-based core and avoids the need for extra circuits such as voltage references, comparators, or logic blocks, which helps reduce both area and power. To implement the required high resistance, a series of diode-connected zero-threshold NMOS transistors is used. This approach enables very high resistance in a compact area without additional power consumption or biasing issues at low voltages. A PMOS transistor is also integrated at the EM output to directly control different types of loads. The circuit was designed and fabricated using a 65 nm CMOS standard process. Experimental measurements from the fabricated chips show a quiescent current of 170 nA at 3 V and a voltage hysteresis of over 0.9 V. In addition, temperature and process variation were simulated to verify robust operation. These results confirm that the circuit operates reliably under ultra-low-power conditions and is well-suited for EH systems.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040064

Authors: Devendra G. Sutar Nitesh B. Guinde

Accurate branch prediction is crucial for achieving high instruction throughput and minimizing control hazards in modern pipelines. This paper presents a novel LXOR (Local eXclusive-OR) branch predictor, which enhances prediction accuracy while reducing hardware complexity and memory usage. Unlike traditional predictors (GAg, GAp, PAg, PAp, Gshare, Gselect) that rely on large Pattern History Tables (PHTs) or intricate global/local history combinations, the LXOR predictor employs complemented local history and XOR-based indexing, optimizing table access and reducing aliasing. Implemented and evaluated using the MARSS-RISCV simulator on a 64-bit in-order RISC-V core, the LXOR’s performance was compared against traditional predictors using Coremark and SPEC CPU2017 benchmarks. The LXOR consistently achieved competitive results, with a prediction accuracy of up to 83.92%, lower misprediction rates, and instruction flushes as low as 5.83%. It also attained an IPC rate of up to 0.83, all while maintaining a compact memory footprint of approximately 2 KB, significantly smaller than current alternatives. These findings demonstrate that the LXOR predictor not only matches the performance of more complex predictors but does so with less memory and logic overhead, making it ideal for embedded systems, low-power RISC-V processors, and resource-constrained IoT and edge devices. By balancing prediction accuracy with simplicity, the LXOR offers a scalable and cost-effective solution for next-generation microprocessors.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040063

Authors: John Reuben Felix Zeller Benjamin Seiler Dietmar Fey

Image convolution is a commonly required task in machine vision and Convolution Neural Networks (CNNs). Due to the large data movement required, image convolution can benefit greatly from in-memory computing. However, image convolution is very computationally intensive, requiring (n−(k−1))2 Inner Product (IP) computations for convolution of a n×n image with a k×k kernel. For example, for a convolution of a 224 × 224 image with a 3 × 3 kernel, 49,284 IPs need to be computed, where each IP requires nine multiplications and eight additions. This is a major hurdle for in-memory implementation because in-memory adders and multipliers are extremely slow compared to CMOS multipliers. In this work, we revive an old technique called ‘Distributed Arithmetic’ and judiciously apply it to perform image convolution in memory without area-intensive hard-wired multipliers. Distributed arithmetic performs multiplication using shift-and-add operations, and they are implemented using CMOS circuits in the periphery of ReRAM memory. Compared to Google’s TPU, our in-memory architecture requires 56× less energy while incurring 24× more latency for convolution of a 224 × 224 image with a 3 × 3 filter.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040062

Authors: Shivakumar Rajagopal Viet-Thanh Pham Fatemeh Parastesh Karthikeyan Rajagopal Sajad Jafari

Neuromorphic circuits emulate the brain’s massively parallel, energy-efficient, and robust information processing by reproducing the behavior of neurons and synapses in dense networks. Memristive technologies have emerged as key enablers of such systems, offering compact and low-power implementations. In particular, locally active memristors (LAMs), with their ability to amplify small perturbations within a locally active domain to generate action potential-like responses, provide powerful building blocks for neuromorphic circuits and offer new perspectives on the mechanisms underlying neuronal firing dynamics. This paper introduces a novel second-order locally active memristor (LAM) governed by two coupled state variables, enabling richer nonlinear dynamics compared to conventional first-order devices. Even when the capacitances controlling the states are equal, the device retains two independent memory states, which broaden the design space for hysteresis tuning and allow flexible modulation of the current–voltage response. The second-order LAM is then integrated into a FitzHugh–Nagumo neuron circuit. The proposed circuit exhibits oscillatory firing behavior under specific parameter regimes and is further investigated under both DC and AC external stimulation. A comprehensive analysis of its equilibrium points is provided, followed by bifurcation diagrams and Lyapunov exponent spectra for key system parameters, revealing distinct regions of periodic, chaotic, and quasi-periodic dynamics. Representative time-domain patterns corresponding to these regimes are also presented, highlighting the circuit’s ability to reproduce a rich variety of neuronal firing behaviors. Finally, two unknown system parameters are estimated using the Aquila Optimization algorithm, with a cost function based on the system’s return map. Simulation results confirm the algorithm’s efficiency in parameter estimation.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040061

Authors: Wu Cong Lim Liter Siek Eng Leong Tan

Battery cell balancing is crucial in series-connected lithium-ion packs to maximize usable capacity, ensure safe operation, and prolong cycle life. This paper presents a comprehensive study and a novel adaptive duty-cycled hybrid balancing system that combines passive bleed resistors and an active switched-capacitor (SC) balancer, specifically designed for a 4-cell series-connected battery pack. This work also explored open circuit voltage (OCV)-driven adaptive pulse-frequency modulation (PFM) active balancing to achieve higher efficiency and better balancing speed based on different system requirements. Finally, this paper compares passive, active (SC-based), and adaptive duty-cycled hybrid balancing strategies in detail, including theoretical modeling of energy transfer and efficiency for each method. Simulation showed that the adaptive hybrid balancer speeds state-of-charge (SoC) equalization by 16.24% compared to active-only balancing while maintaining an efficiency of 97.71% with minimal thermal stress. The simulation result also showed that adaptive active balancing was able to achieve a high efficiency of 99.86% and provided an additional design degree of freedom for different applications. The results indicate that the adaptive hybrid balancer offered an excellent trade-off between balancing speed, efficiency, and implementation simplicity for 4-cell Li-ion packs, making it highly suitable for applications such as high-voltage portable chargers.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040060

Authors: Tong Zhang Bosen Huang Xiewen Liu Jiaqi Fan Junbo Li Zhao Yue Yanfang Wang

Microcontroller units (MCUs) serve as the core components of embedded systems. In the era of smart IoT, embedded devices are increasingly deployed on mobile platforms, leading to a growing demand for low-power consumption. As a result, low-power technology for MCUs has become increasingly critical. This paper systematically reviews the development history and current technical challenges of MCU low-power technology. It then focuses on analyzing system-level low-power optimization pathways for integrating MCUs with artificial intelligence (AI) technology, including lightweight AI algorithm design, model pruning, AI acceleration hardware (NPU, GPU), and heterogeneous computing architectures. It further elaborates on how AI technology empowers MCUs to achieve comprehensive low power consumption from four dimensions: task scheduling, power management, inference engine optimization, and communication and data processing. Through practical application cases in multiple fields such as smart home, healthcare, industrial automation, and smart agriculture, it verifies the significant advantages of MCUs combined with AI in performance improvement and power consumption optimization. Finally, this paper focuses on the key challenges that still need to be addressed in the intelligent upgrade of future MCU low power consumption and proposes in-depth research directions in areas such as the balance between lightweight model accuracy and robustness, the consistency and stability of edge-side collaborative computing, and the reliability and power consumption control of the sensor-storage-computing integrated architecture, providing clear guidance and prospects for future research.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040059

Authors: Orazio Aiello

After the success of the first edition [...]

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040058

Authors: Kaijun Song Xinsheng Chen Zongrui He

This paper presents a microstrip active quasi-circulator designed for low-power wireless communication systems. The circuit consists of a second-order Wilkinson power divider and two power amplifiers with high gain and ultra-low noise characteristics. By leveraging the unidirectional transmission characteristics of the transistors and the isolation provided by resistors within the power divider, the interference between the transmitter (TX) and receiver (RX) is effectively suppressed. Additionally, thanks to the dual-amplifier architecture, no extra power amplification circuitry is required, thereby reducing the overall complexity and power consumption of the communication system. The detailed design procedure of the proposed quasi-circulator is presented. The measurement results show that, within the frequency range of 4.75 GHz to 6.11 GHz, the isolation between the TX and RX ports exceeds 20 dB, the return loss at each port is greater than 10 dB, and the transmission gains from the TX port to the antenna and from the antenna to the RX port are 3.1–8.7 dB and 2.7–4.0 dB, respectively, demonstrating a relative bandwidth of 25%.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040057

Authors: Jiale Guo Rongsheng Han Zibo Yang Guoqing An Rui Li Long Zhang

The frequency characteristics of the switching-mode power supply (SMPS) control loop under all operating conditions are crucial for performance evaluation and defect detection. Traditional methods, relyingon experiments under preset conditions, struggle to achieve comprehensive evaluation. This study proposes a frequency characteristic fitting method for all operating conditions based on FT-WOA-MLP. A discrete-point dataset covering all conditions of an LLC SMPS was obtained using the small-signal perturbation method, including input voltage, output current, injection frequency, and corresponding amplitude- and phase-frequency characteristics. The multilayer perceptron (MLP) model was trained on the training set covering all operating conditions, with the whale optimization algorithm (WOA) used to optimize the learning rate, and fine tuning (FT) applied to further enhance accuracy. Independent test set validation showed that, for amplitude-frequency characteristics, the mean absolute error (MAE) was 2.0995, the mean absolute percentage error (MAPE) was 0.0974, the root mean square error (RMSE) was 4.0474, and the coefficient of determination (R2) reached 0.92; for phase-frequency characteristics, the MAE was 3.502, the MAPE was 0.0956, the RMSE was 10.5192, and the R2 reached 0.94. The method accurately fits frequency characteristics under all conditions, supporting defect identification and performance optimization.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040056

Authors: Marco Grossi Martin Omaña

Portable and wearable sensors have gained attention in recent years to perform measurements in many different applications. Sensors based on Electrical Impedance Spectroscopy (EIS) are particularly promising, because they can make accurate measurements with minimum perturbation to the sample under test. Electrochemical biosensors are devices that use electrochemical techniques to measure a target analyte. In the case of electrochemical biosensors based on EIS, the measured impedance spectrum is fitted to that of an equivalent electrical circuit, whose component values are then used to estimate the concentration of the target analyte. Fitting EIS data is usually carried out by sophisticated algorithms running on a PC. In this paper, we have evaluated the feasibility to perform EIS data fitting using simple Artificial Neural Networks (ANNs) that can be run on resource constrained microcontrollers, which are typically used for portable and wearable sensors. We considered a typical case of an impedance spectrum in the range 0.1 Hz–10 kHz, modeled by using the simplified Randles equivalent circuit. Our analyses have shown that simple ANNs can be a low power alternative to perform EIS data fitting on low-cost microcontrollers with a memory occupation in the order of kilo bytes and a measurement accuracy between 1% and 3%.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15040055

Authors: Suhao Chen Xiaopeng Yu Xiongchun Huang

The rapid growth of the Internet of Things (IoT) has driven the need for ultra-low-power wireless communication systems. Wake-up receivers (WuRXs) have emerged as a key technology to enable energy-efficient, near-always-on operation for IoT devices. This review explores the state of the art in WuRXs design, focusing on low-power architectures, key trade-offs, and recent advancements. We discuss the challenges in achieving low power consumption while maintaining sensitivity, power consumption, and interference resilience. The review highlights the evolution from radio frequency (RF) envelope detection architectures to more complex heterodyne and subthreshold designs and concludes with future directions for WuRXs research.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030054

Authors: Apinan Aurasopon Boontan Sriboonrueng Jirapong Jittakort Saichol Chudjuarjeen

This paper presents a Class E zero-voltage soft-switching (ZVS) resonant inverter integrated with a CLC filter and a digital resonant frequency tracking technique for driving a piezoelectric ceramic transducer (PZT) in ultrasonic cleaning applications. A digital signal processor (DSP) is used to dynamically monitor and adjust the operating frequency in response to slight variations in the cleaning load, employing a phase-locked loop (PLL) control scheme. The proposed method ensures that the inverter maintains ZVS operation across a frequency range from 30.0 kHz to 34.0 kHz, thereby improving energy efficiency and reducing switching losses. The system is capable of delivering a stable power output of 100 W. Both the simulation and experimental results validate the effectiveness of the proposed technique, demonstrating improved performance under varying load conditions. The combination of CLC filtering and frequency tracking offers a compact and robust solution suitable for ultrasonic cleaner systems and similar resonant-load applications.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030053

Authors: Benjamin Zambrano Sebastiano Strangio Esteban Garzón Alessandro Catania Giuseppe Iannaccone Marco Lanuzza

This paper introduces a physical unclonable function (PUF) based on a differential array of minimum-sized PMOS devices. Each response bit is obtained by comparing the two analog outputs of the differential array through a dynamic comparator with a trimmable offset. This offset is effectively used to mask potentially unstable response bits. To further improve PUF reliability, spatial majority voting is also implemented, resulting in a near-zero (<3.12×10−9) bit error rate (BER) at 1.2 V and 25 °C. Under variations in supply voltage (0.8–1.3 V) and temperature (0–75 °C), the native bit error rate of 3.5% is reduced to 9.73×10−4 after stabilization, consuming only 1.37 pJ per output bit.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030052

Authors: Dimitris Patrinos George Souliotis

A ring-oscillator based voltage-controlled oscillator (VCO) architecture with reduced frequency drift across temperature and process variations is presented in this paper. The frequency stability is achieved through two dedicated compensation techniques: a temperature compensation circuit that generates a proportional-to-absolute-temperature (PTAT) current to mitigate frequency shifts due to temperature changes, and a process compensation circuit that dynamically adjusts the frequency based on detected process corners. The proposed design is implemented in a 22 nm CMOS technology with a 0.8 V supply voltage and targets a nominal oscillation frequency of 2.5 GHz. The post-layout simulation results demonstrate a significant improvement in frequency stability, reducing temperature-induced frequency drift from 23.9% to a range of 5.4% over the −40 °C to 125 °C temperature range for the typical corner. Combining temperature and process compensation, the frequency drift is improved from 47.3% to better than 7.2%. The VCO also achieves a phase noise value about −80 dBc/Hz at a 1 MHz offset with an average power consumption of 380 µW, including the tuning mechanism and the compensation circuits.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030051

Authors: Teng Bao Mingmin Zhu Zhifeng He Yi Zhang Guoliang Yu Yang Qiu Jiawei Wang Yan Li Haibin Zhu Hao-Miao Zhou

With the rapid growth of unmanned aerial vehicles (UAVs) and IoT users, spectrum resources are becoming increasingly scarce, making cognitive radio (CR) technology a key approach to improving spectrum utilization. However, traditional antennas are difficult to meet the lightweight, compact, and low-drag requirements of small UAVs due to spatial constraints. This paper proposes a tri-mode frequency reconfigurable flexible antenna that can be conformally integrated onto UAV wing arms to enable CR dynamic frequency communication. The antenna uses a polyimide (PI) substrate and has compact dimensions of 31.4 × 58 × 0.05 mm3. A microstrip line-based frequency-selective network is designed, incorporating PIN and varactor diodes to realize three operation modes, dual-band (2.25~3.55 GHz, 5.6~6.75 GHz), single-band (3.35~5.3 GHz), and continuous tuning (4.3~6.1 GHz), covering WLAN, WiMAX, and 5G NR bands. Test results show that the antenna maintains stable performance under conformal conditions, with frequency shifts less than 4%, gain (3.65~4.77 dBi), and radiation efficiency between 67.2% and 82.9%. The tuning ratio reaches 38.8% in the continuous mode. This design offers a new solution for CR communication in compact UAV platforms and shows promising application potential.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030050

Authors: James S. Plank Charles P. Rizzo Bryson Gullett Keegan E. M. Dent Catherine D. Schuman

For most, if not all, AI-accelerated hardware, communication with the agent is expensive and heavily bottlenecks the hardware performance. This omnipresent hardware restriction is also found in neuromorphic computing: a novel style of computing that involves deploying spiking neural networks to specialized hardware to achieve low size, weight, and power (SWaP) compute. In neuromorphic computing, spike trains, times, and values are used to communicate information to, from, and within the spiking neural network. Input data, in order to be presented to a spiking neural network, must first be encoded as spikes. After processing the data, spikes are communicated by the network that represent some classification or decision that must be processed by decoder logic. In this paper, we first present principles for interconverting between spike trains, times, and values using custom-designed spiking subnetworks. Specifically, we present seven networks that encompass the 15 conversion scenarios between these encodings. We then perform three case studies where we either custom design a novel network or augment existing neural networks with these conversion subnetworks to vastly improve their communication performance with the outside world. We employ a classic space vs. time tradeoff by pushing spike data encoding and decoding techniques into the network mesh (increasing space) in order to minimize intra- and extranetwork communication time. This results in a classification inference speedup of 23× and a control inference speedup of 4.3× on field-programmable gate array hardware.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030049

Authors: Lin Xu Wengan Li Zenglong Zhao Fanyi Meng

At present, environmental pollution is becoming more and more serious, and the energy problem is becoming more prominent. Energy-braking recovery can collect the mechanical energy lost in the traditional braking process and convert it into electricity or other forms of energy for vehicle reuse, thus reducing carbon emissions, achieving energy saving and emission reduction, and promoting green development. Based on this, this paper studies the energy-braking recovery method. The study focuses specifically on the recovery of energy during vehicle braking triggered by brake-signal activation, without addressing alternative deceleration strategies under braking conditions. The proposed energy-braking recovery scheme is evaluated primarily through simulation, with the analysis grounded in practical application scenarios and leveraging existing technologies. Firstly, the principle of energy-braking recovery is introduced, and the method of estimating the State on Charge (SOC) of the battery and controlling the motor speed is determined. Then, the simulation model of the energy brake recovery system is built with MATLAB R2023b (MathWorks, Natick, MA, USA), and the design ideas and specific structures of the three modules of the simulation model are introduced in detail. Finally, the results of the simulated motor speed and SOC value of the battery are analysed, and it is confirmed that they meet the requirements of the system and achieve close to the ideal effect.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030048

Authors: Yuqing Yang Song Xu Wei Jiang Seiji Hashimoto

Hybrid electric vehicles (HEVs) have gained significant attention for their superior energy efficiency and are becoming a predominant mode of urban transportation. The DC/DC converter plays a critical role in HEV energy management systems, especially in matching the voltage levels between the battery and DC bus. This paper proposes a novel high-gain DC/DC converter with a wide input voltage range based on coupled inductors. The innovation lies in the integration of a resonant cavity and the simultaneous realization of zero-voltage switching (ZVS) and zero-current switching (ZCS), effectively reducing both voltage/current stresses on the power switches and switching losses. Compared with conventional topologies, the proposed design achieves higher voltage gain without extreme duty cycles, improved conversion efficiency, and enhanced reliability. Detailed operating principles are analyzed, and design conditions for voltage stress reduction, gain extension, and soft switching are derived. The simulation model has been conducted in a PSIM environment, and a 300 W experimental prototype, implemented using a dsPIC33FJ64GS606 digital controller, has been established and demonstrates 93% peak efficiency at a 10 times voltage gain. The performance and practical feasibility of the proposed topology have been evaluated by both simulation and experiments.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030047

Authors: Geethu Remadevi Somanathan Ujarla Harshavardhan Reddy Ramesh Bhakthavatchalu

This paper presents a power-aware Reconfigurable Parameterizable Pseudorandom Pattern Generator (RP-PRPG) for a number of applications, including built in self-testing (BIST) and cryptography. Linear Feedback Shift Registers (LFSRs) are broadly utilized in pattern generation due to their efficiency and simplicity. However, the diversity of generated patterns, as well as their power consumption, improves through circuit modifications. This work explores enhancements to LFSR structures to achieve broader range of patterns with reduced power consumption for BIST-based applications. The proposed circuit constructed on the LFSR platform can be programmed to generate patterns with varying degrees of different LFSR configurations. Diverse set of patterns of any circuit arrangement can be created using any characteristic polynomial and by utilizing the reseeding capacity of the circuit. The circuit combines a double-tier linear feedback circuit with zero forcing methods, resulting in more than 70% transition reduction, thus significantly lowering power dissipation. The behaviour of the proposed circuit is assessed for characteristic polynomials with degrees ranging from 4 to 128 using various Linear Feedback Shift Register (LFSR) topologies. For reconfigurable HDL and ASIC synthesis, the power-aware RP-PRPG can be used to generate an efficient set of stream ciphers as well as applications involving the scan-for-test protocol.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030046

Authors: Lei Zhong Xuejiao Jiang Jialong Xu Kaihong Zheng Min Wu Lei Gao Chao Ma Dewen Zhu Yuan Ai

Privacy-sensitive electricity scene classification requires robust models under data localization constraints, making federated learning (FL) a suitable framework. Existing FL frameworks face two critical challenges in multi-label electricity scene classification: (1) Label correlations and their strengths significantly impact classification performance. (2) Electricity scene data and labels show distributional inconsistencies across regions. However, current FL frameworks lack explicit modeling of label correlation strengths, and locally trained regional models naturally capture these differences, leading to regional differences in their model parameters. In this scenario, the server’s standard single-stage aggregation often over-averages the global model’s parameters, reducing its discriminative ability. To address these issues, we propose FMMAN, a federated multi-stage attention neural network for multi-label electricity scene classification. The main contributions of this FMMAN lie in label correlation learning and the stepwise model aggregation. It splits the client–server interaction into multiple stages: (1) Clients train models locally to encode features and label correlation strengths after receiving the server’s initial model. (2) The server clusters these locally trained models into K groups to ensure that models within a group have more consistent parameters and generates K prototype models via intra-group aggregation to reduce over-averaging. The K models are then distributed back to the clients. (3) Clients refine their models using the K prototypes with contrastive group-specific consistency regularization to further mitigate over-averaging, and sends the refined model back to the server. (4) Finally, the server aggregates the models into a global model. Experiments on multi-label benchmarks verify that FMMAN outperforms baseline methods.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030045

Authors: Ziyuan Yang Shengquan Li Kaiwen Cao Donglei Chen Juan Li Wei Cao

Considering the challenges posed by traditional continuous control set model predictive control (CCS-MPC) calculations, this paper proposes an event-triggered-based model predictive control (ET-MPC). First, a novel tracking error state-space model is proposed to improve tracking performance. Second, a reduced-order extended state observer (RESO) is designed to estimate and compensate for the total disturbances, thereby effectively improving robustness against the variations of the load resistance and reference voltage. At the same time, RESO significantly reduces computational complexity and accelerates the convergence speed of state estimation. Subsequently, an event trigger mechanism is introduced to enhance the MPC with a threshold function for the converter status. Finally, the reduced-order extended state observer-based model predictive control (RESO-MPC) is compared with the proposed ET-MPC through experiments. The ripple voltage of ET-MPC is within 2%, and the computational burden is reduced by more than 57%, verifying the effectiveness of the proposed ET-MPC.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030044

Authors: Zhihao Xu Dan Zhang Rongkang Xuan Shenxiang Yang Na Wang

This study investigates the propagation characteristics and field distribution of photonic crystals composed of epsilon-near-zero (ENZ) materials and metal cylinders. The research reveals that the cutoff frequency of the photonic crystal formed by combining metal cylinders with an ENZ background is independent of the volume fraction of the metal cylinders and exhibits a stop-band profile within the measured frequency range. This unique behavior is attributed to the scattering of long-wavelength light when the wavelength approaches the effective wavelength range of the ENZ material. Taking advantage of this feature, the study selectively filters specific wavelength ranges from the mid-frequency band by varying the ratio of cylinder radius to lattice constant (R/a). Decreasing the R/a ratio enables the design of waveguide devices that operate over a broader guided wavelength range within the intermediate-frequency band. The findings emphasize the importance of the interaction between light and ENZ materials in shaping the transmission characteristics of photonic crystal structures.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030043

Authors: Yangfan Liu Qixiao Li Zhongxuan Wang

Bipolar power supply can effectively reduce line losses and optimize power transmission. This paper proposes a low-power bipolar DC–DC converter with voltage self-balancing, which not only achieves bipolar output but also automatically balances the inter-pole voltage under load imbalance conditions without requiring additional voltage balancing control. This paper first elaborates on the derivation process of the proposed converter, then analyzes its working principles and performance characteristics. A 400 W experimental prototype is built to validate the correctness of the theoretical analysis and the voltage self-balancing capability. Finally, loss analysis and conclusions are presented.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030042

Authors: Vadim Kuznetsov

XSPICE models for a generic transmission line, a microstrip line, and coupled microstrips are presented. The developed models extend general-purpose circuit simulation tools using RF circuits design features. The models could be used for circuit simulation in frequency, DC, and time domains for any active or passive RF or microwave schematic (including microwave monolithic integrated circuits—MMICs) involving transmission lines. The presented models could be used with any circuit simulation backend supporting XSPICE extensions and could be integrated without patching the core simulator code. The presented XSPICE models for microstrip lines take into account the frequency dependency of characteristic impedance and dispersion. The models were designed using open-source circuit simulation software. This study provides a practical example of the low-noise RF amplifier (LNA) design with Ngspice simulation backend using the proposed models.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030041

Authors: Rasoul Akbari Afshin Izadian

Split-shaft wind turbines decouple the turbine’s shaft from the generator’s shaft, enabling several modifications in the drivetrain. One of the significant achievements of a split-shaft drivetrain is the reduction in size of the excitation circuit. The grid-side converter is eliminated, and the rotor-side converter can safely reduce its size to a fraction of a full-size excitation. Therefore, this low-power-rated converter operates at low voltage and handles regular operations well. However, fault conditions may expose weaknesses in the converter and push it to its limits. This paper investigates the effects of the reduced-size rotor-side converter on the voltage ride-through capabilities required from all wind turbines. Four different protection circuits, including the active crowbar, active crowbar along a resistor–inductor circuit (C-RL), series dynamic resistor (SDR), and new-bridge fault current limiter (NBFCL), are employed, and their effects are investigated and compared. Wind turbine controllers are also utilized to reduce the impact of faults on the power electronic converters. One effective method is to store excess energy in the generator’s rotor. The proposed low-voltage ride-through strategies are simulated in MATLAB Simulink (2022b) to validate the results and demonstrate their effectiveness and functionality.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030040

Authors: Muhammet Arucu Teodor Iliev

This study presents a comprehensive performance evaluation of field-programmable gate array (FPGA), graphics processing unit (GPU), and central processing unit (CPU) platforms for implementing finite impulse response (FIR) filters in semiconductor-based digital signal processing (DSP) systems. Utilizing a standardized FIR filter designed with the Kaiser window method, we compare computational efficiency, latency, and energy consumption across the ZYNQ XC7Z020 FPGA, Tesla K80 GPU, and Arm-based CPU, achieving processing times of 0.004 s, 0.008 s, and 0.107 s, respectively, with FPGA power consumption of 1.431 W and comparable energy profiles for GPU and CPU. The FPGA is 27 times faster than the CPU and 2 times faster than the GPU, demonstrating its suitability for low-latency DSP tasks. A detailed analysis of resource utilization and scalability underscores the FPGA’s reconfigurability for optimized DSP implementations. This work provides novel insights into platform-specific optimizations, addressing the demand for energy-efficient solutions in edge computing and IoT applications, with implications for advancing sustainable DSP architectures.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030039

Authors: Zhengqiang Xiong Chang Han Xiaoliang Wang Li Gao

Coverage path planning solves the problem of moving an effector over all points within a specific region with effective routes. Most existing studies focus on geometric constraints, often overlooking robot-specific features, like the available energy, weight, maximum speed, sensor resolution, etc. This paper proposes a coverage path planning algorithm for Unmanned Aerial Vehicles (UAVs) that minimizes energy consumption while satisfying a set of other requirements, such as coverage and observation resolution. To deal with these issues, we propose a novel energy-optimal coverage path planning framework for monitoring tasks. Firstly, the 3D terrain’s spatial characteristics are digitized through a combination of parametric modeling and meshing techniques. To accurately estimate actual energy expenditure along a segmented trajectory, a power estimation module is introduced, which integrates dynamic feasibility constraints into the energy computation. Utilizing a Digital Surface Model (DSM), a global energy consumption map is generated by constructing a weighted directed graph over the terrain. Subsequently, an energy-optimal coverage path is derived by applying a Genetic Algorithm (GA) to traverse this map. Extensive simulation results validate the superiority of the proposed approach compared to existing methods.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030038

Authors: Longsheng Zhang Kaihong Wang Shilong Guo Binxin Zhu

The eGaN HEMT power devices face serious crosstalk problems when applied to high-frequency bridge circuits, thereby limiting the switching performance of these devices. To address this issue, a gate driver is proposed in this paper that can suppress both positive and negative crosstalk of eGaN HEMT power devices, offering the advantages of simple control and easy integration. The basic idea is to suppress positive crosstalk by constructing a negative voltage capacitor, and to suppress negative crosstalk by reducing the impedance of the gate loop. To verify the capability of the proposed gate driver, double-pulse and synchronous Buck test platforms are constructed. The experimental results clearly demonstrate that the proposed gate driver reduces the positive and negative crosstalk spikes by 2.03 V and 1.54 V, respectively, ensuring that the positive and negative crosstalk spikes fall within a safe operating range. Additionally, the turn-off speed of the device is enhanced, leading to a reduction in switching loss.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15030037

Authors: Jennifer Hasler Praveen Raj Ayyappan

This article presents an energy-efficient IC architecture implementation of an analog image-processing ML system, where the primary issue is analog architecture development for existing energy-efficient analog computing devices. An architecture is developed for image classification, transforming a typical imager input into a classified result using a particular NN algorithm, a convolutional NN (ConvNN). These efforts show the need to continue to develop energy-efficient analog architectures alongside efficient analog circuits to fully exploit the opportunities of analog computing for system application.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020036

Authors: Fahad M. Alotaibi

Wireless Power Transfer (WPT) enables efficient, contactless charging for mobile devices by eliminating mechanical connectors and wiring, thereby enhancing user experience and device longevity. However, conventional WPT systems remain prone to performance issues such as coil misalignment, resonance instability, and thermal losses. Addressing these challenges involves designing coil geometries that operate at lower resonant frequencies to strengthen magnetic coupling and decrease resistance. This work introduces a WPT system with a performance-driven coil design aimed at maximizing magnetic coupling and mutual inductance between the transmitting (Tx) and receiving (Rx) coils in mobile devices. Due to the nonlinear behavior of magnetic flux and the high computational cost of simulations, exploring the full design space for coils using ANSYS Maxwell becomes impractical. To address this complexity, a machine learning (ML)-based optimization framework is developed to efficiently navigate the design space. The framework integrates a hybrid sequential neural network and multivariate regression model to optimize coil winding and ferrite core geometry. The optimized structure achieves a mutual inductance of 12.52 μH with a conventional core, outperforming many existing ML models. Finite element simulations and experimental results validate the robustness of the method, which offers a scalable solution for efficient wireless charging in compact, misalignment-prone environments.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020035

Authors: Juan Cuenca Benjamin Zambrano Esteban Garzón Luis Miguel Prócel Marco Lanuzza

Dynamic comparators play an important role in electronic systems, requiring high accuracy, low power consumption, and minimal offset voltage. This work proposes an accurate and low-complexity offset calibration design based on a capacitive load approach. It was designed using a 65 nm CMOS technology and comprehensively evaluated under Monte Carlo simulations and PVT variations. The proposed scheme was built using MIM capacitors and transistor-based capacitors, and it includes Verilog-based calibration algorithms. The proposed offset calibration is benchmarked, in terms of precision, calibration time, energy consumption, delay, and area, against prior calibration techniques: current injection via gate biasing by a charge pump circuit and current injection via parallel transistors. The evaluation of the offset calibration schemes relies on Analog/Mixed-Signal (AMS) simulations, ensuring accurate evaluation of digital and analog domains. The charge pump method achieved the best Energy-Delay Product (EDP) at the cost of lower long-term accuracy, mainly because of its capacitor leakage. The proposed scheme demonstrated superior performance in offset reduction, achieving a one-sigma offset of 0.223 mV while maintaining precise calibration. Among the calibration algorithms, the window algorithm performs better than the accelerated calibration. This is mainly because the window algorithm considers noise-induced output oscillations, ensuring consistent calibration across all designs. This work provides insights into the trade-offs between energy, precision, and area in dynamic comparator designs, offering strategies to enhance offset calibration.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020034

Authors: Nikolay Hinov Tsvetana Grigorova

As power electronics continue to advance, the demand for highly efficient and low-loss DC/DC converters has grown significantly. This article comprehensively analyses ZCS quasi-resonant switch cell losses and efficiency in buck L-type zero-current switching (ZCS) quasi-resonant DC/DC converters. The main part of the study includes a comparative analysis of conduction losses in semiconductor switches of conventional PWM buck converters and zero-current switching (ZCS) quasi-resonant buck converters (L-type), utilizing both specific and generalized design equations. Novel coefficients are introduced that enable the evaluation of static power losses in the classical buck converter compared to those in L-type ZCS buck quasi-resonant converters under identical conditions. The article also discusses design considerations aimed at minimizing static losses. An L-type half-mode zero-current switching (ZCS) buck quasi-resonant DC/DC converter (QRC) is implemented to verify the analytical results. Various simulations were conducted using PSpice in the Texas Instruments simulation environment, along with experimental studies at different switching frequencies and load conditions. The proposed methodology integrates both analytical and simulation approaches to analyze energy losses and key parameters influencing the converter’s efficiency. The obtained results show that the relative error between the analytical, simulation, and experimental results is below 5%.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020033

Authors: Manon Fourniol Rémy Vauché Guillaume Rao Eric Watelain Edith Kussener

In the context of aging populations, it has become necessary to develop new methods and devices for the daily home-based self-rehabilitation of elderly people. To this end, this paper proposes and evaluates the use of an easy-to-use single battery-powered device including a 3D accelerometer and a 3D gyroscope, where light algorithms, such as the complementary filter and the Kalman filter, are implemented to estimate the elbow joint angle. During experiments, a robotic arm and a human arm were used to obtain an error interval for each tested algorithm; the robotic arm allows for reproducible movements and reproducible results, which allows us to independently verify the impact of parameters such as the sensor’s movement speed on the algorithm precision. The experimental results show that the algorithm that uses only accelerometer data is one of the most relevant since it allows us to obtain a Root Mean Square Error between 1.83° and 5.52° at a sensor data rate of 100 Hz, which is similar to the results obtained using the data fusion algorithms tested. Nevertheless, it has a lower power consumption since it requires only 58 cycles when using an ARM Cortex-M4 processor (which is lower than that of the other data fusion algorithms tested by a factor of at least two), and it does not necessitate the additional sensor required by the other data fusion algorithms tested (such as a gyroscope or a magnetometer). The algorithm using only accelerometer data also seems to be the algorithm with the lowest power consumption and should be preferred. Moreover, its power consumption can be reduced by more than the increase in the error when reducing the rate of the data output by the sensor. In this work, a reduction in the data rate from 100 Hz to 10 Hz increased the RMSE by a factor of 1.8 but could reduce the power consumption associated with the sensor and the algorithm’s computation by a factor of 10. Finally, the experimental results show that the higher the speed of the sensor’s motion, the higher the error obtained using only accelerometer data. Nevertheless, the algorithm that uses only accelerometer data remains well suited to rehabilitation exercises or mobility evaluations since the speed of the sensor’s movement is also moderate.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020032

Authors: Jung-Jen Hsu Yao-Chian Lin Stephen J. H. Yang

This paper presents a 0.8 V low-power CMOS voltage-controlled oscillator (VCO) with a wide tuning range, fabricated using a TSMC 0.18 μm process. The proposed design incorporates body-biasing techniques and an optimized varactor structure to achieve a tuning range of 1124 MHz (5.829–4.705 GHz) and low phase noise of −117.6 dBc/Hz at a 1 MHz offset. Operating at an ultra-low supply voltage of 0.8 V, the VCO consumes only 3.4 mW, demonstrating excellent power efficiency. A buffer circuit is also employed to enhance output symmetry and suppress flicker noise without introducing additional control complexity. With a figure-of-merit (FOM) of −188.6 dBc/Hz and a wide tuning range of 22.2%, the proposed VCO is well-suited for modern low-power communication systems, including 802.11ac, 5G transceivers, satellite links, and compact IoT devices.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020031

Authors: Béatrice Guénégo Caroline Lelandais-Perrault Emilie Avignon-Meseldzija Gérard Sou Philippe Bénabès

The ST segment of an ECG signal is a feature that changes in the event of cardiac ischemia, a condition that is an early warning sign of myocardial infarction. Being able to monitor this feature in real time would be highly beneficial for preventing recurrent heart attacks. However, to be worn daily, such a monitoring device must be extremely miniaturized, down to the scale of a single integrated circuit. Currently, it is possible to integrate a heart rate detector, but, to our knowledge, no existing work presents a chip capable of detecting ST segment deviation. This is mainly because accurate ST segment measurement requires low-distortion signal processing, as specified in the International Electrotechnical Commission (IEC) standard. At the same time, the system is required to filter out baseline wander, whose frequency components may partially overlap with those of the ST segment. In this study, we relied on wavelet-based analysis and reconstruction to compare several wavelet types. We optimized their hyperparameters to minimize implementation complexity while satisfying the low-distortion constraints. We also propose an ASIC-oriented architecture and evaluate its post-layout performance in terms of area and power consumption. The post-layout results indicate that the Daubechies wavelet db3 offers the best trade-off among the evaluated configurations. It exhibits an area utilization of 1.18 mm2 and a post-layout power consumption of 4.89 μW, while preserving the ST segment in compliance with the IEC standard, thanks in particular to its effective baseline wandering filtering of 6.9 dB. These results demonstrate the feasibility of embedding automatic ST segment extraction on-chip.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020030

Authors: Hao Jiang Zenglong Zhao Nengxu Zhu Fanyi Meng

This paper presents an active phase shifter for phased array system applications, implemented using 0.18 μm SiGe BiCMOS technology. The phase shifter circuit consists of a wideband quadrature signal generator, a vector modulator, an input balun, and an output balun. To enhance the bandwidth, a polyphase filter is employed as the quadrature signal generator, and a two-stage RC-CR filter with a highly symmetrical miniaturized layout is cascaded to create multiple resonant points, thus extending the phase shifter’s bandwidth to cover the required range. The gain of the variable-gain amplifier within the vector modulator is adjustable by varying the tail current, thereby enlarging the range of selectable points, improving phase-shifting accuracy, and reducing gain fluctuations. The measurement results show that the proposed active phase shifter achieves an RMS phase error of less than 2° and a gain variation ranging from −1.2 dB to 0.1 dB across a 20 GHz to 30 GHz bandwidth at room temperature. The total chip area is 0.4 mm2, with a core area of 0.165 mm2, and consumes 19.5 mW of power from a 2.5 V supply.

Journal of Low Power Electronics and Applications doi: 10.3390/jlpea15020029

Authors: Xin Wang Zishuo Li Zhen Lin Fanyi Meng

This paper introduces a novel topology called the dual-path step-down converter with auxiliary switches to minimize voltage stress and enable wide voltage conversion ranges. The proposed dual-path step-down converter with auxiliary switches, which uses an inductor and flying capacitor as power conversion components, helps to reduce the voltage stress on the power switches. By adding auxiliary switches, the proposed topology achieves the same voltage conversion ratio range as that of a conventional buck converter. Additionally, soft-start technology is incorporated to reduce the initial inrush current. Furthermore, this paper introduces a system-level design procedure for DC-DC converters. Designed for low-power applications with lithium-ion (Li-ion) batteries, the proposed converter steps down the battery voltage to 1.2 V. With a 380 nH inductor and a 5 µF output capacitor, the converter attains a peak efficiency of 90% under the conditions of 2.7 V to 1.2 V conversion.