Search Results (70)

This work presents the design of a $\beta$-Ga₂O₃ MOSFET incorporating a P-type Ga₂O₃ buffer layer on a high-thermal-conductivity AlN/SiC composite substrate. The electrical characteristics of the device were simulated using Sentaurus TCAD. Results demonstrate that the integration of the composite substrate effectively mitigates self-heating effects, reducing the peak temperature ($T_{\mathit{max}}$) from 776.5 K to 570.9 K at 300 K, while simultaneously increasing the threshold voltage ($V_{\mathit{th}}$) from −0.35 V to 1.52 V. Through systematic optimization of the P-Ga₂O₃ buffer layer thickness and doping concentration, the device achieves a breakdown voltage ($V_{\mathit{br}}$) of 4781 V, a power figure of merit (PFOM) of 2.18 GW/cm², an $I_{DS}$, on/off ratio of 9.20 × 10⁹, and cut-off/maximum oscillation frequencies ($f_{\mathit{t}}$/$f_{\mathit{max}}$) of 1.29 GHz and 1.40 GHz, respectively. These findings provide a theoretical foundation for developing $\beta$-Ga₂O₃-based power devices with high breakdown voltage, improved thermal conductivity, and low specific on-resistance ($R_{\mathit{on},\mathit{sp}}$). Full article

Silicon carbide (SiC) MOSFETs are critical for next-generation power electronics, yet their reliability is challenged by alternating-current Bias Temperature Instability (AC BTI). While charge trapping and Recombination-Enhanced Defect Reaction (REDR) are known degradation pathways, the specific role of gate oxide thickness in determining the dominant mechanism remains unclear. This study investigates the degradation behaviors of SiC MOSFETs with varying oxide thicknesses under 150 kHz Dynamic Gate Stress. By maintaining a constant electric field, we decouple the effects of oxide thickness using high-frequency C-V, quasi-static gate current (I_GS) characteristics, and transconductance analysis. Results reveal that thin-oxide devices exhibit parallel C-V shifts and stable transconductance, indicating degradation driven by deep-level charge trapping. Conversely, thick-oxide devices display significant C-V stretch-out, negligible I_GS peak shifts, and severe transconductance degradation, accompanied by irreversible threshold voltage drift. We conclude that despite identical electric fields, the higher driving voltages in thick-oxide devices trigger severe interface state generation consistent with the REDR model, whereas thin-oxide devices are dominated by bulk oxide trapping. These findings highlight the necessity of thickness-dependent optimization strategies for SiC power devices. Full article

With the rapid advancement of silicon carbide technology, device reliability has emerged as a critical concern for high-performance power electronics applications. Among various reliability challenges, the limited short-circuit withstand time (SCWT) of SiC MOSFETs, coupled with significant device-to-device variation, poses a serious risk, as it can lead to catastrophic field failures. In addition, established short-circuit screening technique utilizes high-voltage and high-stress condition that may degrade the long-term reliability of otherwise good devices. Hence, this work proposes a novel short-circuit screening methodology employing lower voltages and verifies it using commercial 1.2 kV 4H-SiC MOSFETs. The proposed approach can remove devices with lower SCWT while minimizing electrical and thermal overstress during screening. The results indicate that the proposed low-voltage screening technique offers a safe, repeatable, and reliable alternative to conventional short-circuit screening method, making it well suited for practical manufacturing, leading to system-level reliability enhancement in SiC-based power electronics applications. Full article

This work presents a highly compact and scalable 1.2-kV SiC MOSFET half-bridge building-block module enabled by a die-integrated 3D PCB packaging technology. Compared with conventional DBC-based or TO-247-based SiC half-bridge modules, the proposed design reduces the physical volume and weight by more than 90% while maintaining full compatibility with standard PCB manufacturing processes. The vertically laminated DC+/DC− conductors and symmetric PCB–die–PCB stack establish a tightly confined commutation loop, resulting in a measured power-loop inductance of 2.2 nH and a 3.8 nH gate-loop inductance—representing up to 94% and 89% reduction relative to discrete device implementations. Because the parasitic parameters are intrinsically well-balanced across replicated units and the mutual inductance between adjacent modules remains extremely small, the structure naturally supports current sharing during parallel operation. Thermal and insulation evaluations further confirm the suitability of copper filling via high-Tg laminated PCB substrates for high-power SiC applications, achieving withstand voltages exceeding twice the rated bus voltage. The proposed module is experimentally validated through finite-element parasitic extraction and 950 V double-pulse testing, demonstrating controlled dv/dt behavior and robust switching performance. This work establishes a manufacturable and parallel-friendly packaging approach for high-density SiC power conversion systems. Full article

4H-SiC has been studied and applied in power semiconductor devices due to its wider band gap and higher thermal conductivity than those of Si and hence has great potential for power devices operating at high powers and high temperatures. The introduction of the superjunction (SJ) structure for the power MOSFETs enables further reduction in the ON resistance while maintaining the breakdown voltage. In this work, we examined the dc and ac performance of the 1.2 kV 4H-SiC SJ double-implanted MOSFET (DMOSFET) with different configurations of pillars by the Atlas device simulator. The simulation results suggest the step-shape SJ DMOSFET can further reduce the specific ON resistance and the gate-drain capacitance while maintaining the breakdown voltage compared with the optimized conventional SJ DMOSFET. In addition, that the multi-pillar SJ DMOSFET demonstrates better performance than that of the optimized conventional SJ DMOSFET was also verified in this work. Full article

A Si/SiC heterojunction double-trench MOSFET with improved conduction characteristics is proposed. By replacing the N+ source and P-ch regions with silicon, the device forms a Si/SiC heterojunction that exhibits Schottky-like characteristics, effectively deactivating the parasitic PiN body diode and improving third-quadrant performance. A high-k gate dielectric is incorporated to induce a strong electron accumulation layer at the heterointerface, thinning the energy barrier and enabling tunneling-dominated current transport, thereby significantly enhancing the first-quadrant performance. TCAD simulation results demonstrate that the proposed device achieves a specific on-resistance (R_on,sp) of 1.78 mΩ·cm², representing a 20.5% reduction compared to the conventional SiC DTMOS, while maintaining a comparable breakdown voltage (BV) of approximately 1380 V. A significant reduction in the third-quadrant turn-on voltage (V_on) is achieved with the proposed structure, from 2.74 V to 1.53 V. Meanwhile, the unipolar conduction mechanism similar to that of Schottky effectively suppresses bipolar degradation. To enhance device reliability, the design incorporates a trenched source and heavily doped P-well, which collectively mitigate high electric field concentrations at the trench corners. The proposed device offers an integration strategy enhancing both forward conduction and reverse conduction in high-voltage power electronics. Full article

The choice of a suitable isolated and bidirectional DC/DC converter (IBDC) topology is an important step in the design of a bidirectional electric vehicle (EV) charging system. In this context, six 10 kW rated silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET)-based dual-active bridge (DAB) converter topologies, supplied by a +750/0/−750 V bipolar DC link, are analyzed and compared in this article. The evaluation criteria include the required volt-ampere semiconductor ratings, loss distribution, efficiency, and thermal considerations of the considered converter configurations. The IBDC topologies are compared based on the observations and results obtained from theoretical analysis, electro-thermal simulations, and experiments, considering the same voltage and power conditions. The advantages and disadvantages of the topologies, in terms of the considered evaluation criteria, are discussed. It is shown that the series-resonant (SR) input-series output-parallel (ISOP) full-bridge (FB) DAB converter configuration is the most suitable design choice for the considered EV charging application based on the chosen operating conditions and evaluation criteria. Full article

This work details the development of a 10-stage solid-stage linear transformer driver (SSLTD) capable of producing 24 kV, 1 kA pulses with a rise-time of ∼10 ns utilizing SiC MOSFET switches. Throughout the development process, various design parameters were investigated for their influence on the LTD’s performance. Among these considerations was an evaluation of the behavior of several nanocrystalline magnetic core materials subject to high-voltage pulsed conditions, with an emphasis on minimizing energy losses. Another design parameter of interest lies in the physical layout of the LTD structure, particularly the diameter of the central stalk and the dielectric material, which together define the characteristics of the coaxial transmission line, as well as the overall height of each stage. The influence of each of these parameters was weighed to optimize the final design for fastest output pulse rise-time, highest efficiency, and cleanest output pulse waveform profile across varying load resistance. This work also introduces a pulsed reset technique, where repetition-rated burst testing was used to find the maximum operational frequency of the LTD without driving the magnetic cores into saturation. Full article

This study presents a machine learning-enhanced optimization framework for proton exchange membrane fuel cell (PEMFC), designed to address critical challenges in dynamic load adaptation and thermal management for automotive applications. A high-fidelity model of a 65-cell stack (45 V, 133.5 A, 6 kW) is developed in MATLAB/Simulink, integrating four core subsystems: PID-controlled fuel delivery, humidity-regulated air supply, an electrochemical-thermal stack model (incorporating Nernst voltage and activation, ohmic, and concentration losses), and a 97.2–efficient SiC MOSFET-based DC/DC boost converter. The framework employs the NSGA-II algorithm to optimize key operational parameters—membrane hydration (λ = 12–14), cathode stoichiometry (λO₂ = 1.5–3.0), and cooling flow rate (0.5–2.0 L/min)—to balance efficiency, voltage stability, and dynamic performance. The optimized model achieves a 38% reduction in model-data discrepancies (RMSE < 5.3%) compared to experimental data from the Toyota Mirai, and demonstrates a 22% improvement in dynamic response, recovering from 0 to 100% load steps within 50 ms with a voltage deviation of less than 0.15 V. Peak performance includes 77.5% oxygen utilization at 250 L/min air flow (1.1236 V/cell) and 99.89% hydrogen utilization at a nominal voltage of 48.3 V, yielding a peak power of 8112 W at 55% stack efficiency. Furthermore, fuzzy-PID control of fuel ramping (50–85 L/min in 3.5 s) and thermal management (ΔT < 1.5 °C via 1.0–1.5 L/min cooling) reduces computational overhead by 29% in the resulting digital twin platform. The framework demonstrates compliance with ISO 14687-2 and SAE J2574 standards, offering a scalable and efficient solution for next-generation fuel cell electric vehicle (FCEV) aligned with global decarbonization targets, including the EU’s 2035 CO₂ neutrality mandate. Full article

Silicon carbide (SiC) MOSFETs with voltage ratings above 3.3 kV are emerging as key enablers for next-generation medium-voltage (MV) power conversion systems, offering superior blocking capabilities, faster switching speeds, and an improved thermal performance compared to conventional silicon IGBTs. However, the practical deployment of 10 kV SiC devices remains constrained by the immaturity of high-voltage chip and packaging technologies. Current development is often limited to engineering samples provided by a few suppliers and custom packaging solutions evaluated only in laboratory settings. To advance the commercialization of 10 kV SiC power modules, this paper presents the design and characterization of a 10 kV, 60 A half-bridge module employing the XHP housing and newly developed SiC MOSFET chips from China Electronics Technology Group Corporation (CETC). Electro-thermal simulations based on a finite element analysis were conducted to extract key performance parameters, with a measured parasitic inductance of 24 nH and a thermal resistance of 0.0948 K/W. To further validate the packaging concept, a double-pulse test platform was implemented. The dynamic switching behavior of the module was experimentally verified under a 6 kV DC-link voltage, demonstrating the feasibility competitiveness of this approach and paving the way for the industrial adoption of 10 kV SiC technology in MV applications. Full article

This paper presents the design and implementation of a high-efficiency, full silicon carbide (SiC)-based center-tapped phase-shifted full-bridge (PSFB) converter for NiCd battery charging applications in railway systems. The converter utilizes SiC MOSFET modules on the primary side and SiC diodes on the secondary side, resulting in significant efficiency improvements due to the superior switching characteristics and high-temperature tolerance inherent in SiC devices. A nanocrystalline-cored center-tapped transformer is optimized to minimize voltage stress on the rectifier diodes. Additionally, the use of a nanocrystalline core provides high saturation flux density, low core loss, and excellent permeability, particularly at high frequencies, which significantly enhances system efficiency. The converter also compensates for temperature fluctuations during operation, enabling a wide and adjustable output voltage range according to the temperature differences. A prototype of the 10-kW, 50-kHz PSFB converter, operating with an input voltage range of 700–750 V and output voltage of 77–138 V, was developed and tested both through simulations and experimentally. The converter achieved a maximum efficiency of 97% and demonstrated a high power density of 2.23 kW/L, thereby validating the effectiveness of the proposed design for railway battery charging applications. Full article

SiC MOSFETs are becoming increasingly popular due to their superior material properties, but they lack the required reliability and ruggedness for safe applications. One of the biggest challenges in short-circuit (SC) reliability of the commercial devices and hence in the SC protection circuit design is the variability of SC withstand time (SCWT) among the devices from the same vendor, even with the same lot and batch number. In this work, a novel SC screening methodology has been presented to remove devices with lower SCWT from a pool of devices without damaging the reliable ones. The SC screening methodology has been developed using Sentaurus TCAD simulation, which is further verified using commercial devices. This work can potentially reduce field failure and, as a result, can enhance the reliability of the SiC MOSFETs in real-world applications. Full article

This paper investigates the short-circuit characteristics of 1.2 kV symmetrical and asymmetrical trench-gate SiC MOSFETs. Based on the self-designed short-circuit test platform, single and repetitive short-circuit tests were carried out to characterize the short-circuit capability of the devices under different electrical stresses through the short-circuit withstanding time (SCWT). Notably, the asymmetric trench structure exhibited a superior short-circuit capability under identical test conditions, achieving a longer SCWT compared to its symmetrical counterpart. Moreover, TCAD was used to model the two devices and fit the short-circuit current waveforms to study the difference in short-circuit characteristics under different conditions. For the degradation of the devices after repetitive short-circuit stresses, repetitive short-circuit pulse experiments were conducted for the two groove structures separately. The asymmetric trench devices show a positive Vth drift, increasing on-resistance, increasing C_gs and C_ds, and decreasing C_gd, while the symmetric trench devices show a negative Vth drift, decreasing on-resistance, and inverse variation in capacitance parameters. Both blocking voltages are degraded, but the gate-source leakage current remains low, indicating that the gate oxide has not yet been damaged. Full article

The high switching speed of SiC MOSFETs can induce resonance between parasitic inductors and capacitors, owing to rapid changes in current and voltage, leading to excessive crosstalk parasitic oscillation. This can increase SiC MOSFETs’ gate oxide voltage stress, reducing their service life and even directly leading to gate overvoltage failure. However, there is still a lack of investigations of active control of gate driving in systematic converters because crosstalk parasitic oscillation, indicated by high frequencies in MHz, is challenging to control in a power converter with gate voltage stability and high switching speed. This paper investigates an active gate drive based on negative feedback to fully drive SiC MOSFETs with high efficiency and stable gate voltage to exploit the advantages of high dv/dt over 20 V/ns in SiC MOSFETs and further realize the miniaturization of power conversion systems. It first investigates a dynamic model of SiC MOSFET gate-interfered oscillation in parallel application derived from a circuit with equivalent junction capacitance in power devices. Then, the operating principle of the Negative Feedback Active Gate Drive (NFAGD) application strategy for parallel SiC MOSFETs is demonstrated. Finally, the experiment verifies the proposed strategy’s effectiveness in suppressing crosstalk parasitic oscillation in parallel SiC MOSFETs, and an 8 kW synchronous buck converter prototype is built to verify the NFAGD’s performance in systematic converter applications. Full article

This paper proposes a 1200V 4H-SiC MOSFET incorporating a High-K dielectric-integrated fused source-gate (HKSG) structure, engineered to concurrently enhance the third-quadrant operation and high-frequency figure of merit (HF-FOM). The High-K dielectric enhances the electric field effect, reducing the threshold voltage of the source-gate. As a result, the reverse conduction voltage drops from 2.79 V (body diode) to 1.53 V, and the bipolar degradation is eliminated. Moreover, by incorporating a shielding area within the merged source-gate architecture, the gate-to-drain capacitance C_gd of the HKSG-MOS is reduced. The simulation results show that the HF-FOM C_gd × R_on,sp and Q_gd × R_on,sp of the HKSG-MOS are decreased by 48.1% and 58.9%, respectively, compared with that of conventional SiC MOSFET. The improved performances make the proposed SiC MOSFEET have great potential in high-frequency power applications. Full article