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9 pages, 2339 KB

Open AccessArticle

Demonstration of Steep Switching Behavior Based on Band Modulation in WSe₂ Feedback Field-Effect Transistor

by Seung-Mo Kim, Jae Hyeon Jun, Junho Lee, Muhammad Taqi, Hoseong Shin, Sungwon Lee, Haewon Lee, Won Jong Yoo and Byoung Hun Lee

Nanomaterials 2024, 14(20), 1667; https://doi.org/10.3390/nano14201667 - 17 Oct 2024

Cited by 1 | Viewed by 2119

Abstract

Feedback field-effect transistors (FBFETs) have been studied to obtain near-zero subthreshold swings at 300 K with a high on/off current ratio ~10¹⁰. However, their structural complexity, such as an epitaxy process after an etch process for a Si channel with a [...] Read more.

Feedback field-effect transistors (FBFETs) have been studied to obtain near-zero subthreshold swings at 300 K with a high on/off current ratio ~10¹⁰. However, their structural complexity, such as an epitaxy process after an etch process for a Si channel with a thickness of several nanometers, has limited broader research. We demonstrated a FBFET using in-plane WSe₂ p−n homojunction. The WSe₂ FBFET exhibited a minimum subthreshold swing of 153 mV/dec with 30 nm gate dielectric. Our modeling-based projection indicates that the swing of this device can be reduced to 14 mV/dec with 1 nm EOT. Also, the gain of the inverter using the WSe₂ FBFET can be improved by up to 1.53 times compared to a silicon CMOS inverter, and power consumption can be reduced by up to 11.9%. Full article

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9 pages, 2172 KB

Open AccessCommunication

Generation and Storage of Random Voltage Values via Ring Oscillators Comprising Feedback Field-Effect Transistors

by Jaemin Son, Juhee Jeon, Kyoungah Cho and Sangsig Kim

Nanomaterials 2024, 14(7), 562; https://doi.org/10.3390/nano14070562 - 23 Mar 2024

Viewed by 1911

Abstract

In this study, we demonstrate the generation and storage of random voltage values using a ring oscillator consisting of feedback field-effect transistors (FBFETs). This innovative approach utilizes the logic-in-memory function of FBFETs to extract continuous output voltages from oscillatory cycles. The ring oscillator [...] Read more.

In this study, we demonstrate the generation and storage of random voltage values using a ring oscillator consisting of feedback field-effect transistors (FBFETs). This innovative approach utilizes the logic-in-memory function of FBFETs to extract continuous output voltages from oscillatory cycles. The ring oscillator exhibited uniform probability distributions of 51.6% for logic 0 and 48.4% for logic 1. The generation of analog voltages provides binary random variables that are stored for over 5000 s. This demonstrates the potential of the ring oscillator in advanced physical functions and true random number generator technologies. Full article

(This article belongs to the Special Issue Nanostructured Electronic Components and Devices)

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9 pages, 2517 KB

Open AccessCommunication

Temperature-Dependent Feedback Operations of Triple-Gate Field-Effect Transistors

by Taeho Park, Kyoungah Cho and Sangsig Kim

Nanomaterials 2024, 14(6), 493; https://doi.org/10.3390/nano14060493 - 9 Mar 2024

Viewed by 1785

Abstract

In this study, we examine the electrical characteristics of triple-gate feedback field-effect transistors (TG FBFETs) over a temperature range of −200 °C to 280 °C. With increasing temperature from 25 °C to 280 °C, the thermally generated charge carriers increase in the channel [...] Read more.

In this study, we examine the electrical characteristics of triple-gate feedback field-effect transistors (TG FBFETs) over a temperature range of −200 °C to 280 °C. With increasing temperature from 25 °C to 280 °C, the thermally generated charge carriers increase in the channel regions such that a positive feedback loop forms rapidly. Thus, the latch-up voltage shifts from −1.01 V (1.34 V) to −11.01 V (10.45 V) in the n-channel (p-channel) mode. In contrast, with decreasing temperature from 25 °C to −200 °C, the thermally generated charge carriers decrease, causing a shift in the latch-up voltage in the opposite direction to that of the increasing temperature case. Despite the shift in the latch-up voltage, the TG FBFETs exhibit ideal switching characteristics, with subthreshold swings of 6.6 mV/dec and 7.2 mV/dec for the n-channel and p-channel modes, respectively. Moreover, the memory window widens with increasing temperature. Specifically, at temperatures above 85 °C, the memory windows are wider than 3.05 V and 1.42 V for the n-channel and p-channel modes, respectively. Full article

(This article belongs to the Special Issue Innovation in Nanoelectronic Semiconductor Devices and Materials)

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7 pages, 1458 KB

Open AccessCommunication

Doping-Less Feedback Field-Effect Transistors

by Hakin Kim and Doohyeok Lim

Micromachines 2024, 15(3), 316; https://doi.org/10.3390/mi15030316 - 24 Feb 2024

Cited by 2 | Viewed by 2374

Abstract

In this study, we propose doping-less feedback field-effect transistors (DLFBFETs). Our DLFBFETs are 5 nm thick intrinsic semiconductor bodies with dual gates. Usually, DLFBFETs are virtually doped through charge plasma phenomena caused by the source, the drain, and the dual-gate electrodes as well [...] Read more.

In this study, we propose doping-less feedback field-effect transistors (DLFBFETs). Our DLFBFETs are 5 nm thick intrinsic semiconductor bodies with dual gates. Usually, DLFBFETs are virtually doped through charge plasma phenomena caused by the source, the drain, and the dual-gate electrodes as well as the gate biases. Our DLFBFETs can be fabricated through a simple process of creating contact between a metal and a silicon body without any doping processes. The voltages applied to both gates determine whether the DLFBFETs operate in diode or feedback field-effect transistor (FBFET) modes. In the FBFET mode, our DLFBFETs show good characteristics such as an on/off current ratio of ~10⁴ and steep switching characteristics (~1 mV/decade of current) that result from positive feedback phenomena without dopants. Full article

(This article belongs to the Section D1: Semiconductor Devices)

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7 pages, 2055 KB

Open AccessCommunication

Read Operation Mechanism of Feedback Field-Effect Transistors with Quasi-Nonvolatile Memory States

by Juhee Jeon, Kyoungah Cho and Sangsig Kim

Nanomaterials 2024, 14(2), 210; https://doi.org/10.3390/nano14020210 - 18 Jan 2024

Cited by 2 | Viewed by 2400

Abstract

In this study, the read operation of feedback field-effect transistors (FBFETs) with quasi-nonvolatile memory states was analyzed using a device simulator. For FBFETs, write pulses of 40 ns formed potential barriers in their channels, and charge carriers were accumulated (depleted) in these channels, [...] Read more.

In this study, the read operation of feedback field-effect transistors (FBFETs) with quasi-nonvolatile memory states was analyzed using a device simulator. For FBFETs, write pulses of 40 ns formed potential barriers in their channels, and charge carriers were accumulated (depleted) in these channels, generating the memory state “State 1 (State 0)”. Read pulses of 40 ns read these states with a retention time of 3 s, and the potential barrier formation and carrier accumulation were influenced by these read pulses. The potential barriers were analyzed, using junction voltage and current density to explore the memory states. Moreover, FBFETs exhibited nondestructive readout characteristics during the read operation, which depended on the read voltage and pulse width. Full article

(This article belongs to the Special Issue Semiconductor Nanomaterials for Memory Devices)

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12 pages, 1954 KB

Open AccessArticle

Investigation of the Electrical Coupling Effect for Monolithic 3-Dimensional Nonvolatile Memory Consisting of a Feedback Field-Effect Transistor Using TCAD

by Jong Hyeok Oh and Yun Seop Yu

Micromachines 2023, 14(10), 1822; https://doi.org/10.3390/mi14101822 - 23 Sep 2023

Viewed by 1799

Abstract

In this study, the electrical characteristics and electrical coupling effect for monolithic 3-dimensional nonvolatile memory consisting of a feedback field-effect transistor (M3D-NVM-FBFET) were investigated using technology computer-aided design. The M3D-NVM-FBFET consists of an N-type FBFET with an oxide–nitride–oxide layer and a metal–oxide–semiconductor FET [...] Read more.

In this study, the electrical characteristics and electrical coupling effect for monolithic 3-dimensional nonvolatile memory consisting of a feedback field-effect transistor (M3D-NVM-FBFET) were investigated using technology computer-aided design. The M3D-NVM-FBFET consists of an N-type FBFET with an oxide–nitride–oxide layer and a metal–oxide–semiconductor FET (MOSFET) in the top and bottom tiers, respectively. For the memory simulation, the programming and erasing voltages were applied at 18 and −18 V for 1 μs, respectively. The memory window of the M3D-NVM-FBFET was 1.98 V. As the retention simulation was conducted for 10 years, the memory window decreased from 1.98 to 0.83 V. For the M3D-NVM-FBFET, the electrical coupling that occurs through an electrical signal in the bottom-tier transistor was investigated. As the thickness of the interlayer dielectric (T_ILD) decreases from 100 to 10 nm, the change in the V_TH increases from 0.16 to 0.87 V and from 0.15 to 0.84 V after the programming and erasing operations, respectively. M3D-NVM-FBFET circuits with a thin T_ILD of 50 nm or less need to be designed considering electrical coupling. Full article

(This article belongs to the Special Issue Recent Advances in Memory Materials and Devices)

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10 pages, 3307 KB

Open AccessArticle

Disturbance Characteristics of 1T DRAM Arrays Consisting of Feedback Field-Effect Transistors

by Juhee Jeon, Kyoungah Cho and Sangsig Kim

Micromachines 2023, 14(6), 1138; https://doi.org/10.3390/mi14061138 - 28 May 2023

Cited by 16 | Viewed by 4510

Abstract

Challenges in scaling dynamic random-access memory (DRAM) have become a crucial problem for implementing high-density and high-performance memory devices. Feedback field-effect transistors (FBFETs) have great potential to overcome the scaling challenges because of their one-transistor (1T) memory behaviors with a capacitorless structure. Although [...] Read more.

Challenges in scaling dynamic random-access memory (DRAM) have become a crucial problem for implementing high-density and high-performance memory devices. Feedback field-effect transistors (FBFETs) have great potential to overcome the scaling challenges because of their one-transistor (1T) memory behaviors with a capacitorless structure. Although FBFETs have been studied as 1T memory devices, the reliability in an array must be evaluated. Cell reliability is closely related to device malfunction. Hence, in this study, we propose a 1T DRAM consisting of an FBFET with a p⁺–n–p–n⁺ silicon nanowire and investigate the memory operation and disturbance in a 3 × 3 array structure through mixed-mode simulations. The 1T DRAM exhibits a write speed of 2.5 ns, a sense margin of 90 μA/μm, and a retention time of approximately 1 s. Moreover, the energy consumption is 5.0 × 10⁻¹⁵ J/bit for the write ‘1’ operation and 0 J/bit for the hold operation. Furthermore, the 1T DRAM shows nondestructive read characteristics, reliable 3 × 3 array operation without any write disturbance, and feasibility in a massive array with an access time of a few nanoseconds. Full article

(This article belongs to the Special Issue Advances in Nanoscale Semiconductor Devices: Design, Fabrication and Application)

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9 pages, 5392 KB

Open AccessBrief Report

Capacitor-Less Low-Power Neuron Circuit with Multi-Gate Feedback Field Effect Transistor

by Junhyeong Lee, Misun Cha and Min-Woo Kwon

Appl. Sci. 2023, 13(4), 2628; https://doi.org/10.3390/app13042628 - 17 Feb 2023

Cited by 8 | Viewed by 2656

Abstract

Recently, research on artificial neuron circuits imitating biological systems has been actively studied. The neuron circuit can implement an artificial neural network (ANN) capable of low-power parallel processing by configuring a biological neural network system in hardware. Conventional CMOS analog neuron circuits require [...] Read more.

Recently, research on artificial neuron circuits imitating biological systems has been actively studied. The neuron circuit can implement an artificial neural network (ANN) capable of low-power parallel processing by configuring a biological neural network system in hardware. Conventional CMOS analog neuron circuits require many MOSFETs and membrane capacitors. Additionally, it has low energy efficiency in the first inverter stage connected to the capacitor. In this paper, we propose a low-power neuron circuit with a multi-gate feedback field effect transistor (FBFET) that can perform integration without a capacitor to solve the problem of an analog neuron circuit. The multi-gate FBFET has a low off-current due to its low operating voltage and excellent sub-threshold characteristics. We replace the n-channel MOSFET of the inverter with FBFET to suppress leakage current. FBFET devices and neuron circuits were analyzed using TACD and SPICE mixed-mode simulation. As a result, we found that the neuron circuit with multi-gate FBFET has a low subthreshold slope and can completely suppress energy consumption. We also verified the temporal and spatial integration of neuron circuits. Full article

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10 pages, 2096 KB

Open AccessArticle

A Monolithic 3-Dimensional Static Random Access Memory Containing a Feedback Field Effect Transistor

by Jong Hyeok Oh and Yun Seop Yu

Micromachines 2022, 13(10), 1625; https://doi.org/10.3390/mi13101625 - 28 Sep 2022

Cited by 4 | Viewed by 2647

Abstract

A monolithic three-dimensional integrated static random access memory containing a feedback field effect transistor (M3D-FBFET-SRAM) was proposed. The M3D-FBFET-SRAM cell consists of one metal oxide semiconductor field effect transistor (MOSFET) and one FBFET, and each transistor is located on the top tier and [...] Read more.

A monolithic three-dimensional integrated static random access memory containing a feedback field effect transistor (M3D-FBFET-SRAM) was proposed. The M3D-FBFET-SRAM cell consists of one metal oxide semiconductor field effect transistor (MOSFET) and one FBFET, and each transistor is located on the top tier and one on the bottom tier in a monolithic 3D integration, respectively. The electrical characteristics and operation of the NFBFET in the M3D-FBFET-SRAM cell were investigated using a TCAD simulator. For SRAM operation, the optimum doping profile of the NFBFET was used for non-turn-off characteristics. For the M3D-FBFET-SRAM cell, the operation of the SRAM and electrical coupling occurring between the top and bottom tier transistor were investigated. As the thickness of interlayer dielectric decreases, the reading ‘ON’ current decreases. To prevent performance degradation, two ways to compensate for current level were suggested. Full article

(This article belongs to the Special Issue NANO KOREA 2022)

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8 pages, 1682 KB

Open AccessArticle

Design and Simulation of Logic-In-Memory Inverter Based on a Silicon Nanowire Feedback Field-Effect Transistor

by Eunwoo Baek, Jaemin Son, Kyoungah Cho and Sangsig Kim

Micromachines 2022, 13(4), 590; https://doi.org/10.3390/mi13040590 - 9 Apr 2022

Cited by 11 | Viewed by 3043

Abstract

In this paper, we propose a logic-in-memory (LIM) inverter comprising a silicon nanowire (SiNW) n-channel feedback field-effect transistor (n-FBFET) and a SiNW p-channel metal oxide semiconductor field-effect transistor (p-MOSFET). The hybrid logic and memory operations of the LIM inverter were investigated by mixed-mode [...] Read more.

In this paper, we propose a logic-in-memory (LIM) inverter comprising a silicon nanowire (SiNW) n-channel feedback field-effect transistor (n-FBFET) and a SiNW p-channel metal oxide semiconductor field-effect transistor (p-MOSFET). The hybrid logic and memory operations of the LIM inverter were investigated by mixed-mode technology computer-aided design simulations. Our LIM inverter exhibited a high voltage gain of 296.8 (V/V) when transitioning from logic ‘1’ to ‘0’ and 7.9 (V/V) when transitioning from logic ‘0’ to ‘1’, while holding calculated logic at zero input voltage. The energy band diagrams of the n-FBFET structure demonstrated that the holding operation of the inverter was implemented by controlling the positive feedback loop. Moreover, the output logic can remain constant without any supply voltage, resulting in zero static power consumption. Full article

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11 pages, 13946 KB

Open AccessArticle

Optimization of Feedback FET with Asymmetric Source Drain Doping Profile

by Inyoung Lee, Hyojin Park, Quan The Nguyen, Garam Kim, Seongjae Cho and Ilhwan Cho

Micromachines 2022, 13(4), 508; https://doi.org/10.3390/mi13040508 - 25 Mar 2022

Cited by 2 | Viewed by 3615

Abstract

A feedback field-effect transistor (FBFET) is a novel device that uses a positive feedback mechanism. FBFET has a high on-/off ratio and is expected to realize ideal switching characteristics through steep changes from off-state to on-state. In this paper, we propose and optimize [...] Read more.

A feedback field-effect transistor (FBFET) is a novel device that uses a positive feedback mechanism. FBFET has a high on-/off ratio and is expected to realize ideal switching characteristics through steep changes from off-state to on-state. In this paper, we propose and optimize FBFET devices with asymmetric source/drain doping concentrations. Additionally, we discuss the changes in electrical characteristics across various channel length and channel thickness conditions and compare them with those of FBFET with a symmetric source/drain. This shows that FBFET with an asymmetric source/drain has a higher on-/off ratio than FBFET with a symmetric source/drain. Full article

(This article belongs to the Special Issue Steep Switching Field Effect Transistor)

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11 pages, 2476 KB

Open AccessArticle

Investigation of Monolithic 3D Integrated Circuit Inverter with Feedback Field Effect Transistors Using TCAD Simulation

by Jong Hyeok Oh and Yun Seop Yu

Micromachines 2020, 11(9), 852; https://doi.org/10.3390/mi11090852 - 13 Sep 2020

Cited by 10 | Viewed by 4016

Abstract

The optimal structure and process for the feedback field-effect transistor (FBFET) to operate as a logic device are investigated by using a technology computer-aided design mixed-mode simulator. To minimize the memory window of the FBFET, the channel length (L_ch), thickness [...] Read more.

The optimal structure and process for the feedback field-effect transistor (FBFET) to operate as a logic device are investigated by using a technology computer-aided design mixed-mode simulator. To minimize the memory window of the FBFET, the channel length (L_ch), thickness of silicon body (T_si), and doping concentration (N_ch) of the channel region below the gate are adjusted. As a result, the memory window increases as L_ch and T_si increase, and the memory window is minimum when N_ch is approximately 9 × 10¹⁹ cm⁻³. The electrical coupling between the top and bottom tiers of a monolithic 3-dimensional inverter (M3DINV) consisting of an n-type FBFET located at the top tier and a p-type FBFET located at the bottom tier is also investigated. In the M3DINV, we investigate variation of switching voltage with respect to voltage transfer characteristics (VTC), with different thickness values of interlayer dielectrics (T_ILD), T_si, L_ch, and N_ch. The variation of propagation delay of the M3DINV with different T_ILD, T_si, L_ch, and N_ch is also investigated. As a result, the electrical coupling between the stacked FBFETs by T_ILD can be neglected. The switching voltage gaps increase as L_ch and T_si increase and decrease, respectively. Furthermore, the slopes of VTC of M3DINV increase as T_si and N_ch increase. For transient response, t_pHL decrease as L_ch, T_si, and N_ch increase, but t_pLH increase as L_ch and T_si increase and it is almost the same for N_ch. Full article

(This article belongs to the Section E：Engineering and Technology)

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19 pages, 5264 KB

Open AccessArticle

Understanding of Feedback Field-Effect Transistor and Its Applications

by Changhoon Lee, Juho Sung and Changhwan Shin

Appl. Sci. 2020, 10(9), 3070; https://doi.org/10.3390/app10093070 - 28 Apr 2020

Cited by 33 | Viewed by 10292

Abstract

Feedback field-effect transistors (FBFETs) are devices based on a positive feedback loop in which the electrons and holes in the channel region act on the energy states of the potential barrier and wall. Owing to the positive feedback phenomenon, FBFETs have an excellent [...] Read more.

Feedback field-effect transistors (FBFETs) are devices based on a positive feedback loop in which the electrons and holes in the channel region act on the energy states of the potential barrier and wall. Owing to the positive feedback phenomenon, FBFETs have an excellent subthreshold swing (~0 mV/decade at 300 K), a high on-/off current ratio (~10¹⁰), and a clear saturation region. The power consumption of both the turn-on state and turn-off state is significantly low until operation commences. In addition, the hysteresis caused by the carriers accumulated in the potential wall allows the FBFET to act as a memory device. Moreover, the power consumption of neuromorphic devices can be suppressed by ~100 times with the use of FBFETs. In this work, we analyze the device structure and operating principle of the FBFET and summarize its applications. Full article

(This article belongs to the Special Issue Device Modeling for TCAD and Circuit Simulation)

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