Coordination of SRF-PLL and Grid Forming Inverter Control in Microgrid with Solar PV and Energy Storage

Abstract

Recently, there has been a huge advancement in renewable energy integration in power systems. Power converters with grid-forming or grid-following topologies are typically employed to link these decentralized power sources to the grid. However, because distributed generation has less inertia than synchronous generators, their use of renewable energy sources threatens the electrical grid’s reliability. Suitable control approaches for ensuring frequency and voltage stability in the grid-connected form of operation are established in this study, which offers dynamic, seamless power switching in the islanded mode of operation. In this research, effective Phase Locked Loop (PLL) techniques for grid-forming (GFM) and grid-following (GFL) converters are designed to achieve a smooth transition from grid-tied to islanded mode of operation. In this work, PLL configurations are implemented while considering the active and reactive power, frequency, voltage, and current parameters of the system, and ensuring voltage and frequency stability. The simulation results in a microgrid network that ensures a smooth transition of power transfer while switching between modes of operation, and supports the voltage and frequency stability of the system.

1. Introduction

Renewable energy systems in the power system have gained popularity in the last two decades due to the increased energy demand and depletion of fossil fuels. This paper compares and develops three PLL methods (Traditional PLL, Non-Frequency-Dependent (NTD-PLL) and Second-Order Generalized Integrator (SOGI-PLL)), and the cascaded delayed signal cancellation Phase Locked Loop (CDSC-PLL). Synchronous Reference Frame (SRF) PLL architecture and modeling, as well as simulation results for harmonics, voltage dip, phase jump, and frequency fluctuations, are provided. The open loop approach detects grid voltage zero crossing and filters it directly. The PLL technique detects grid voltage phase angle quickly and accurately for grid-connected power converter synchronization. PLL controls regulate grid-side parameters: voltage dips, phase angle jumps, frequency fluctuations, and higher harmonics et al. The authors of [1] proposed a method to increase system stability and PLL bandwidth without affecting SOGI harmonic rejection. This is a three-phase grid synchronization technique that separates the DSOGI harmonic filtering subsystem from the main PLL block. Because the PLL gain in a conventional DSOGI-PLL configuration is substantially larger, it can monitor grid voltage frequency changes and phase jumps [2]. An axis drift control adapting the CDSC-PLL is proposed. When the grid frequency varies, the predicted grid angle of the PLL drifts with an error residual proportionate to the frequency, limiting the accuracy as well as performance of traditional CDSC-PLLs. The analysis of the adaptive loop replaces conventional control methods to make the system more reliable. The suggested LPN-PLL in [3] is a better PLL that employs FFT-PLL to tolerate grid voltage harmonics and imbalance. The SRF-PLL and FFT-PLL were used to compare with the suggested PLL method. Despite changes in grid voltage phase and frequency, the LPN-PLL was able to reject disturbances caused by grid voltage sag, imbalance, and harmonic distortion. By utilizing the FFT principle, the FFT-PLL synchronization method avoided the need for three-phase voltage and PI controller gain tuning, in contrast to the SRF-PLL approach [4]. The idea of relative harmonic gain error measures digital implementation as a result of grid-frequency fluctuations and nonideal system sampling frequencies. Both the synchronous dq-frame and the stationary αβ-frame are used to analyse the generalised DSC and CDSC operators. A practical implementation difficulty is addressed in [5], which transfers the dq-frame DSC/CDSC operator to the αβ-frame. PLL loops utilize the conditioned voltage signal to attain rapid transient response while maintaining a broad control bandwidth, all while preventing steady-state inaccuracies [6]. We go over a novel method for detecting positive-sequence voltages in [7] to respond quickly, precisely, and frequency-adaptively to different grid situations. The instantaneous symmetrical components (ISC) approach to the αβ reference frame simplifies the calculation of the positive sequence voltage component [8]. Due to its simplicity and reliability, SRF-PLL is a popular synchronization method. Under optimal grid conditions, the SRF-PLL detects phase/frequency quickly and accurately [9]. Detecting the utility voltage’s phase angle, amplitude, and frequency is crucial for generating reference signals and meeting new standards [10]. Due to Delayed Signal Cancellation (DSC), the generalized DSC (GDSC) operator is an intriguing PLL prefiltering option. As usual, the GDSC operator feeds the grid fundamental component to a regular synchronous reference frame PLL. SRF-PLL frequency estimates are sent back to the GDSC operator to make it frequency-adaptable [11]. The test findings support the proposed system’s control approach under steady-state and dynamic situations, such as load inequalities and solar insolation changes. In [12,13,14], the authors has proposed a controller for seamless transition between grid connected mode and islanded mode of operation. An overview of GFM inverters, and recent innovations in GFM inverters were discussed in [15]. The study in [16,17,18] shows that the grid-forming converter can provide grid support functions under normal operating conditions, and fault ride-through capability can be achieved by only changing the outer power reference generation, rather than the inner structure. In this work, Grid Forming (GFM) and Grid Following (GFL) inverter controls are developed for solar PV systems in a microgrid network. The different PLL techniques are tested in both a GFL and a GFM control-based inverter. The proposed models are tested in a microgrid test system and the results are validated. Using a proper resynchronization with PLL unit, the grid-connected solar PV with a Battery Energy Storage System (BESS) can be islanded and resynchronized with the main grid with less switching transients and faster resynchronization. But, the grid-forming inverters can restore the grid after a blackout along with other sources without the need for a PLL unit. Even during disturbance in the grid, it is essential to maintain the renewable energy integration and ensuring grid stability. Grid-forming control adjusts the inverter’s voltage and frequency, making the inverter act like a voltage source. Droop-based, virtual synchronous machine, virtual oscillator, direct power, and matching control methods are well-known GFM control methods, while the GFL inverter considers grid voltage and current as the reference to generated the PWM signal fed to the inverter.

2. Schematic Representation of Microgrid

A grid-connected microgrid has been developed with both GFM and GFL inverter controls for solar PV and battery systems in order to understand system response during disturbances such as load changes, grid faults, and inverter switching. The schematic layout of the microgrid is as shown in Figure 1.

Table 1. Specifications of microgrid test system.

Description	Value
Solar PV	1 MW
DC Link Voltage	750 V
Battery	1 MWh
Voltage at point of common coupling	600 V
Inverter	10 MVA
Boost converter	1.5 MW
Bidirectional converter	1.5 MW

provides the system specifications of the microgrid. The PLL technique regulates the inverter’s output frequency to a reference signal with a feedback loop. A phase detector, a voltage-controlled oscillator, and a loop filter are needed to maintain the output phase and frequency of the microgrid network.

2.1. Proposed Methodology of Microgrid Inverter Controls

2.1.1. Grid following Type Solar PV Fed Inverter

The proposed control technique makes the PV and battery inverter operate in grid-connected, island, and resynchronization modes of operation. The grid-following inverter control mechanism of the grid-integrated PV system with a battery is shown in Figure 2. Most grid converters that include renewable energy are grid-following-type voltage source converters [6]. The grid-following type of inverter control needs a grid reference for regulating the voltage and frequency of the microgrid, and the GFL inverter maintains roughly constant output currents or power during load disruptions [7,12].

Figure 2a shows the PLL block diagram, Figure 2b displays the V_dc control loop, Figure 2c represents the current control loop, Figure 2d shows PWM generation of the GFL-type inverter control algorithm and Figure 2e shows the Boost control. In the V_dc control loop, $i_{dref}$ is calculated as follows:

$$i_{dref}=\left[k_p+\frac{k_i}{s}\right](Vd{c}_{ref}-Vd{c}_{meas})$$

(1)

where $Vd{c}_{ref}$ and $Vd{c}_{meas}$ are the references and actual DC voltage in the dc link, respectively. The PI controller’s K_p and K_i, respectively, represent the proportional and integral gains of the PI controller.

T_i = K_p/K_i

(2)

2.1.2. Grid-Forming Type Inverter

A grid-forming inverter is required by the MG during islanding operation in order to compute reference values of voltage and frequency. Here, the voltage-fed inverter behaves more or less like a voltage source since the grid-forming (GFM) inverter controls both voltage and frequency [7]. The control algorithms for grid forming inverter is shown in Figure 3. The control algorithm consists of PLL block as in Figure 3a, voltage and current control block as in Figure 3b, current control block as shown in Figure 3c, resynchronization unit as shown in Figure 3d, droop control strategy as shown in Figure 3e and PWM generation as shown in Figure 3f. Figure 3b displays the voltage control loop Vdc, which computes the $i_{dref}$. The converter’s output voltage is maintained by an internal voltage control loop, which is cascaded with a current control loop to limit LC filter resonance and prevent overcurrent.

The reference voltage $V_{ref}$ and the observed d-q voltages are processed by the voltage regulators to provide the reference currents $I_d$ ref and $I_q$ ref. Figure 3 depicts voltage-independent control using two different PI controllers. The $I_d$ and $I_q$ in the reference frame are calculated as follows:

$$I_{dref}=\left[k_p+\frac{k_i}{s}\right]\left(V_{dref}-V_{dmeas}\right)$$

(3)

$$I_{qref}=\left[k_p+\frac{k_i}{s}\right]\left(0-V_{qmeas}\right)$$

(4)

where $V_{dref}$ is modified as the reference voltage signal. The d-axis active and reactive voltage components are denoted as $V_{dmeas}$ and $V{q}_{meas}$, respectively; Kp and Ki represent the proportional and integral gains, respectively, of the PI controller. $I_d$ and $I{d}_{ref}$ are the inverter current components on the d-axis, both actual and reference; and $I_q$ and $I{q}_{ref}$ are actual reference inverter current components on the q-axis. In this work, the dq frame shown in Figure 3c has individual output current regulations for each phase. The $V_{dq}$ is the L-inductor filter, and utilizing the PI controller’s output, voltage references are generated: $V_d$ Conversion and $V_q$ Conversion. By modifying the current component’s id and $i_q$ at the inverter output, controlling the quantities of active and reactive power is feasible [14,15].

As a measure of system strength at the PV POI, short circuit ratio (SCR) is used in this example.

• The SCR is calculated by dividing the three-phase short circuit mega volt ampere (MVA) at a given location by the associated renewable source’s megawatt (MW) rating.

$$SCR=\frac{Short circuit MVA at POI}{MW of renewable power injected at POI}$$

• In a case with a low SCR, the renewable source can drastically alter the voltages and frequencies at the POI, suggesting a fragile grid.

(a)

Active and reactive power control:

The grid-forming inverter active and reactive power outputs are controlled to regulate the power references. This generates the reference currents $I{d}_{ref}$ and $I{q}_{ref}$ by processing the measured power at the BESS primary bus and the power reference signal $P_{ref}$ and $Q_{ref}$ using the PI controller, as shown in Figure 3b.

$$I_{dref}=\left[k_p+\frac{k_i}{s}\right]\left(P_{ref}-P_{meas}\right)$$

(5)

$$I_{qref}=\left[k_p+\frac{k_i}{s}\right]\left(Q_{ref}-Q_{meas}\right)$$

(6)

where the references for active and reactive power are $P_{ref}$ and $Q_{ref}$, the nominal active and reactive power are $P_{meas}$ and $Q_{meas}$, and the references for active and reactive current are $I_{dref}$ and $I_{qref}$.

(b)

Droop Control

The droop control regulates the voltage amplitude and frequency, as shown in Figure 3d. Droop-based PQ and QV controls regulate voltage and frequency accordingly. The BESS-based frequency droop is set to 0.5 percent, which allows the microgrid frequency to fluctuate between 60.3 Hz and 59.7 Hz. While the voltage droop is adjusted to 3%, the voltage at the PCC ranges from 610 V to 582 V.

The droop coefficient of active power can be described as the ratio of frequency variation to active power change [19,20]. The link between voltage and reactive power variation is known as the reactive power droop coefficient [21,22,23,24,25]. To regulate the frequency and phase angle of the inverter equal to the frequency and phase angle of the voltage at the PCC, the adjustment terms $V_{ref}$ and $f_{ref}$ are calculated using the PI controller. As seen in Figure 3e, the phase angle measured by the PI controller is restricted to the reference phase angle at the PCC. The droop controller of voltage and frequency regulation is expressed as follows:

$$f=\left(\left(f_{ref}+∆\mathrm{f}\right)-m{P}_{meas}\right)$$

(7)

$$V=\left(\left(V_{ref}+∆\mathrm{V}\right)-m{Q}_{meas}\right)$$

(8)

where $f_{ref}$ and $V_{ref}$ are the frequency and voltage references, and $∆\mathrm{f}$ and $∆\mathrm{V}$ are the frequency and voltage deviation, respectively, at PCC. P_meas and Q_meas are the active and reactive power as measured, and their coefficient for adjusting the measured active and reactive power is “m”.

(c)

PLL based Resynchronization

When the grid switches to normal mode, the microgrid inverter needs to be reconnected to the utility grid. The change in mode from islanded to grid-connected operation requires proper resynchronization. The effective reconnection is only feasible if there is lower than 5% voltage and less than 0.3 Hz frequency variations. The reconnection of the microgrid to the grid without synchronization can cause out-of-phase reclosing, which will result in abnormally high over currents. Thus, upon receiving a resynchronization request from the PCC, the microgrid needs to line up its voltage phases with the main grid [14]. To examine the voltage readings and synchronization signals from both sides of the PCC, a three-phase phase-locked loop (PLL) technique is taken into consideration [9]. The controller changes from (V-f) to (P-Q) mode upon reconnection to the PCC, and the inverter’s ability to control the frequency and amplitude of the output voltage is compromised [10,11].

The PLL automatically compares the phase of an input signal to that of a locally generated signal. In grid-connected systems, PLL brings the inverter voltage’s instantaneous phase angle into sync with the grid voltage’s phase angle, allowing for a power factor close to one. This is composed of three components: a phase detector (PD), a loop filter (LF), and a voltage-controlled oscillator (VCO). In order to determine the phase difference, the phase detector (PD) compares the input signal with the repeating output signal, which then generates a voltage based on the difference in phase between two signals. The Low-Pass Filter (LPF) separates the dc component from any higher frequency signals. To create an output signal frequency, after this, the DC component is amplified and transmitted to a VCO. The PLL’s control structure is displayed in Figure 4.

For the input signal $V_g$ = $V_m$Cos${\theta }_g$ with ${\theta }_g={\omega }_{g+}\phi$, and the output signal y = sin$\theta$ with $\theta =$ $\omega$t + $\phi$, the output signal of PD is expressed as follows:

$$v^{\prime }= v_{g}y=V_{m}Sin\theta Cos{\theta }_g$$

(9)

$$v^{\prime }=\frac{V_m}{2}\sin \left(\theta -{\theta }_g\right)+\frac{V_m}{2}\sin \left(\theta +{\theta }_g\right)$$

(10)

$$v^{\prime }=\frac{V_m}{2}\sin [\left(\omega -{\omega }_g\right)t+\left(\phi -{\phi }_g\right)]+\frac{V_m}{2}\sin [\left(\omega +{\omega }_g\right)t+\left(\phi +{\phi }_g\right)]$$

(11)

The phase difference between v and y is found in the initial component of Equation (10), which is a low-frequency component. The loop filter filters out the following expression, which is a component with a high frequency. Therefore, the LF’s output is

$$d=\frac{V_m}{2}sin[\left(\omega -{\omega }_g\right)t+\left(Ø-{Ø}_g\right)]$$

(12)

This is sent into the PI controller in order to obtain the estimated frequency $\omega =\theta$ until d = 0. After integrating the predicted frequency, the phase of the output signal is generated, $\mathrm{y} = \sin \theta$, which is subsequently returned to PD. When d is set to zero and $\omega ={\omega }_g$ with $Ø-{Ø}_g$ in the steady state, it is said that the phase of the output signal is locked with the phase of the signal that originates from the input v, and as a result, the phases of the signals that are being input and output are synchronized.

(a)

Synchronous Reference Frame-PLL:

The SRF PLL is utilized for grid synchronization in three-phase systems based on frequency. An essential principle of PLL is a feedback loop that uses a PI controller to monitor the phase angle. When a three-phase grid voltage is input, the PLL outputs the phase angle of one phase. As illustrated in Figure 5, using Clarke’s transformation and Park’s transformation, the three-phase voltage vector in SRF PLL is transformed from the natural reference frame ABC to the stationary reference frame αβ, and then to the rotating reference frame dq.

To ensure that the d-axis intersects the grid voltage vector, the feedback loop controls the angular position of the dq reference frame. Therefore, at steady state, the amplitude of the voltage vector is represented by the q-axis component, while its frequency and phase are shown by the output of the d-channel feedback loop.

(b)

Double Second-Order Generalized Integrator-PLL

Figure 6 shows the basic layout of a DSOGIPLL, a device that is commonly used to synchronize with a three-phase grid that is inconsistent and distorted. The first of its three main parts is the DSOGI, which uses two SOGI-QSGs to filter out voltages with low-order harmonics. To get the voltages in the positive sequence, one can use a Positive Sequence Calculator. The PCC’s synchronous frame PLL determines the grid voltages’ phase angles and frequencies. The DSOGI becomes frequency-adaptive after receiving this estimated frequency and transmitting it back. The two SOGI-QSG blocks operate on the grid PCC stationary frame α and H voltages, which are generated from the observed abc voltages using a typical Clarke transform, in the following way:

$$V_{\alpha \beta }=\left[T_{\alpha \beta }\right] \ast V_{abc}$$

(13)

where

$$\left[T_{\alpha \beta }\right]=\frac{2}{3}\left[\begin{array}{ccc}1& -\frac{1}{2}& -\frac{1}{2}\\ 0& \frac{\surd 3}{2}& -\frac{\surd 3}{2}\end{array}\right]$$

(14)

Using unity feedback, a second-order generalized integrator produces the SOGI-QSG, which stands for quadrature signal generator. The input to output connections in these SOGI-QSGs are made possible by the direct and quadrature transfer functions, which are given by

$${\mathrm{D}}_{\mathrm{x}}\left(\mathrm{s}\right)=\frac{{\mathrm{V}}_{\mathrm{x}}^{\prime }}{{\mathrm{V}}_{\mathrm{x}}}=\frac{\mathrm{k}\mathsf{\omega }\prime \mathrm{s}}{{\mathrm{S}}^2+\mathrm{k}\mathsf{\omega }\prime \mathrm{s}+{\mathsf{\omega }\prime }^2}$$

(15)

$${\mathrm{Q}}_{\mathrm{x}}\left(\mathrm{s}\right)=\frac{{\mathrm{qV}}_{\mathrm{x}}^{\prime }}{{\mathrm{V}}_{\mathrm{x}}}=\frac{{\mathrm{k}\mathsf{\omega }\prime }^2}{{\mathrm{S}}^2+\mathrm{k}\mathsf{\omega }\prime \mathrm{s}+{\mathsf{\omega }\prime }^2}$$

(16)

where $x\in$ {α, β}. The operator q stands for a 90° lagging phase shift, k for the damping factor, and ω’ for the center frequency. The SOGI-QSG structures all have two filtering characteristics: a direct channel band-pass and a quadrature channel low-pass, as provided in Equations (15) and (16). As a result, they can greatly reduce voltage harmonics; the damping factor k determines both dynamic performance and harmonic rejection.

Unbalanced systems need to keep the synchronous frame voltages from oscillating at two different frequencies. This can happen when the measured input three-phase voltages are not balanced. From the DSOGI outputs, a positive sequence component (PSC) gets positive sequence fixed-frame voltages. The Clarke transform Equation (13) is used in sequence extraction to turn basic abc frame voltages into a positive sequence of basic αβ frame voltages. It is known that the positive sequence transforms [T+] can take an uneven set and turn it into this positive sequence set of voltages. Using the reverse Clarke transform, the unbalanced DSOGI outputs make the positive series of abc voltages, which is expressed in the following way:

$$\begin{gathered} V_{\alpha \mathsf{\beta } }^{+}=\left[T_{\alpha \beta }\right]. V_{abc }^{+}=\left[T_{\alpha \beta }\right]{[T_{+}]}^{\ast } V_{abc} \\ =\left[T_{\alpha \beta }\right][T_{+}]\left[T_{\alpha \beta }\right]{\mathrm{T}}^{\ast } V^{\prime }\alpha \mathsf{\beta } \end{gathered}$$

(17)

where

$$\left[{\mathrm{T}}_{+}\right]=\frac{2}{3}\left[\begin{array}{ccc}1& {\mathrm{a}}^2& \mathrm{a}\\ \mathrm{a}& 1& {\mathrm{a}}^2\\ {\mathrm{a}}^2& \mathrm{a}& 1\end{array}\right], \mathrm{a}={\mathrm{e}}^{-\mathrm{j}\frac{2\mathrm{\pi }}{3}}$$

(18)

$$\left[\begin{array}{c}{V}_{\alpha }^{+}\\ V_{\mathsf{\beta } }^{+}\end{array}\right]=\frac{2}{3}\left[\begin{array}{cc}1& -q\\ q& 1\end{array}\right]\left[\begin{array}{c}{V}_{\alpha }^{’}\\ V_{\mathsf{\beta } }^{’}\end{array}\right]$$

(19)

$$\left.\begin{array}{l}\left[\begin{array}{c}{V}_{\alpha }^{+\text{'}}\left(s\right)\\ V_{\beta }^{+\text{'}}\left(s\right)\end{array}\right]=\frac{1}{2}\left[\begin{array}{cc}D\left(s\right)& -q\left(s\right)\\ Q\left(s\right)& D\left(s\right)\end{array}\right] \left[\begin{array}{c}{V}_{\alpha }\left(s\right)\\ V_{\beta }\left(s\right)\end{array}\right]\\ =\frac{1}{2}\frac{k{\omega }^{\prime }}{S^2+k{\omega }^{\prime }s+{\omega \prime }^2}\left[\begin{array}{cc}s& -{\omega }^{\prime }\\ {\omega }^{\prime }& s\end{array}\right] \left[\begin{array}{c}{V}_{\alpha }\left(s\right)\\ V_{\beta }\left(s\right)\end{array}\right]\end{array}\right\}$$

(20)

The low-pass filter circuit produced by the DSOGI and PSC eliminates harmonic voltages and exclusively extracts the positive sequence from an input voltage set that is distorted and unbalanced, as illustrated in Equation (19). When ignoring the influence of DC offset, the lowest-order harmonic of the input voltage signal is caused by the fundamental negative sequence component. Equation (20) represents the calculated positive sequence components, $V_{\alpha }^{+\text{'}}$ and $V_{\mathsf{\beta }}^{+\text{'}}$, which are given as input to the SRF-PLL in order to estimate the phase angle and frequency.

(c)

Cascaded Delayed Signal Cancellation-PLL:

As illustrated in Figure 7, the GCDSC method is applicable to both stationary and SRF conditions. The latency introduced by the GCDSC operator in a fixed reference frame can be disregarded during the construction of the closed-loop model, undoubtedly allowing for a wider controller bandwidth and faster dynamic performance [8].

The traditional SRF-PLL will have a prefilter and stationary reference frame (αβCDSC) operators. Typically, a DSC operator’s single block can be expressed mathematically as

$$u\prime \left(t\right)=\frac{1}{2}\left[u\left(t\right)+u\left(t-\frac{T_0}{n}\right)\right]$$

(21)

The input and output of the block are represented by u(t) and $u^{\prime }$(t). Depending on sampling frequency, grid nominal time period $T_o$, and delay factor “n”, Equation (20) obtains the observed signal using $d{N}_n$.

A block’s input and output are denoted by u(t) and $u^{\prime }$(t), respectively. By adjusting the sampling frequency, grid nominal time period $T_o$, and delay factor “n”, the observed signal can be obtained using the Equation (20) as $d{N}_n$.

$$d{N}_n=\frac{T_0}{n{T}_s}$$

(22)

Applying the above equation to the voltage vectors in the αβ-axis gives:

$${u\prime }_{\alpha \beta }(\mathrm{t})=\frac{1}{2}\left[u_{\alpha \beta }\left(t\right)+e^{\frac{2\pi j}{n}}\left(t-\frac{T_0}{n}\right)\right]u_{\alpha \beta }\left(t\right)$$

(23)

3. Description of Test Systems

3.1. Simulation Test System

There are DC/AC power electronic connections that link the microgrid test system’s solar PV systems and battery to the utility grid, as shown in Figure 8 and the specifications of the simulation system is given in

Table 2. Specifications of test system.

Sl. No	Description	Specifications
1	PV Array	1 MW, 650 V
2	Load	1 MW, 600 V
3	Battery	1 MW, 920 V
4	Boost Converter	1.5 MW, 750 V
5	Bidirectional Converter	1.5 MW, 750 V
6	Inverter	10 MVA, 950 V

. The 1 MW solar PV system is linked to the dc bus by 24 parallel strings that connect the panel modules in series. The input voltage is increased from 281 V to 700 V by means of the dc–dc boost converter. A bidirectional converter may draw electricity from the 32,500 Ah, 920 V batteries that make up the battery storage system, which can deliver 1 MW of power.

3.2. Description of Hardware Setup

The hardware configuration for a microgrid that is connected to the grid and uses solar photovoltaics and batteries is shown in Figure 9 and the specifications of the test system is given in

Table 3. Hardware setup components.

Components	Ratings
PV module	1 kW, 200 V
Boost converter	1.5 kW, 300 V
Battery rating	42 Ah, 300 V
Bi-Directional converter	1.5 kW, 300 V
DC link voltage	300 V
Grid-side inverter	10 kVA, 500 V

. Various PLL techniques were used in the development and testing of the proposed GFM inverter controls, which were then implemented in the hardware arrangement. The battery is connected to the DC link through the 1.5 kW bidirectional converter. A grid-forming inverter with a capacity of 10 kVA connects the solar panels and the battery bank. To ensure efficient and stable functioning and smooth power transmission, the suggested energy management system is implemented using the FPGA SPARTAN6 board. The grid-sensing module measures both the grid and the battery sides of the system.

4. Results and Discussions

The algorithm that has been suggested was created in the R2022b MATLAB environment using a 2.60 GHz Intel Pentium Core i7-6600U processor from USA. Thepower generated from photovoltaic cells and batteries is sent to the electricity grid in this setup. The control algorithms for GFL-type and forming-type inverters are developed in the microgrid setup, and are validated with the different PLL techniques discussed in the previous sections. The GFLI and GFMI are discussed with different types of PLLs with and without resynchronization, as they transition from an isolated to a grid-connected mode of operation, and we evaluate their performance.

The different case studies carried out in this work are on the following setups:

• GFM inverter control without PLL based resynchronization;
• GFM inverter control with DSOGI-PLL;
• GFM inverter control with CDSC-PLL;
• GFM inverter control with SRF-PLL;
• Comparison of SRF-PLL in GFL- and GFM-based inverter control.

• Case 1 Grid forming inverter control without PLL-based resynchronization.

Grid-forming inverter control without PLL-based resynchronization stabilizes the PCC point frequency at 59.7 Hz in islanded mode, fluctuates for 40 s, and then stabilizes as shown in Figure 10. The phase angle varies and stabilizes after 4 s. The PCC voltage stabilizes within 0.4 s of switching transients. It is shown that switching transients in frequency, voltage, and phase angle are high during the switchover operation of the GFM inverter control without PLL-based resynchronization when switching from islanded to grid-linked mode.

• Case 2 GFM inverter control with DSOGI-PLL.

Upon implementation of DSOGI PLL, the frequency of the PCC point is 59.7 Hz, which remains steady in islanded mode for 10 s and fluctuates for 3 s. The fluctuation and sudden stabilization signals occur in 0.02 s, and are stabilized during switchover from islanded to grid-connected mode, while the phase angle fluctuates at 4 s. After changing the mode of operation, the PCC voltage stabilizes in 0.2 s, with fewer switching transients as shown in Figure 11. It is shown that switching transients in frequency, voltage, and phase angle are detected during the switchover operation of the GFM inverter control with PLL-based resynchronization while moving from islanded to grid-connected mode.

• Case 3 GFM inverter control with CDSC-PLL.

The CDSC PLL-based technique stabilizes PCC point frequency at 59.7 Hz in islanded mode, which then varies for 10 s and becomes unstable at 3 s. The phase angle varies and is unstable after 4 s. The PCC voltage stabilizes within 0.4 s with fewer switching transients as shown in Figure 12. It is shown that switching transients in frequency, voltage, and phase angle are detected during the switchover operation of the GFM inverter control with PLL-based resynchronization, moving from islanded to grid-linked mode.

• Case 4 Grid-forming inverter control with SRP-PLL technique.

After the implementation of SRF-PLL, the PCC point frequency is 59.6 Hz, and is stable in islanded mode; it then fluctuates for 10 s and stabilizes at 2.6 s. The phase angle fluctuates initially and then stabilizes after 3.5 s. The PCC voltage stabilizes within 0.2 s with fewer switching transients as shown in Figure 13.

• Case 5 Comparison of SRF-PLL in GFL- and GFM-based inverter control.

The SRF-PLL was investigated in both the GFL inverter and the GFM inverter, and the results are here compared. Regarding the GFL inverter’s performance, the PCC point frequency is 65 Hz, and is stable in islanded mode and grid-connected mode. The phase angle fluctuates and stabilizes within 4 s in islanded mode, and is stable in the grid connected mode. The PCC voltage stabilizes within 4 s, with more switching transients. In GFM-based inverter performance, the PCC point frequency is 59.6 Hz, and is stable in islanded mode; it then fluctuates for 10 s and stabilizes at 2.6 s. The phase angle fluctuates initially and stabilizes after 3.5 s. The PCC voltage stabilizes within 0.2 s, with fewer switching transients as shown in Figure 14. The GFM inverter control is investigated without any PLL-based resynchronization while switching from islanded to grid-connected mode, and it is understood that switching transients are observed with high frequency during switchover operation in frequency, voltage and phase angle. The results for SRF-PLL-based GFM and GFL inverters as regards PV, battery and grid voltage, and current are shown in Figure 15.

5. Conclusions

The GFM and GFL inverter-based controls were developed in a solar PV-integrated microgrid network. The different PLL techniques, namely, DSOGI, CDSC, and SRF-PLL, were developed and implemented in GFM- and GFL-based inverter controls. It is understood that combining SRF-PLL with a GFM inverter provides better responses than other PLL techniques. The switching transient, which switches from islanded to grid-connected mode, is notably reduced compared to GFL-based inverter control. The proposed model has been tested in a simulation test system and a hardware setup, and has shown satisfactory performance in reducing the switching transient during resynchronization.