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Article

PSP-Equivalent Model for Double-Gate and Surrounding-Gate Field Effect Transistors for Circuit Simulation

1
Dipartimento di Ingegneria dell’Informazione (DII), University of Brescia, 25123 Brescia, Italy
2
PDF Solutions, Desenzano Del Garda, 25015 Brescia, Italy
*
Author to whom correspondence should be addressed.
Electronics 2024, 13(9), 1725; https://doi.org/10.3390/electronics13091725
Submission received: 10 March 2024 / Revised: 27 April 2024 / Accepted: 28 April 2024 / Published: 30 April 2024
(This article belongs to the Special Issue Feature Papers in Semiconductor Devices)

Abstract

:
We introduce a compact core model for double-gate (DGFET) and surrounding-gate (SGFET) MOSFETs designed for circuit simulations. Despite its high precision, the model is crafted to retain the same analytic formulation of the industry standard Pennsylvania State and Philips (PSP). Instead of linearizing the drain current as in the PSP model, we employ a quadratic symmetric polynomial interpolation of the charge in the channel. This eliminates the need for cumbersome derivatives, simplifications, and intricate coding when integrating into a circuit simulator, thereby preventing singularities during numerical iterations. Moreover, thanks to its mathematical formulation equivalent to PSP, this model simplifies the coding of terminal charges, capacitances, potentials, and electric fields in the channel within circuit simulators. We validate the accuracy of the model through comparisons with numerical solutions and experiments from the literature.

1. Introduction

Multiple gate MOSFETs (MGFETs), including FINFETs and nano sheets, have gained widespread adoption in the electronics industry as replacements for conventional planar transistors [1]. This is due to their enhanced gate control, nearly ideal subthreshold slope, and mitigated short-channel effects (SCE). In theory, MGFETs hold the potential to scale down the MOSFETs as technology advances to the end of the roadmap. Consequently, there is a significant interest in the development of compact CAD models of MGFETs for circuit simulation [2,3,4,5,6,7,8,9,10,11,12]. A compact CAD model for circuit simulations comprises a core model of an ideal long-channel transistor, wherein SCE and quantum effects (QE) are subsequently introduced as appropriate approximations. In the literature, various excellent closed-form equations for the drain current of symmetric DGFETs and SGFETs have been developed [2,3,4,5,6,7,8,9,10,11,12]. Nevertheless, the exact closed-form expressions of the terminal charges prove to be somewhat more cumbersome compared to compact models for planar transistors, requiring simplifications. Furthermore, the complexity of existing core models does not easily allow for the inclusion of short-channel and quantum effects. The objective of this work is to introduce a new compact model of MGFETs without resorting to the charge-sheet approximation. A quadratic symmetric polynomial interpolation is employed to compute the transistor current. In [11], we demonstrated that this approach is particularly suited to accurately model DGFETs and SGFETs. Here, the model from [11] is reformulated to be entirely equivalent to the widely recognized PSP current equation. Then, the terminal charges, capacitances, surface potential and electric field in the channel are worked out to hold the same expression of the PSP but with higher precision. The midpoint charge of PSP is replaced with an equivalent midpoint charge. The equivalent midpoint charge accommodates nonlinearities in the channel, maintaining high accuracy even when the surface potential exhibits strong nonlinearity. The model retains all the appealing characteristics of the traditional compact models of planar MOSFETs. These include computational efficiency, symmetry, and straightforward polynomial expressions of current, terminal charges, potentials, and electric fields in the channel. Furthermore, despite its compactness and ease of integration into circuit simulators, it attains a remarkable level of accuracy. The largest error of the drain current, compared to the numerical solution, is so minimal that the model can be assumed to be equivalent to the exact solution. Finally, this core model, thanks to its high accuracy, numeric stability, versatility, and ease of implementation in circuit simulations, can be exploited as a core model in a variety of recent technologies, for example, junctionless, dual-material, dual-metal cylindrical gate-all-around MOSFETs, heterojunction tunneling transistors, nanotubes, etc. [13,14,15,16,17].

2. DGFET Drain Current

In the DGFET, the channel is typically undoped (or lightly doped) to mitigate threshold voltage fluctuations. Here, the device geometry and all the symbols are exactly the same as in the well-known paper of Taur [2] (Figure 1) and, for the sake of brevity, are summarized in Table 1. Assuming the current flows in the y-direction, in order to compute the surface potential, Poisson’s equation must be solved. Poisson’s equation is solved following the same approach as Taur [2]. The solution, without introducing any approximations, reads
q ( V G S ψ V ) 2 k T ln   2 t s i 2 ε s i k T q 2 n i     = ln β ln cos β   + 2 ε s i t o x ε o x t s i   β tan β
where β is a parameter that is computed by solving transcendental Equation (1), q is the electron charge, k is the Boltzmann constant, T is the lattice temperature, ψ is the work function difference between the gate electrode and the intrinsic silicon, V is the channel potential, n i is the intrinsic concentration, ε o x is the insulator dielectric constant, ε s is the silicon dielectric constant, t o x is the insulator thickness, t s i is the semiconductor thickness, and V G S is the voltage applied to the gate. Once β is computed, the electrostatic potential normal to the channel (x-direction) in the semiconductor reads [2,11]
ψ x = V 2 k T q ln   t s i 2 β q 2 n i 2 ε s i k T cos 2 β x t s i
and the inversion charge in the channel [2] reads
Q i = C o x ( V G S ψ ψ s ) = 2 ε s i 2 k T q 2 β t s i tan β
where ψ s = ψ ± t s i / 2 and C o x = ε o x / t o x . To develop a surface potential formulation for the drain current, it is important to note that the charge sheet approximation (CSM), commonly employed in planar MOSFET modeling, is not applicable to DGFETs. Specifically, for DGFETs, the exact solution of the Pao–Sah equation becomes necessary to precisely model the volume inversion in the subthreshold region [2,9,10,11]. Following the approach of [9], in [11], the Pao–Sah double integral is worked out using a second-order symmetric polynomial centered at the midpoint of the surface potential, ψ M = ( ψ s S + ψ s D ) / 2 , without the charge sheet simplification. This method yields a precise and considerably simplified representation of drain current and terminal charges compared to the current core models of DGFETs, all while maintaining a clear physical interpretation. The drain current reads [11]
I D   = 2 W L μ   4 Q ~ i M + Q ~ i D + Q ~ i S 6 + C o x   v T ϕ
where
Q ~ i = Q i   1 + γ 4 g β  
g β = sin ( 2 β ) 2 β cos ( 2 β ) β tan β   [ 2 β + sin ( 2 β ) ] ,   γ = ε o x t s i ε s i t o x
and v T = k T / q ; Q ~ i S , Q ~ i D ,   a n d   Q ~ i M are the “perturbed charges” of Equation (5), computed at the source, drain, and surface potential midpoint, and ϕ = ψ s D ψ s S [11]. It is important to highlight that ϕ , Q ~ i S , Q ~ i D , and Q ~ i M are explicit functions of β S , β D , and β M . In turn, β is computed through numerical iteration using Equation (1) at the source drain and midpoint. Nonetheless, numerous highly accurate explicit approximations for β are reported in the literature [18], and the numeric iteration is not required. Equation (4) represents an accurate and considerably simplified version of the drain current compared to existing core models of DGFETs, while maintaining a clear physical interpretation [11]. The linear and concise mathematical expression of Equation (4), its high accuracy, and the availability of precise explicit approximations for β make this model particularly well suited for integration into circuit simulation programs. Furthermore, Equation (4), despite its similarity to the well-known PSP model, removes the requirement to calculate derivatives at the midpoint [7,8,9,10]. The derivative is cumbersome and requires careful coding during integration into a circuit simulator to prevent issues like division by zero or imaginary solutions during numerical iterations. Now, taking into account that the DGFET has two gates and that both Equation (4) and the PSP model are linear functions of charges and potentials, Equation (4) can be reformulated to be fully equivalent to the PSP current equation I D S   P S P as follows:
I D S   P S P = 2 W L μ   Q M v T α ϕ   I D S   e q . 4 = 2 W L μ   Q M e q v T α e q ϕ
where
Q M e q = 4 Q ~ i M + Q ~ i D + Q ~ i S 6 ,   α e q = C o x
and the midpoint charge Q M of the PSP here is replaced by an equivalent midpoint charge Q M e q as well as the charge derivative α e q = d Q i / d ψ s . It is noteworthy that Equation (7), as it stands, is the same as Equation (4) but presented in a different form and seemingly does not introduce anything new compared to [11]. However, its utility lies in efficiently computing the terminal charges, capacitances, surface potential, and electric field in the channel, as shown below. Equation (7) is a matter of efficiency when implemented in a circuit simulator.
To assess the accuracy of Equation (7), in Figure 2, it is juxtaposed with the exact numerical solution of the Pao–Sah double integral [2]. In Figure 2, the percentage error, defined as 100 × | ( I D S ) / I D S | , is shown. All device parameters and terminal voltages are identical to those in [2,11]. Furthermore, in [2], the analytic solution is further verified through validation against numerical simulations and experimental data. Equation (7) provides a continuous and very accurate expression of the current with smoot derivatives [11,12]. Additionally, Equation (7) successfully passes the Gummel symmetry tests [11,12]. These characteristics are crucial for achieving rapid and seamless convergence in circuit simulations and for implementing short-channel effects (SCE). Equation (7) reproduces the numerical solution with a larger percentage error of approximately 0.1% (Figure 2). Notably, the error is about one order of magnitude smaller compared to the compact models in [9,10], as shown in Figure 2 and Figure 3.

3. SGFET Drain Current

An equivalent formulation can be developed for the cylindrical n-type SGFET of radius R in Figure 1. The geometry and symbols are the same as in [4]. Assuming that transport is in the y-direction ( 0 < r < R is the direction normal to the current), the integral of Poisson’s equation reads [4]:
q ( V G S ψ V ) k T ln 8 δ R 2 = ln ( 1 β ) ln β 2 + η   1 β   β
where η = 4 ε s i / ( C o x R ) , and δ = q 2 n i / ( k T ε s i ) . All other parameters carry the same meaning as in the DGFET. Once β is known after solving transcendental Equation (8), the potential in the semiconductor as a function of r can be readily calculated [4]:
ψ r = V + k T q ln   8   B δ ( 1 + B r 2 ) 2
as well as the charge in the channel
Q i = C o x V G S ψ ψ s = 2 ε s i 2 k T q 1 β R   1 β  
where C o x = ε o x / [ R ln 1 +   t o x / R ) ] , ψ s = ψ R , and β = 1 + B R 2 . Pao–Sah’s double integral for a cylindrical SGFET reads [11]
I D   = 2 π R L   4 Q ~ i M + Q ~ i D + Q ~ i S 6 + C o x v T ϕ  
where
Q ~ i = Q i   g β
g β = 1 + 1 β S 1 β D + ln β S β D γ 1 β S 2 1 β D 2 + 2 β D 2 β S
and
γ = 2 ε s i ε o x   ln 1 + t o x R
where Q ~ i M , Q ~ i S , Q ~ i D , Q i S , and Q i D are calculated by means of Equations (10)–(14). Equation (11) depends on the terminal voltages through ψ s S and ψ s D and, in turn, on β , as is the case for the DGFET.
Yet again, Equation (11) reproduces the numerical solution of the drain current ID with a percentage error smaller than 0.1%. In [18], an accurate explicit approximate solution of β is worked out for the SGFET as well. It makes this model very suitable for circuit simulators. In Figure 4 and Figure 5, Equation (11) is compared to the numerical solution. Now, Equation (11) can also be reformulated to be entirely equivalent to the widely recognized PSP current equation:
I D   = 2 π R L μ   Q M e q v T α e q ϕ .
In (15), the charge at the midpoint of PSP is substituted by an equivalent charge Q M e q = 4 Q ~ i M + Q ~ i D + Q ~ i S / 6 derived from (11), as well as α e q = C o x .

4. PSP-Equivalent Charge Model

Although the drain currents of the DGFET and SGFET in [2,4] are derived with no simplifications, they are complex functions of β that cannot be used to calculate terminal charges without introducing simplifications. In ref. [11], the terminal charges, derived from Equations (4) and (11), are computed without simplification, exploiting the polynomial equations of the charge in the channel. However, these calculations result in complex polynomial functions. In contrast, here, thanks to Equations (7) and (15), which are fully equivalent to Equations (4) and (11), the terminal charges are directly and easily computed, akin to the PSP approach. The terminal charges will be derived for the DGFET, and similar equations hold for the SGFET. The terminal charges are worked out by means of the well-known Ward–Dutton charge partitioning [19] as follows:
Q G 2 W = 0 L   Q i d y = ϕ / 2 ϕ / 2   Q i d y d ψ s d ψ s  
Q D 2 W = 0 L   y L   Q i d y = ϕ / 2 ϕ / 2   y L Q i d y d ψ s d ψ s
Q S = Q G Q D
where Q G , Q S , and Q D are the gate, source, and drain terminal charge densities per unit area. The above integrals are worked out as in PSP [7,8], exploiting the equivalence devised in Equation (7). To compute the terminal charges, first the expressions of y ( ψ s ) and d y / d ψ s must be derived. Since the current in the channel is solenoidal [7,8,9,10,11],
I D   = 2 W μ   Q ~ i d ψ s d y v T d Q i d y  
and, recalling that in (7), d Q i / d ψ s = α e q = C o x , Equation (19) can be rewritten as
I D   = 2 W μ   Q M e q + v T α e q d ψ s d y
and in turn, d y / d ψ s reads
d ψ s d y = I D   2 W μ   Q M e q + v T α e q .
Finally, after substituting the drain current of (7) into Equation (21) and following the linear approach of PSP, d y / d ψ s reads [7,8]
  d y d ψ s =   L   ϕ     1 ψ s ψ M   H e q  
where H e q = v T Q M e q / α e q = v T + Q M e q / C o x . It is worth noting that Equation (22) is related to the electric field parallel to the channel:
E Y ψ s = d ψ s d y = ϕ   L     H e q ψ s ψ M H e q .
Then, after integrating Equation (22), the analytical expression of the position in channel y with respect to the surface potential reads [7,8]
y = y M + L ϕ   ψ s ψ M ψ s ψ M 2 2 H e q
where y M represents the “surface potential midpoint”, which is the y -coordinate corresponding to ψ M :
y M = L 2   1 ϕ 4 H e q .
Note that when ϕ > 0 , y M > L / 2 , indicating that the potential midpoint shifts towards the drain from the geometric midpoint (Figure 6).
Conversely, the dependence ψ s ( y ) can be derived by solving Equation (19) with respect to ψ s , yielding
ψ s = ψ M + H e q 1 1 2 ϕ H e q L y y M .
A close comparison between Equations (23)–(26) and the original model [11] reveals that the significantly simplified expression in Equation (26), which is based on the PSP-like approach, is nearly numerically identical to the exact expression presented in [11]. The maximum error of the surface potential is always smaller than 2%.
Furthermore, the expressions above are identical to those for bulk MOSFETs [7,8], with the only difference being the value of H , which is H e q here. The position dependence of the surface potential is shown in Figure 7.
Then, substituting Equations (22) and (24) in Equation (16) and integrating, the gate charge Q G reads
Q G = 2 Q i M α e q ϕ 2 12 H e q .
Also, in turn, replacing Equations (22) and (24) with Equation (17), the drain charge Q D reads
Q D = 2 Q i M 2 + α e q   ϕ 12   1 ϕ 2 H e q ϕ 2 20 H e q .
In Figure 8, the terminal charges derived with the PSP-equivalent approach are compared to both the numerical solution and the polynomial expressions of [11]. Again, the percentage error, with respect to the numerical solution, is below 2 % . As a further check of Equations (27) and (28), the asymptotic behavior when V D S 0 is also shown in Figure 8 (dashed lines). When V D S 0 , the gate charge equals the inversion charge density and Q D = Q S = Q G / 2 . In fact, if using the explicit expression of the charges when V D S 0 , ϕ 0 , Q ~ i S Q ~ i D Q ~ i M , then
lim ϕ 0 H e q = l i m ϕ 0   v T Q M e q α e q = lim ϕ 0 v T 4 Q ~ i M + Q ~ i D + Q ~ i S 6   α e q v T + Q ~ i M   C o x
and, eventually, the terminal charges read
lim ϕ 0 Q G = lim ϕ 0 2   Q i M C o x 12   v T + Q ~ i M   C o x ϕ 2 2 Q i M
lim ϕ 0 Q D = lim ϕ 0 2 Q i M 2 + α e q   ϕ 12   1 ϕ 2 H e q ϕ 2 20 H e q   Q i M
Q S   Q G Q G 2   Q G 2 Q i M .
Furthermore, Figure 9 also shows that the transcapacitances ( C i j = 2 δ i j 1   Q i / V j , with i, j = G, S, D) essentially overlap with the exact numeric solution. Again, the larger percentage error is on the order of 2 % . The expressions in Equations (7), (27), and (28) represent a new form of symmetric linearization, typical of PSP, for MGFETs. Unlike the simpler formulation with respect to [11], the result is, of course, the same for the drain current and, although simplified, very accurate for the terminal charges and transcapacitances as well (Figure 9). An important feature of this formulation of Q G , Q S , and Q D is that they are extremely simple, with PSP [7,8] differing only with the expression of H. This means that small-geometry effects can be worked out as they were in [7,8], and these effects were previously shown to be accurate with respect to numeric simulations and experimental data. Finally, the electric field in the channel, required to implement short-channel effects (SCE), quantum effects (QE), and other advanced physical phenomena, is derived as it was in [7,8]. E y is worked out by replacing Equation (27) with Equation (23). In Figure 10, the electric field for different gate voltages, both in the saturation and linear regions, is shown.
E ( y ) = d ψ s d y =   ϕ L   1 2 ϕ H e q L y y M

5. Symmetry and Derivatives

A common issue of surface potential-based models in bulk MOSFETs, and consequently, MGFETs, involves resolving implicit transcendental Equations (1) and (8). Iterative methods represent the most commonly employed approach for addressing implicit equations due to their potential for high accuracy. Nevertheless, they are accompanied by several drawbacks, including computational inefficiency and occasional exceptions, such as divergence. Hence, an explicit approximation of Equations (1) and (8) that offers sufficient accuracy is always preferable to streamline applications for industry standards.
In ref. [18], an accurate explicit solution of Equations (1) and (8) is presented, utilizing high-order mathematical corrections. This solution exhibits accuracy not only concerning drain current but also with respect to its derivatives. The explicit expression of β is very efficient: it requires the computation of two exponents, two square roots, and three logarithms. Despite the compact form of β as described in [18], the algorithm yields a β with a maximum error of 17 fV, which proves sufficient for computing current and its derivatives with precision that is suitable for circuit simulation. A more stringent way to understand the accuracy of the solution is to compare the derivatives of the drain current or the terminal charges.
Partial derivatives, such as drain conductance, transconductance, and transcapacitance, play a crucial role in AC and transient circuit simulations. These derivatives are particularly sensitive to the errors of intermediate parameters. Moreover, when designing integrated circuits, such as passive RF mixers and transfer gates, it is essential for a compact model to show symmetry with respect to the interchange of the source and drain terminals. This property is frequently referred to as Gummel symmetry (GS). The Gummel symmetry of Equations (7) and (11) is depicted as solid lines in Figure 11 and Figure 12 for the DGFET and SGFET, respectively, indicating that this model successfully passes this GS test. The GS is extremely important when the model is implemented in a circuit simulator. When implementing a compact model in a circuit simulator, the condition I D = f V S ,   V D , V G S = f V S ,   V D , V G S is enforced, regardless of the internal symmetry of the model. If a compact MOSFET model inherently possesses symmetry, the imposition of this symmetry condition by the circuit simulator has no effect. However, for asymmetric models, enforcing this condition may lead to singularities that typically manifest as the nonexistence of the second derivative. The results shown in Figure 11 and Figure 12 demonstrate that the model not only passes the GS test but also accurately reproduces the exact numerical solution (symbols).

6. Conclusions

This work presents a compact core model for MGFETs designed for advanced CAD applications. It provides a remarkably accurate and considerably simplified expression of the Pao–Sah equation while maintaining a clear physical interpretation. The largest percentage error with respect to the numerical solution was on the order of 0.1 % . Moreover, the current equations of [11] were formulated to be fully equivalent to the Pennsylvania State and Philips model, PSP. Due to its formulation, this model simplifies the coding of terminal charges, capacitances, potentials, and electric fields in the channel within circuit simulators. This is highly advantageous, given that the complexity of the exact DGFET and SGFET core models makes it challenging to incorporate small-geometry effects and hinders the direct application of experience (and code) gained in the development of advanced bulk and SOI models. The model is fully scalable and is suitable for the full range of device geometries, from the long-channel limit down to the shortest channels, with a single set of parameters. We validated the accuracy of this core model through comparisons with exact numerical solutions and experimental data from the literature [2,4]. It is a useful kernel for the future generation of SPICE models of FINFET and nano sheets, maintaining the same ease of implementation of today’s most advanced planar MOSFET models.

Author Contributions

Conceptualization, L.C. and S.C.; Writing—review & editing, L.C., S.C. and A.R. All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding.

Data Availability Statement

Data is contained within the article.

Conflicts of Interest

Author Simone Comensoli was employed by the company PDF Solutions. The remaining authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.

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Figure 1. Schematic cross sections of the DGFET (left) and SGFET (right).
Figure 1. Schematic cross sections of the DGFET (left) and SGFET (right).
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Figure 2. DGFET output currents and percentage error (% err = 100 × | ( I D S ) / I D S | ) at VGS = 2 V (blue), 1.5 V (orange), and 1 V (green) ; lines indicate numerical solutions, and dots indicate Equation (7). The largest percentage error is about 0.2% (dashed lines). The simulation parameters are reported in Table 1. Both the numerical solution and Equation (7) accurately fit the experiments in [2].
Figure 2. DGFET output currents and percentage error (% err = 100 × | ( I D S ) / I D S | ) at VGS = 2 V (blue), 1.5 V (orange), and 1 V (green) ; lines indicate numerical solutions, and dots indicate Equation (7). The largest percentage error is about 0.2% (dashed lines). The simulation parameters are reported in Table 1. Both the numerical solution and Equation (7) accurately fit the experiments in [2].
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Figure 3. DGFET transfer characteristics at VDS = 0.1 V; 1 V: lines indicate numerical solutions, and dots indicate Equation (7). Both the numerical solution and Equation (7) accurately fit the experiments in [2].
Figure 3. DGFET transfer characteristics at VDS = 0.1 V; 1 V: lines indicate numerical solutions, and dots indicate Equation (7). Both the numerical solution and Equation (7) accurately fit the experiments in [2].
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Figure 4. SGFET output currents and percentage error (% err = 100 × | ( I D S ) / I D S | ) at VGS = 2 V (blue), 1.5 V (orange), 1 V (green); solid lines indicate exact numerical solutions, and dots indicate Equation (15). The largest percentage error is about 0.1% (dashed lines). The simulation parameters are reported in Table 1. Both the numerical solution and Equation (7) accurately fit the experiments in [4].
Figure 4. SGFET output currents and percentage error (% err = 100 × | ( I D S ) / I D S | ) at VGS = 2 V (blue), 1.5 V (orange), 1 V (green); solid lines indicate exact numerical solutions, and dots indicate Equation (15). The largest percentage error is about 0.1% (dashed lines). The simulation parameters are reported in Table 1. Both the numerical solution and Equation (7) accurately fit the experiments in [4].
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Figure 5. SGFET transfer characteristics at VDS = 0.1 V; 1 V: lines indicate numerical solutions, and dots indicate Equation (15). Both the numerical solution and Equation (7) accurately fit the experiments in [4].
Figure 5. SGFET transfer characteristics at VDS = 0.1 V; 1 V: lines indicate numerical solutions, and dots indicate Equation (15). Both the numerical solution and Equation (7) accurately fit the experiments in [4].
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Figure 6. Position in the channel y(s) as a function of the surface potential at V G S = 3   V (blue), V G S = 2   V (orange), V G S = 1   V (green), and V D S = 1   V . Dashed line, surface potential midpoint yM.
Figure 6. Position in the channel y(s) as a function of the surface potential at V G S = 3   V (blue), V G S = 2   V (orange), V G S = 1   V (green), and V D S = 1   V . Dashed line, surface potential midpoint yM.
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Figure 7. Surface potential (Equation (26)) vs. y in the channel of the DGFET at V s = 0   V , V D = 1   V , and V G S = 0.5 ,   1 ,   1.5 ,   2 ,   2.5 ,   a n d   3   V .
Figure 7. Surface potential (Equation (26)) vs. y in the channel of the DGFET at V s = 0   V , V D = 1   V , and V G S = 0.5 ,   1 ,   1.5 ,   2 ,   2.5 ,   a n d   3   V .
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Figure 8. Normalized terminal charges (27) and (28) vs. numerical solution (circles) and [11] at V s = 0   V and V D = 1   V : QG (blue), QS (green), and QD (orange). The numerical solution and [11] perfectly overlap and are almost indistinguishable. Dot dashed lines indicate normalized charges at low drain voltage: V D = 0.1   V . Dashed line: percentage error (% err = 100 × | ( Q ) / Q | ) .
Figure 8. Normalized terminal charges (27) and (28) vs. numerical solution (circles) and [11] at V s = 0   V and V D = 1   V : QG (blue), QS (green), and QD (orange). The numerical solution and [11] perfectly overlap and are almost indistinguishable. Dot dashed lines indicate normalized charges at low drain voltage: V D = 0.1   V . Dashed line: percentage error (% err = 100 × | ( Q ) / Q | ) .
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Figure 9. Normalized transcapacitances: lines are CGG (blue), CSG (green), and CDG (orange) vs. numerical solution (circles) and [11] at V s = 0   V and V D = 1   V . The numerical solution and [11] perfectly overlap and are almost indistinguishable. Dashed lines indicate normalized capacitances at low drain voltage: V D = 0.1   V .
Figure 9. Normalized transcapacitances: lines are CGG (blue), CSG (green), and CDG (orange) vs. numerical solution (circles) and [11] at V s = 0   V and V D = 1   V . The numerical solution and [11] perfectly overlap and are almost indistinguishable. Dashed lines indicate normalized capacitances at low drain voltage: V D = 0.1   V .
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Figure 10. Electric field parallel to channel (33) vs. y at V s = 0   V , V D = 1   V , and V G = 1 ,   1.5 ,   2 ,   2.5 ,   a n d   3   V .
Figure 10. Electric field parallel to channel (33) vs. y at V s = 0   V , V D = 1   V , and V G = 1 ,   1.5 ,   2 ,   2.5 ,   a n d   3   V .
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Figure 11. Gummel symmetry test for the DGFET (Equation (7)): V s = V x , V D = V x at VGS = 2 V (blue), 1.5 V (orange), and 1 V (green). I D , left axis (solid line); d I D / d V X (dashed line), right axis. Dots are the exact numerical solution.
Figure 11. Gummel symmetry test for the DGFET (Equation (7)): V s = V x , V D = V x at VGS = 2 V (blue), 1.5 V (orange), and 1 V (green). I D , left axis (solid line); d I D / d V X (dashed line), right axis. Dots are the exact numerical solution.
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Figure 12. Gummel symmetry test for the SGFET (Equation (15)): V s = V x , V D = V x at VGS = 2 V (blue), 1.5 V (orange), and 1 V (green). I D , left axis (solid line); d I D / d V X , right axis (dashed line). Dots are the exact numerical solution.
Figure 12. Gummel symmetry test for the SGFET (Equation (15)): V s = V x , V D = V x at VGS = 2 V (blue), 1.5 V (orange), and 1 V (green). I D , left axis (solid line); d I D / d V X , right axis (dashed line). Dots are the exact numerical solution.
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Table 1. Physical and geometrical parameters.
Table 1. Physical and geometrical parameters.
DGFETSGFET
L [µm]1 1
tSi [nm]5
R [nm]2.5
tOX [nm]1.51.5
µ [cm2/Vs]300300
ψ [V]00
εSi11.711.7
εOX3.93.9
Physical and geometrical device parameters for both the DGFET and SGFET [2,4].
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Colalongo, L.; Comensoli, S.; Richelli, A. PSP-Equivalent Model for Double-Gate and Surrounding-Gate Field Effect Transistors for Circuit Simulation. Electronics 2024, 13, 1725. https://doi.org/10.3390/electronics13091725

AMA Style

Colalongo L, Comensoli S, Richelli A. PSP-Equivalent Model for Double-Gate and Surrounding-Gate Field Effect Transistors for Circuit Simulation. Electronics. 2024; 13(9):1725. https://doi.org/10.3390/electronics13091725

Chicago/Turabian Style

Colalongo, Luigi, Simone Comensoli, and Anna Richelli. 2024. "PSP-Equivalent Model for Double-Gate and Surrounding-Gate Field Effect Transistors for Circuit Simulation" Electronics 13, no. 9: 1725. https://doi.org/10.3390/electronics13091725

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