A Dual Half-Bridge Converter with Adaptive Energy Storage to Achieve ZVS over Full Range of Operation Conditions

Abstract

The phase-shifted full-bridge (PSFB) converter is widely employed in high-power applications. However, circulating current, duty-cycle loss, secondary voltage oscillation, and narrow zero-voltage-switching (ZVS) range are the main drawbacks of the conventional PSFB converter. This paper proposes a novel full-bridge converter to improve the performance of the conventional PSFB converter. The proposed converter contains two paralleled half-bridge inverters and an auxiliary inductor on the primary side. The rectifier stage is composed of six diodes connected with the form of full-bridge rectification. This structure allows the stored energy for ZVS operation to change adaptively with duty-cycle. The power can be transferred from the primary side to the secondary side during the whole period. Therefore, the requirement of output filter inductance is reduced and the circulating current is removed. The proposed converter is a good candidate for high power, high voltage and variable input voltage applications. The operation principle and performance are verified on a laboratory prototype.

1. Introduction

The traditional full-bridge DC/DC converter with phase-shifted control can achieve zero-voltage-switching (ZVS) without any additional devices. The switching loss can be significantly reduced. Hence, the converter can achieve high efficiency and power density. These advantages make the phase-shifted full-bridge (PSFB) converter well-suited for high efficiency, power density, and reliability applications [1,2,3,4,5,6]. However, the drawback of the PSFB converter is the dependency of the ZVS characteristic on the load condition: ZVS is lost as load current decreases. Loss of ZVS at light loads results in low efficiency and high electro-magnetic interference (EMI) due to the increase of switching losses [5]. Another drawback is the existence of circulating current, which will significantly increase conduction loss [6]. Extending ZVS range and reducing circulating current are two key areas to improve the PSFB converter’s performance.

Many studies have been proposed to overcome the drawbacks of the traditional PSFB converter. Generally, the ZVS range can be extended by utilizing energy stored in the auxiliary circuits [7,8,9,10]. However, the auxiliary circuits lead to higher circulation current and more conduction loss. The zero-voltage and zero-current-switching (ZVZCS) full-bridge converters are another solution to the problems [11,12,13,14]. In these converters, metal–oxide–silicon field-effect transistors (MOSFETs) as leading-leg switches are turned on with ZVS, while insulated gate bipolar translators (IGBTs) as lagging-lag switches are turned off with ZCS. The ZVS operation is achieved over a wide range of load conditions, and circulating current can be removed by ZCS operation. Generally, these ZVZCS converters result in high secondary-voltage stress and increase the ripple of output voltage. The dual half-bridge converters are a novel solution to extend the ZVS range and remove circulating current [15,16,17]. However, these converters require the specified leakage and magnetizing inductances, which makes the design of transformers complex.

This paper proposes a new dual half-bridge converter with a simple auxiliary circuit. Since the required energy for ZVS increases as duty-cycle decreases, the proposed converter can achieve ZVS operation for all of the primary switches over the entire load range. In addition, the energy from the primary side can be transferred to the output side during the whole switching period, so the output filter requirement is reduced. The proposed converter is well suited for the high-output-voltage applications. Because of these applications, a large filter inductor is required to reduce the ripple current, which results in low efficiency and power density. The operation principle and theoretical analysis are presented to verify these advantages. Experimental results demonstrate the performance of the proposed converter.

2. Operation Principle

The circuit diagram of the proposed converter is shown in Figure 1. The converter is composed of two half-bridge inverters (HBIs) in parallel, which are driven with phase-shifted control. The transformers of T₁ and T₂ have the same characteristics with turns ratio of 1:n. L_lk1 and L_lk2 are the leakage inductances of T₁ and T₂, respectively. Q₁, Q₃, C_dc1, and T₁ form the lagging-HBI. Q₂, Q₄, C_dc2, and T₂ form the leading-HBI. The auxiliary inductor L_aux is used to adaptively adjust the energy for ZVS operation. Two full-bridge rectifiers are employed at the rectifier stage.

For the convenience of circuit analysis, the following assumptions are made:

(1)

The blocking capacitors C_dc1, C_dc2 are considered as two constant voltage sources of 0.5V_in.

(2)

All the output capacitances of MOSFETs have the same values, C_oss.L_lk1 and L_lk2 also have the same values, L_lk.

(3)

The output filter inductor L_o is large enough to be treated as a constant current source during a switching period.

Figure 2 shows the key waveforms of the proposed converter in the steady state. D means the duty-cycle and T_s is the switching period. All the primary switches’ duty-cycles keep constant (50%) if the dead-time is ignored. The output voltage is regulated by adjusting the phase-shift time 0.5DT_s between leading-HBI and lagging-HBI. The operating sequence during each switching period can be divided into two half cycles—t₀–t₈ and t₈–t₁₅. Due to the symmetrical structure, only the first half cycle is given. This half cycle can be divided into eight operating modes, whose topological states are shown in Figure 3.

Mode 1 [t₀-t₁]: Q₁ and Q₂ are on. The primary voltages of T₁ and T₂ are 0.5V_in, which leads to the current of L_aux keeping negative maximum. The output current I_o flows through D₃ and D₄. Several primary currents are expressed as follows:

$$\begin{gathered} i_{aux}(t)=-I_{aux} \\ {i}_{13}(t)=n{I}_o-I_{aux} \\ {i}_{24}(t)=n{I}_o+I_{aux} \end{gathered}$$

(1)

Mode 2 [t₁-t₂]: Q₂ is turned off at time t₁. The voltage across junction capacitances of Q₂ and Q₄ are charged and discharged linearly by the constant current source i₂₄(t₁). The voltage of point A V_A(t) decreases from V_in to 0.5V_in. v_s1(t) keeps 0.5nV_in and v_s2(t) falls from 0.5V_in to zero. Thus, V_rec(t) decreases from nV_in to 0.5V_in. The voltage of L_aux starts to increase from zero. The voltages in this mode are expressed as:

$$\begin{gathered} V_A(t)=V_{in}-\frac{i_{24}(t_1)}{2C_{oss}}(t-t_1) \\ {V}_{rec}(t)=n{V}_{in}-\frac{n{i}_{24}(t_1)}{2C_{oss}}(t-t_1) \end{gathered}$$

(2)

Mode 3 [t₂-t₃]: When V_A(t) becomes 0.5V_in in Mode 2, v_s2(t) falls to zero and D₂ starts to conduct. v_s2(t) is maintained at zero since D₂ and D₃ are in conducting state during this mode. The resonance between L_lk2 and the junction capacitances occurs. The capacitances are charged or discharged by the energy stored in L_lk2. V_A(t) decrease from 0.5V_in to zero with a resonance waveform. The voltage of L_aux continuously increases. The currents and voltages are expressed as follows:

$$\begin{gathered} i_{p2}(t)=i_{24}(t_1)\cos \omega (t-t_2)-I_{aux} \\ {V}_A(t)=0.5V_{in}-i_{24}(t_1)\sqrt{\frac{L_{lk}}{2C_{oss}}}\sin \omega (t-t_2) \end{gathered}$$

(3)

where ${\omega }_1=\frac{1}{2\sqrt{L_{lk}{C}_{oss}}}$.

Mode 4 [t₃-t₄]: V_A(t) reaches zero at time t₃ and the parasitic diode of Q₄ starts to conduct. Q₄ can be turned on with zero voltage in this mode. v_s2(t) is maintained at zero and the commutation between D₂ and D₃ is progressed during this mode. The voltage of L_aux rises to V_in. The primary current of T₂ is expressed as:

$$i_{p2}(t)=i_{p2}(t_3)-\frac{V_{in}}{2L_{lk}}(t-t_3)$$

(4)

Mode 5 [t₄-t₅]: Mode 5 begins when i_p2(t) falls to zero. The commutation between D₂ and D₃ is completed at t₄. v_s2(t) becomes −0.5nV_in and T₂ stops to transfer the power from input side to output side. The voltage of L_aux and V_rec(t) are continuously maintained at V_in and 0.5nV_in, respectively. The current of L_aux is given by:

$$i_{aux}(t)=-I_{aux}+\frac{V_{in}}{L_{aux}}(t-t_4)$$

(5)

Mode 6 [t₅-t₆]: Q₁ is turned off at t₅. At the same time, the commutation between D₄ and D₆ isprogressed. The resonance of junction capacitances and leakage inductances occurs. V_B(t) is decreased from V_in to zero and V_rec(t) falls to zero. The current of L_aux can be considered to increase to the positive maximum (+I_aux). The primary currents of T₁ and T₂ are expressed as follows:

$$\begin{gathered} i_{p1}(t)=(n{I}_o+I_{aux})\cos {\omega }_1(t-t_5)-I_{aux} \\ {i}_{p2}(t)=-(n{I}_o+I_{aux})\left[1-\cos {\omega }_1(t-t_5)\right] \\ {V}_B(t)=V_{in}-\sqrt{\frac{L_{lk}}{C_{oss}}}(n{I}_o+I_{aux})\sin {\omega }_1(t-t_5) \end{gathered}$$

(6)

Mode 7 [t₆-t₇]: Mode 7 begins when V_B(t) falls to zero. The body diode of Q₃ starts to conduct and Q₃ can be turned on with zero voltage. v_s1(t) and v_s2(t) are maintained zero in this mode. The voltage across L_lk1 or L_lk2 equals to −0.5V_in. The commutation between D₄ and D₆ is continually progressed. The currents are expressed as follows:

$$\begin{gathered} i_{p1}(t)=-i_{p1}(t_6)+\frac{V_{in}}{2L_{aux}}(t-t_6) \\ {i}_{p2}(t)=-i_{p2}(t_6)+\frac{V_{in}}{2L_{aux}}(t-t_6) \end{gathered}$$

(7)

Mode 8 [t₇-t₈]: Mode 8 begins when i_p1(t) falls to zero and D₄ is naturally turned off. At the same time, v_s2(t) becomes −0.5nV_in and v_s1(t) becomes zero since the commutation between D₁ and D₂ starts. The voltage across L_lk1 is −0.5V_in and i_p1(t) decreases linearly.

Mode 8 ends when i_p1(t) reaches nI_o and D₂ is naturally turned off. The commutation between D₁ and D₂ ends at t₈. The power is transferred from the primary side to the secondary side through T₁ and T₂. The voltage across L_aux is zero and i_aux is maintained at the positive maximum.

3. Analysis of the Proposed Converter

3.1. Voltage Gain Analysis

Since the durations of duty-cycle loss and dead-time are very narrow, they can be ignored to simplify analysis. Figure 4a shows the simplified rectifier output voltage in the proposed converter. The voltage gain is derived from the volt-second balance of the output filter inductor, and it can be expressed as follows:

$$G=\frac{V_o}{V_{in}}=\frac{n(1+D)}{2}$$

(8)

The rectifier output voltage waveform in the conventional full-bridge converter is shown in Figure 4b. It can be noted that the energy from the primary side cannot be transferred to the secondary side during freewheel period. For the proposed converter, the energy can always be transferred to the output side during the whole period. Therefore, the filter requirement can be significantly less and the power loss can also be reduced.

As shown in Figure 4b, the voltage of the output filter inductor is nV_in − V_o during the duty-cycle period, while the value is −V_o during the freewheeling period. The output filter inductor for the conventional full-bridge converter is calculated based on the given current ripple.

$$L_{con}=\frac{D(n{V}_{in}-V_o)}{4f_s\Delta I_{out}}=\frac{V_o}{4f_s\Delta I_{out}}(1-D)$$

(9)

where ΔI_out is the current ripple of L_o. In general, ΔI_out is set at 20 percent of full load current.

For the proposed converter, the voltage applied on L_o is 0.5nV_in − V_o during the freewheeling period. The filter inductor for the proposed converter is calculated as

$$L_{pro}=\frac{D(n{V}_{in}-V_o)}{4f_s\Delta I_{out}}=\frac{V_o}{4f_s\Delta I_{out}}\frac{D(1-D)}{1+D}$$

(10)

Figure 5 shows the relationship between the required value of filter inductor and duty-cycle. It can be noted that the filter inductance of the proposed converter is much smaller than that of the traditional full-bridge converter. Therefore, the proposed converter benefits from the reduction of the inductor’s size and copper loss.

3.2. ZVS Characteristics

For the ZVS of leading-HBI switches, the transition is accomplished in Mode 2 and Mode 3. During Mode 2, the output filter inductor takes part in the transition and the voltage of leading-leg is decreased from V_in to 0.5V_in. Then, the transformer is shorted and the remaining voltage falls by the resonance between junction capacitances and leakage inductance of the transformer during Mode 3. The required energy for ZVS can be obtained according to (3)

$$\frac{1}{2}{L}_{lk2}{(n{I}_o+I_{aux})}^2>C_{oss}{(0.5V_{in})}^2$$

(11)

When the lagging-HBI switch is turned off during Mode 6, the transformers are shorted and only the energies stored in the leakage inductances can be available for lagging-leg transition. According to the Equation (6), the ZVS condition of lagging-leg switches can be expressed as

$$\frac{1}{2}(L_{lk1}+L_{lk2}){(n{I}_o+I_{aux})}^2>C_{oss}{V_{in}}^2$$

(12)

According to Equations (11) and (12), the ZVS energies are related to I_aux. If the durations of duty-cycle loss and dead-time are ignored, I_aux can be calculated as

$$I_{aux}=\frac{V_{in}}{4L_{aux}{f}_s}(1-D)$$

(13)

According to Equation (13), I_aux and duty-cycle have an inverse relationship. When D is low (e.g., increasing the input voltage or decreasing the load current), the maximum value of auxiliary inductor current will increase. Sufficient energy can be stored in the leakage inductances to achieve ZVS operation. Therefore, the proposed converter can achieve ZVS over the full range of load conditions.

4. Experimental Results

A prototype was built to demonstrate the performance of the proposed converter. The components used in the prototype are shown in

Table 1. Components list.

Main switches (Q1–Q4)	SPW20N60C3
Rectifier diodes (D1–D6)	IDH08SG60C
Blocking capacitor (Cdc1Cdc2)	10 µF
Main transformers (T1 T2)	Core PQ3535 Turns ratio n = 0.9 Llk1 = Llk2 = 12 µH
Output inductor (Lo)	60 µH

. The circuit parameters of the prototype are given as follows:

(1)

Input voltage: V_in = 200–300 V

(2)

Output voltage: V_o = 150 V

(3)

Maximum output current I_o(max) = 5 A

(4)

Switching frequency: f_s = 80 kHz

The digital-signal-processor (DSP) TMS320F28027 (Texas Instruments, Dallas, TX, USA) was adopted for the digital control of the proposed converter. SPW20N60C3 (Infineon Technologies, Munich, Germany) were used as the primary switches, and the effective output capacitance was 160 pF [18]. The rectifier was formed by IDH08SG60C (Infineon Technologies, Munich, Germany). The input power was evaluated through DC Power Supply 62150H, and the output power was measured through DC Electronic Load 63204, manufactured by the Chroma Company (Taiwan, China).

Figure 6 shows the key waveforms of the proposed converter at V_in = 230 V, I_o = 5 A. It can be noted that the experimental waveforms coincide well with the theoretical analysis described in Figure 3.

Figure 7 shows the key waveforms of the auxiliary inductor when the proposed converter operates at different duty-cycles. As shown in Figure 7, both the maximum current value of the auxiliary inductor and the available energy for ZVS operation are increased when duty-cycle is decreased. This characteristic is helpful to realize the ZVS under all kinds of operation conditions and can reduce the conduction loss caused by the auxiliary circuit.

Figure 8 and Figure 9 show the gate-source and drain-source voltage waveforms at I_o = 1 A and I_o = 50 mA, respectively. It can be noted that all the switches in the proposed converter can achieve ZVS operation over the entire load current and input voltage ranges.

In order to compare the performances, a conventional PSFB converter was built with an external inductance of 20 µH to achieve the ZVS operation over a load range from 50% to 100%. Figure 10 shows the experimental efficiencies of the proposed converter and the conventional converter under different load currents. At heavy loads, both converters could achieve ZVS, while the additional components in the proposed converter increased the conduction losses. Therefore, the efficiency of the proposed converter was a little lower than that of the conventional converter. At light loads, the switching losses were dominant and the conventional converter failed to obtain ZVS. The proposed converter could maintain the ZVS operation and achieve higher efficiency at light loads, as shown in Figure 10. The efficiency improvement was determined by the saved switching losses.

5. Conclusions

A dual half-bridge converter with an auxiliary inductor was proposed to solve the drawbacks of the conventional PSFB converters. The proposed converter can transfer the power from the primary side to the secondary side during the whole period. Therefore, the circulating current is removed and the filter requirement is reduced. The ZVS energy can be changed with the duty-cycle, which is helpful for the realization of ZVS under the whole range of operation conditions. The experimental results coincide with the theoretical analysis. The proposed converter is a good candidate for high power, high voltage, and variable input voltage applications.