SatEC: A 5G Satellite Edge Computing Framework Based on Microservice Architecture
Abstract
:1. Introduction
2. Related Work
2.1. Satellite Communication with 5G
2.2. Satellite On-Board Computing
2.3. Drone Communications with 5G
3. System Framework
3.1. System Design
3.2. Hardware Platform
- Master node: The master node is the core of the system, so it is designed with high reliability systems. Multiple control nodes are deployed in the system, and the data consistency is guaranteed by a high availability database based on the paxos protocol [40]. There is only one leader node at a time. When the leader node is unavailable for some reason, the system automatically selects a new leader from the following nodes, allowing the system to keep running.
- Common resource node: The common resource source nodes provide common resources such as CPU, memory, and storage to the SetEC system. Considering the power consumption constraints of on-board devices, the hardware system of these nodes is made of ARM CPU, which is based on the Reduced Instruction Set Computer (RISC) architecture. Compared with the Intel X86 processor, the ARM process has small instruction sets: the hardware logic is relatively simple. Therefore, it has fewer transistors than the X86 processor. The power consumption is consequently relatively low. Using container-based virtual technologies (such as Docker), common resource nodes can easily be used for virtualization.
- GPU resource node: This kind of nodes provide GPU computing resources, which are mainly used in image processing, deep learning computation, and other compute-intensive applications. GPU resource nodes are based on GPU NVIDIA jetson chips. This series of chips contains several GPU cores and several ARM CPU cores. Using container virtual machines installed in the ARM CPU, the master node can control and schedule GPU resources.
- FPGA resource nodes: This node provides FPGA computing resources for the system [41]. It is used for hardware acceleration in the fields of video/image processing, deep learning, gene detection, financial data analysis, and so on. The FPGA resource node is built on the Xilinx Zynq UltraScale + MPSoC FPGA platform, which contains multiple CPU cores and FPGA programmable logic (PL) resources. The PL logic can be dynamically reconfigured. Using container virtual machines installed in the ARM CPU, the master node can control and schedule FPGA programmable logical resources.
- Storage resource nodes: The storage resources of SatEC are distributed in each node, and hard disks in all resource nodes can be used as storage resources in the SatEC resource platform.However, other types of resource nodes have limited storage capability. Their storage resource is mainly for their own use. The storage resource node is composed of ARM CPU and a large capacity solid-state hard disk, which is mainly used for the storage of massive data. Storage resource nodes support a variety of storage protocols: they can provide data access interfaces for files, objects, and data blocks. Database system can also be deployed in the storage resource nodes, and the database access interface is provided to the users.
- Network resource nodes: The software defined network (SDN) is used in the management of the network resources, and the master node uses the OpenFlow protocol to manage network resource nodes. Based on the status of the network, a flow table is generated in the master node, and is sent to network resource nodes. The packets passing through the nodes will be routed according to rules in the flow table.Master nodes and other resource nodes are all connected to the network resource node. Data exchange between master nodes and resource nodes occurs through network resource nodes. Except for network resource nodes, a Representational State Transfer (REST) interface is used in resource management.
3.3. Software Framework
4. Analysis, Comparisons, and Future Plans
4.1. Simulation Environment
4.2. Simulation Results
5. Conclusions
Author Contributions
Funding
Conflicts of Interest
References
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Nodes | Quantity | Remarks |
---|---|---|
Master node | 3 | Also used as common resource nodes |
Common resource node | 1 | ----- |
FPGA resource nodes | 1 | ----- |
GPU resource node | 1 | ----- |
Storage resource node | 1 | ----- |
Network resource nodes | 1 | ----- |
Time Cost | Meaning |
---|---|
T1 | The time cost of moving to the coverage of communication networks |
T2 | The time cost of forwarding data in terrestrial 5G network |
T3 | The time cost of processing data in terrestrial 5G network |
T4 | The time cost of uploading data |
T5 | The time cost of forwarding data among intersatellite links |
T6 | The time cost of downloading result |
T7 | The time cost of forwarding data to data center |
Network Type | Ground 5G Network | 5GsatEC |
---|---|---|
Delay (s) | 50.0000 | 0.0016 |
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Yan, L.; Cao, S.; Gong, Y.; Han, H.; Wei, J.; Zhao, Y.; Yang, S. SatEC: A 5G Satellite Edge Computing Framework Based on Microservice Architecture. Sensors 2019, 19, 831. https://doi.org/10.3390/s19040831
Yan L, Cao S, Gong Y, Han H, Wei J, Zhao Y, Yang S. SatEC: A 5G Satellite Edge Computing Framework Based on Microservice Architecture. Sensors. 2019; 19(4):831. https://doi.org/10.3390/s19040831
Chicago/Turabian StyleYan, Lei, Suzhi Cao, Yongsheng Gong, Hao Han, Junyong Wei, Yi Zhao, and Shuling Yang. 2019. "SatEC: A 5G Satellite Edge Computing Framework Based on Microservice Architecture" Sensors 19, no. 4: 831. https://doi.org/10.3390/s19040831
APA StyleYan, L., Cao, S., Gong, Y., Han, H., Wei, J., Zhao, Y., & Yang, S. (2019). SatEC: A 5G Satellite Edge Computing Framework Based on Microservice Architecture. Sensors, 19(4), 831. https://doi.org/10.3390/s19040831