FPGA Implementation of Efficient CFAR Algorithm for Radar Systems
Abstract
:1. Introduction
2. Previously Proposed CFAR Algorithms
2.1. ACCA-ODV CFAR
2.2. VI CFAR and MVI CFAR
3. Proposed CFAR Algorithm
Algorithm 1 Pseudocode of the Proposed CFAR. |
|
4. Performance Analysis
5. Hardware Architecture
5.1. Sorting Unit (SU)
5.2. Parameter-Calculation Unit (PCU)
5.3. Environmental-Decision Unit (EDU)
5.4. Comparator Unit (VCU)
5.5. Implementation and Results
6. Conclusions
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Conflicts of Interest
References
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Reference Window Size | Guard Cell Size | CNR | Number of Partition Windows | Size of Partition Window | Number of Trials | Noise Power | ||
---|---|---|---|---|---|---|---|---|
36 | 1 | 10 dB | 4 | 9 | 1 dB |
⋯ | Mask Enable | ||||
---|---|---|---|---|---|
× | × | ⋯ | × | 0 | 0000_0000_0000 |
× | × | ⋯ | 0 | 1 | 1000_0000_0000 |
⋯ | ⋯ | ||||
× | 1 | ⋯ | 1 | 1 | 1111_1111_1110 |
1 | 1 | ⋯ | 1 | 1 | 1111_1111_1111 |
Unit | LUT | Registers |
---|---|---|
SU | 3189 | 1846 |
PCU | 3531 | 1351 |
EDU | 579 | 105 |
VCU | 371 | 194 |
Top Block | 8260 | 3823 |
Fmax | 118.39 MHz |
Ref. | Platform | Algorithm | Resource | Fmax (MHz) | Operation Time | Process (nm) | Tnorm | |
---|---|---|---|---|---|---|---|---|
LUT | Register (Slices) | |||||||
[22] | Altera Stratix IV | ACOSD 1 | 4273 | 3074 | 250 | 0.45 s | 40 | 0.23 s |
[23] | Altera Stratix II | ACOSD 1 | N/A | N/A | 100 | 110 ms | 90 | 24.44 ms |
[24] | Altera Stratix IV | ACOSD 1, CA, OS | 11,094 | 11,192 | 200 | 0.27 s | 40 | 0.16 s |
[25] | Xilinx Zynq 7000 | ACOSD 1 | 10,441 | 12,688 | 148 | 0.24 s | 28 | 0.17 s |
[26] | Xilinx Virtex-IV | CA, GO, SO, OSCA 2, OSGO 3, OSSO 4 | 690 | 1364 | N/A | 84 ms | 90 | 18.67 ms |
[27] | Xilinx Virtex-IV | CA, OS | 11,197 | 6027 | 59 | N/A | 90 | N/A |
[28] | Xilinx Virtex-6 | CA, OS, TM | 9272 | 5004 | N/A | 503 ms | 40 | 251.5 ms |
[29] | Xilinx KCU105 | OS, OSCA 2, OSGO 3, OSSO 4 | 5697 | 2923 | 100 | 0.26 s | 20 | 0.26 s |
[30] | Xilinx Kintex-7 | Mean Level, Log-t | 99,650 | 27,082 | 100 | 83 s | 28 | 59.29 s |
[31] | Altera Stratix II | ACCA-ODV | 18,861 | 5943 | 109.37 | 0.21 s | 90 | 0.05 s |
Proposed | Altera Stratix II | MVI, ACCA-ODV | 8260 | 3823 | 118.39 | 0.6 s | 90 | 0.13 s |
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Sim, Y.; Heo, J.; Jung, Y.; Lee, S.; Jung, Y. FPGA Implementation of Efficient CFAR Algorithm for Radar Systems. Sensors 2023, 23, 954. https://doi.org/10.3390/s23020954
Sim Y, Heo J, Jung Y, Lee S, Jung Y. FPGA Implementation of Efficient CFAR Algorithm for Radar Systems. Sensors. 2023; 23(2):954. https://doi.org/10.3390/s23020954
Chicago/Turabian StyleSim, Yunseong, Jinmoo Heo, Yongchul Jung, Seongjoo Lee, and Yunho Jung. 2023. "FPGA Implementation of Efficient CFAR Algorithm for Radar Systems" Sensors 23, no. 2: 954. https://doi.org/10.3390/s23020954
APA StyleSim, Y., Heo, J., Jung, Y., Lee, S., & Jung, Y. (2023). FPGA Implementation of Efficient CFAR Algorithm for Radar Systems. Sensors, 23(2), 954. https://doi.org/10.3390/s23020954