A Review on Soft Error Correcting Techniques of Aerospace-Grade Static RAM-Based Field-Programmable Gate Arrays
Abstract
:1. Introduction
2. SRAM-Based FPGA Soft Error Sensitivity Analysis Techniques
2.1. Sensitivity Analysis of Application Layer Resources in SRAM-Based FPGAs
2.1.1. Fault Emulation-Based Soft Error Sensitivity Analysis
2.1.2. Analytical Model-Based Soft Error Sensitivity Analysis
2.2. Sensitivity Analysis of Configuration Bitstreams in SRAM-Based FPGAs
2.2.1. Configuration Bits Classification
2.2.2. Methods for Locating Essential and Critical Bits
3. SRAM-Based FPGA Configuration Scrubbing
3.1. Basic Configuration Scrubbing Techniques
3.1.1. External and Internal Scrubbing
3.1.2. Periodic Scrubbing and Corrective Scrubbing
3.1.3. Device-Level Scrubbing, Frame-Based Scrubbing, and Mixed Granularity Scrubbing
3.1.4. Redundant Configuration Scrubbing
3.2. Advanced Configuration Scrubbing Techniques
3.2.1. Nonlinear Configuration Scrubbing
3.2.2. Multitasking Scrub Scheduling
4. Memory Scrubbing Techniques
5. Challenges and Future Directions
- (1)
- Develop more detailed and accurate models for soft error analysis in FPGA application layers. Current technologies struggle to accurately emulate the operational processes and states of circuits during functioning. Consequently, it is difficult to precisely determine which resources have a more significant impact on circuit performance when soft errors occur. Moreover, conducting more refined emulations requires substantial computational resources and time. Therefore, developing more accurate models for soft error analysis and enhancing the speed of such analyses represent one of the future directions for research in this field.
- (2)
- For memory scrubbing techniques, expand coverage to a broader range of storage units. Compared to configuration scrubbing, research on memory scrubbing is relatively scarce and has mostly focused on major storage units in the application layer, such as BRAM and LUTs. However, there has been limited research on the correction of soft errors in crucial but less data-intensive storage resources, such as control registers, which are critical for operation. Developing methods to detect and promptly correct soft errors in these key registers may become a focal point in future research on FPGA soft error mitigation techniques.
- (3)
- Incorporate artificial intelligence into the mitigation, detection, and repair of soft errors in FPGAs. The task of optimizing the layout of user circuits within FPGAs to minimize sensitivity to SEE is a heuristic problem with a vast variable space, making it challenging to find optimal solutions. Artificial intelligence is well-suited for solving such high-dimensional data space issues [85]. AI can be utilized to analyze designs within FPGAs, identify vulnerabilities in the circuits, and suggest appropriate improvements.
6. Conclusions
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Acknowledgments
Conflicts of Interest
References
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Analysis Techniques | Advantages | Disadvantages | ||
---|---|---|---|---|
Analysis of application layer resources | Fault emulation-based | Using radiation tests | Emulate space radiation environments to the greatest extent. | High costs, time-consuming, potentially destructive to devices, and uncontrollable error locations. |
Using hardware emulation | High repeatability and minimal destructive impact on circuits. | Complex, specialized hardware is required to perform error emulation tasks. | ||
Analytical model-based | Has no damage to the circuit under analysis. | Long analysis time and low accuracy. | ||
Analysis of configuration bitstream | Based on dual-layer mapping | A certain research foundation. | Limited research on newer FPGA models. | |
Using fault injection | The principle is simple and easy to operate. | Performing a comprehensive error injection on a large-scale FPGA takes too much time. |
Research | Description |
---|---|
[43] | Shifted scrubbing. Derive the optimal scrubbing starting frame address based on the number of critical bits in each frame. |
[44] | Scatter scrubbing. Derive the optimal starting frame address and adopt a jumping read-back verification method. |
[70] | Combine essential-frame scrubbing and full-device scrubbing. |
[33] | Further subdivide critical bits into PCB and SCB. |
[71] | Categorize configuration frames into unused frames, basic frames, priority basic frames, and critical frames. |
[72] | Distinguish highly critical bits within the critical bits. |
Research | Scheduling Methods | Advantages | Disadvantages |
---|---|---|---|
[73] | Static scheduling method based on task criticality and execution time. | Implemented scrubbing scheduling in multi-circuit task scenarios. | Adopts a static scheduling algorithm, unable to adapt to dynamic hardware task lists. |
[74] | Dynamic scrubbing scheduling method based on time windows. | Requires less storage space and can adapt to dynamic hardware task lists. | Reliability decreases in scenarios with frequent parallel circuit tasks. Discriminates against low-criticality tasks. |
[75] | Heterogeneous application scrubbing scheduling method based on time windows. | Considers DSP-related and high-data-throughput application tasks. | Allocates very low scrubbing frequencies for tasks of low criticality. |
[76] | Dynamic scheduling based on DVFS. | Reduces conflicts among scrubbing tasks, further enhancing reliability. | Allocates very low scrubbing frequencies for tasks of low criticality. |
[77] | Negotiation-driven scrubbing scheduling. | Better manages conflicts between scrubbing tasks. | Requires substantial storage space when there are a large number of tasks. |
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Wang, W.; Li, X.; Chen, L.; Sun, H.; Zhang, F. A Review on Soft Error Correcting Techniques of Aerospace-Grade Static RAM-Based Field-Programmable Gate Arrays. Sensors 2024, 24, 5356. https://doi.org/10.3390/s24165356
Wang W, Li X, Chen L, Sun H, Zhang F. A Review on Soft Error Correcting Techniques of Aerospace-Grade Static RAM-Based Field-Programmable Gate Arrays. Sensors. 2024; 24(16):5356. https://doi.org/10.3390/s24165356
Chicago/Turabian StyleWang, Weihang, Xuewu Li, Lei Chen, Huabo Sun, and Fan Zhang. 2024. "A Review on Soft Error Correcting Techniques of Aerospace-Grade Static RAM-Based Field-Programmable Gate Arrays" Sensors 24, no. 16: 5356. https://doi.org/10.3390/s24165356