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Article

An Anisotropic Equivalent Thermal Model for Shield Differential Through-Silicon Vias

School of Microelectronics, Xidian University, Xi’an 710071, China
*
Authors to whom correspondence should be addressed.
Micromachines 2021, 12(10), 1223; https://doi.org/10.3390/mi12101223
Submission received: 14 September 2021 / Revised: 29 September 2021 / Accepted: 4 October 2021 / Published: 7 October 2021

Abstract

:
An accurate equivalent thermal model is proposed to calculate the equivalent thermal conductivity (ETC) of shield differential through-silicon via (SDTSV). The mathematical expressions of ETC in both horizontal and vertical directions are deduced by considering the anisotropy of SDTSV. The accuracy of the proposed model is verified by the finite element method (FEM), and the average errors of temperature along the X-axis, Y-axis, diagonal line, and vertical directions are 1.37%, 3.42%, 1.76%, and 0.40%, respectively. Compared with COMSOL, the proposed model greatly improves the computational efficiency. Moreover, the effects of different parameters on the thermal distribution of SDTSV are also investigated. The thermal conductivity is decreased with the increase in thickness of SiO2. With the increase in pitch, the maximum temperature of SDTSV increases very slowly when β = 0 ° , and decreases very slowly when β = 90 ° . The proposed model can be used to accurately and quickly describe the thermal distribution of SDTSV, which has a great prospect in the design of 3D IC.

1. Introduction

Through-silicon via (TSV) is a key structure of 3D integrated circuits (IC) [1,2,3,4,5]. TSV-based 3D ICs have a shorter interconnect length, higher integration density, faster data communication, and lower power consumption [6,7,8,9,10]. Due to the excellent anti-noise characteristic during the transmission of different signals, shielded differential through-silicon vias (SDTSV) have wide prospects in 3D ICs [11]. However, with the increasing integration level of 3D ICs, the thermal effect obviously influences its performance, and has become an inevitable and urgent challenge [12,13,14]. Therefore, it is important to investigate the thermal effect on 3D ICs and establish an accurate thermal model of SDTSV for the design of 3D ICs.
In the last decade, the thermal models of TSV, coaxial TSV, and TSV arrays have been systematically investigated and established [15,16]. Meanwhile, the thermal models of 3D ICs have also been studied [17,18,19]. The thermal models in 3D ICs mainly include 1D networks, ETC models, the finite element method (FEM), and so on. Xiao et al. [20] established a fast and accurate equivalent thermal model for TSV. In this model, several parameters, including pitch, the thickness of SiO2, and the radius of TSV, have been considered, and the accuracy of the proposed model has been verified by FEM. Hu et al. [19] proposed a thermal model of a high-power 3D-integrated RF module based on a TSV interposer, and the thermal model was verified by FEM. In addition, Chieh et al. [21] developed the equivalent thermal model of a TSV cell, and the maximum error was within 15%. Min et al. [22] proposed a 3D-equivalent thermal circuit model for coaxial TSV by equivalent thermal circuit, and the results showed that the proposed model worked well with FEM at transient temperatures. Feng et al. [23] proposed an equivalent thermal model for 2.5D packages, and the calculation time was reduced from 15 min to 23 s. Lau et al. [24] also investigated the thermal performance of three-layer-stacked chips using the computational fluid dynamics analysis method, and the empirical formula of effective thermal conductivity was proposed. Heng [25] proposed an equivalent model considering TSV, bump, and metallic trace, which could effectively improve the calculation efficiency of 3D system in package (SiP). Chen et al. [26] established an equivalent thermal resistance model for TSV, and the thermal performance of a 3D stacked-die package with TSV was quickly estimated by the proposed model. Pi et al. [17] established a fast and implementable full-chip scale numerical simulation method for thermal management of 3D ICs. In addition, the temperature difference is below 7.5%, and the grid number is reduced by 77%. Han et al. [27] proposed a thermal resistance network model based on 3D structures, and the proposed model could describe the temperature distribution of 3D structures. Konstantin O et al. [28] proposed an equivalent thermal model by using a quasi-3D approach, and the computational difficulties, processor time, and RAM volume were significantly reduced, while the simulation error of the maximal temperature was less than 20%. Wu et al. [29] proposed a thermal model using Laplace’s equation and the thermal resistance network, which could accurately predict the temperature of a heat source on the chip in these models; however, the 1D network was a simple model, and its accuracy was low. The accuracy of FEM is high, and generally used to verify the accuracy of the model, but it is complex and time consuming. TSV is treated as an equivalent thermal resistance in the equivalent model, which has high accuracy and calculation efficiency. Therefore, the ETC model can be used to describe the thermal distribution of SDTSV.
In recent years, SDTSV and derivative structures have been investigated by several researchers [30,31,32]. Lu et al. [11] proposed an equivalent circuit model of SDTSV in 3D ICs, and the proposed model worked well with the full-wave extraction method when the work frequency was up to 100 GHz. Fu et al. [30] investigated the equivalent circuit model of shielded differential annular through-silicon via, and analyzed its thermomechanical stress. Zhao et al. [31] proposed a novel differential TSV structure, and the accuracy of the circuit model was validated when the work frequency was up to 100 GHz. Liao et al. [32] proposed an equivalent electrical model for shielded-pair through-silicon vias, and the accuracy of the proposed model was verified. However, the thermal distribution of SDTSV is rarely investigated, whilst SDTSV plays a critical part in 3D ICs; therefore, it is necessary to establish an accurate ETC model for SDTSV to study its heat transfer performance. The equivalent thermal resistance models of typical and coaxial TSVs have been established in [11,22]. The thermal resistances in x and y directions are assumed to be the as the same in these models. However, the thermal resistances of SDTSV in different directions vary. In addition, SDTSV is composed of more oxide layers than common TSV and coaxial TSV. With the increase in oxide layers, finer grids are needed in the FEM, which can greatly increase the calculation burden and run-time; therefore, it is important to establish an accurate ETC model for SDTSV in order to quickly describe its heat distribution in both horizontal and vertical directions.
In this paper, an accurate and fast ETC model is established for SDTSV. The mathematical equations for the ETC of SDTSV are deduced in Section 2. The accuracy of the proposed ETC model is verified by FEM in Section 3, and the effects of different parameters on the thermal distribution of SDTSV are investigated and analyzed. Section 4 concludes this paper.

2. Expressions for Equivalent Thermal Conductivities of SDTSV

The particular structure of SDTSV is shown in Figure 1 [11,30]. In this SDTSV, the differential signals are transmitted by the inner two TSVs, and the function of the outer shell is shielding the external signal interference. The inner two TSVs are filled with Cu, and surrounded by the oxide insulation layer. The main structure parameters of SDTSV are shown in Table 1. Compared with TSV and coaxial TSV, the thermal distribution of SDTSV in horizontal directions may be affected by the number and location of inner TSVs; thus, the ETCs of SDTSV in horizontal and vertical directions are deduced to describe the thermal distribution of SDTSV. Subsequently, an accurate ETC model is established for SDTSV with an area of a × b. Three assumptions for the ETC model of SDTSV can be described: (1) since the horizontal temperature gradient is relatively large and the most of thermal flow comes from the outside, the heat generated by SDTSV can be ignored; (2) due to the isotropy of materials in different layers, the thermal resistances among different layers can be ignored; and (3) since the heat flow is assumed to be straight in the SDTSV, the detour of heat flow close to the other layer can be considered negligible.
When the heat flow Q in any direction is applied to SDTSV, it is divided into vertical and horizontal components, and the ETC model in the vertical direction is deduced first. In this model, the heat flow along the copper (Cu), silicon dioxide (SiO2), and silicon (Si) can be assumed as the parallel relationship, and the thermal resistance R eff _ vertical in the vertical direction for SDTSV cell can be calculated by
1 / R e f f _ v e r t i c a l = 1 / R S i _ sub + 1 / R S i O 2 _ 1 + 1 / R C u _ o u t s i d e + 1 / R S i O 2 _ 2 + 1 / R S i _ i n n e r + 1 / R S i O 2 _ 3 + 1 / R C u _ i n n e r
where R S i _ s u b is the thermal resistance of the Si substrate; R S i O 2 _ 1 is the thermal resistance of outer oxide insulation layer of shielding shell; R C u _ o u t s i d e is the thermal resistance of metal layer of shielding shell; R S i O 2 _ 2 is the thermal resistance of inner oxide insulation layer of shielding shell; R S i _ i n n e r   is the thermal resistance of inner Si; R S i O 2 _ 3 is the thermal resistance of oxide insulation layer of inner signal TSV; and R C u _ i n n e r is the thermal resistance of the copper core of the inner signal TSV. The ETC K e f f _ v e r t i c a l of SDTSV in vertical direction can be obtained by
K e f f _ v e r t i c a l = [ K S i ( a b π r 1 2 ) + K S i O 2 π ( r 1 2 r 2 2 ) + K C u π ( r 2 2 r 3 2 ) + K S i O 2 π ( r 3 2 r 4 2 ) + K S i π ( r 4 2 2 r 5 2 ) + K S i O 2 2 π ( r 5 2 r 6 2 ) + K C u 2 π r 6 2 ] / ( a b )
According to Equation (2), K e f f _ v e r t i c a l is mainly related to the area ratio of Cu, SiO2, and Si in the SDTSV cell.
The horizontal section of SDTSV is shown in Figure 2, and the thermal conductivities of SDTSV in different directions are distinct. The proposed model is established in the Cartesian coordinate system. The direction of the heat flow is fixed, and the SDTSV is rotated to simulate the heat flow coming from different directions and passing through the SDTSV unit. The blue line connects the centers of two inner metal holes, and the red line is parallel to the X-axis. The angle between the blue line and the red line is the rotation angle β. Based on the relationship of the rotation angle β, the pitch of inner metal holes p, and the oxide radius of the TSV r5, the thermal conductivity of SDTSV in the horizontal direction can be divided into two cases, as shown in Figure 2. In Figure 2a, the heat flow can be roughly split into seven regions (q1, q2, q3, q4, q5, q6, and q7) when s i n β < 2 × r 5 / p . The thermal resistance R h o r i z o n t a l can be calculated by
1 / R h o r i z o n t a l = 1 / R q 1 + 1 / R q 2 + 1 / R q 3 + 1 / R q 4 + 1 / R q 5 + 1 / R q 6 + 1 / R q 7
The materials in q1 and q7 are Si, and the thermal resistances in q1 and q7 can be calculated by Equation (5). Meanwhile, the thermal resistance in q2 and q6 can be obtained by Equation (6), and the thermal resistance in q3 and q5 can be obtained by Equation (7). The thermal conductivity in q4 can be obtained by Equation (8). Accordingly, the ETC of SDTSV can be calculated by Equation (4) when s i n β < 2 × r 5 / p .
K c a s e 1 = a 2 × b × h ( 1 / R q 1 + 1 / R q 2 + 1 / R q 3 + 1 / R q 4 + 1 / R q 5 + 1 / R q 6 + 1 / R q 7 )
R q 1 = R q 7 = K S i × ( b 2 r 1 ) × h 2 a
R q 2 = R q 6 = 1 2 p sin β / 2 + r 5 r 1 [ ( b 2 r 1 cos θ 1 ) K S i h d y + 2 ( r 1 cos θ 1 r 2 cos θ 2 ) K S i O 2 h d y + 2 ( r 2 cos θ 2 r 3 cos θ 3 ) K C u h d y + 2 ( r 3 cos θ 3 r 4 cos θ 4 ) K S i O 2 h d y + 2 r 4 cos θ 4 K S i h d y ]
R q 3 = r 5 p sin β / 2 p sin β / 2 + r 5 [ b 2 r 1 cos θ 1 + 2 r 4 cos θ 4 2 r 5 cos θ 5 K S i h d y + 2 r 1 cos θ 1 2 r 2 cos θ 2 K S i O 2 h d y + 2 r 3 cos θ 3 2 r 4 cos θ 4 K S i O 2 h d y + 2 r 5 cos θ 5 _ m e t a l 1 2 r 6 cos θ 6 _ m e t a l 1 K S i O 2 h d y + 2 r 2 cos θ 2 2 r 3 cos θ 3 + 2 r 6 cos θ 6 _ m e t a l 1 K C u h d y ]
R q 4 = r 5 p sin β / 2 p sin β / 2 r 5 [ b 2 r 1 cos θ 1 + 2 r 4 cos θ 4 2 r 5 cos θ 5 _ m e t a l 1 2 r 5 cos θ 5 _ m e t a l 2 K S i h d y + 2 r 1 cos θ 1 2 r 2 cos θ 2 K S i O 2 h d y + 2 r 3 cos θ 3 2 r 4 cos θ 4 K S i O 2 h d y + 2 r 5 cos θ 5 _ m e t a l 1 2 r 6 cos θ 6 _ m e t a l 1 + 2 r 5 cos θ 5 _ m e t a l 2 2 r 6 cos θ 6 _ m e t a l 2 K S i O 2 h d y + 2 r 6 cos θ 6 _ m e t a l 1 + 2 r 6 cos θ 6 _ m e t a l 2 K C u h d y ]
R q 5 = r 5 p sin β / 2 r 5 p sin β / 2 [ b 2 r 1 cos θ 1 + 2 r 4 cos θ 4 2 r 5 cos θ 5 K S i h d y + 2 r 1 cos θ 1 2 r 2 cos θ 2 K S i O 2 h d y + 2 r 3 cos θ 3 2 r 4 cos θ 4 K S i O 2 h d y + 2 r 5 cos θ 5 _ m e t a l 2 2 r 6 cos θ 6 _ m e t a l 2 K S i O 2 h d y + 2 r 2 cos θ 2 2 r 3 cos θ 3 + 2 r 6 cos θ 6 _ m e t a l 2 K C u h d y ]
θ n = arcsin c r n ( n = 1 , 2 , 3 , 4 , 5 , 6 )
where θ n are the angles between radius r n and the X-axis. From Equations (4)–(10), K c a s e 1 is determined by the radius and the thermal conductivity of materials in different parts. θ 5 _ m e t a l 1 and θ 5 _ m e t a l 2 are the angles between radius r 5 and the X-axis of two inner metal holes, and θ 6 _ m e t a l 1 and θ 6 _ m e t a l 2 are the angles between radius r 6 and the X-axis of two inner metal holes. cis the distance from the center of the circle to the transversal line that is parallel to X-axis.
In the Figure 2b, the thermal resistance R h o r i z o n t a l can be roughly split into seven regions (q1, q2, q3, q4, q5, q6, and q7), where s i n β 2 × r 5 / p . Similarly, the thermal resistance R c a s e 2 can be calculated by
1 / R h o r i z o n t a l = 1 / R q 1 + 1 / R q 2 + 1 / R q 3 + 1 / R q 4 + 1 / R q 5 + 1 / R q 6 + 1 / R q 7
Similarly, the ETC in case 2 K c a s e 2 of SDTSV can be calculated by Equation (12).
K c a s e 2 = b 2 × a × h ( 1 R q 1 + 1 R q 2 + 1 R q 3 + 1 R q 4 + 1 R q 5 + 1 R q 6 + 1 R q 7 )
R q 1 = R q 7 = 2 K S i × ( b 2 r 1 ) × h a
R q 2 = R q 6 = 1 2 p sin β / 2 + r 5 r 1 [ ( b 2 r 1 cos θ 1 ) K S i h d y + 2 ( r 1 cos θ 1 r 2 cos θ 2 ) K S i O 2 h d y + 2 ( r 2 cos θ 2 r 3 cos θ 3 ) K C u h d y + 2 ( r 3 cos θ 3 r 4 cos θ 4 ) K S i O 2 h d y + 2 r 4 cos θ 4 K S i h d y ]
R q 3 = 1 2 p sin β / 2 r 5 p sin β / 2 + r 5 [ ( b 2 r 1 cos θ 1 ) K S i h d y + 2 ( r 1 cos θ 1 r 2 cos θ 2 ) K S i O 2 h d y + 2 ( r 2 cos θ 2 r 3 cos θ 3 ) K C u h d y + 2 ( r 3 cos θ 3 r 4 cos θ 4 ) K S i O 2 h d y + 2 ( r 4 cos θ 4 r 5 cos θ 5 _ m e t a l 1 ) K S i h d y + 2 ( r 5 cos θ 5 _ m e t a l 1 r 6 cos θ 6 _ m e t a l 1 ) K S i O 2 h d y + 2 r 6 cos θ 6 _ m e t a l 1 K C u h d y ]
R q 4 = r 5 p sin β / 2 p sin β / 2 r 5 [ ( b 2 r 1 cos θ 1 ) K S i h d y + 2 ( r 1 cos θ 1 r 2 cos θ 2 ) K S i O 2 h d y + 2 ( r 2 cos θ 2 r 3 cos θ 3 ) K C u h d y + 2 ( r 3 cos θ 3 r 4 cos θ 4 ) K S i O 2 h d y + 2 r 4 cos θ 4 K S i h d y ]
R q 5 = 1 2 p sin β / 2 r 5 r 5 p sin β / 2 [ ( b 2 r 1 cos θ 1 ) K S i h d y + 2 ( r 1 cos θ 1 r 2 cos θ 2 ) K S i O 2 h d y + 2 ( r 2 cos θ 2 r 3 cos θ 3 ) K C u h d y + 2 ( r 3 cos θ 3 r 4 cos θ 4 ) K S i O 2 h d y + 2 ( r 4 cos θ 4 r 5 cos θ 5 _ m e t a l 2 ) K S i h d y + 2 ( r 5 cos θ 5 _ m e t a l 2 r 6 cos θ 6 _ m e t a l 2 ) K S i O 2 h d y + 2 r 6 cos θ 6 _ m e t a l 2 K C u h d y ]
Equations (11)–(17) show that K c a s e 2 is determined by the radius, pitch between two inner signal TSVs, and the thermal conductivity of materials in different parts.

3. Model Validation and Discussion

The accuracy of the ETC model established in the previous section is verified by FEM, and the effects of the parameters on the thermal distribution are investigated. In addition, the error of the proposed model is analyzed.

3.1. Numerical Validation

The accuracy of the proposed ETC model is verified by COMSOL. In this study, the numerical solutions of Equations (1)–(17) are solved by MATLAB, and the results are compared with those obtained by COMSOL. The parameters of FEM are shown in Table 2. In particular, the thickness of SiO2 is set to 0.2 μm, the rotation angles β are set to 0° (parallel to X-axis), 45° (diagonal line) and 90° (parallel to Y-axis), and the pitch of the inner metal hole is set from 25 μm to 90 μm, with a step size of 5 μm. The established SDTSV structure is shown in Figure 3. In this simulation, the heat flux Q (300 W/cm2) is imposed on the left [33,34]. The opposite side of the heat surface is set to the constant temperature, and the other surfaces have no heat exchange with the outside. The initial temperature of the SDTSV is set to 20℃ [26,35,36,37]. The experiments were performed using COMSOL 5.6 software with a 2.7 GHz quad-core CPU.
The comparison between the proposed model and COMSOL is shown in Figure 4. The thermal conductivities obtained by the proposed model have a good agreement with those obtained by COMSOL. When the rotation angle β is equal to 0°, 45°, and 90°, the maximum deviations between the two models are 6.91%, 10.51%, and 6.96%, respectively. The maximum temperature of SDTSV and run-time of the two models are shown in Table 3. The maximum deviations between the two models when the rotation angle β is equal to 0°, 45°, 90° are 1.37%, 3.42%, and 1.76%, respectively. The maximum deviations between the two models in a vertical direction are 0.40%, which implies that the proposed model can accurately describe the maximum temperature of SDTSV. In addition, the calculation efficiency of the proposed model is greatly improved compared with that of COMSOL.
The 3D temperature distributions of SDTSV obtained by the proposed model and COMSOL are shown in Figure 5. Obviously, the temperature distribution obtained by the proposed model is in accordance with that obtained by COMSOL, and the maximum error of the two models is 0.394 K, which also indicates that the proposed model can precisely simulate the thermal distribution of SDTSV. Isotherms of SDTSV obtained by the proposed model and COMSOL are shown in Figure 6. As shown in Figure 6a, the isotherm makes a detour in the interfaces of different martials, whereas the isotherm obtained by the proposed model is smooth. This is because SiO2 has a poorer heat-transfer performance than Cu and Si, which results in the detour of the isotherm. However, the SDTSV is treated as a lump model in the proposed model, which ignores the inside features, so the isotherm is smooth.

3.2. Effects of Different Parameters on the Temperature Distribution of SDTSV

The accuracy of the proposed model is verified above. Based on the proposed model, the effects of different parameters (the pitch and thickness of SiO2) on the thermal conductivity of SDTSV are investigated. In particular, the thickness of SiO2 is set from 0.1 μm to 0.6 μm, with a step size of 0.1 μm, and the pitch between the TSVs in SDTSV changes from 25 μm to 90 μm, with a step size of 5 μm. The ETCs of SDTSV in horizontal and vertical directions obtained by COMSOL are calculated by
K m _ c o m s o l = q Δ m Δ S × Δ T , m = x , y , z
where Δ m is the length of heat flow through the conductor,   Δ S is the cross-sectional area of heat flow through the conductor, and Δ T is the temperature drop of heat flow through the conductor.
The effects of different parameters on ETC in x, y and z directions are shown in Figure 7. The red surface is the result obtained COMSOL, and the blue surface is the result of the proposed model. As shown in Figure 7a, the ETC obtained by COMSOL decreases as the SiO2 thickness increases, but it changes little with the increase in pitch. When the SiO2 thickness is below 0.3 μm, the maximum error of thermal conductivity is 10.39%. Since the thermal conductivity of SiO2 is much lower than that of Si and Cu, the ETC decreases with the increase in SiO2 thickness. In addition, simulation results show that the pitch of the inner metal has little influence on the thermal distribution of SDTSV; however, the variation position of the isotherm is affected by the pitch of inner metals.
As shown in Figure 7b, the ETC obtained by COMSOL decreases with the increase in SiO2 thickness, but it changes little with the increase in pitch. The ETC obtained by the proposed model increases with the increase in pitch, and it decreases with the increase in SiO2 thickness. In addition, the error of thermal conductivities between the proposed model and FEM increases with the increase in SiO2 thickness. This is because when the thickness of SiO2 is larger than 0.4 μm, the heat flow along the tangential direction cannot be ignored; however, this situation is not considered in the proposed model.
As shown in Figure 7c, the ETC obtained by FEM changes little with the increase in pitch, and it decreases with the increase in SiO2 thickness. The ETC obtained by the proposed model is in accordance with that obtained by FEM. When the thickness of SiO2 is less than 0.4 μm, the maximum error of thermal conductivity is 9.61%.
The effects of different parameters on the thermal distributions of SDTSV in x, y, and z directions are shown in Figure 8. The variation trends in temperature are consistent with those of thermal conductivities in x, y, and z directions. In addition, the maximum errors of steady-state temperature are 5.53%, 4.21%, and 1.44%, respectively. As such, the proposed model is highly accurate.

3.3. Thermal Distribution of SDTSV Array

The thermal distributions of SDTSV array in x and y directions are further investigated in this section. A 4 × 4 SDTSV array is established, in which the pitch is 50 μm and the thickness of the SiO2 is 0.2 μm. The structure of the SDTSV array is shown in Figure 9. The heat flux Q (300 W/cm2) is imposed on the left. The opposite side of the heat surface is set to 20 °C, and the other surfaces have no heat exchange with the outside. The simulation results of the temperature distribution by FEM are shown in Figure 10a–c. Obviously, the temperature is decreased along the direction of heat conduction. In addition, the results of temperature distribution obtained by the proposed model are shown in Figure 11a–c. The errors of maximum temperature between COMSOL and the proposed model are 0.3056 K, 1.4277 K, and 1.5165 K when the rotation angle β is equal to 0°, 45°, and 90°, respectively. As such, the temperature distribution of the SDTSV array obtained by the proposed model has a good agreement with that obtained by FEM.

3.4. Discussion and Analysis

Based on the comparisons, the accuracy of the proposed model is verified by COMSOL. The maximum temperature error is lower than 1.5165 K, which is relatively small. In addition, compared with FEM, the calculation time of the proposed model is reduced from approximately 300 s to 1.9 s. However, the error of equivalent model is inevitable, which is its limitation. Compared with the finite element method (FEM), the equivalent model greatly improves the computational efficiency at the expense of certain accuracy. In the published studies, the maximum error of thermal conductivity in [21] is approximately 15%, and the temperature difference in [17] is below 7.5%. The simulation error of maximal temperature in [28] is less than 20%. The error of the proposed model is within 10% for thermal conductivity, and the maximum temperature error is 5.53%. As such, the proposed model is relatively accurate in comparison with other models. In addition, the heat flow is assumed to propagate along a straight line in the proposed model. However, due the heat flow propagating along the direction of small thermal resistance in practice, the detour phenomenon exists in the thermal propagation, which leads to the error in the proposed model. Moreover, compared with TSV and coaxial TSV, the structure of SDTSV is more complicated, which leads to the complex heat flow. In our future research, we will further study the characteristics of heat propagation in multi-layer media, so as to establish a more accurate equivalent thermal model.
According to the results obtained by COMSOL, the ETC in a vertical direction is larger than in a horizontal direction. This is because the Cu runs through the SDTSV along the vertical direction, and it is treated as the main channel of thermal dissipation. When β is equal to 0 ° , 45 ° , and 90 ° , the simulation results show that the thermal conductivities of the SDTSV cell are nearly equal. This is due to the radius of inner metal being very small, which has little effect on the thermal conductivity in horizontal directions. However, the maximum temperature of the SDTSV array obtained by COMSOL at β = 0 ° is higher than that at β = 90 ° , and the difference in maximum temperatures between β = 0 °   and   β = 90 ° is approximately 1.77 K in the 4 × 4 SDTSV array. This is because the thermal conductivities at β = 0 ° , 45 ° , and 90 ° are slightly different, and the difference in temperature is accumulated during thermal conduction along different directions; therefore, the difference in thermal dissipation in horizontal directions is magnified in the SDTSV array. In our future research, the effects of different parameters on the thermal distribution of SDTSV array will be studied, and the design and fabrication of SDTSV will be investigated to be applied in differential signal transmission of 3D ICs.

4. Conclusions

In this paper, an accurate equivalent thermal model is proposed to describe the thermal distribution of SDTSV, and the main conclusions can be summarized as follows:
(1)
An accurate equivalent thermal model is established for SDTSV, which can describe the thermal distribution of SDTSV along an arbitrary angle. The mathematical expressions of ETC in horizontal and vertical directions are deduced;
(2)
The accuracy of the proposed model is verified by COMSOL, and the average errors of temperature at β = 0 ° , 45 ° , 90 ° and vertical directions are 1.37%, 3.42%, 1.76%, and 0.40%, respectively. In addition, the calculation time of the proposed model is reduced from approximately 300 s to 1.92 s;
(3)
The effects of different parameters on the thermal distribution of SDTSV are investigated based on the proposed model. As the pitch increases, the maximum temperature of SDTSV increases very slowly when β = 0 ° , and decreases very slowly when β = 90 ° ; however, the ETC decreases as the thickness of SiO2 increases.

Author Contributions

Conceptualization, G.S., G.L. and D.C.; formal analysis, G.L.; funding acquisition, G.S., D.L. and Y.Y.; investigation, G.L.; methodology, G.S., G.L. and D.C.; project administration, Y.Y.; software, D.C. and Z.Y.; supervision, D.L. and Y.Y.; validation, G.L.; visualization, Z.Y.; writing—original draft, G.S. and G.L.; writing—review and editing, G.S. and D.C. All authors have read and agreed to the published version of the manuscript.

Funding

This work was supported in part by the National Key Research and Development Program of China under Grant 2019YFB2204402, and in part by the National Natural Science Foundation of China (NSFC) under Grant 62074121, Grant 62034002 and Grant 62104177, in part by the Fundamental Research Funds for the Central Universities under Grant XJS211105, in part by the Natural Science Foundation of Shaanxi Province under Grant 2019GY-010, and in part by the Scientific Research Program Funded by Shaanxi Provincial Education Department under Grant 20JY018.

Conflicts of Interest

The authors declare no conflict of interest.

References

  1. Liu, H.; Fang, R.; Miao, M.; Jin, Y. Accurate Modeling of the Capacitance of Through Silicon Via Considering Minority Carrier Effects. IEEE Trans. Compon. Packag. Manuf. Technol. 2020, 99, 749–762. [Google Scholar] [CrossRef]
  2. Pan, Y.; Li, F.; He, H.; Li, J.; Zhu, W. Effects of dimension parameters and defect on TSV thermal behavior for 3D IC packaging. Microelectron. Reliab. 2017, 70, 97–102. [Google Scholar] [CrossRef]
  3. Wang, M.; Ma, S.; Jin, Y.; Wang, W.; Chen, J.; Hu, L.; He, S. A RF Redundant TSV Interconnection for High Resistance Si Interposer. Micromachines 2021, 12, 169. [Google Scholar] [CrossRef]
  4. Shan, G.; Lu, Q.; Liu, S.; Yang, Y. Through-Silicon Capacitor Interconnection for High-Frequency 3-D Microsystem. IEEE Trans. Compon. Packag. Manuf. Technol. 2019, 9, 1310–1318. [Google Scholar] [CrossRef]
  5. Jin, J.; Zhao, W.S.; Wang, D.W.; Chen, H.S.; Li, E.P.; Yin, W.Y. Investigation of Carbon Nanotube-Based Through-Silicon Vias for PDN Applications. IEEE Trans. Electromagn. Compat. 2018, 60, 638–646. [Google Scholar] [CrossRef]
  6. Li, H.; Liu, J.; Xu, T.; Xia, J.; Tan, X.; Tao, Z. Fabrication and Optimization of High Aspect Ratio Through-Silicon-Vias Electroplating for 3D Inductor. Micromachines 2018, 9, 528. [Google Scholar] [CrossRef] [Green Version]
  7. Chiang, T.Y. Thermal analysis of heterogeneous 3D ICs with various integration scenarios. In Proceedings of the International Electronics Devices Meeting, Washington, DC, USA, 2–5 December 2001; pp. 31.2.1–31.2.4. [Google Scholar]
  8. Yue, Q.; Lu, Z.; Dou, W. From 2D to 3D NoCs: A case study on worst-case communication performance. In Proceedings of the International Conference Computer-Aided Design, San Jose, CA, USA, 2–5 November 2009; pp. 555–562. [Google Scholar]
  9. Wang, S.; Yin, Y.; Hu, C.; Rezai, P. 3D Integrated Circuit Cooling with Microfluidics. Micromachines 2018, 9, 287. [Google Scholar] [CrossRef] [PubMed] [Green Version]
  10. Chan, J.M.; Lee, K.C.; Tan, C.S. Effects of Copper Migration on the Reliability of Through-Silicon Via (TSV). IEEE Trans. Device Mater. Reliab. 2018, 18, 520–528. [Google Scholar] [CrossRef]
  11. Lu, Q.; Zhu, Z.; Yang, Y.; Ding, R. Electrical Modeling and Characterization of Shield Differential Through-Silicon Vias. IEEE Trans. Electron Devices 2015, 62, 1544–1552. [Google Scholar]
  12. Salvi, S.S.; Jain, A. A Review of Recent Research on Heat Transfer in Three-Dimensional Integrated Circuits (3D ICs). IEEE Trans. Compon. Packag. Manuf. Technol. 2021, 11, 802–821. [Google Scholar] [CrossRef]
  13. Ren, Z.; Alqahtani, A.; Bagherzadeh, N.; Lee, J. Thermal TSV Optimization and Hierarchical Floorplanning for 3D Integrated Circuits. IEEE Trans. Compon. Packag. Manuf. Technol. 2020, 4, 599–610. [Google Scholar] [CrossRef]
  14. Lu, T.; Zhang, F.; Jin, J.M. Multiphysics Simulation of 3-D ICs With Integrated Microchannel Cooling. IEEE Trans. Compon. Packag. Manuf. Technol. 2016, 6, 1620–1629. [Google Scholar] [CrossRef]
  15. Alqahtani, A.; Ren, Z.; Lee, J.; Bagherzadeh, N. System-Level Analysis of 3D ICs with Thermal TSVs. ACM J. Emerg. Technol. Comput. Syst. 2018, 14, 37. [Google Scholar] [CrossRef]
  16. Ren, Z.; Yu, Z.; Kim, J.C.; Lee, J. TSV-integrated thermoelectric cooling by holey silicon for hot spot thermal management. Nanotechnology 2018, 30, 035201. [Google Scholar] [CrossRef]
  17. Pi, Y.; Wang, N.; Chen, J.; Miao, M.; Jin, Y.; Wang, W. Anisotropic equivalent thermal conductivity model for efficient and accurate full-chip-scale numerical simulation of 3D stacked IC. Int. J. Heat Mass Transf. 2018, 120, 361–378. [Google Scholar] [CrossRef]
  18. Sridhar, A.; Vincenzi, A.; Ruggiero, M.; Brunschwiler, T.; Atienza, D. 3D-ICE: Fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling. In Proceedings of the 2010 International Conference Computer-Aided Design (ICCAD), San Jose, CA, USA, 7–11 November 2010; pp. 463–470. [Google Scholar]
  19. Hu, X.; Ma, S.; Gong, D.; Wang, M.; Jin, Y.; Wang, W.; Chen, J.; He, S.; Hu, L.; Zhou, B. Thermal resistance analysis for a high power 3D integrated RF Module based on TSV interposer. In Proceedings of the 21st Electronics Packaging Technology Conference (EPTC 2019), Singapore, 4–6 December 2019. [Google Scholar]
  20. Xiao, C.; He, H.; Li, J.; Cao, S.; Zhu, W. An effective and efficient numerical method for thermal management in 3D stacked integrated circuits. Appl. Therm. Eng. 2017, 121, 200–209. [Google Scholar] [CrossRef]
  21. Chien, H.C.; Lau, J.H.; Chao, Y.L.; Tain, R.M.; Dai, M.J.; Wu, S.T.; Lo, W.O.; Kao, M.J. Thermal performance of 3D IC integration with Through-Silicon Via (TSV). In Proceedings of the International Symposium on Microelectronics 2011, Long Beach, CA, USA, 9–13 October 2011; Volume 1, pp. 25–32. [Google Scholar]
  22. Min, Q.; Li, E.P.; Jin, J.M.; Chen, W. Electrical–Thermal Cosimulation of Coaxial TSVs With Temperature-Dependent MOS Effect Using Equivalent Circuit Models. IEEE Trans. Electromagn. Compat. 2020, 62, 2247–2256. [Google Scholar] [CrossRef]
  23. Feng, Q.; Min, T.; Fu, G.; Mao, J. Fast transient thermal simulation of 2.5-D packages on through silicon via interposer. In Proceedings of the 2016 IEEE 20th Workshop on Signal and Power Integrity (SPI), Turin, Italy, 8–11 May 2016; pp. 1–4. [Google Scholar]
  24. Lau, J.H.; Yue, T.G. Thermal management of 3D IC integration with TSV (through silicon via). In Proceedings of the 2009 59th Electronic Components and Technology Conference, San Diego, CA, USA, 26–29 May 2009; pp. 635–640. [Google Scholar]
  25. Chien, H.C.; Lau, J.H.; Chao, Y.L.; Dai, M.J.; Brillhart, M. Thermal evaluation and analyses of 3D IC integration SiP with TSVs for network system applications. In Proceedings of the Electronic Components & Technology Conference, San Diego, CA, USA, 29 May–1 June 2012; pp. 1866–1873. [Google Scholar]
  26. Chen, Z.; Luo, X.; Liu, S. Thermal analysis of 3D packaging with a simplified thermal resistance network model and finite element simulation. In Proceedings of the 11th International Conference on Electronic Packaging Technology and High Density Packaging, Xi’an, China, 16–19 August 2010; pp. 737–741. [Google Scholar]
  27. Han, L.; Tong, Z. A thermal resistance network model based on three-dimensional structure. Measurement 2019, 133, 439–443. [Google Scholar] [CrossRef]
  28. Petrosyants, K.O.; Ryabov, N.I. Quasi-3D Thermal Simulation of Integrated Circuit Systems in Packages. Energies 2020, 13, 3054. [Google Scholar] [CrossRef]
  29. Wu, M.L.; Lan, J.S. Analytical and finite element methodology modeling of the thermal management of 3D IC with through silicon via. Solder. Surf. Mt. Technol. 2016, 28, 177–187. [Google Scholar] [CrossRef]
  30. Kai, F.; Zhao, W.S.; Wang, G.; Swaminathan, M. Modeling and Performance Analysis of Shielded Differential Annular Through-Silicon Via (SD-ATSV) for 3-D ICs. IEEE Access 2018, 6, 33238–33250. [Google Scholar]
  31. Zhao, W.S.; Hu, Q.H.; Fu, K.; Zhang, Y.Y.; Wang, G. Modeling of Carbon Nanotube-Based Differential Through-Silicon Vias in 3-D ICs. IEEE Trans. Nanotechnol. 2020, 19, 492–499. [Google Scholar] [CrossRef]
  32. Liao, C.; Zhu, Z.; Lu, Q.; Liu, X.; Yang, Y. Wideband Electromagnetic Model and Analysis of Shielded-Pair Through-Silicon Vias. IEEE Trans. Compon. Packag. Manuf. Technol. 2018, 8, 473–481. [Google Scholar] [CrossRef]
  33. Wei, H.; Wu, T.F.; Sekar, D.; Cronquist, B.; Pease, R.F.; Mitra, S. Cooling three-dimensional integrated circuits using power delivery networks. In Proceedings of the International Electron Devices Meeting. Technical Digest, San Francisco, CA, USA, 10–13 December 2012; pp. 14.2.1–14.2.4. [Google Scholar]
  34. Zhu, W.; Dong, G.; Yang, Y. Thermal-Aware Modeling and Analysis for a Power Distribution Network Including Through-Silicon-Vias in 3-D ICs. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 2019, 38, 1278–1290. [Google Scholar] [CrossRef]
  35. Liu, Z.; Swarup, S.; Tan, S.X.D.; Chen, H.B.; Wang, H. Compact Lateral Thermal Resistance Model of TSVs for Fast Finite-Difference Based Thermal Analysis of 3-D Stacked ICs. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 2014, 33, 1490–1502. [Google Scholar] [CrossRef]
  36. Wang, J.; Carson, J.K.; North, M.F.; Cleland, D.J. A new approach to modelling the effective thermal conductivity of heterogeneous materials. Int. J. Heat Mass Transf. 2006, 49, 3075–3083. [Google Scholar] [CrossRef]
  37. Jain, A.; Jones, R.E.; Chatterjee, R.; Pozder, S.; Huang, Z. Thermal modeling and design of 3D integrated circuits. In Proceedings of the 2008 11th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, Orlando, FL, USA, 28–31 May 2008; pp. 1139–1145. [Google Scholar]
Figure 1. Shield differential through-silicon via.
Figure 1. Shield differential through-silicon via.
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Figure 2. Shield differential through-silicon via in (a) case 1; (b) case 2.
Figure 2. Shield differential through-silicon via in (a) case 1; (b) case 2.
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Figure 3. Stereogram of SDTSV for thermal conductivity verification in (a) horizontal direction and (b) vertical direction.
Figure 3. Stereogram of SDTSV for thermal conductivity verification in (a) horizontal direction and (b) vertical direction.
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Figure 4. Comparison between the proposed model and COMSOL.
Figure 4. Comparison between the proposed model and COMSOL.
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Figure 5. The 3D temperature distributions of SDTSV obtained by: (a) COMSOL and (b) the proposed model.
Figure 5. The 3D temperature distributions of SDTSV obtained by: (a) COMSOL and (b) the proposed model.
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Figure 6. Isotherms of SDTSV obtained by: (a) COMSOL and (b) the proposed model.
Figure 6. Isotherms of SDTSV obtained by: (a) COMSOL and (b) the proposed model.
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Figure 7. Effects of different parameters on equivalent thermal conductivity in (a) x-direction; (b) y-direction; (c) z-direction.
Figure 7. Effects of different parameters on equivalent thermal conductivity in (a) x-direction; (b) y-direction; (c) z-direction.
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Figure 8. Effects of different parameters on the thermal distribution in (a) x-direction; (b) y-direction; and (c) z-direction.
Figure 8. Effects of different parameters on the thermal distribution in (a) x-direction; (b) y-direction; and (c) z-direction.
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Figure 9. The 4 × 4 SDTSV array.
Figure 9. The 4 × 4 SDTSV array.
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Figure 10. Temperature distribution of 4×4 SDTSV array obtained by COMSOL when the rotation is equal to (a) 0°; (b) 45°; and (c) 90°.
Figure 10. Temperature distribution of 4×4 SDTSV array obtained by COMSOL when the rotation is equal to (a) 0°; (b) 45°; and (c) 90°.
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Figure 11. Temperature distribution of 4×4 SDTSV array obtained by the proposed model when the rotation is equal to (a) 0°; (b) 45°; and (c) 90°.
Figure 11. Temperature distribution of 4×4 SDTSV array obtained by the proposed model when the rotation is equal to (a) 0°; (b) 45°; and (c) 90°.
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Table 1. Main structure parameters of SDTSV.
Table 1. Main structure parameters of SDTSV.
SymbolDefinition
h T S V the height of TSV
ppitch between two inner signal TSVs
t o x oxide thickness
r 1 outer oxide radius of the shielding shell
r 2 outer metal radius of the shielding shell (=r1 − tox)
r 3 inner metal radius of the shielding shell
r 4 inner oxide radius of the shielding shell (=r3 − tox)
r 5 oxide radius of the TSV
r 6 metal radius of the TSV (=r5 − tox)
K s i the thermal conductivity of Si
K S i O 2 the thermal conductivity of SiO2
K C u the thermal conductivity of Cu
athe width of SDTSV cell
bthe length of SDTSV cell
Table 2. Model parameters.
Table 2. Model parameters.
SymbolDefinitionValue
h T S V the height of TSV100 μm
t o x oxide thickness0.2 μm
r 1 outer oxide radius of the shielding shell10.2 μm
r 2 outer metal radius of the shielding shell(=r1−tox)10 μm
r 3 nner metal radius of the shielding shell60 μm
r 4 inner oxide radius of the shielding shell(=r3−tox)59.8 μm
r 5 oxide radius of the TSV65.2 μm
r 6 metal radius of the TSV (=r5−tox)65 μm
K s i the thermal conductivity of Si150   K / ( W · m )
K S i O 2 the thermal conductivity of SiO21.38   K / ( W · m )
K C u the thermal conductivity of Cu400   K / ( W · m )
athe width of SDTSV cell200 μm
bthe length of SDTSV cell200 μm
Table 3. Error and run-time of different models.
Table 3. Error and run-time of different models.
ModelMax. Temperature (°C)Av. ErrorAv. Time (s)
Pitch (μm)2530354045505560--
Proposed method β = 0 °24.83 24.73 24.63 24.54 24.45 24.36 24.28 24.19 1.37%1.92
β = 45 ° 25.41 25.41 25.41 25.41 25.41 25.41 25.41 25.40 3.42%1.89
β = 90 ° 25.40 25.29 25.18 25.08 24.99 24.89 24.80 24.71 1.76%1.87
Qz21.81 21.81 21.81 21.81 21.81 21.81 21.81 21.81 0.40%1.96
COMSOL β = 0 ° 24.5624.5624.5624.5624.5624.5724.5724.57-297
β = 45 ° 24.57 24.57 24.57 24.57 24.57 24.57 24.57 24.57 -287
β = 90 ° 24.5724.5724.5724.5724.5724.5724.5724.57-293
Qz21.9021.9021.9021.9021.9021.9021.9021.90-306
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Shan, G.; Li, G.; Chen, D.; Yang, Z.; Li, D.; Yang, Y. An Anisotropic Equivalent Thermal Model for Shield Differential Through-Silicon Vias. Micromachines 2021, 12, 1223. https://doi.org/10.3390/mi12101223

AMA Style

Shan G, Li G, Chen D, Yang Z, Li D, Yang Y. An Anisotropic Equivalent Thermal Model for Shield Differential Through-Silicon Vias. Micromachines. 2021; 12(10):1223. https://doi.org/10.3390/mi12101223

Chicago/Turabian Style

Shan, Guangbao, Guoliang Li, Dongdong Chen, Zifeng Yang, Di Li, and Yintang Yang. 2021. "An Anisotropic Equivalent Thermal Model for Shield Differential Through-Silicon Vias" Micromachines 12, no. 10: 1223. https://doi.org/10.3390/mi12101223

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