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Article

High Step-Up Converter Based on Non-Series Energy Transfer Structure for Renewable Power Applications

by
Luis Humberto Diaz-Saldierna
* and
Jesus Leyva-Ramos
Instituto Potosino de Investigación Científica y Tecnológica, Camino a la Presa San José No. 2055, San Luis Potosí 78216, Mexico
*
Author to whom correspondence should be addressed.
Micromachines 2021, 12(6), 689; https://doi.org/10.3390/mi12060689
Submission received: 26 May 2021 / Revised: 7 June 2021 / Accepted: 10 June 2021 / Published: 13 June 2021

Abstract

:
In this paper, a high step-up boost converter with a non-isolated configuration is proposed. This configuration has a quadratic voltage gain, suitable for processing energy from alternative sources. It consists of two boost converters, including a transfer capacitor connected in a non-series power transfer structure between input and output. High power efficiencies are achieved with this arrangement. Additionally, the converter has a common ground and non-pulsating input current. Design conditions and power efficiency analysis are developed. Bilinear and linear models are derived for control purposes. Experimental verification with a laboratory prototype of 500 W is provided. The proposed configuration and similar quadratic configurations are compared experimentally using the same number of components to demonstrate the power efficiency improvement. The resulting power efficiency of the prototype was above 95% at nominal load.

1. Introduction

Nowadays, the even increase in energy consumption and the worldwide concern about environmental issues have led to increase the power generation through renewable sources, like photovoltaic and fuel-cell sources [1,2]. The output voltage of these alternative sources is low and unregulated [3,4]; therefore, an interface with DC-DC power converters is needed to obtain a high and regulated output voltage. [5]. On the other hand, these energy sources can suffer permanent damage if high ripples appear in the demanded current [6,7]. According to the above, DC-DC switching power converters for renewable applications should have high-voltage gains, low-input current ripples and high-power efficiencies [8].
The conventional boost converter has been proposed for renewable applications [9,10]; however, larger duty cycles are required to achieve high voltage gains. The above produces large voltage spikes, diode reverse recovery time problems, and high conduction losses on the active switch due to the intrinsic resistances [11,12].
In the open literature, several configurations are available to further extend the voltage gain without large duty cycles. A boost converter with a quadratic conversion ratio is discussed in [13]. This configuration is based on stackable switching cells with a modular structure that can be extended to boost the output voltage. This converter exhibits a pulsating input current; therefore, a coupled capacitor is needed for renewable energy applications [14]. A quadratic boost converter with two conventional boost converters connected in series (QBC-SC) is proposed in [15]. The power flows in cascade from the input source to the first converter; then, the power flows to the second converter and later to the load.
The quadratic relationship of the conversion ratio provides a high-voltage gain for this configuration. A quadratic boost converter with a single switch (QBC-SS) is disscused in [16]. It is similar to the QBC-SC, the power flows in series through the two converters and load; however, it includes only one switch. A QBC-SS that includes a voltage doubler to achieve an extra voltage gain (QBC-TR) is proposed in [17]. It includes a voltage doubler to achieve an extra voltage gain. The voltage doubler consists of two capacitors, two diodes, and a coupled inductor that provides an additional gain respect to the quadratic conversion ratio. A current-fed boost converter with a quadratic voltage gain (QBC-CF) is proposed in [18]. This converter has two operation modes. Energy from the input source is stored in two inductors; after that, the energy is transfer to two output capacitors. The quadratic gain is obtained by a series arrangement of capacitors, where the output voltage is the sum of both capacitor voltages. The number of diodes and the way to charge both inductors have an impact on the power efficiency. A boost converter with an active switched inductor-capacitor (LC) network is proposed in [19]. The configuration consists of two inductors that are charged in parallel across two active switches, one diode, and one capacitor. This configuration uses a non-common grounding. The energy stored in both inductors is transferred in series to the output capacitor and the load. The structure of this configuration allows an enlargement of the conversion ratio respect to the gain of the quadratic boost converter. On the other hand, a coupling capacitor needs to be connected to the input of the converter because the input current has a pulsating waveform. Two boost configurations based on the quadratic and Cuk converters are shown in [20]. These configurations offer an extra voltage gain by adding a factor increment to the quadratic voltage gain. They are classified into two types, depending on the voltage gain of each configuration. Both converters have non-common grounding. An isolated boost converter that includes forward and flyback configurations is proposed in [21]. This converter is based on a quadratic configuration with an extended voltage gain because of the turns ratio of the transformer; however, the input current has a pulsating waveform.
The quadratic boost converter is a feasible option for processing energy generated by renewable sources, because it has a higher voltage conversion ratio. Quadratic conversion ratios can achieve higher voltage gains with duty cycles less than 0.7. This configuration generates a non-pulsating input current, which is critical for renewable sources as fuel and photovoltaic cells. The circuit of the conventional quadratic boost converter (QBC-SC) is depicted in Figure 1.
A major drawback of the conventional quadratic configuration is the series power transfer between the input source and the load, resulting in a low overall efficiency. The above implies a reprocessing of the energy generated by the source; thus, a slow energy propagation between the input of the converter and the load is obtained. On the other hand, energy reprocessing yields an increment on the power losses due to the parasitics of the converter elements. This issue is described in Figure 2, where the power is transferred throughout the two boost converters of the QBC-SC. As can be seen, the power flow is done in series between the input source and the load, where the capacitor C 1 acts as the input source of the second converter.
A boost converter with a quadratic voltage gain, common ground, and non-series power transfer for better efficiency is proposed in this work. This configuration consists of two conventional boost converters with a transfer capacitor between both converters. This capacitor allows a parallel energy transfer between both converters and the output. The main advantage is an increase in power efficiency due to the non-series power transfer. Moreover, this configuration can be used for processing energy from alternative sources without the need to add a filter for reducing the input current ripple.
The organization of this work is as follows. A description and operation of the proposed configuration are shown in Section 2. The state-steady conditions and the converter design are developed in Section 3. The power efficiency of the proposed configuration is analyzed in Section 4. Bilinear and linear models of the proposed converter are developed in Section 5. Design criteria of the proposed converter are shown in Section 6. Experimental verification with a 500 W laboratory prototype is provided in Section 7. Final remarks are given in Section 8.

2. Converter Operation

The proposed configuration is depicted in Figure 3. The input voltage is represented by E, the currents and voltages through L 1 and L 2 are denoted by i L 1 , v L 1 , i L 2 , and v L 2 , respectively. The voltages and currents through C p , and C 0 are denoted by v C p , i C p , v 0 , and i C 0 , respectively. On the other hand, the voltages through S 1 , D S 1 , S 2 and D S 2 are denoted by v S 1 , v D S 1 , v S 2 , and v D S 2 . Finally, the current through the load R is denoted by I 0 .
The analysis is carried out considering the following points:
  • The study is developed for continuous conduction mode operation (CCM).
  • The passive elements ( L 1 , L 2 , C p , C 0 ), the active switches ( S 1 , S 2 ), and the passive switches ( D S 1 , D S 2 ) are considered as an ideal components.
  • The active switches operate under the same duty cycle D. Thus, D 1 = D 2 = D , f s = 1 / T s is the switching frequency, and T s is the period of the PWM signal that drives the active switches.
  • For steady-state operation, T s = t O N + t O F F , where t O N = D T s and t O F F = ( 1 D ) T s .
Due to the above assumptions, the proposed configuration operates in two modes. The power transfer from the input to the output of the proposed configuration is shown in Figure 4. As can be seen, a non-series power transfer between the input source and the load occurs due to the transfer capacitor C p .
The two operating modes of the converter are described as follows:
Mode I [ t O N ]: Both active switches ( S 1 , S 2 ) are turned ON. The diodes D S 1 and D S 2 are not conducting; then, the input source E delivers energy to the inductor L 1 . The inductor L 2 is charged through capacitor C p by the energy stored in the capacitor C 0 , which also supplies energy to the load. The circuit that describes this operating mode is exhibited in Figure 5.
Mode II [ t O F F ]: Both active switches ( S 1 , S 2 ) are turned OFF. For this interval, the output capacitor C 0 and the load R are supplied by the energy stored in inductor L 1 , through capacitor C p . The inductor L 2 delivers energy to the output ( C 0 and R) through the diode D S 2 . The circuit that describes this operating mode is exhibited in Figure 6.
The analysis, modeling, and the expressions in steady-state are easy to develop in two operating modes. On the other hand, the capacitor C p acts as a power transfer element between the first converter and the output capacitor C 0 . Due to this arrangement, the cascade power transfer between the first and second converter is avoided; thus, there is an improvement in the converter efficiency.

3. Converter Analysis

Figure 7 shows the theoretical waveforms of the proposed configuration. The input converter current i L 1 has a non-pulsating waveform, and its ripple amplitude depends on the inductance value.

3.1. Converter Voltage Gain

Applying the volt-second balance principle to L 1 and L 2 results in:
E D T s + ( E + V C p V 0 ) ( 1 D ) T s = 0 ( V C p + V 0 ) D T s V C p ( 1 D ) T s = 0
By using the last equations, the expression for V C p can be derived:
V C p = V 0 E ( 1 D ) = D V 0
From the above expression, the voltage gain M is:
M = V 0 E = 1 ( 1 D ) 2
According to Equation (3), the voltage gain M has a quadratic conversion ratio.

3.2. Steady-State Conditions

For calculating the inductances L 1 and L 2 , the period when the active switches are turned ON is analyzed, see Figure 5. For large enough inductances, the currents rise linearly from their minimum value to their maximum value during t O N ; then, the voltages in the inductor terminals of L 1 and the inductor terminals of L 2 are, respectively:
V L 1 = L 1 Δ I L 1 t O N = E V L 2 = L 2 Δ I L 2 t O N = V C p + V 0
Substituting t O N = D T s , V C p = D V 0 , and V 0 = E / ( 1 D ) 2 into Equation (4), the expressions for the inductor current ripples are:
Δ i L 1 = E D L 1 f s Δ i L 2 = E D ( 1 D ) L 2 f s
Considering the equality between the input and output power ( E I L 1 = V 0 2 / R ) , the average current through L 1 can be computed. On the other hand, the average current of L 2 can be computed using the relationship I L 2 = ( 1 D ) I L 1 ; then, the corresponding expressions for I L 1 and I L 2 are:
I L 1 = E R ( 1 D ) 4 I L 2 = E R ( 1 D ) 3
The maximum and minimum current values reached by the first and second inductors can be obtained as follows:
I L 1 M A X = I L 1 + Δ I L 1 2 , I L 1 M I N = I L 1 Δ I L 1 2 I L 2 M A X = I L 2 + Δ I L 2 2 , I L 2 M I N = I L 2 Δ I L 2 2
In switching converters, it is essential to find out the critical inductance values for operation in CCM [22]. The critical inductance values of the proposed configuration can be computed using the relationships:
0 = I L 1 Δ I L 1 2 0 = I L 2 Δ I L 2 2
then, the inductances for the CCM operation are:
L 1 > D R ( 1 D ) 4 2 f s L 2 > D R ( 1 D ) 2 2 f s
The charge variation in a capacitor is defined as Δ Q C = C Δ v C , where Δ Q C depicted the area under the current curve when the capacitor stores energy, C denotes the capacitance, and Δ v C is the voltage ripple (see Figure 7). For t O N , the capacitor C p is charged by the current i L 2 ( i L 2 = i C p ). On the other hand, the capacitor C 0 is charged by the current of L 1 at time t O F F . In this interval, the current through C 0 is i C 0 = i L 1 I 0 , that is:
Δ Q C p = t 0 t 1 i L 2 ( t ) d t = C p Δ v C p Δ Q C 0 = t 1 t 2 [ i L 1 ( t ) I 0 ] d t = C 0 Δ v C 0
where t O N = t 1 t 0 and t O F F = t 2 t 1 . Calculating Δ Q C for C p and C 0 , the following expressions for the capacitor ripples are obtained:
Δ v C p = V C p R ( 1 D ) 3 C p f s Δ v 0 = V 0 D ( 2 D ) R ( 1 D ) C 0 f s
According to Equations (5) and (11), the inductor current and capacitor voltage ripples can be chosen for a specific amplitude. Selecting a ripple value is essential, especially in the first inductor current ( Δ i L 1 ). The above is due to the requirements of renewable sources as in fuel and photovoltaic cells, which do not allow high ripples on the demanded currents. Large magnitude of current ripple in high frequency (>10 kHz) cause degradation of the catalyst of fuel cell plates. Moreover, fuel-cell currents should not have a high pulsating either negative profile.

3.3. Stress on Semiconductor Devices

The current stress values on active and passive switches are computed using the Equations (5),(6) and (7). The current stress on S 1 , D S 1 , S 2 , and D S 2 are:
I S 1 = I D S 1 = E [ 2 L 1 f s + D R ( 1 D ) 4 ) ] 2 R ( 1 D ) 4 L 1 f s I S 2 = I D S 2 = E [ 2 L 2 f s + D R ( 1 D ) 2 ) ] 2 R ( 1 D ) 3 L 2 f s
Using the Figure 5, the voltage stress values on active and passive switches are computed as:
V S 1 = V D S 1 = V 0 ( 1 D ) V S 2 = V D S 2 = V 0
The Equation (13) shows that the voltage stress on S 1 and D S 1 increases when the duty cycle is reduced. The stress on S 2 and D S 2 does not depend on the duty cycle.

3.4. Comparison with Other Quadratic Converters

A comparison of the proposed converter with other quadratic configurations described in the Introduction section is now given. The number of components and voltage gains of each converter are shown in Table 1. It can be noticed that, QBC-CS, QBC-SS and the proposed converter consist of only eight components, while QBC-CF includes nine components, and QBC-TR twelve components. Moreover, the voltage gains have the same relationship, with the exception of QBC-TR, which depends on the turns ratio of the transformer n = N 2 / N 1 .

4. Study of the Power Efficiency

Now, the analysis and expressions for computing the power losses of each element for the proposed converter are provided. According to [23], the corresponding circuit including the parasitics of all elements of the configuration is exhibited in Figure 8. The resistances R L 1 , R L 2 , R C p , R C 0 , R D 1 , R D 2 , R O N 1 , and R O N 2 are the equivalent series resistance (ESR) of L 1 , L 2 , C p , C 0 , D S 1 , D S 2 , S 1 , and S 2 , respectively. The voltages V F D S 1 and V F D S 2 are the forward voltage drops of D S 1 , and D S 2 . The gate voltage for S 1 and S 2 is V g . In the interval t O N , both active switches are conducting. The respective circuit for this interval is described in Figure 9. On the other hand, the respective circuit for the interval t O F F (both active switches are not conducting) is depicted in Figure 10.
Using the volt-second balance principle over L 1 and L 2 , two expressions for V C p are derived. From these two expressions, it is possible to find the relationship for computing the duty cycle ( D l o s s ) and the losses of each component of the converter. To precisely quantify the losses associated with the parasitics of the converter, it is necessary to recalculate the duty cycle ( D l o s s > D ). The resulting equation for D l o s s has a fourth-order behavior:
D l o s s 4 + a D l o s s 3 + b D l o s s 2 + c D l o s s + d = 0
where:
a = 4 R V 0 + R V F D S 1 + 4 R V F D S 2 + R D 2 R O N 2 V 0 R V 0 + R V F D S 2 b = 6 R V 0 + 3 R V F D S 1 + 6 R V F D S 2 + 3 R D 2 V 0 + R L 2 V 0 2 R O N 2 V 0 + E R R V 0 + R V F D S 2 c = ( R O N 1 + R O N 2 2 R L 2 4 R R D 1 3 R D 2 ) V 0 + 2 E R 3 R V F D S 1 4 R V F D S 2 R V 0 + R V F D S 2 d = R V 0 + R V F D S 1 + R D 1 V 0 + R V F D S 2 + R D 2 V 0 + R L 1 V 0 + R L 2 V 0 E R R V 0 + R V F D S 2
to obtain the duty cycle D l o s s , it is necessary to solve Equation (14) and choose the adequate root.
The expressions for the power losses of each element are shown in Table 2 (conduction and switching losses are included). The diode junction capacitances of D S 1 and D S 2 are C j _ D S 1 and C j _ D S 2 , respectively. The time intervals are t r r 1 = t r 1 + t O N 1 , t r r 2 = t r 2 + t O N 2 , t f f 1 = t f 1 + t O F F 1 , and t f f 2 = t f 2 + t O F F 2 , where t r 1 , t O N 1 , t r 2 , t O N 2 , t f 1 , t O F F 1 , t f 2 , and t O F F 2 are the rise time, turn ON delay time, fall time, and turn OFF delay time of S 1 , and S 2 , respectively. The input capacitances of S 1 and S 2 are C i s s 1 and C i s s 2 , respectively. The RMS current values can be obtained as:
I L 1 R M S 2 = V 0 2 R 2 ( 1 D l o s s ) 4 , I L 2 R M S 2 = V 0 2 R 2 ( 1 D l o s s ) 2 I S 1 R M S 2 = I L 1 R M S 2 D l o s s , I D 1 R M S 2 = I L 1 R M S 2 ( 1 D l o s s ) I S 2 R M S 2 = I L 2 R M S 2 D l o s s , I D 2 R M S 2 = I L 2 R M S 2 ( 1 D l o s s ) I C P R M S 2 = V 0 D l o s s ( D l o s s 2 D l o s s + 1 ) R 2 ( 1 D l o s s ) 6 I C 0 R M S 2 = V 0 2 D l o s s ( 2 D l o s s ) 2 R 2 ( 1 D l o s s ) 3
The total power loss is:
P T l o s s = P l o s s _ L 1 + P l o s s _ L 2 + P l o s s _ C P + P l o s s _ C 0 + P l o s s _ D 1 + P l o s s _ D 2 + P l o s s _ S 1 + P l o s s _ S 2 + P l o s s _ d v r 1 + P l o s s _ S 2 .
The expression for computing the power efficiency is:
η = P 0 P 0 + P T l o s s
where P 0 is defined as P 0 = V 0 2 / R .

5. Modeling of the Converter

The average modeling is commonly used to describe the behavior of power electronic circuits [24]. The PWM-switch model is a useful technique for describing the electrical behavior of DC-DC power converters.

Nonlinear Average Model of the Converter

The differential equations for each mode can be derived from Figure 5 and Figure 6, respectively. The differential equations for mode I and mode II are :
i ˙ L 1 = 1 L 1 E i ˙ L 2 = 1 L 2 v C p + v 0 v ˙ C p = 1 v C p i L 2 v ˙ C 0 = 1 C 0 i L 2 v 0 R
i ˙ L 1 = 1 L 1 v C p v 0 + E i ˙ L 2 = 1 L 2 v C p + v 0 v ˙ C p = 1 v C p i L 2 v ˙ C 0 = 1 C 0 i L 2 v 0 R
By using the switching function as a weighting factor, the average non-linear model can be derived as:
i ˙ L 1 i ˙ L 2 v ˙ C p v ˙ C 0 = 0 0 ( 1 d ) L 1 ( 1 d ) L 1 0 0 1 L 2 d L 2 ( 1 d ) C p 1 C p 0 0 ( 1 d ) C 0 d C 0 0 1 R C 0 i L 1 i L 2 v C p v C 0 + 1 L 1 0 0 0 e
The above description can be generalized as:
x ˙ ( t ) = A ( d ) x + B ( d ) e
where the state vector is x ( t ) = [ i L 1 , i L 2 , v C p , v 0 ] R + 4 , the control signal d ( 0 , 1 ) , and the input voltage e R . The model described in (19) is bilinear, since the signal d is multiplying to all state variables.
Linealization of non-linear systems is a useful technique for analyzing and controlling complex high-order dynamical systems. This process describes the converter behaviour to small perturbations around an operation point, where the perturbations are applied to the input signals [25].
According to above, each state variable and the input signal are the sum of DC and AC components, which can be decomposed as:
i L 1 = I L 1 + i ˜ L 1 i L 2 = I L 2 + i ˜ L 2 v C p = V C p + v ˜ C 1 v C 0 = V C 0 + v ˜ C 0 d = D + d ˜ e = E + e ˜
where I L 1 , I L 2 , V C p , V C 0 , D, E represent the DC components, and i ˜ L 1 , i ˜ L 2 , v ˜ C p , v ˜ C 0 , d ˜ , e ˜ are the AC components. In steady state, the AC components are equal to zero.
Linearizing around an equilibrium point
ε : = ( I L 1 , I L 2 , V C p , V C 0 ) R + 4
The linear representation of the systems shown in (19) can be rewritten as:
x ˜ ˙ = A x ˜ + B u ˜
where x ˜ R + 4 is the state vector, and u ˜ = [ d ˜ , e ˜ ] R + 2 is the vector with inputs. A is a constant matrix in R 4 X 4 , and B is a constant matrix in R 4 X 2 . The average linear time-invariant model is:
i ˜ ˙ L 1 i ˜ ˙ L 2 v ˜ ˙ C p v ˜ ˙ C 0 = 0 0 ( 1 D ) L 1 ( 1 D ) L 1 0 0 1 L 2 D L 2 ( 1 D ) C p 1 C p 0 0 ( 1 D ) C 0 d C 0 0 1 R C 0 i ˜ L 1 i ˜ L 2 v ˜ C p v ˜ C 0 + E L 1 ( 1 D ) 1 L 1 E L 2 ( 1 D ) 2 0 E R C p ( 1 D ) 4 0 E ( 2 D ) R C 0 ( 1 D ) 4 0 d ˜ e ˜

6. Converter Design

Now, the design of a 500 W power converter using the procedure shown in Section 3 is now described. The input voltage E is 30 V, the output voltage V 0 is set to 220 V, and the load R is 96.8 Ω . A switching frequency of f s = 100 kHz is selected with an ideal duty cycle of D = 0.63 . The selection criterion of the switching frequency was made based on the sizing of the passive elements, which increase in value with low switching frequencies. Due to the above, the power efficiency decreases when high inductance and capacitance values are selected. On the other hand, generally the value of the switching frequency used for medium and high power DC-DC converters ranges from 25 kHz to 100 kHz. The corresponding parameters for the designed converter are shown in Table 3.
The theoretical power efficiency at the nominal load of the proposed configuration is 95.4%, which was obtained using (14)–(16). The parameters of Table 2 were computed using the datasheet of the semiconductor devices used used to build the prototypes. The ESR values of the two inductors and two capacitors were measured using the meter model LCR-821 from GW Insteak. The theoretical duty cycle, including the power losses, is D l o s s = 0.635 .
Figure 11 shows a comparison between the ideal gain obtained with expression (3) and the gain given in expression (14), where all losses are included. It can be observed that both plots are similar until the duty cycle reaches 0.8; after that, the non-idealities produce a difference as shown in the plot.

7. Experimental Verification

Experimental verification with a 500 W laboratory prototype is provided in this section. The prototype was designed according to the parameters given in Table 3, and it is shown in Figure 12. The prototype for QBC-SC and QBC-SS converter is shown in Figure 13. Both converters were built in the same prototype, only one switch was replaced by a diode and vice versa.
The experimental set-up of the converter is described in Figure 14. The relationship of the voltage gain ( V 0 /E) is 220 V/30 V, and the peak value of the ramp signal is 5 V. Additionally, QBC-SC (Figure 15) and QBC-SS (Figure 16) prototypes were built to compare the experimental power efficiencies of the three configurations.
For a fair comparison, all converters were built using the same components. For the QBC-SS, the active switch S 1 was replaced by the Schottky diode DSA90C200HB.
The parameters of the QBC-SC and the QBC-SS are shown in Table 4. The parameters were obtained by using the expressions developed in [26]. The theoretical and experimental plots for the comparison of efficiencies are shown in Figure 17. The teoretical plot was obtained using the Equations (14)–(16), while the experimental plots of the three converter were obtained for a voltage gain of 220 V/30 V, and varying the load from 484 Ω (100 W) to 96.8 Ω (500 W), with steps of 100 W. The voltage and current values were obtained using the osciloscopie model MDO3034 and the current probe model TCP303 from Tektronix. As can be seen, the theoretical and experimental plots for the proposed converter are similar, only with small variations. The experimental efficiency of the proposed converter ranges from 97.8% (20% of nominal load) to 95.1% (nominal load). It can be noticed that the proposed configuration offers an improvement in the power efficiency due to the non-series power transfer. One part of the energy processed by the first converter flows directly to the output through the transfer capacitor without being reprocessed by the second converter. A pie chart of breakdown losses for nominal load is shown in Figure 18. It is clear that the biggest losses are in the diodes and inductors, while the switch losses are not significant due to the low ESR value of both switches.
The inductor and output currents of the prototype are exhibited in Figure 19. The average value of i L 1 is 17.5 A, the average value of i L 2 is 6.3 A, and for I 0 is 2.7 A. In Figure 20, the input and capacitors voltages are exhibited The value of E is 30 V, the average transfer capacitor voltage V C p is 139 V, while the average output capacitor voltage V 0 is 220 V.
The voltage waveforms in the active switch S 1 and the diode D S 1 are exhibited in Figure 21. The voltage stress on S 1 and D S 1 is 98 V. The voltage waveforms in the active switch S 2 and the diode D S 2 are exhibited in Figure 22, where the voltage stress on S 2 and D S 2 is 222 V.
Voltage and current ripples of the prototype are exhibited in Figure 23. The value of Δ v 0 is 2.8 V (1.30%), the value of Δ v C p is 2.2 V (1.60%), the value of Δ i L 2 is 1.7 A (27%), and the value of Δ i L 1 is 3 A (17.1%).

8. Concluding Remarks

A step-up configuration with a quadratic conversion ratio and a non-series power transfer is proposed in this work. It consists of two conventional boost converters, with two active switches operating with the same duty cycle. This configuration uses a transfer capacitor to avoid reprocessing power between both converters. The proposed configuration can be used for processing energy from renewable generation systems, due to the wide voltage conversion ratio, non-pulsating input current, and higher efficiency compared to other quadratic configurations. The steady-state values and power efficiency analysis are derived for design purposes. A power converter with 220 V output voltage @ 500 W is designed using the procedure given in this work. Experimental validation with a laboratory prototype is exhibited to prove the theoretical results given within. By comparing the experimental power efficiency with the QBC-SC, and the QBC-SS shows that the proposed configuration offers an improvement in the power efficiency. The average linear time-invariant model is derived. This model is a useful tool for control purposes due to the transfer functions of all state variables can be obtained. An appropriate control technique for controlling the proposed converter is the average current-mode control, which consists of two feedback loops (inner and outer). The inner loop uses the inductor current, while the outer loop uses the output voltage for regulation purposes. This configuration can be constructed using a single active switch; however, there is a reduction in the power efficiency.

Author Contributions

Conceptualization, L.H.D.-S. and J.L.-R.; methodology, L.H.D.-S.; software, L.H.D.-S.; validation, L.H.D.-S. and J.L.-R.; formal analysis, J.L.-R.; investigation, L.H.D.-S. and J.L.-R.; writing—original draft preparation, L.H.D.-S.; writing—review and editing, J.L.-R.; visualization, L.H.D.-S.; supervision, J.L.-R.; project administration, J.L.-R.; funding acquisition, J.L.-R. All authors have read and agreed to the published version of the manuscript.

Funding

This research received funding from the Consejo Nacional de Ciencia y Tecnología (CONACyT).

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. Quadratic boost converter with series power transfer.
Figure 1. Quadratic boost converter with series power transfer.
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Figure 2. Power flows of the QBC-SC: (a) Equivalent scheme when both inductor are storing energy, and (b) equivalent scheme when both inductor are delivering energy.
Figure 2. Power flows of the QBC-SC: (a) Equivalent scheme when both inductor are storing energy, and (b) equivalent scheme when both inductor are delivering energy.
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Figure 3. Quadratic boost converter with non-series power transfer.
Figure 3. Quadratic boost converter with non-series power transfer.
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Figure 4. Power flows of the proposed configuration: (a) Equivalent scheme when both inductor are storing energy, and (b) equivalent scheme when both inductors are delivering energy.
Figure 4. Power flows of the proposed configuration: (a) Equivalent scheme when both inductor are storing energy, and (b) equivalent scheme when both inductors are delivering energy.
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Figure 5. Circuit for the intervale t O N .
Figure 5. Circuit for the intervale t O N .
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Figure 6. Circuit for the interval t O F F .
Figure 6. Circuit for the interval t O F F .
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Figure 7. Current and voltage waveforms of the converter in the time T s .
Figure 7. Current and voltage waveforms of the converter in the time T s .
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Figure 8. Equivalent circuit with the parasitics of elements.
Figure 8. Equivalent circuit with the parasitics of elements.
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Figure 9. Equivalent circuit for the interval t O N .
Figure 9. Equivalent circuit for the interval t O N .
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Figure 10. Equivalent circuit for the interval t O F F .
Figure 10. Equivalent circuit for the interval t O F F .
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Figure 11. Comparison between the ideal gain and the gain including the power losses.
Figure 11. Comparison between the ideal gain and the gain including the power losses.
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Figure 12. Laboratory prototype of the proposed converter.
Figure 12. Laboratory prototype of the proposed converter.
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Figure 13. Laboratory prototype of the QBC-SC and QBC-SS converters.
Figure 13. Laboratory prototype of the QBC-SC and QBC-SS converters.
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Figure 14. Experimental schematic for the proposed converter.
Figure 14. Experimental schematic for the proposed converter.
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Figure 15. Circuit of the QBC-SC prototype for the experimental efficiency comparison with the proposed converter.
Figure 15. Circuit of the QBC-SC prototype for the experimental efficiency comparison with the proposed converter.
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Figure 16. Circuit of the QBC-SS prototype for the experimental efficiency comparison with the proposed converter.
Figure 16. Circuit of the QBC-SS prototype for the experimental efficiency comparison with the proposed converter.
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Figure 17. Comparison of power efficiencies. (From top to bottom) (a) Proposed converter, (b) theoretical efficiency, (c) QBC-SC, and (d) QBC-SS.
Figure 17. Comparison of power efficiencies. (From top to bottom) (a) Proposed converter, (b) theoretical efficiency, (c) QBC-SC, and (d) QBC-SS.
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Figure 18. Pie chart of loss breakdown at nominal load.
Figure 18. Pie chart of loss breakdown at nominal load.
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Figure 19. Current waveforms of the prototype. (From top to bottom) Load current I 0 (1 A/div), second inductor current i L 2 (5 A/div), and first inductor current i L 1 (10 A/div) (10 μ s/div).
Figure 19. Current waveforms of the prototype. (From top to bottom) Load current I 0 (1 A/div), second inductor current i L 2 (5 A/div), and first inductor current i L 1 (10 A/div) (10 μ s/div).
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Figure 20. Voltage waveforms of the prototype. (From top to bottom) Output capacitor voltage v 0 (100 V/div), transfer capacitor voltage v C p (100 V/div), and input voltage E (20 V/div) (10 μ s/div).
Figure 20. Voltage waveforms of the prototype. (From top to bottom) Output capacitor voltage v 0 (100 V/div), transfer capacitor voltage v C p (100 V/div), and input voltage E (20 V/div) (10 μ s/div).
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Figure 21. Voltage waveforms in the input of converter. (From top to bottom) Voltage waveforms in D S 1 (50 V/div) and S 1 (50 V/div) (10 μ s/div).
Figure 21. Voltage waveforms in the input of converter. (From top to bottom) Voltage waveforms in D S 1 (50 V/div) and S 1 (50 V/div) (10 μ s/div).
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Figure 22. Voltage waveforms in the output of converter. (From top to bottom) Voltage waveforms in D S 2 (100 V/div) and S 2 (100 V/div) (10 μ s/div).
Figure 22. Voltage waveforms in the output of converter. (From top to bottom) Voltage waveforms in D S 2 (100 V/div) and S 2 (100 V/div) (10 μ s/div).
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Figure 23. Voltage and current ripples of the prototype. (From top to bottom) Output capacitor ripple Δ v 0 (5 V/div), transfer capacitor ripple Δ v C p (5 V/div), second inductor ripple Δ i L 2 (2.5 A/div) and first inductor ripple Δ i L 1 (5 A/div) (10 μ s/div).
Figure 23. Voltage and current ripples of the prototype. (From top to bottom) Output capacitor ripple Δ v 0 (5 V/div), transfer capacitor ripple Δ v C p (5 V/div), second inductor ripple Δ i L 2 (2.5 A/div) and first inductor ripple Δ i L 1 (5 A/div) (10 μ s/div).
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Table 1. Comparison of the proposed converter with other quadratic configurations.
Table 1. Comparison of the proposed converter with other quadratic configurations.
ComponentsProposed ConverterQBC-CS
Ref. [15]
QBC-SS
Ref. [16]
QBC-CF
Ref. [17]
QBC-TR
Ref. [18]
Capacitors22242
Inductors22212
Diodes22354
Switches22111
Transformers00 0 1 0
Gain (CCM) 1 ( 1 D ) 2 1 ( 1 D ) 2 1 ( 1 D ) 2 1 + n ( 1 D ) 2 1 ( 1 D ) 2
Table 2. Power losses calculation.
Table 2. Power losses calculation.
Inductors P l o s s _ L 1 = I L 1 R M S 2 R L 1
P l o s s _ L 2 = I L 2 R M S 2 R L 2
Capacitors P l o s s _ C P = I C P R M S 2 R C P
P l o s s _ C 0 = I C 0 R M S 2 R C 0
Diodes P l o s s _ D 1 = I D 1 R M S 2 R D 1 + I L 1 V F D 1 + 1 2 C j _ D 1 V S 1
P l o s s _ D 2 = I D 2 R M S 2 R D 2 + I L 2 V F D 2 + 1 2 C j _ D 2 V S 2
Switches P l o s s _ S 1 = I S 1 R M S 2 R O N 1 + 1 2 ( t r r 2 + t f f 2 ) I L 2 V S 2
P l o s s _ S 2 = I S 2 R M S 2 R O N 2 + 1 2 ( t r r 2 + t f f 2 ) I L 2 V S 2
Drivers P l o s s _ d v r 1 = 1 2 C i s s 1 V g 2 f s
P l o s s _ d v r 2 = 1 2 C i s s 2 V g 2 f s
Table 3. Parameters of the proposed converter.
Table 3. Parameters of the proposed converter.
L 1 = 90 μ H L 2 = 330 μ H C p = 20 μ F C 0 = 20 μ F
I L 1 = 16.6 A I L 2 = 6.1 A V C p = 138 V V 0 = 220 V
Δ i L 1 = 2 A Δ i L 2 = 1.5 A Δ v C p = 2 V Δ v 0 = 2.6 V
r I = 12.6 % r I = 25.2 % r V = 1.4 % r V = 1.2 %
where rI = 100 × (∆IL/IL) and rV = 100 × (∆VC/VC).
Table 4. Parameters of the QBC-SC and QBC-SS converters.
Table 4. Parameters of the QBC-SC and QBC-SS converters.
L 1 = 90 μ H L 2 = 330 μ H C 1 = 20 μ F C 0 = 20 μ F
I L 1 = 16.6 A I L 2 = 6.1 A V C p = 81 V V 0 = 220 V
Δ i L 1 = 2 A Δ i L 2 = 1.5 A Δ v C p = 2 V Δ v 0 = 0.7 V
r I = 12.6 % r I = 25.2 % r V = 2.4 % r V = 0.3 %
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Diaz-Saldierna, L.H.; Leyva-Ramos, J. High Step-Up Converter Based on Non-Series Energy Transfer Structure for Renewable Power Applications. Micromachines 2021, 12, 689. https://doi.org/10.3390/mi12060689

AMA Style

Diaz-Saldierna LH, Leyva-Ramos J. High Step-Up Converter Based on Non-Series Energy Transfer Structure for Renewable Power Applications. Micromachines. 2021; 12(6):689. https://doi.org/10.3390/mi12060689

Chicago/Turabian Style

Diaz-Saldierna, Luis Humberto, and Jesus Leyva-Ramos. 2021. "High Step-Up Converter Based on Non-Series Energy Transfer Structure for Renewable Power Applications" Micromachines 12, no. 6: 689. https://doi.org/10.3390/mi12060689

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