1. Introduction
Transformerless photovoltaic (PV) systems have increased their popularity due to their high performance in terms of efficiency, size, and price. Nevertheless, the loss of galvanic isolation involves other challenges, for instance, reducing or eliminating leakage currents (LKC) that appear in the ground path.
In three-phase transformerless PV systems, conventional topologies such as the six-switch three-phase inverter or the three-phase cascade multilevel inverter (3P-CMI) generate high-frequency common-mode voltage (CMV) components, which due to the structure of the system, cause the common-mode current (CMC), also known as LKC. The CMC is the major issue in transformerless grid connected PV systems, as it can lead to additional power losses, protection tripping, important safety problems, and high total harmonic distortion (THD) of the current injected into the grid. Due to these issues, international norms have been developed to limit the CMC circulation through the PV system to guarantee the security of the system and humans in contact with it, for instance, the international standard DIN VDE 0126-1-1 establishes the maximum limit of the value of the CMC in 300 mA. The scientific community has reported several techniques based on different approaches to mitigate the CMC. Among these, pulse width modulation (PWM) solutions have been popular because it is not necessary to increase the number of semiconductors in the topology or to implement complex control systems. Furthermore, additional functions such as voltage balancing of capacitors can be performed in split DC bus topologies as in neutral point clamped (NPC) inverters, and total system efficiency can be improved through a proper modulation design.
The six-switch three-phase inverter (3P-FB) has been widely studied under space vector modulation techniques for transformerless grid connection and motor drive applications. In [
1], a near-state PWM (NSPWM) method was proposed; here, a comparison with similar PWM methods is performed. The NSPWM method makes use of a set of three voltage vectors to match the output and volt-second references. The three voltage vectors are two adjacent vectors together with a near-neighbor vector; then, nonzero voltage vectors are utilized. The sectors are displaced from each other by 30
; therefore, new regions are defined with respect to the conventional distribution. As no zero voltage vectors are used, the CMV does not take values produced by those vectors; therefore, CMV variations are reduced. In the case of PV systems, in [
2], an evaluation of three-phase converters without galvanic isolation is reported. The analysis considers the conventional 3P-FB, the 3P-FB with split capacitor (3P-FBSC), and the three-phase NPC inverter (3P-NPC). The results demonstrate that the 3P-FBSC and 3P-NPC inverters produce low CMC, which make them two suitable solutions in three-phase transformerless inverters.
Derived from the 3P-FB inverter topology, some modified topologies have been also proposed to solve the CMC issue. For example, by adding passive components, as in the Z-source inverter topology presented in [
3], it is possible to avoid the use of a boost stage at the input of the system. Additionally, the CMC magnitude can be reduced by modifying the PWM strategy as in [
4], where the authors proposed a modified Z-source inverter and a space vector based modulation (SVM) technique that reduces the CMC magnitude. Moreover, in [
5,
6,
7], a family of topologies called Quasi Z-source inverters is presented, the main idea is to reduce the component rating, the source stress, and component count and to make some contributions to simplify the control strategies. Another approach consists in the addition of active components in order to deal with the CMC, for instance, diodes, IGBTs, or MOSFETs as in [
8], where additional diodes connected as a three-phase rectifier plus an IGBT are used to implement the null vectors in an SVM technique. The main idea is to connect the output of the inverter to
or to
, thus avoiding some CMV transitions and reducing the magnitude of the CMC. Another alternative based on the traditional 3P-FB inverter is to use the idea of DC decoupling developed in the H5 and H6 topologies for single-phase systems [
9,
10]. In this case, [
11,
12] proposed the H7 topology and a study of several SVM techniques to reduce the CMC, and [
13] proposed that the H8 topology and its SVM technique are presented. In both cases, the main idea is to disconnect the DC bus during the null vectors, which in combination with an adequate sequence of active vectors allows us to mitigate the CMC. Another topology that is a combination of a NPC topology and the 3P-FB inverters is presented in [
14] where a type of NPC circuit is added at the output of the inverter following the idea of the HERIC single-phase inverter [
15]. The null vectors are now implemented in a freewheeling circuit, which reduces the transitions of the CMV in the circuit, obtaining a reduction in the CMC magnitude.
The DCM-232 topology and its space vector PWM strategy have been designed to deal with the CMC issue. The main objective as in the aforementioned cases is to reduce the fast changes in the CMV by as much as possible and consequently to decrease the magnitude of the CMC. This inverter is based also on the 3P-FB topology at the AC output side, while on the DC input side, there are two DC sources that can be completely decoupled from the 3P-FB circuit by means of two semiconductors switched at the same time [
16]. The PWM strategy is based on the space vector PWM technique, where the main difference is that the active vectors are implemented in the 3P-FB circuit and that the zero vectors are implemented by decoupling the DC sources using power semiconductor switches. In the literature, some PWM strategies have also been designed for the DCM-232 inverter; see for instance [
17], where a carrier-based PWM is proposed to solve the CMC issue using the principle explained above.
In this paper, three PWM methods based on the Space Vector PWM (SVPWM) technique are studied to reduce the CMC components. The proposed modulation strategies are used to control the three-phase DCM-232 topology. The time intervals to control on and off conditions for each switch are defined using the waveforms obtained by means of the SVPWM concept and then a comparison with a triangular carrier signal is performed. Finally, the resulting signals are processed by a Boolean function implemented in a Complex Programable Logic Device (CPLD) to determine the final sequence for each switch. The DCM-232 topology consists in a 3P-FB inverter plus four switches that decouples the signal to generate two independent DC sources, i.e., two PV generators. The main idea is to control the decoupling switches in order to keep the CMV constant, thereby achieving a reduction in the CMC. The CMV evaluation is performed by driving the Common Mode Model (CMM) of the DCM-232 inverter. In addition, the paper considers an efficiency analysis based on numerical results obtained by means of the implementation of the real models of the semiconductors. Finally, a comparative analysis between the proposed PWM techniques and some solutions available in the literature is performed.
3. Numerical Results
To validate the proposed SVM technique for the three-phase DC-232 inverter, the numerical results are reported using the parameters shown in
Table 3. It is important to highlight that the numerical results are obtained in an open loop configuration, since the main objective is to validate the proposed SVM techniques operating with this topology. The general scheme implemented in the PSIM software is shown in
Figure 7, where (a) the three-phase signals, (b) the Clark transformation, (c) the module and angle of the reference vector, (d) time vector calculation, (e) the reference signals for the space vectors, and (f and g) PWM signal generation are presented. In the particular case of the block (e), the reference signals are defined in different ways for the three-proposed SVM strategies. In
Figure 8, the reference signals for CSSVM, CASVM, and DSVMMAX are depicted. Note that the reference signals for CSSVM have only positive values, CASVM is centered at zero and has positive and negative values, and DSVMMAX is centered at zero but has an unsymmetrical waveform. Note that these reference signals are generated by the addition of the time intervals calculated for each vector along each sector and their magnitude is related to the switching period. Moreover, the block depicted in (f) is dedicated to generate the PWM signals, in particular, the signals for the switches on the DC side are generated using the digital circuit depicted in
Figure 9 according to (
22) and (
23).
The numerical results were obtained for the three SVM techniques; however, the waveforms for the output currents and voltages are very similar in the three cases. Therefore, for brevity, only the waveforms for the CSSVM technique are included.
Figure 10 shows the simulation results for the three-phase output currents, line-to-neutral voltages, and line-to-line voltages. As observed, these waveforms are similar to those typical waveforms of a three-phase conventional inverter. It can be observed also that the switching ripple appears at the sinusoidal current waveforms in which peak current is around
A. It is important to note that, under these conditions, the ripple magnitude is large and the measured THDi is around 16%, which is not allowed by the international standard, for instance, IEEE 519-2014 (considering a low grid voltage). It should be also noted that, in this case, a first-order low-pass filter is used at the output of the inverter (see
Figure 11), so this can be improved by implementing a third-order filter. It is possible to increase the switching frequency or the rated power to improve the THDi as well; however, in this case, these parameters are limited by the experimental setup. On the other hand, the common mode voltage and current are also obtained by simulations; in this case, the three sets of results are presented in
Figure 12. As it can be observed, the results show that these two parameters are similar for the three proposed cases. In the case of the CMV, the magnitude is predominantly constant, and in the case of the CMC, the maximum value is around 40 mA, which is well below the limits imposed by the DIN VDE 0126-1-1 international standard, which is up to 300 mA (RMS). It should be noted that the numerical simulations were performed considering a balanced DC-bus, that is
. However, in a transformerless PV application, when the irradiance changes along a day, the voltage at the maximum power point also changes. This variation, which is typically around 10% to 20%, produces a DC component at the output of the DCM-232 inverter. Under these conditions, the inverter is still capable of operating but with a DC component which is not allowed. To solve this problem, a balance technique should be implemented, and this can be solved either by implementing a balance control loop or by modifying the modulation strategy; however, this issue is out of the scope of this paper.
To better compare the three SVM strategies under study, an efficiency analysis was performed. For this purpose, the IGBT model was loaded into the Thermal Module of the PSIM software and the total losses of the DCM-232 converter were calculated. The model loaded in the software considers the parameters provided by the manufacturer; then, the behavior of the power losses is expected to be close to the real behavior. The results of the switching and conduction losses are shown in
Figure 13. As can be observed, the sum of the switching and conduction power losses is greater for the DSVMMAX with respect to the other techniques, while the CASVM presents the lowest total power losses. Therefore, the CASVM should be expected to present the highest efficiency. To validate this parameter, the efficiency of the system was also measured and the results are presented in
Table 4, where, as expected, the CASVM technique presents the best efficiency.
Considerations for a Practical Implementation
The DCM-232 three-phase inverter was implemented as a laboratory prototype to validate the proposed SVM strategies. A flow chart of the implementation process is shown in
Figure 14. The algorithms for the SVM strategies were implemented using a Digital Signal Processor (DSP) TMS320F28335 device together with the PSIM software. Additionally, the digital functions for the PWM signals were implemented in a complex programmable logic device (CPLD) CoolRunner-II according with
Figure 14. The power module SKM50GB12T4 was used to implement the DCM-232 three-phase inverter, and the diodes
to
were implemented using the power module 200RD4TVL. The electrical parameters are in accordance with the parameters used for the simulation test, as listed in
Table 3. A simplified block diagram of the experimental setup is depicted in
Figure 11. The ground path was implemented by connecting the neutral point of the
load to the available terminal of the parasitic capacitors
, and
through a resistance with a value equal to 22
.
4. Experimental Validation
The experimental implementation was performed considering the parameters and conditions described in
Section 3 and in
Table 3. In
Figure 15, the output currents in (a), the line-to-neutral voltages in (b), and the line-to-line voltages in (c) for the CSSVM strategy are presented. As can be observed, the waveforms are similar to those obtained for the simulation results. Namely, the output current for the three phases is sinusoidal plus the switching ripple, the voltage between each phase and the neutral connection has the typical five levels, and the voltages between lines are also the typical of a full-bridge three-phase system. Since these waveforms are close to the waveforms of the other two proposed SVPWM strategies, only the results for the CSSVM are included. In
Figure 16, the results obtained for the common mode behavior for (a) CSSVM, (b) CASVM, and (c) DSVMMAX at the DC bus 1 and the common mode current are shown. Notice that, in all cases, the CMC has a value below 300 mA, which is established by the international norm DIN VDE 0126-1-1 as the maximum allowable limit. Note that the
waveform contains a noise component, which is due to the oscilloscope internal calculations and the effect of parasitic components during the switching process. Moreover, the CMV regarding the second DC bus
has also been obtained. The average value of this parameter is close to
, which is the value obtained by means of simulations; however, and considering that the waveform is similar to the signal presented for the
, the last is not included in the paper.
In order to better compare the results obtained by the implementation of the proposed SVM algorithms regarding CMC, the measures are summarized in
Table 5. As can be noted, the RMS value for the CMC for the three proposed cases is similar and complies with the international standard mentioned before. Moreover, the results regarding CMC were compared with the conventional full-bridge three-phase inverter (3PFB-VSI) under SVM, and it can be noted that the CMC has a larger magnitude regarding the proposed modulation topology and SVPWM algorithms.