Investigation of Tunneling Effect for a N-Type Feedback Field-Effect Transistor
Abstract
:1. Introduction
2. Simulation Results
2.1. Simulation Structure and Parameter
2.2. Mechanism of the NFBFET
3. Tunneling Effect for the NFBFET
3.1. VDS Dependence of Leakage Current
3.2. VGS Dependence of Leakage Current
3.3. Tunneling Effect with Various Doping Profile
4. Conclusions
Author Contributions
Funding
Acknowledgments
Conflicts of Interest
References
- Ramaswamy, S.; Kumar, M.J. Junctionless Impact Ionization MOS: Proposal and Investigation. IEEE Trans. Electron Devices 2014, 61, 4295–4298. [Google Scholar] [CrossRef]
- Sarkar, D.; Singh, N.; Banerjee, K. A Novel Enhanced Electric-Field Impact-Ionization MOS Transistor. IEEE Electron Device Lett. 2010, 31, 1175–1177. [Google Scholar] [CrossRef]
- Lahgere, A.; Kumar, M.J. The charge plasma n-p-n impact ionization MOS on FDSOI technology. IEEE Trans. Electron Devices 2017, 64, 3–7. [Google Scholar] [CrossRef]
- Ionescu, A.M.; Riel, H. Tunnel field-effect transistors as energy efficient electronic switches. Nature 2011, 479, 329–337. [Google Scholar] [CrossRef]
- Krishnamohan, T.; Kim, D.; Raghunathan, S.; Saraswat, K. Double-gate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and ≪60 mV/dec subthreshold slope. In Proceedings of the 2008 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 15–17 December 2008; pp. 1–3. [Google Scholar]
- Smith, J.T.; Das, S.; Appenzeller, J. Broken-gap tunnel MOSFET: A constant-slope sub-60-mV/decade transistor. IEEE Electron Device Lett. 2011, 32, 1367–1369. [Google Scholar] [CrossRef]
- Wang, L.; Yu, E.; Taur, Y.; Asbeck, P. Design of tunneling field-effect transistors based on staggered heterojunctions for ultralow-power applications. IEEE Electron Device Lett. 2010, 31, 431–433. [Google Scholar] [CrossRef]
- Rahi, S.B.; Tayal, S.; Upadhyay, A.K. A review on emerging negative capacitance field effect transistor for low power electronics. Microelectron. J. 2021, 116, 105242. [Google Scholar] [CrossRef]
- Khan, A.I.; Yeung, C.W.; Hu, C.; Salahuddin, S. Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation. In Proceedings of the 2011 International Electron Devices Meeting (IEDM), Washington, DC, USA, 5–7 December 2011; pp. 11.3.1–11.3.4. [Google Scholar]
- Lin, C.-I.; Khan, A.I.; Salahiddin, S.; Hu, C. Effects of the variation of ferroelectric properties on negative capacitance FET characteristics. IEEE Trans. Electron Devices 2016, 63, 2197–2199. [Google Scholar] [CrossRef]
- Padilla, A.; Yeung, C.W.; Shin, C.; Hu, C.; King Liu, T.-J.K. Feedback FET: A novel transistor exhibiting steep switching behavior at low bias voltages. In Proceedings of the 2008 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 15–17 December 2008; pp. 1–4. [Google Scholar]
- Yeung, C.W.; Padilla, A.; Liu, T.-J.K.; Hu, C. Programming characteristics of the steep turn-on/off feedback FET (FBFET). In Proceedings of the 2009 Symposium on VLSI Technology, Kyoto, Japan, 15–17 June 2009; pp. 176–177. [Google Scholar]
- Cho, J.; Lim, D.; Woo, S.; Cho, K.; Kim, S. Static random access memory characteristics of single-gated feedback field-effect transistors. IEEE Trans. Electron Devices 2019, 66, 413–419. [Google Scholar] [CrossRef]
- Woo, S.; Cho, J.; Lim, D.; Cho, K.; Kim, S. Transposable 3T-SRAM synaptic array using independent double-gate feedback field-effect transistor. IEEE Trans. Electron Devices 2019, 66, 4753–4758. [Google Scholar] [CrossRef]
- Kang, H.; Cho, J.; Kim, Y.; Lim, D.; Woo, S.; Cho, K.; Kim, S. Nonvolatile and volatile memory characteristics of a silicon nanowire feedback field-effect transistor with a nitride charge-storage layer. IEEE Trans. Electron Devices 2019, 66, 3342–3348. [Google Scholar] [CrossRef]
- Wan, J.; Le Royer, C.; Zaslavsky, A.; Cristoloveanu, S. Z2-FET used as 1-transistor high-speed DRAM. In Proceedings of the 2012 European Solid-State Device Research Conference (ESSDERC), Bordeaux, France, 17–21 September 2012; pp. 197–200. [Google Scholar]
- Martinie, S.; Lacord, J.; Rozeau, O.; Parihar, M.-S.; Lee, K.; Bawedin, M.; Cristoloveanu, S.; Taur, Y.; Barbe, J.-C. Z2-FET SPICE model: DC and memory operation. In Proceedings of the 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Burlingame, CA, USA, 16–19 October 2017; pp. 1–3. [Google Scholar]
- Wan, J.; Le Royer, C.; Zaslavsky, A.; Cristoloveanu, S. Progress in Z2-FET 1T-DRAM: Retention time, writing modes, selective array operation, and dual bit storage. Solid State Electron. 2013, 84, 147–154. [Google Scholar] [CrossRef]
- Wan, J.; Le Royer, C.; Zaslavsky, A.; Cristoloveanu, S. Z2-FET: A zero-slope switching device with gate-controlled hysteresis. In Proceedings of the Technical program of 2012 VLSI Technology, System and Application, Hsinchu, Taiwan, 23–25 April 2012; pp. 1–4. [Google Scholar]
- El Dirani, H.; Solaro, Y.; Fonteneau, P.; Ferrari, P.; Cristoloveanu, S. Sharp-switching Z2-FET device in 14 nm FDSOI technology. In Proceedings of the 2015 45th European Solid State Device Research Conference (ESSDERC), Graz, Austria, 14–18 September 2015; pp. 250–253. [Google Scholar]
- Wan, J.; Le Royer, C.; Zaslavsky, A.; Cristoloveanu, S. A systematic study of the sharp-switching Z2-FET device: From mechanism to modeling and compact memory applications. Solid State Electron 2013, 90, 2–11. [Google Scholar] [CrossRef]
- Kim, M.; Kim, Y.; Lim, D.; Woo, S.; Cho, K.; Kim, S. Steep switching characteristics of single-gated feedback field-effect transistors. Nanotechnology 2016, 28, 055205. [Google Scholar] [CrossRef]
- Lee, C.; Ko, E.; Shin, C. Steep slope silicon-on-insulator feedback field-effect transistor: Design and performance analysis. IEEE Trans. Electron Devices 2019, 66, 286–291. [Google Scholar] [CrossRef]
- Oh, J.H.; Yu, Y.S. Investigation of monolithic 3D integrated circuit inverter with feedback field effect transistors using TCAD Simulation. Micromachines 2020, 11, 852. [Google Scholar] [CrossRef]
- Kwon, M.-W.; Hwang, S.; Baek, M.-H.; Cho, S.; Park, B.-G. Dual gate positive feedback field-effect transistor for low power analog circuit. In Proceedings of the 2017 Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, 4–5 June 2017; pp. 115–116. [Google Scholar]
- Lee, I.; Park, H.; Nguyen, Q.T.; Kim, G.; Cho, S.; Cho, I. Optimization of Feedback FET with Asymmetric Source Drain Doping profile. Micromachines 2022, 13, 508. [Google Scholar] [CrossRef]
- Singh, D.; Patil, G.C. Performance analysis of feedback field-effect transistor-based biosensor. IEEE Sens. J. 2020, 20, 13269–13276. [Google Scholar] [CrossRef]
- Kwon, M.-W.; Park, K.; Baek, M.-H.; Lee, J.; Park, B.-G. A low-energy high-density capacitor-less I&F neuron circuit using feedback FET Co-integrated with CMOS. IEEE J. Electron Devices Soc. 2019, 7, 1080–1084. [Google Scholar]
- Kwon, M.-W.; Park, K.; Park, B.-G. Low-power adaptive integrate-and-fire neuron circuit using positive feedback FET Co-Integrated with CMOS. IEEE Access 2021, 9, 159925–159932. [Google Scholar] [CrossRef]
- Woo, S.; Cho, J.; Lim, D.; Park, Y.-S.; Cho, K.; Kim, S. Implementation and characterization of an integrate-and-fire neuron circuit using a silicon nanowire feedback field-effect transistor. IEEE Trans. Electron Devices 2020, 67, 2995–3000. [Google Scholar] [CrossRef]
- Silvaco Int. ATLAS, ver. 5. 32. 1.; R Manual; Silvaco Int.: Santa Clara, CA, USA, 2021. [Google Scholar]
- Biswas, A.; Dan, S.S.; Le Royer, C.; Grabinski, W.; Ionescu, A.M. TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model. Microelectron. Eng. 2012, 98, 334–337. [Google Scholar] [CrossRef]
- Kane, O.E. Theory of tunneling. J. Appl. Phys. 1961, 32, 83–91. [Google Scholar] [CrossRef]
- Najam, F.; Yu, Y.S. Compact model for L-shaped tunnel field-effect transistor including the 2D region. Appl. Sci. 2019, 9, 3716. [Google Scholar] [CrossRef]
- Yu, Y.S.; Najam, F. Compact capacitance model of L-shape tunnel field-effect transistors for circuit simulation. J. Inf. Commun. Converg. Eng. 2021, 19, 263–268. [Google Scholar] [CrossRef]
Parameters | Description | Value/Unit |
---|---|---|
Ldrain | Length of drain region | 30 nm |
Lugc | Length of ungated channel region | 40 nm |
Lugc | Length of gated channel region | 40 nm |
Lsource | Length of source region | 30 nm |
Tsi | Thickness of silicon body | 15 nm |
Tox | Thickness of gate-oxide | 3 nm |
Ngc | Doping concentration of gated channel region | Var. |
Doping concentration of P+ region | 1 × 1020 cm−3 | |
Doping concentration of N+ region | 1 × 1020 cm−3 |
Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations. |
© 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).
Share and Cite
Oh, J.H.; Yu, Y.S. Investigation of Tunneling Effect for a N-Type Feedback Field-Effect Transistor. Micromachines 2022, 13, 1329. https://doi.org/10.3390/mi13081329
Oh JH, Yu YS. Investigation of Tunneling Effect for a N-Type Feedback Field-Effect Transistor. Micromachines. 2022; 13(8):1329. https://doi.org/10.3390/mi13081329
Chicago/Turabian StyleOh, Jong Hyeok, and Yun Seop Yu. 2022. "Investigation of Tunneling Effect for a N-Type Feedback Field-Effect Transistor" Micromachines 13, no. 8: 1329. https://doi.org/10.3390/mi13081329
APA StyleOh, J. H., & Yu, Y. S. (2022). Investigation of Tunneling Effect for a N-Type Feedback Field-Effect Transistor. Micromachines, 13(8), 1329. https://doi.org/10.3390/mi13081329