Bi-Directional and Operand-Controllable In-Memory Computing for Boolean Logic and Search Operations with Row and Column Directional SRAM (RC-SRAM)
Abstract
:1. Introduction
2. RC-SRAM and IMC Architecture
3. Operating Mode and Working Principle
3.1. SRAM Mode
3.2. Boolean Logic Mode
3.2.1. Row-Wise Boolean Logic Operation
3.2.2. Column-Wise Boolean Logic Operation
3.3. CAM Mode
3.3.1. Row-Wise CAM Operation
3.3.2. Column-Wise CAM Operation
4. Simulation Results
5. Conclusions
Author Contributions
Funding
Data Availability Statement
Conflicts of Interest
References
- Horowitz, M. 1.1 Computing’s energy problem (and what we can do about it). In Proceedings of the 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, USA, 9–13 February 2014; pp. 10–14. [Google Scholar] [CrossRef]
- Verma, N.; Jia, H.; Valavi, H.; Tang, Y.; Ozatay, M.; Chen, L.Y.; Zhang, B.; Deaville, P. In-Memory Computing: Advances and Prospects. IEEE Solid-State Circuits Mag. 2019, 11, 43–55. [Google Scholar] [CrossRef]
- Aga, S.; Jeloka, S.; Subramaniyan, A.; Narayanasamy, S.; Blaauw, D.; Das, R. Compute Caches. In Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), Austin, TX, USA, 4–8 February 2017; pp. 481–492. [Google Scholar] [CrossRef]
- Seshadri, V.; Lee, D.; Mullins, T.; Hassan, H.; Boroumand, A.; Kim, J.; Kozuch, M.A.; Mutlu, O.; Gibbons, P.B.; Mowry, T.C. Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology. In Proceedings of the 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Boston, MA, USA, 14–17 October 2017; pp. 273–287. [Google Scholar]
- He, M.; Song, C.; Kim, I.; Jeong, C.; Kim, S.; Park, I.; Thottethodi, M.; Vijaykumar, T.N. Newton: A DRAM-maker’s Accelerator-in-Memory (AiM) Architecture for Machine Learning. In Proceedings of the 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Athens, Greece, 17–21 October 2020; pp. 372–385. [Google Scholar] [CrossRef]
- Agrawal, A.; Wang, C.; Sharma, T.; Roy, K. Magnetoresistive Circuits and Systems: Embedded Non-Volatile Memory to Crossbar Arrays. IEEE Trans. Circuits Syst. I Regul. Pap. 2021, 68, 2281–2294. [Google Scholar] [CrossRef]
- Jain, S.; Ranjan, A.; Roy, K.; Raghunathan, A. Computing in Memory With Spin-Transfer Torque Magnetic RAM. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2018, 26, 470–483. [Google Scholar] [CrossRef]
- Wang, C.; Wang, Z.; Wang, G.; Zhang, Y.; Zhao, W. Design of an Area-Efficient Computing in Memory Platform Based on STT-MRAM. IEEE Trans. Magn. 2021, 57, 1–4. [Google Scholar] [CrossRef]
- Khwa, W.S.; Chen, J.J.; Li, J.F.; Si, X.; Yang, E.Y.; Sun, X.; Liu, R.; Chen, P.Y.; Li, Q.; Yu, S.; et al. A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors. In Proceedings of the 2018 IEEE International Solid-State Circuits Conference—(ISSCC), San Francisco, CA, USA, 11–15 February 2018; pp. 496–498. [Google Scholar] [CrossRef]
- Biswas, A.; Chandrakasan, A.P. CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks. IEEE J. Solid-State Circuits 2019, 54, 217–230. [Google Scholar] [CrossRef]
- Si, X.; Chen, J.J.; Tu, Y.N.; Huang, W.H.; Wang, J.H.; Chiu, Y.C.; Wei, W.C.; Wu, S.Y.; Sun, X.; Liu, R.; et al. 24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning. In Proceedings of the 2019 IEEE International Solid-State Circuits Conference—(ISSCC), San Francisco, CA, USA, 17–21 February 2019; pp. 396–398. [Google Scholar] [CrossRef]
- Jaiswal, A.; Chakraborty, I.; Agrawal, A.; Roy, K. 8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2019, 27, 2556–2567. [Google Scholar] [CrossRef]
- Rajput, A.K.; Pattanaik, M. Implementation of Boolean and Arithmetic Functions with 8T SRAM Cell for In-Memory Computation. In Proceedings of the 2020 International Conference for Emerging Technology (INCET), Belgaum, India, 5–7 June 2020; pp. 1–5. [Google Scholar] [CrossRef]
- Chang, Y.J.; Chen, S.H. Multi-Logic Sense Amplifier (MLSA) Design for In-Memory Computing. IEEE J. Emerg. Sel. Top. Circuits Syst. 2023, 13, 371–381. [Google Scholar] [CrossRef]
- Lin, Z.; Zhu, Z.; Zhan, H.; Peng, C.; Wu, X.; Yao, Y.; Niu, J.; Chen, J. Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports. IEEE J. Solid-State Circuits 2021, 56, 2832–2844. [Google Scholar] [CrossRef]
- Lin, Z.; Tong, Z.; Wang, F.; Zhang, J.; Zhao, Y.; Sun, P.; Xu, T.; Zhang, C.; Li, X.; Wu, X.; et al. In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic and Copy Operations. IEEE J. Solid-State Circuits 2023, 58, 1472–1486. [Google Scholar] [CrossRef]
- Agrawal, A.; Jaiswal, A.; Lee, C.; Roy, K. X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories. IEEE Trans. Circuits Syst. I Regul. Pap. 2018, 65, 4219–4232. [Google Scholar] [CrossRef]
- Jeloka, S.; Akesh, N.B.; Sylvester, D.; Blaauw, D. A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory. IEEE J. Solid-State Circuits 2016, 51, 1009–1021. [Google Scholar] [CrossRef]
- Lin, Z.; Zhan, H.; Li, X.; Peng, C.; Lu, W.; Wu, X.; Chen, J. In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2020, 28, 1316–1320. [Google Scholar] [CrossRef]
This Work | JSSC’16 [18] | JSSC’21 [15] | TVLSI’20 [19] | |||
---|---|---|---|---|---|---|
Technology | 28 nm | 28 nm FDSOI | 28 nm | 65 nm | ||
Cell type | 10 T | 6 T | 10 T | 8 T | ||
Array size | 1 Kb | 4 Kb | 4 Kb | 16 Kb | ||
Supply voltage | 0.9 V | 1 V | 0.9 V | 1.2 V | ||
Boolean logic | Row-wise | Freq.(MHz) | 759 | 594 | ∼300 | 793 |
Customizable a | Yes | No | Yes | No | ||
Column-wise | Freq.(MHz) | 683 | NA | ∼300 | NA | |
Customizable a | Yes | Yes | ||||
CAM search | Row-wise | Freq.(MHz) | 775 | NA | 262 | NA |
Customizable b | Yes | No | ||||
Column-wise | Freq.(MHz) | 567 | ∼370 | 256 | 813 | |
Customizable b | Yes | No | No | No |
Disclaimer/Publisher’s Note: The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of MDPI and/or the editor(s). MDPI and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content. |
© 2024 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).
Share and Cite
Xiao, H.; Zhao, R.; Liu, Y.; Liu, Y.; Chen, J. Bi-Directional and Operand-Controllable In-Memory Computing for Boolean Logic and Search Operations with Row and Column Directional SRAM (RC-SRAM). Micromachines 2024, 15, 1056. https://doi.org/10.3390/mi15081056
Xiao H, Zhao R, Liu Y, Liu Y, Chen J. Bi-Directional and Operand-Controllable In-Memory Computing for Boolean Logic and Search Operations with Row and Column Directional SRAM (RC-SRAM). Micromachines. 2024; 15(8):1056. https://doi.org/10.3390/mi15081056
Chicago/Turabian StyleXiao, Han, Ruiyong Zhao, Yulan Liu, Yuanzhen Liu, and Jing Chen. 2024. "Bi-Directional and Operand-Controllable In-Memory Computing for Boolean Logic and Search Operations with Row and Column Directional SRAM (RC-SRAM)" Micromachines 15, no. 8: 1056. https://doi.org/10.3390/mi15081056