A Sub-0.01 °C Resolution All-CMOS Temperature Sensor with 0.43 °C/−0.38 °C Inaccuracy and 1.9 pJ · K² Resolution FoM for IoT Applications

Abstract

A high resolution, acceptable accuracy and low power consumption time-domain temperature sensor is proposed and simulated in this paper based on a 180 nm standard CMOS technology. A diode stacking structure is introduced to enhance the accuracy of the temperature sensing core. To improve the resolution of the sensor, a dual-input capacitor multiplexing voltage-to-time converter (VTC) is implemented. Additionally, a low-temperature drift voltage-mode relaxation oscillator (ROSC) is proposed, effectively reducing the large oscillation frequency drift caused by significant temperature impacts on delay errors. The simulated results show that the resolution is as high as 0.0071 °C over 0∼120 °C with +0.43 °C/−0.38 °C inaccuracy and 1.9 pJ · K² resolution FoM, consuming only 1.48 $\mathsf{\mu }$W at a 1.2 V supply voltage.

1. Introduction

The Internet of Things (IoT) is rapidly expanding, incorporating smart wearables and intelligent household appliances that enhance daily convenience [1]. As a result, there is a growing demand for temperature sensors in these applications, necessitating features like low power consumption, compact size, high accuracy, and especially excellent resolution [2,3,4]. CMOS temperature sensors, which are preferred for their energy efficiency and ease of integration with other signal-processing units, effectively meet these requirements [5,6,7]. They support on-chip dynamic thermal management across various IoT devices, ensuring efficient heat dissipation and optimal performance.

CMOS temperature sensors typically require a high-quality frequency reference circuit to convert temperature-related information such as delay/frequency into digital codes [8]. Using an off-chip reference poses challenges in system integration and miniaturization while integrating an on-chip frequency reference can significantly reduce the overall size and power consumption of the sensor chip [9]. Therefore, a fully integrated reference circuit and clock generator are often considered essential in CMOS temperature sensors.

The existing classification of CMOS temperature sensors is based on the types of temperature-sensing devices used in CMOS processes, namely BJT-based, resistive-based, all-MOSFET-based, and TD-based [10]. For example, in a BJT-based front-end circuit, the temperature-related signal it generates is an analog voltage signal, specifically $V_{BE}$ and $\Delta V_{BE}$ [11]. However, there are various ways to digitize this signal. For instance, the temperature-related voltage can be directly quantified using an analog-to-digital converter (ADC), or it can be first converted into a current, and then a current-mode ADC can be designed to quantify this current. Alternatively, the temperature-related voltage or current can be converted into delay, frequency, or other signals that can be directly processed by digital circuits. Based on the different methods of converting analog signals into digital signals, common CMOS temperature sensor architectures can be categorized into four domains: the voltage domain, current domain, frequency domain, and time domain.

Figure 1 displays the basic diagrams of the four typical temperature sensors reported above. It is important to note that the $CL{K}_{ref}$ before FDC and TDC represents a temperature-independent clock.

As shown in Figure 1a, BJT-based voltage-domain temperature sensors are capable of high precision utilizing a SAR ADC or a $\Delta$$\mathsf{\Sigma }$ ADC, enhanced by various calibration techniques [12]. The precision of these sensors is minimally affected by small variations in clock frequency, so they typically do not require a temperature-independent clock signal. However, voltage-domain CMOS temperature sensors are not limited to BJT-based temperature sensors. By integrating with other types of temperature-sensing devices and custom ADCs, different performance requirements can be met [13].

For example, in BJT-based temperature sensors, the current-domain solution modifies the analog front-end circuit to convert $\Delta V_{BE}$ and $V_{BE}$ into temperature-related currents. These currents are then quantified using a current-domain $\Delta$$\mathsf{\Sigma }$ modulator, as illustrated in Figure 1b [14]. Compared to direct voltage readout, current-domain readout reduces dependence on voltage swing and, in low-precision scenarios, it offers advantages such as smaller areas and lower voltage supply. Similar to the voltage-domain solution, if combined with different types of temperature-sensing devices, the current-domain temperature sensor can also achieve a wider range of performance options [15].

Time-domain CMOS temperature sensors mainly adopt two approaches. One approach outputs duty cycle information proportional to temperature, producing a duty cycle-modulated square wave (or PWM wave) that can be directly processed by digital circuits, simplifying the circuit interface [16]. The other type, shown in Figure 1d, directly converts temperature into temperature-related pulse signals or periodic time-domain signals, which are subsequently quantified using an all-digital TDC [17]. However, this approach requires an additional precise clock as a reference signal for the TDC to digitize the temperature-related time-domain signal. Compared to traditional voltage-domain or current-domain readouts, TDCs used in time-domain readouts are better suited to digital circuit implementation, allowing their area and power consumption to benefit from process node scaling.

As shown in Figure 1c, similar to the time-domain readout architecture, converting temperature into frequency signals is another viable approach. Like the time-domain method, the frequency-domain approach converts temperature into delay information; however, instead of directly quantifying the width of a single pulse, it measures the signal frequency generated by the sensor. This significantly reduces the need for a single delay duration, enabling a smaller area and faster temperature measurement, although the temperature measurement error is typically larger [18].

In this paper, a CMOS-based time-domain temperature sensor suitable for IoT applications is proposed. To improve accuracy in the temperature sensing core, a diode stacking structure is implemented, generating $V_{PTAT}$ and $V_{CTAT}$ with high-temperature coefficients (TCs). A dual-input capacitor multiplexing voltage-to-time converter is introduced to enhance resolution by fully utilizing both temperature-negative and temperature-positive correlated information. Furthermore, a low-temperature drift voltage-mode relaxation oscillator is proposed, effectively mitigating large oscillation frequency drift due to temperature-induced delay errors.

The remainder of this paper is organized as follows. Section 2 describes the system architecture and operation principle of the proposed temperature sensor. Section 3 shows the circuit implementation details of the three main parts. Section 4 demonstrates the simulation results with comparison to recently reported temperature sensors, while Section 5 concludes this paper.

2. Architecture and Operation Principle

Figure 2 shows the block diagram of the proposed temperature sensor. The structure consists of three major parts: (1) a temperature sensing core, (2) a voltage-to-time converter, and (3) a time-to-digital converter with a temperature-stabilized relaxation oscillator.

The proposed temperature sensing core serves the purpose of generating temperature-related signals with high TC ($V_{PTAT}$/$V_{CTAT}$) and reference signals ($I_{REF}$/$V_{REF}$). The relaxation oscillator generates the reference frequency ($f_{REF}$) using $V_{REF}$. The dual-input capacitor multiplexing voltage-to-time converter is proposed to convert $V_{PTAT}$ and $V_{CTAT}$ to temperature-dependent time quantity $\Delta$t, as represented by the width of $V_{pulse}$. Since $\Delta$t is proportional to temperature, digitization is performed by converting $\Delta$t to 15 bits of digital code via a proposed time-to-digital converter clocked by an on-chip relaxation oscillator. To ensure digitization is not influenced by temperature, the oscillator is designed to be temperature stable [19].

As shown in Figure 2, the capacitor is successively charged to $V_{PTAT}$ and $V_{CTAT}$ by $I_{REF}$ [20]. During the time from when $V_{ip}$ charges to $V_{CTAT}$ until it charges to $V_{PTAT}$, the logic circuit generates the time signal $V_{pulse}$. As the temperature rises, the time required to charge to $V_{CTAT}$ shortens, while the time to charge to $V_{PTAT}$ lengthens. With the combination of high-TC $CTAT$ and $PTAT$ signals, the temperature-dependent time quantity $\Delta$t is significantly extended with temperature, thus improving the resolution [21]. The change in the time signal $V_{pulse}$ as the temperature increases and decreases is shown in Figure 3.

To support the above point, assuming there are two temperature points $T_1$ and $T_2$ ($T_1$>$T_2$), the change in $\Delta$t as the temperature increases can be represented as follows:

$$\begin{array}{cc}\hfill \Delta t=\Delta t\left(T_1\right)-\Delta t\left(T_2\right)& ={\displaystyle \frac{C\left[k_{PTAT}\left(T_1-T_2\right)+k_{CTAT}\left(T_2-T_1\right)\right]}{I_{REF}}}\hfill \\ \hfill & ={\displaystyle \frac{C\left(k_{PTAT}-k_{CTAT}\right)\left(T_1-T_2\right)}{I_{REF}}},\hfill \end{array}$$

(1)

where $k_{CTAT}$ and $k_{PTAT}$ are the absolute value of the TC of $V_{CTAT}$ and $V_{PTAT}$, respectively, while C represents the capacitance in Figure 2.

As a supplement, in Equation (1), we assume that $V_{CTAT}$ and $V_{PTAT}$ exhibit ideal linear temperature characteristics, considering only first-order temperature dependency, with minimal influence from higher-order terms.

3. Circuit Implementation Details

This section provides a detailed overview of the three key components mentioned earlier, focusing on the innovative strategies used to enhance the core performance of the temperature sensor and highlighting the unique contributions of our work.

3.1. Temperature Sensing Core

The proposed temperature sensing core is shown in Figure 4. The current negative feedback of the amplifier is used to increase the output impedance so that the output current is weakly correlated with the supply voltage. $V_{REF}$ is the reference voltage provided by the pre-stage reference circuit, with a resistor R composed of positive and negative temperature coefficient resistors, ensuring the output current is independent of temperature. The reference current and reference voltage in the initial part are applied in the implementation of $PTAT$ and $CTAT$ voltages, while the diode-stacked architecture achieves temperature-dependent voltages with larger temperature coefficients.

The schematic of the $V_{REF}$ generator is shown in the yellow dotted box [22]. $M_4$ and $M_5$ operate in the subthreshold region, $M_6$ and $M_7$ operate in the linear triode region, and other transistors operate in the saturation region. M6 is used to reduce power consumption by reducing the static current of the branch. $M_2$ and $M_3$ are the same, so the current of $M_7$ is equal to the current of $M_8$. Therefore,

$$\begin{array}{c}\hfill \mu C_{ox}{S}_7\left[\left(V_{REF}-V_{TH7}\right)V_{DS7}-{\displaystyle \frac{1}{2}}{V_{DS7}}^2\right]={\displaystyle \frac{1}{2}}\mu C_{ox}{S}_8{\left(V_{REF}-V_{TH8}\right)}^2,\end{array}$$

(2)

where $\mu$ is the carrier mobility and $C_{ox}$ is the gate-to-oxide capacitance, S is the width-to-length ratio W/L of the transistor, $V_{TH}$ is the threshold voltage of the transistor, and $V_{DS}$ is the drain-source voltage of the transistor.

In the same process, the threshold voltage of the MOS transistor is nearly equal under the same type, so $V_{TH7}$≈$V_{TH8}$; therefore,

$$\begin{array}{c}\hfill V_{REF}=V_{TH}+\eta {\displaystyle \frac{kT}{q}}ln\left({\displaystyle \frac{S_5}{S_4}}\right)\left[{\displaystyle \frac{S_7}{S_8}}+\sqrt{{\left({\displaystyle \frac{S_7}{S_8}}\right)}^2-{\displaystyle \frac{S_7}{S_8}}}\right].\end{array}$$

(3)

The relationship between threshold voltage and temperature is given by the following:

$$\begin{array}{c}\hfill V_{TH}\left(T\right)=V_{TH0}-{\displaystyle \frac{d{V}_{TH}}{dT}}T,\end{array}$$

(4)

where $V_{TH0}$ is the threshold voltage of the transistor at 0 K, and ${\displaystyle \frac{d{V}_{TH}}{dT}}$ is the temperature coefficient of the threshold voltage. According to Equations (3) and (4), as long as

$$\begin{array}{c}\hfill {\displaystyle \frac{d{V}_{TH}}{dT}}=\eta {\displaystyle \frac{k}{q}}ln\left({\displaystyle \frac{S_5}{S_4}}\right)\left[{\displaystyle \frac{S_7}{S_8}}+\sqrt{{\left({\displaystyle \frac{S_7}{S_8}}\right)}^2-{\displaystyle \frac{S_7}{S_8}}}\right],\end{array}$$

(5)

a reference voltage $V_{REF}$ independent of temperature can be obtained, thereby further achieving the reference current.

The $CTAT$ and $PTAT$ voltage generators are biased through the $I_{REF}$ and $V_{REF}$. It is noteworthy that all MOSFETs of the $CTAT$ and $PTAT$ voltage generator operate in the subthreshold region, as shown in the red dotted box and blue dotted box, respectively. The subthreshold leakage current of the MOS transistor is exponentially related to the gate and drain voltages. The I-V characteristics can be expressed as follows:

$$\begin{array}{c}\hfill I_D=\mu C_{ox}S(\eta -1)V_T^{2}exp\left({\displaystyle \frac{V_{GS}-V_{TH}}{\eta V_T}}\right)\left[1-exp\left(-{\displaystyle \frac{V_{DS}}{V_T}}\right)\right],\end{array}$$

(6)

where $\eta$ is the subthreshold slope factor, $V_{GS}$ is the gate-source voltage of the transistor, and $V_T$ is the thermal voltage ($V_T$ = $kT$/q, where k is the Boltzmann constant, q is the electron charge, and T is the temperature).

For typical application temperature ranges, it holds that $V_{DS}$≫ 4 $V_T$, and we can ignore the effect of $V_{DS}$ on the leakage current $I_D$. Consequently, at this time, $I_D$ can be approximated as follows:

$$\begin{array}{c}\hfill I_D\approx \mu C_{ox}S(\eta -1)V_T^{2}exp\left({\displaystyle \frac{V_{GS}-V_{TH}}{\eta V_T}}\right).\end{array}$$

(7)

Therefore, the expression for $V_{GS}$ can be represented by the following equation:

$$\begin{array}{c}\hfill V_{GS}=V_{TH}+\eta V_{T}ln\left(M\right),\end{array}$$

(8)

$$\begin{array}{c}\hfill M={\displaystyle \frac{I_D}{\mu C_{ox}S(\eta -1)V_T^2}},\end{array}$$

(9)

$$\begin{array}{c}\hfill \mu ={\mu }_0{\left({\displaystyle \frac{T}{T_0}}\right)}^{-m},\end{array}$$

(10)

where ${\mu }_0$ is the mobility at $T_0$ and m is the mobility temperature exponent. The value of m is about 1.5 in standard CMOS technologies according to [23], so the temperature coefficient in the logarithmic term can be disregarded. By taking the partial derivative of Equation (8), the TC of $V_{GS}$ can be expressed as follows:

$$\begin{array}{c}\hfill {\displaystyle \frac{\partial V_{GS}}{\partial T}}={\displaystyle \frac{\partial V_{TH}}{\partial T}}+\eta {\displaystyle \frac{k_B}{q}}ln\left(M\right).\end{array}$$

(11)

Based on the fact that $\left|{\displaystyle \frac{\partial V_{TH}}{\partial T}}\right|>\eta {\displaystyle \frac{k_B}{q}}ln\left(M\right)$, it follows that ${\displaystyle \frac{\partial V_{GS}}{\partial T}}<0$, leading to a negative temperature coefficient (NTC) of $V_{GS}$. Drawing from the earlier discussions, as illustrated in Figure 4, the utilization of the diode stacking structure serves to treble the TC of $V_{GS}$ and generate $V_{CTAT}$:

$$\begin{array}{cc}\hfill {\displaystyle \frac{\partial V_{CTAT}}{\partial T}}& ={\displaystyle \frac{\partial V_{GSC2}}{\partial T}}+{\displaystyle \frac{\partial V_{GSC3}}{\partial T}}+{\displaystyle \frac{\partial V_{GSC4}}{\partial T}}\hfill \\ \hfill & ={\displaystyle \frac{\partial V_{THC2}}{\partial T}}+{\displaystyle \frac{\partial V_{THC3}}{\partial T}}+{\displaystyle \frac{\partial V_{THC4}}{\partial T}}+\eta {\displaystyle \frac{k}{q}}ln\left(M_{C2}{M}_{C3}{M}_{C4}\right).\hfill \end{array}$$

(12)

Furthermore, the $V_{PTAT}$ is formed using a principle similar to that of $V_{CTAT}$:

$$\begin{array}{cc}\hfill V_{PTAT}& =V_{DSP1}=V_{DD}-V_{SGP2}-V_{SGP3}-V_{SGP4}.\hfill \end{array}$$

(13)

Due to the NTC of $V_{GSP2}$, $V_{GSP3}$, and $V_{GSP4}$, $V_{PTAT}$ exhibits a positive temperature coefficient (PTC). Additionally, the utilization of the diode stacking technique serves to treble the TC of $V_{PTAT}$. The high TC voltages obtained above will be beneficial for improving the overall resolution.

3.2. Voltage-to-Time Converter

The logic circuit of the proposed dual-input capacitor multiplexing VTC is shown in Figure 5. The $TIMER$ signal is used for time-setting purposes, controlling switch $S_2$ and the XOR gate that, in turn, controls switch $S_1$. It generates a rising edge at 12 ms, after $V_{ip}$ equals $V_{CTAT}$, to ensure the capacitor is fully discharged and to prevent overlapping the first and second charging processes. The two TG gates, controlled by signals $Q_0$ and $Q_0^{\prime }$, sequentially connect the inverting input of the comparator, $V_{in}$, to $V_{CTAT}$ and $V_{PTAT}$. Switch $S_3$ is also controlled by $Q_0^{\prime }$. The output signals $Q_0$ and $Q_1$ from the two D flip-flops are XORed to produce $V_{out}$, which is then XORed again with the $TIMER$ signal to control switch $S_1$. In the initial state, the D flip-flops are reset, setting both $Q_0$ and $Q_1$ to 0.

The operation process can be divided into four steps as shown in Figure 6.

(1) First charging: The $C_0$ is charged to $V_{CTAT}$ by $I_{REF}$. During this period, $Q_0^{\prime }$ is at a high level; thus, switch $S_3$ is turned off, and $V_{CTAT}$ is connected to the inverting input of the comparator, while $V_{out}$ remains at a low level.

(2) Discharging: When switch $S_1$ is closed, $V_{ip}$ is discharged to zero after the $V_{ip}$ surpasses $V_{CTAT}$ and $V_{out}$ rises. At this time, $Q_0$ reaches a high level, and $V_{PTAT}$ is connected to the inverting input of the comparator.

(3) Time slot: This period allows sufficient time to ensure that the capacitor can fully discharge at any temperature until the $TIMER$ signal appears, moving to the next stage.

(4) Second charging: The $C_0$ is charged to $V_{PTAT}$ by $I_{REF}$. During this time, switch $S_2$ is closed, while $S_1$ and $S_3$ are opened. When $V_{ip}$ surpasses $V_{PTAT}$, $Q_1$ reaches a high level and $V_{out}$ goes low.

The points in time when $V_{ip}$ reaches $V_{CTAT}$ and $V_{PTAT}$ are denoted as $t_1$ and $t_2$, respectively, which can be described as follows:

$$\begin{array}{c}\hfill t_1={\displaystyle \frac{C_0{V}_{CTAT}}{I_{REF}}},\end{array}$$

(14)

$$\begin{array}{c}\hfill t_2=t_{TIMER}+{\displaystyle \frac{C_0{V}_{PTAT}}{I_{REF}}}.\end{array}$$

(15)

As shown in Figure 6, the period $\Delta t$ during which $V_{out}$ stays high lies exactly between $t_1$ and $t_2$, which can be expressed as follows:

$$\begin{array}{c}\hfill \Delta t=t_2-t_1=t_{TIMER}+{\displaystyle \frac{C_0\left(V_{PTAT}-V_{CTAT}\right)}{I_{REF}}}.\end{array}$$

(16)

As mentioned before, $k_{CTAT}$ and $k_{PTAT}$ are the absolute values of the TC of $V_{CTAT}$ and $V_{PTAT}$. Equation (16) can be rewritten as follows:

$$\begin{array}{c}\hfill \Delta t=t_{TIMER}+{\displaystyle \frac{C_0\left(k_{PTAT}+k_{CTAT}\right)T}{I_{REF}}}+Const.\end{array}$$

(17)

According to Equation (17), by examining the coefficient of the temperature-related term in $\Delta t$, it is evident that the proposed dual-input capacitor multiplexing VTC increases the variation in $V_{out}$’s high-level duration with temperature by fully leveraging the large temperature coefficients of both $V_{CTAT}$ and $V_{PTAT}$ generated by the temperature sensing core. As a result, since the reference frequency provided by the subsequent relaxation oscillator remains constant with temperature, the proposed VTC significantly enhances resolution.

The comparator in the proposed VTC is shown in Figure 7. The structure is modified from the traditional double-tail comparator by introducing a cross-coupled configuration to increase the latch’s regeneration speed under low-power constraints [24]. This modification significantly reduces the delay time and avoids unnecessary errors during the comparison of $V_{in}$ and $V_{ip}$ in the VTC.

The comparator delay, $t_{delay}$, consists of two parts: $t_0$ and $t_{latch}$. The delay $t_0$ represents the charging time of the load capacitance $C_{Lout}$ at the output nodes $V_{on}$ and $V_{op}$ of the latch stage. The delay $t_{latch}$ represents the latch’s regeneration time, which is related to the initial output voltage difference $\Delta V_0$ and the effective transconductance $g_{meff}$ of the latch. Specifically, the larger the $\Delta V_0$ and $g_{meff}$, the shorter the regeneration time.

For the proposed dynamic comparator based on a cross-coupled structure, two control transistors, $M_{C1}$ and $M_{C2}$, are added to the pre-amplification stage in parallel with the $M_5$/$M_6$ transistors but in a cross-coupled manner to increase the differential voltage $\Delta V_{fn/fp}$ between $f_n$ and $f_p$. This, in turn, increases the output voltage difference $\Delta V_0$ at the start of latch regeneration. By adding two key transistors, $M_{K1}$ and $M_{K2}$, to the latch stage, the effective transconductance of the intermediate stage transistors is increased. The cross-coupled structure causes one of the first-stage output nodes ($f_n$/$f_p$) to be charged back to $V_{DD}$ at the beginning of the decision phase, turning on one of the intermediate stage transistors and thereby increasing the latch’s effective transconductance $g_{meff}$. In other words, positive feedback is enhanced [24].

In summary, the increases in $\Delta V_0$ and $g_{meff}$ improve the latch regeneration speed, reducing the overall comparator delay $t_{delay}$, which perfectly meets the requirements of the proposed VTC.

Additionally, it is worth noting that the pre-amplification stage introduces NMOS switch transistors $M_{sw1}$ and $M_{sw2}$, controlled by $f_n$ and $f_p$, respectively. These transistors simulate the latch operation, minimizing static power consumption and ensuring the low power consumption of the comparator circuit.

3.3. Relaxation Oscillator

The conventional current-mode relaxation oscillator is shown in Figure 8. In this design, the current in the $M_1$ branch generates the voltage reference $V_{ref}$, which is replicated to the $M_2$ branch to charge the capacitor C. When the voltage $V_c$ on capacitor C exceeds $V_{ref}$ across resistor R, the buffer generates a pulse that both switches the circuit to discharge the capacitor and feeds into the clock divider to produce the output clock. After a time $\tau$, the transistor $M_{SW}$ is turned on, discharging the capacitor C and completing the oscillation cycle [25]. This current-mode relaxation oscillator eliminates the need for comparators, significantly reducing power consumption.

In summary, the output frequency of the relaxation oscillator is determined by the inverter delay and the charge/discharge time of the capacitor, which are in turn determined by the reference current $I_{ref}$. The oscillation period $T_{RC}$ is given by the following:

$$\begin{array}{c}\hfill T_{RC}={\displaystyle \frac{V_{ref}C}{I_{ref}}}+\tau =RC+\tau .\end{array}$$

(18)

Using a D flip-flop for frequency division, the output frequency $f_{CLK}$ of the relaxation oscillator is as follows:

$$\begin{array}{c}\hfill f_{CLK}={\displaystyle \frac{1}{2T_{RC}}}={\displaystyle \frac{1}{2(RC+\tau )}}.\end{array}$$

(19)

Typically, conventional current references have a nonlinear temperature coefficient, making it difficult to compensate for the temperature dependency of the output frequency. To achieve weak temperature dependence of frequency, traditional methods often use series and parallel combinations of resistors with positive and negative temperature coefficients [25]. However, the accuracy achieved by these methods is insufficient to meet the stringent requirements of temperature sensors, and it is generally challenging to achieve a frequency with a minimal temperature drift at higher oscillation frequencies.

Figure 9 shows the schematic of the proposed voltage-mode relaxation oscillator. The amplifier ensures that the source voltage of $M_2$ equals $V_{REF}$, which has a low-temperature dependency. This voltage, together with resistor R, sets the current in the $M_2$ branch, which is then mirrored to the $M_3$ branch. The resistor R is composed of two resistors, $R_a$ and $R_b$: $R_a$ is an n-well resistor with a positive temperature coefficient, while $R_b$ is a poly resistor with a negative temperature coefficient. By adjusting the ratio of these two resistors, a temperature-independent equivalent resistance can be achieved, resulting in an output frequency with minimal temperature dependence.

In addition, the equation for the transmission delay of the inverter is as follows:

$$\begin{array}{c}\hfill {\tau }_{inv}=0.69C_L{\displaystyle \frac{R_{eqn}+R_{eqp}}{2}}.\end{array}$$

(20)

$$\begin{array}{c}\hfill R_{eq}={\displaystyle \frac{3V_{DD}}{4I_0}}(1-{\displaystyle \frac{7}{9}}\lambda V_{DD}).\end{array}$$

(21)

Therefore,

$$\begin{array}{c}\hfill \tau \propto {\displaystyle \frac{V_{DD}{C}_L}{I_{inv}}}.\end{array}$$

(22)

$R_{eq}$ is the equivalent on-resistance of the inverter, $C_L$ is the load capacitance, $I_0$ is the speed saturation current of the inverter, and $I_{inv}$ is the buffer bias current.

From Equation (18), the oscillation frequency depends on three parameters: R, C, and $\tau$. Since R and C are independent of temperature, minimizing the variation in $\tau$ can improve the accuracy of the oscillation frequency. According to Equation (22), $\tau$ is inversely proportional to the bias current. Thus, by using a temperature-independent current source $I_{REF}$ to bias the inverter, the oscillator period becomes independent of delay errors and is determined solely by the resistor and capacitor values. This design effectively reduces the impact of delay errors on the oscillation frequency, enhancing the overall stability and accuracy of the oscillator across varying temperatures.

3.4. Time-to-Digital Converter

The preceding stage of the TDC, known as a temperature-to-time converter, converts temperature into time. This converter outputs a pulse whose width is ideally linearly proportional to temperature, enabling the conversion of temperature to digital form by digitizing the pulse width. Since the proposed oscillator has a zero temperature coefficient, the temperature-to-digital relationship remains linear, which is crucial for accurate temperature measurement.

The block diagram of the TDC is shown in Figure 10. In this configuration, the output from the temperature-to-time converter and a clock signal from an on-chip relaxation oscillator are connected to an AND gate, allowing counting only during the pulse’s high period ($\Delta t$) for precise timing measurements. To prevent overflow and ensure accurate counting across the entire temperature range of 0 °C to 120 °C, while accounting for potential offsets due to process variations, a 15-bit asynchronous counter is employed [26].

4. Simulation Results and Discussion

The proposed temperature sensor has been implemented using a 180 nm process. The most important parameters for a temperature sensor include resolution, accuracy, and power consumption. In the following sections, we will discuss how such excellent performance is achieved, with a particular focus on the principles behind the ultra-high resolution.

Temperature resolution refers to the smallest temperature change that a temperature sensor can detect, i.e., the smallest temperature variation that can cause a change in the least significant bit (LSB) of the digital output code. Regardless of the type of readout method used in a temperature sensor, the resolution is equal to the ratio of the temperature range to the number of digital codes used for quantization. For the time-domain temperature sensor proposed in this paper, the overall resolution is directly determined by the sensitivity of $V_{out}$ to temperature and the $CL{K}_{REF}$.

Firstly, the utilization of a diode stacking structure results in a high slope of 5.2 mV/°C and 4.44 mV/°C for $V_{PTAT}$ and $V_{CTAT}$, respectively, as shown in Figure 11. Next, a dual-input capacitor multiplexing VTC is introduced, amplifying the effects of the high TC $V_{PTAT}$ and $V_{CTAT}$, thereby increasing the sensitivity of $V_{out}$ to temperature.

It is also noteworthy that the self-designed relaxation oscillator achieved an oscillation frequency higher than 1.03 MHz, as shown in Figure 12. Ultimately, an excellent resolution of 0.0071 °C was achieved.

The temperature sensor’s accuracy is primarily dependent on the precision of the reference frequency and the stability of the temperature coefficients of $V_{PTAT}$ and $V_{CTAT}$. Figure 12 presents the variation in $f_{REF}$, achieving a variation of as low as 0.19 %. The previously mentioned stability can be represented by the TC of ${\displaystyle \frac{\partial V_{PTAT}}{\partial T}}$ and ${\displaystyle \frac{\partial V_{CTAT}}{\partial T}}$. Within the temperature range of 0∼120 °C, the simulated values for these coefficients are 113 ppm/°C and 105 ppm/°C, respectively.

Therefore, Figure 13 presents the simulated inaccuracy of the output temperature code within the target temperature detection range, considering different process corners and two-point calibration using 10 °C and 60 °C as temperature references. The absolute inaccuracy for the TT process corner is +0.43 °C/$-0.38$ °C. This result indicates that the proposed design has a low susceptibility to process variations.

The diode stacking structure of the temperature sensing core, the optimization of the comparator circuit’s static power consumption in the VTC, and the design of a comparator-free relaxation oscillator have resulted in a low-power temperature sensor. The total power consumption of the sensor is measured at 1.48 $\mathsf{\mu }$W, with the relaxation oscillator accounting for a significant fraction of the total sensor power, specifically 962.7 nW. The power consumption of each part of the sensor is plotted in Figure 14.

The performance comparison of the proposed temperature sensor and several prior works is tabulated in

Table 1. Performance comparison with other works.

Paper	JSSC [27]	TCAS-I [8]	TCAS-I [28]	TCAS-II [1]	TCAS-II [29]	MDPI [30]	This Work
Year	2022	2020	2021	2022	2023	2018	2024
Technology (nm)	110	180	130	65	28	180	180
Type	BJT	MOSFET	MOSFET	Res	Res	BJT	MOSFET
Supply Voltage (V)	1.35∼2	1.8	0.95	0.9	0.9	1.8	1.2
Temperature Range (°C)	−40∼140	−20∼80	0∼80	−5∼95	−40∼100	0∼100	0∼120
Resolution (°C)	0.144	0.1	0.1	0.0098	0.0565	0.01	0.0071
Conversion Time (ms)	0.8	25	59	10	0.404	3.4	26
Inaccuracy (°C)	+1/−1	+0.66/−0.73	+0.44/−0.4	+1.8/−1.6	+0.81/−0.62	+0.2/−0.2	+0.43/−0.38
Relative Inaccuracy 1 (%)	1.11	1.39	1.05	3.4	1.02	0.4	0.675
Power 2 ($\mathsf{\mu }$W)	3.1	1.99	0.196	0.31	123.5	11.2	1.48
Energy/Conversion (nJ)	2.48	49.75	11.56	3.1	49.9	38	38.39
Resolution FOM 3 (nJ · K2)	0.0514	0.4975	0.1156	0.000297	0.159	0.0038	0.0019

¹ Relative Inaccuracy (%) = Max error/Temperature range × 100. ² Power or energy for generating external references not include. ³ Resolution FOM (nJ · K²) = Energy/Conversion × (Resolution)².

. It must be stated that our results are based on simulations. Compared to other temperature sensors, the sensor proposed in this paper is featured with high accuracy and low power consumption, particularly excelling in resolution. The resolution of this sensor is better compared to sensors with the same readout structure.

It can be noted that the simulation is limited to the temperature range of 0∼120 °C to achieve the best performance in terms of inaccuracy and resolution. For a wider temperature range, the nonlinearity of the temperature sensing element becomes more significant, as the second-order derivative is always positive. It is scalable to a wider temperature range at the cost of resolution, depending on the application.

5. Conclusions

A CMOS-based temperature sensor with a time-domain readout is designed in a 180 nm CMOS process. It utilizes a reference current and voltage to bias the $V_{PTAT}$ and $V_{CTAT}$ generators, achieving high accuracy through a diode stacking structure that increases the TC of both $V_{PTAT}$ and $V_{CTAT}$. Additionally, a dual-input capacitor multiplexing VTC is used to enhance resolution by fully utilizing both temperature-negative and temperature-positive correlated information. Moreover, a low-temperature drift voltage-mode relaxation oscillator is included to effectively address the issue of large oscillation frequency drift caused by a significant temperature impact on the delay error. The simulation results show that the proposed temperature sensor has a 0.0071 °C resolution, a 1.9 pJ · K² resolution FoM, an acceptable inaccuracy of +0.43 °C/−0.38 °C, and a power consumption of only 1.48 $\mathsf{\mu }$W from 0 °C to 100 °C for 1.2 V supply after two-point calibration.