Electric-Field Induced Doping Polarity Conversion in Top-Gated Transistor Based on Chemical Vapor Deposition of Graphene

Abstract

The top-gated graphene field effect transistor (GFET) with electric-field induced doping polarity conversion has been demonstrated. The polarity of channel conductance in GFET can be transition from p-type to n-type through altering the gate electric field scanning range. Further analysis indicates that this complementary doping is attributed to the charge exchange between graphene and interface trap sites. The oxygen vacancies in Al₂O₃filmare are considered to be the origin of the trap sites. The trapping–detrapping process, which may be tuned by the electric field across the metal/oxide/graphene gate stack, could lead to the changing of the intrinsic electric property of graphene. This study promises to produce the complementary p- and n-type GFET for logic applications.

1. Introduction

As a two-dimensional (2D) sp² hybridized carbon atomic network, graphene has attracted much interest as a new electronic material. Graphene is considered to be a greatly promising material for future electronic applications because of its high carrier mobility, carrier saturation velocity and thermal conductivity [1,2,3,4,5]. Differing from the traditional bulk semiconductor (Si, Ge, GaAs et al.), the carrier type in graphene can be either hole or electron, which is usually called the ambipolar characteristic. This phenomenon can be due to the unique cone-like zero energy band structure of graphene. In graphene, the valence band intersects with its conduction band on the so-called Dirac point energy. When the Fermi level is shifted below or above the Dirac point, the graphene is either p-type or n-type doping, respectively [1]. For further digital logic application, complementary p- and n-type doping graphene transistors are highly demanded [6,7]. Several methods have been proposed to control the doping type of GFET. For example, the p-type doped GFET can be obtained by the physical adsorption molecular oxygen on the graphene surface. Meanwhile, the GFET can also be n-type doped through NH₃ annealing after N+ ion irradiation. The change of the doping polarity can owe to the electron transfer from N atoms decoration [8]. Furthermore, the doping level of graphene can also be tuned by coating the hydrogen silsesquoxane (HSQ). The n-type and p-type doping GFETs were realized due to the carrier injection from the Si-H and Si-O bonds [6]. The titanium (Ti) passivation layer was also utilized as a dopant to acquire the p-type doping graphene transistor. In addition, graphene can be changed to be n-type doped through an annealing process followed by the deposition of silicon nitride (Si₃N₄) dielectric film. The electron doping is caused by exposure to the NH₃ gases involved in the Si₃N₄ deposition process [9,10]. However, the methods reported in the above literature were all related with back-gated GFET, in which the graphene channel was left uncovered. For realistic device applications, graphene would require a dielectric layer and metal electrode. Some groups have fabricated top-gated GFET, in which the carrier type can be tuned by the back-gate electric potential [11,12,13]. However, the extra global bottom-gate structure makes it impractical for complementary doping application. As a result, the new method of converting the doping polarity of graphene in top-gated GFET is required. In this study, we demonstrated that a complementary doping of top-gate GEFTs from p-type to n-type utilizing O₃-based atomic layer deposition Al₂O₃ as dielectric stack. The doping polarity of the GFET can be controlled by the applied top-gate electric field sweeping range, which indicates that the charge traps in the dielectric layer may be the key factor for this p-type to n-type conversion.

2. Experimental

Figure 1a shows process flow for top-gated GFET fabrication. The graphene film used in this study is grown by chemical vapor deposition (CVD) on copper. Then the graphene was transferred onto a heavily doped Si substrate with 100 nm SiO₂. The source-drain contact region was defined by electron beam lithography followed by a Pd/Au (15/50 nm) stack layer evaporation and lift-off process. Next, the sample was carried to the atomic deposition layer (ALD) grown chamber with six cycles of tri-methylaluminium (TMA) and O₃ at 25 °C. This process can provide the dangling bonds for the subsequent ALD deposition. Then, the Al₂O₃ dielectric film was deposited on the simple using ALD process with 200 cycles of TMA/H₂O at 200 °C. TheAl₂O₃ dielectric layer serves as a mask to protect the graphene from the residual resist induced by the subsequent fabrication process. The gate finger stacks of Ti/2 nm Pt/15 nm Au/50 nm were deposited onto the oxide surface. After patterning the channel region of graphene through photolithography, the top gate dielectric film out of the channel region was removed by 1:3 solution of H₃PO₄:H₂O. Oxygen plasma treatment was employed to etch the unwanted graphene below the removed dielectric layer. After the photoresist mask was removed by the acetone, external pads for electrical measurement were formed by a deposition of the Ti/20 nm Au/200 nm and a standard lift-off process. Figure 1b shows the atomic force microscopy (AFM) image of the patterned channel region, which consists of graphene film, Al₂O₃dielectric layer and residual resist originate from photoresist mask. The thickness of the patterned channel region is 30 nm. Considering the 1–2 nm thick CVD-grown graphene film and 6–8 nm residual resist film, the thickness of Al₂O₃ layer (t_ox) is about 20 nm. The value of top-gate capacitance (C_OX) can be estimated to be 350 nF cm⁻² through using the equation, C_OX=κε₀/t_ox, where κ is the relative dielectric constant with value of 8 and ε₀ is the permittivity of free space [5]. Figure 1c shows the evolution of the Raman spectrums of the initial CVD graphene after transfer and Al₂O₃-cotated graphene. The ratio of 2D and G band of pristine graphene is 2.8 and the shape of the 2D band is symmetrical, confirming the single layer nature. The G band and 2D band position shifts 13 cm⁻¹ and 19 cm⁻¹ higher than Reference [14], respectively, indicating p-type doped in the material [15]. The p-type doping of the graphene can be usually observed in the CVD materials, which can be attributed to oxygen, water and polymer residue induced by the transfer process [16,17,18,19]. However, the characteristics of Raman feature from graphene with Al₂O₃ are observed as a splitting of G peak, which can be reproduced by assuming two Lorentzian components, centered at ~1531 and ~1590 cm⁻¹. The G-peak splitting in the Raman spectra can be attributed to the presence of the randomly distributed impurities or surface charges [20]. Figure 1d shows the optical micrograph of the completed top-gated graphene transistor. The source/drain separation, the gate length and the total gate width are 1 µm, 500 nm and 40 µm, respectively.

3. Results and Discussion

The direct current characteristics of our GFET were measured by HP 4142 in an ambient atmosphere at room temperature. Figure 2a shows the drain current (I_DS) as a function of top gate voltage (V_TG) at different drain voltages (V_DS). The V_TG sweeps from 0 V to 6 V. The V_DS is changed from 0.5 V to 2.5 V. The Dirac point voltage (V_Dirac), which is defined as the voltage at I_DS minimum, locates at a positive voltage (1.3 V, 2.3 V, 3.2 V, 4 V, 2.6 V). The positive V_Dirac indicates the p-type behavior of device. It is similar to the performance of most reported GFETs based on CVD grown materials. The p-doping characteristic of GFET may be attributed to the water, oxygen, and residual resist from the transfer and fabricating process [21,22]. Interestingly, it is found that the V_Dirac suddenly decreases from 4 V to 2.6 V when V_DS increases from 2 V to 2.5 V. According to the analysis of X-ray photoelectron spectroscopy (XPS) (seen in the Supplementary Materials), an oxygen deficiency with a Al/O ratio of 1:1.23 at the surface of the Al₂O₃ film was observed. The deficiency of oxygen in the Al₂O₃ film can be due to the oxygen vacancies that are formed during hydrolysis and condensation processes. The oxygen vacancies lead to the formation of interface and bulk traps in Al₂O₃ film. Electrons will transfer from trap sites in Al-rich Al₂O₃ film to graphene, resulting in n-type doping. When the V_DS is biased at 0.5 V, 1.0 V, 1.5V and 2.0 V, the charge trapping/detrapping process only occurs at the interfacial trap sites between graphene and Al₂O₃ layer based on TMA/O₃ ALD process. As the V_DS is increased to 2.5 V, extra electrons will be injected into graphene channel from the bulk trap sites in the Al₂O₃ layer based on TMA/H₂O ALD process. The extra injection of electrons results in the n-type doping and moves the V_Dirac to a more negative direction. Figure 2b shows the output characteristic (I_DS-V_DS) of the GFET with V_TG varying from 0 V to 6 V. The V_DS is swept from 0 to 2.5 V. All curves are linear dependence on V_DS, indicating the ohmic contact properties. When V_DS<1.3 V, the I_DS monotonically increases with the increasing V_TG. After V_DS<1.3 V, the I_DS initially decrease and then increase with the increasing gate voltage.

Interestingly, when the sweeping range of V_TG changes from −6 V to 0 V, the V_Dirac of I_DS-V_DS curve locates at: −2.4 V, −2.2 V, −1.7 V, −0.8 V, 0.7 V (seen in Figure 3a and the Supplementary Materials). The negative shift of V_Dirac suggests the n-type doping of GFET. The n-type doping in our device can be explained in two aspects. One is the less residual on the graphene surface originated from the lithography process benefiting from the protection of oxide dielectric mask. The other is the extra electron carrier in graphene induced by the impurities and trap sits in Al₂O₃ layer [22]. Similar to that in p-type doping condition, the position of V_Dirac also shifts to the positive direction with the increasing V_DS. This V_TG sweeping range dependent shift of V_Dirac suggests that the charge trap mechanism may be the main reason for this conversion of the doping polarity [23]. Besides, the current of the transfer curve revels higher compared with that in Figure 2a, indicating an improved field-effect carrier mobility. Figure 3b shows the corresponding output characteristic. Similar to the p-type doping GFET, the output characteristic also shows linear behavior. When V_DS<0.8 V, the I_DS initially decrease and then increase with the decreasing gate voltage. After V_DS>0.8 V, I_DS monotonically increases with the decreasing V_TG.

Figure 4 shows drain current hysteresis behavior for the GFET at different V_DS varying from 0.5 V to 2.5 V. The V_TG was swept forward from −6 V to 2 V at first. Then V_TG was swept backward from 2 V to −6V. The forward and backward V_TG sweeping lead to the positive shift of V_Dirac, which can be related to the charge exchange between graphene and the interface trap sites. When the V_TG starts at negative gate voltage, holes in graphene are slowly trapped into the interface trap sites induced by the oxygen vacancies in Al₂O₃ film. Hence, after some time the graphene sees a more positive potential than that simply due to the gate voltage.

The mechanism for the p-type to n-type doping conversion in the top-gate GFET is analyzed and discussed below. It is noted that Al₂O₃ film deposited by atomic layer deposition are usually oxygen deficient. The oxygen vacancies are considered to be the most important defects in ALD oxide layer, which can induce border traps near the interface [24]. Thus, the charge exchange between the graphene in channel and trap sites in the Al₂O₃ dielectric layer may be the most likely reason for this complementary doping process. To help understand the mechanism of the charge trap-induced doping, we illustrate the energy band profiles of the top-gate GFET at different bias conditions in Figure 5. The potential profiles of gate metal/Al₂O₃/graphene stack before and after contact in GFET were seen in Figure 5a,b. According to the Aderson model [25], the barrier height Φb (= Φ_Ti − Φ_Al2O3 = 4.3 eV − 1.0 eV) at gate side is 3.3 eV and the conduction band offset ΔΕ (= Φ_Ti − Φ_SLG = 4.3 eV − 4.5 eV) is −0.2 eV. When the positive gate voltage is applied (seen in Figure 5c), the electrons are induced in the graphene channel. In this case, some electrons may be injected into the trap sites at Al₂O₃/graphene interface from graphene due to external electric field (E_EX) across metal/Al₂O₃/graphene stack. The outflow of electrons shifts the Fermi level of graphene down to the neural point and leads to the p-type doping of GFET. At a steady state, the electrons stored in the trap centers could reduce the electrochemical potential and thus weaken the effective electric field near the interface between Al₂O₃ and graphene. Therefore, more positive gate voltage will be required to compensate for the reduced effective electric field and the V_Dirac is shifted to the positive direction [26,27]. Similarly, as the negative gate bias was applied positive, the holes are induced in graphene and injected into the interface trap centers due to E_EX, leading to the n-type doping of GFET (seen in Figure 5d). Furthermore, the stored holes increase the chemical potential in Al₂O₃ layer and reduce the effective electric field near the interface between Al₂O₃ and graphene. In this case, more negative gate voltage is needed to recover the potential in graphene. As a result, the V_Dirac is shifted to the negative direction.

In order to deepen the understanding of the electrical properties of GFET from p-type doping to n-type doping, their resistance profiles (R_T) can be fitted to the expression [28,29]:

$$R_T=R_S+\frac{L_{TG}}{We{\mu }_{FE}\sqrt{n_0{}^2+n^2}}$$

(1)

where R_T is total device resistance, e is the electron charge, n is the carrier concentration controlled by top-gate, n₀ is the residual carrier concentration, L_TG is length oftop-gate length, the W is the width of graphene channel of covered by top-gate, and µ_FEis the field-effect carrier mobility of GFET. In addition, R_S is the parasitic resistance which consists of the contributions from both the access regions and contact regions.

Figure 6a,b show the plot of the total resistance as a function of V_TG for p-type doping and n-type doping GFETs with V_DS fixed at 0.5 V. The measured resistance (symbols) is fitted with the modeling results of Equation (1) (solid line), showing good agreement with the experimental data. Fitting the experimental total resistances to the Equation (1) allows for extrapolation of µ_FE, n₀ and R_S. From this fitting, the values of µ_FE, n₀ and R_S for the p-type doping GFET are extracted to be 720 cm²/Vs, 9.6 × 10¹² cm⁻² and 75.9 Ω, respectively. However, the µ_FE of n-type doping GFET increases to 2535 cm²/Vs. The corresponding n₀and R_S are reduced to 3.0 × 10¹² cm⁻² and 49.5 Ω. The different carrier transport parameters of p-type doping and n-type doping GFETs can be attributed to the asymmetry of the R_T-V_TG curves. In our GFET, the graphene under the metal contact will be p-type doped [16,17,30]. When the Fermi level of graphene in channel region is moved upward neural point by the top gate electric field, the p-n junction will be formed between channel and contact region [29,30]. The p-n junction will increase the metal/graphene contact resistance and therefore enhance the value of R_S. In addition, the electron conduction branch of the total resistance will be suppressed by the increasing total resistance induced by the p-n junction. As a result, the µ_FE extracted from the electron branch of R_T-V_TG curve will be smaller than that of hole branch.

4. Conclusions

In summary, we report the top-gated GFET with electric-field-induced doping polarity conversion. Both p-type and n-type doping GFET can be obtained through altering the gate voltage sweeping range. Further analysis indicates that the charge exchange between graphene and trap sites in Al₂O₃ lead to the conversion of doping type. The trapping–detrapping process can be modulated by the external electric field across the metal/oxide/graphene stack, thus change the doping polarity of the GFET.