Piezoresistive Memories Based on Two-Dimensional Nano-Scale Electromechanical Systems

Abstract

In this work we present piezoresistive memory-bits based on two-dimensional nano-scale electro-mechanical systems. We demonstrate it is possible to achieve different electrical responses by fine control of micro-structural asymmetries and that information can be encoded in the geometrical configuration of the device and read as in classical ReRAM memories by measuring the current flowing across it. Based on the potential energy landscape of the device, we estimate the energy cost to operate the proposed memories. The estimated energy requirements for a single bit compete with existing technologies.

1. Introduction

Resistive switching (RS) is the phenomenon at the base of non volatile resistance change, usually in response to the presence of a strong electric field between the two metal contacts of a metal–insulator–metal interface [1,2,3]. Differently to dielectric breakdown, in which the creation of conductive paths in the body of the insulator is permanent and irreversible, RS is reversible yet preserving the the non-volatility of the resistance states. The existence of two accessible resistance states can be exploited to encode information. This is the base of ReRAM memories, where many memory cells are densely packed in a crossbar array. The resistive switching in the ReRAM cell can originate from different mechanisms, the most common being the formation/interruption of a conductive filament in the matrix [4,5]. RS has been studied mainly in insulating materials such as oxides [6,7,8,9], nitrides [10,11,12], chalcogenides [13,14,15] and organic materials [16,17,18]. Similar phenomena has also been observed in metallic porous films [19]. This latter case being of main importance since (i) it does not require the use of exotic materials or insulating ones, and (ii) the physical mechanism triggering RS is the structural modification of the film at the micro- and nano-scales instead of the creation of conductive paths in an insulating matrix.

Alternatively to common ReRAM resistive switching mechanisms, here we propose a method based on the piezoresistive property of some 2D materials. Molybdene disulfide (MoS₂) along with other Transition Metal Dichalcogenides (TMDs), exhibits piezoresistivity in its mono- and multi-layer crystalline structure [20,21]: a change in its atomic structure provokes a modification of the electronic band structure and, therefore, a modulation of the electron flow under finite bias [22,23]. This suggests it is possible to design and build a memory bit based on Nano-Electro-Mecanical-Systems (NEMS), exploiting the piezoresistivity of 2D materials. The main challenge is to find a structure with two geometrically stable states leading to two different resistance values, defining two logic states, i.e., ‘0’ and ‘1’. Moreover, both logic states should be accessible and, ideally, the transition from one to the other should be effectively triggered by an external electric field.

We consider two different designs implementing such a purpose, each one with pros and cons, in terms of integration, energy consumption and tuning parameters. The piezoresistive material considered in this study is Molybdene disulfide (MoS₂), coupled with hexagonal Boron-Nitride (h-BN) for one of the two designs presented in this work. The proposed devices should exploit asymmetries on the strain across the structures corresponding to two stable configurations leading to different currents, $I_0$ and $I_1$. Therefore, correctly estimating the electrical conductivity of the proposed configurations becomes crucial.

2. Methods

We considered nano-scale devices, with scale factor in the order of the nano-meter. These ultra-scaled devices are extremely interesting for the development of next-generation electronic devices [24,25,26,27]. At this length-scale, the considered devices are formed by not more than few hundreds of atoms, allowing for an atomistic approach. We describe the electronic structure self-consistently using Density Functional Theory (DFT) within the Generalized Gradient Approximation (GGA) as implemented in the SIESTA package [28] (version 4.1-b4). Core electrons are modeled with Troullier–Martins nonlocal pseudopotentials, while the valence electrons are expanded with a double-$\zeta$ basis set. The mesh cutoff is 300Ry and a 10 × 10 × 10 k-point mesh is used for each unit-cell. We relax all the atomic coordinates till atomic forces are below 0.04eV/Å.

It is well known that for a given material, electron transport at length-scales below the electron mean free path, $l_e$, is mainly ballistic. Here, we are interested in MoS₂ and h-BN (hexagonal Boron-Nitride) devices, having both $l_e\approx 30$ nm [29,30], well above the considered device dimensions. Accurate estimates of the ballistic component of electronic transport in nano-structures can be obtained using ab initio methods [31]. We resort again to DFT combined with nonequilibrium Green’s function (NEGF) techniques to study ballistic transport across the proposed devices. We have used the TranSIESTA software [32,33] (version 4.1-b4), which calculates the self-consistent electronic structure of a finite nanostructure, called scattering region, coupled to three-dimensional semi-infinite leads (or electrodes). A different electrochemical potential is set to each lead defining a bias condition. It uses a full atomistic ab initio description of both the electrodes and the scattering region allowing to obtain accurate conductance estimates to assign to each logic state.

We have used gold electrodes for both configurations, which effectively reduces the Schottky barrier for the two metal-semiconductor contacts [22,34]. Additionally, 8 × 8 100-Au electrodes, 4 layers thick, sampled with a converged k-point grid of 3 × 3 × 20 are used in all the calculations shown in this work. Electrode-device contacts have been realized in three steps: (1) relaxing the device structure, fixing the edges; (2) relaxing the semi-infinite Au electrode structure; (3) relaxing the system composed by device and electrodes.

3. Results

Mono-layer MoS₂ is a direct band-gap semiconductor with an energy band-gap of 1.8 eV [35,36]. The atomic structure of a single-layer MoS₂ is shown in Figure 1a. Mo and S atoms are arranged in a hexagonal lattice respect to the yz-plane. Like others transition metal dichalcogenide, MoS₂ consists of weakly coupled sandwich layers S-Mo-S in which a Mo-atom layer is enclosed within two sulfur layers (see Figure 1a) where the zig-zag and arm-chair side views are represented, respectively). The electronic band structure of MoS₂ is highly sensitive to strain: the application of strain modulates the electronic band-gap with a rate of ∼−50 meV/% strain for both compression and elongation. Extreme strain values, i.e., −13% and +11%, can provoke a complete closure of the energy band-gap [37,38] triggering the transition from semiconductor to semi-metal as represented in Figure 1b. MoS₂ have been reported to modulate its energy band gap upon bi-axial and uniaxial deformations, in the xz-plane, with small variations regarding the axis of deformation [21,39,40].

In Figure 2, we report the energy band structures of MoS₂ under three different levels of compression (top panels) along with the density of states (DOS) of pristine uncompressed MoS₂ and compressed MoS₂ (bottom panel). The observation of energy-band gap closure and DOS population around the Fermi energy gives hints to the possibility to exploit different geometrical configurations of a MoS₂ flake with different compression levels to obtain different conductivity states.

These results show the response of infinite single layer MoS₂ but, in order to model real devices, finite structures must be considered. The non-periodic structures considered are suspended ribbons free to relax in the out-of plane direction. In plane compression in 2D material, suspended ribbons is usually followed by buckling: internal stress is released by bending in the out-of-plane direction. For a single layered MoS₂ ribbon, buckling arises at small compression strain [21] and, once buckled, the structure presents two stable configurations. From a geometrical point of view, these configurations are different, and thus, in principle can be exploited to encode a bit of information, e.g., ‘0’ when buckled up, ‘1’ when buckled down. However, when it comes to integrate such a device in an electronic computing system it is desirable to count with an electric read-out circuit measuring, for instance, the current flowing across the device. Unfortunately, these two configurations show the same electrical response since both configurations lead to the same strain distribution along the transport direction. This prevents the use of this device to encode information.

In order to have different output currents, it is required to break the symmetry between the ‘0’ and ‘1’ state so as to develop different strain distributions in the device. In the following we present two approaches based on (i) vertical stacking of MoS₂ and h-BN suspended ribbons (vertical 2D heterostructure) and (ii) asymmetries on the mechanical clamps of a MoS₂ suspended ribbon. A cartoon presenting the two proposed configurations, along with their potential energy landscape is presented in Figure 3. Yellow blocks represent the gold electrodes where the structures are attached to. We set the transport direction along the z-axis (arm-chair direction for the MoS₂), while the structures are free to relax along the out-of plane direction (y-axis). The lower panels in Figure 3 show the expected energy landscape of each structure. While a ribbon composed of a single MoS₂ layer shows a symmetric potential landscape for both compressed and non-compressed configurations (blue long-dashed and red short-dashed lines in left panel of Figure 3), a heterostructure favors one of the two stable states: the neutral axis of the resulting structure does not lay anymore at the interface between the two materials, so upward and downward buckling carry different strain distributions, in particular, for the piezoresistive material. In the right panel of Figure 3, the architecture based on clamping asymmetries is shown. The effect of the clamping angle, $\alpha$, is reflected in the potential energy landscape of the ribbon: for $\alpha =0$ the ribbon buckles symmetrically (blue long-dashed line) while deviations from this ideal situation induce a preferable state in which internal stress is better released compared to the other stable configuration. We identify for both devices the lower energy configuration with the ‘0’ logic state and the higher energy one with the ‘1’ logic state.

All the calculations in this work have been performed at 0 K. By increasing the temperature we expect contributions to the dynamics of the system and on the electronic transport as well. Regarding the dynamics of the systems, thermal noise could affect the geometry of the system, and potentially the system could spontaneously transit from one (metastable) state to the other and vice-versa. However, the studied devices have an energy barrier in the order of few eV while the thermal energy at room temperature is ∼26 meV. The probability of a spontaneous jump is thus negligible. Regarding the electronic transport we expect two major effects on our devices: the increase in the electron–phonon interactions and the modulation of the available electronic states in the leads. The first should reduce the output current for both states, ‘0’ and ‘1’, even if possibly with different strength for each state. The same trend is expected for the latter. The asymmetry between the meta-stable states should be optimized for a specific temperature range to maximize the device response.

Electronic transport could also be affected by the device termination, in the electrode interface, determining the absolute current flowing across the device. However, the meta-stable configurations for the two considered devices share the same contacts and thus the effect of mechanism encoding the information (strain distribution) remain valid.

Finally the device-electrode contact regions are fixed in space. In an actual device, the contact region should be designed to sustain the lateral force due to the compression and thermal agitation to prevent sliding between devices and electrodes. Recent experiments have demonstrated that the Au/MoS₂ interface can hold a stretching strain of the MoS₂ up to 10% without sliding [22]. Given the lower energy increase for the compression respect to the elongation, and the relaxation of the internal energy in the bending, it is possible to achieve sufficient friction between Au/MoS₂ to prevent sliding.

3.1. Vertical 2D Heterostructure

In a vertical 2D heterostructure, different materials are staked one on top of the other. In many cases, atoms belonging to each layer are covalently bonded while coupling between layers is relatively weak via van der Waals forces. From the left panel in Figure 3, we can easily see that a two-layer vertical heterostructure is not symmetrical with respect to the $y=0$ plane. At this point, we consider one material of the heterostructure to be piezoresistive while the other is a semiconductor with high band gap. The presence of a van der Waals bonding ensures that the electronic interaction between the layers is weak, and thus, the in-plane electronic conductance of a heterostructure can be approximated with the parallel of the conductance of each layer. Due to the fact that the piezoresistive material lays out of the neutral axis, its relaxed strain distributions, once the heterostructure is buckled (upwards or downwards), are by construction different, resulting in different conductivity values for each configuration. To produce the results shown in this section, we have used MoS₂ for the piezoresistive layer and an h-BN layer, counting with an energy band gap of 6 eV (three times that for MoS₂), for the non-piezoresistive one, since only slight modifications of the band structure are observed for strained BN [41].

We have relaxed the primitive cell for each material obtaining 3.12 Å and 2.50 Å for MoS₂ and h-BN, respectively. Notice that the lattice constants of the two are quite different [42]. We have set up a heterostrucutre composed of 4 × 3 6-atom MoS₂ unit-cells on top of a 5 × 4 4-atom BN unit-cells, with a size of 1.1 nm × 2.16 nm. This super-cell can be considered periodic with little to no strain in each layer. The mean separation between MoS₂ and BN layers is 0.4 nm.

To achieve the buckled configurations the heterostructure has been compressed by ≈5% and allowed to relax in the out-of-plane direction. The total displacement between the two stable states is ≈1 nm. To evaluate the conductance of the heterostructure in the two states we have attached two gold electrodes at both ends and solved the transport equations with different external bias as explained in Section 2.

The left panel of Figure 4 presents the current flowing across the heterostructure for different voltage bias in both configurations. For both stable configurations, the current across the device increases with the bias voltage. As expected, the two stable configurations lead to different currents at equal bias voltage, demonstrating that the configuration of the device, encoding the bit stored in the memory, can be easily identified monitoring the current. Importantly, the difference in the output current is maintained for all the considered voltage range. The ratio $I_1/I_0$ is presented in the inset of Figure 4, left panel. Larger ratios mean improved distinguishability between the two states. Notice that, since the current is very low, the energy efficiency of this memory device is very high. In order to evaluate the energy required to write a bit of information, we assume that the transition between states happens through a flat configuration and that the energy required for writing a bit is the energy difference between the stable states and the flat configuration (corresponding to the local maximums of the black energy curves in Figure 3). This reasoning leads to an energy cost of maximum 9.14 eV (1.4 aJ) per bit, a few orders of magnitude above the minimum energy required to store a bit of information (2.805 zJ/bit at room temperature), according to the thermodynamic limits [43,44], and a few orders of magnitude below ReRAM memory (∼0.1 pJ/bit) [45,46]. We should note that the energy cost of the write operation in ReRAM memory includes overheads here not considered. The writing energy in our design can be reduced and optimized using ad-hoc force protocols to smooth the transition from one state to the other [47].

3.2. Asymmetries on Clamping

For a monolayer MoS₂ flake, to achieve symmetry in the buckled configuration, it is mandatory to have the two clamping parallel and symmetric. In fact, a tilt in one or both of the clamping areas provokes a bending force which makes one of the two states favored. The favored state has a lower potential energy with respect to the other one.

Depending on the ribbon dimensions and the amount of compression, an exaggerated tilt on the clamping can make the system monostable, even if compressed. Fine tuning of the clamps tilt, characterized through the angle $\alpha$ in Figure 3, makes it possible to design a bistable system where the two stable configurations have two different strain distributions, resulting in different conductance values. As for the previous method, this difference in conductance can be exploited to determine the state of the system, i.e., the bit encoded in the memory. To investigate this scenario we have simulated a MoS₂ ribbon composed of 3 × 10 6-atom MoS₂ unit-cells, compressed as 15%, with a final size of 1.1 nm × 4.6 nm. We have investigated several tilting angles, and the higher the angle is the higher the difference is between the two states, both in terms of potential energy and difference in flowing current across the device. Therefore, better distinguishability requires higher energy expenditure.

The current at different voltage bias for the two stable configurations is shown in Figure 5 corresponding to the MoS₂ ribbon with tilt $\alpha =40$ deg. Red squares refer to the most favorable state while black crosses to the less favorable one. As expected, in the energetically most favorable case, the strain in the structure is lesser than that for the other state. For this reason, in accordance with the reasoning made before, the current for the latter is lower than the one for the less favorable state (i.e., higher strain). In this experiment, we have a difference in current in the order of hundreds of nA for a bias voltage higher than 0.15 V. This condition makes the sensing feasible even without a very sensitive current amplifier. The benefit in terms of sensing has the drawback of higher energy budget, due to the higher current. Even in this case, we can estimate the energy cost of writing a bit into the memory by comparing the potential energy in the two stable configurations with the potential energy of the flat configuration. In this case, we have an average energy difference of 14 eV (2.2 aJ).

4. Conclusions

In this work, we have presented two concepts for realizing a memory bit exploiting the piezoresistive effect of some 2D materials. We have focused our attention on MoS₂, but other materials with similar characteristics can be used, with potential improvements in terms of energy performances. We have shown that it is possible to exploit the difference in strain in a buckled structure for reading the state of the memory monitoring the current flowing across the device. This kind of readout is a well-established method used in nowadays ReRAM memories. The presented memory concepts have the benefits of low energy requirements and low dissipated heat, due to the low current flowing across the device. In particular, we report an electric current in the order of few $\mu$A and hundreds of nA for the heterostructure and asymmetric configuration, respectively. Due to reliability purposes, it is important that the system can support two distinguishable states: while for the first configuration, we measure higher currents for a given polarization voltage, the two state currents differ less in percentage respect to the asymmetric configuration. While low current is good for energy efficiency, this poses some problems to the ability to detect the state of the system. Very low current requires a very sensitive current amplifier to be integrated into the system. This problem can be overcome by increasing the bias voltage across the device, also increasing the current up to the point of finding a trade-off between readout reliability and energy consumption. In terms of writing energy, the two configuration shows promising results (∼aJ/bit), with an order of magnitude below ReRAM memory (∼ 0.1 pJ/bit). This energy, however, is bound to rise considering larger structures. Evidence from the results of this study suggest it is possible to realize energy efficient memory devices exploiting asymmetries in geometrical configurations. Further studies could focus attention on the effect of system size and temperature, in order to point to the realization of an actual device.